Array substrate and display panel

Abstract

An array substrate, comprising: a clock signal line, having a clock signal line main body portion extending in a first direction and a first connection portion extending in a second direction away from the clock signal line main body portion, wherein the second direction intersects with the first direction; and a gate drive circuit, comprising a transistor connected to the clock signal line, wherein a connection electrode of the transistor connected to the clock signal line comprises a second connection portion, and an orthographic projection of the first connection portion on a base substrate and an orthographic projection of the second connection portion on the base substrate at least partially overlap each other in the first direction.

Description

Array substrate and display panel Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] In recent years, various display products (such as wearable products) have been undergoing cost reduction and narrowing of bezels. This poses a greater challenge to the design of the gate-on-array (GOA) circuit. Summary of the Invention

[0003] On one hand, this disclosure provides an array substrate, comprising: a clock signal line having a main body extending along a first direction and a first connection portion extending away from the main body along a second direction, wherein the second direction intersects the first direction; and a gate driving circuit including a transistor connected to the clock signal line, wherein a connection electrode of the transistor connected to the clock signal line includes a second connection portion, wherein the orthographic projection of the first connection portion on the substrate and the orthographic projection of the second connection portion on the substrate at least partially overlap each other along the first direction.

[0004] Optionally, the gate drive circuit includes a plurality of cascaded scanning units, each scanning unit including: a third transistor, the first electrode of which is connected to a first clock signal line, the second electrode of which is connected to the output terminal of the scanning unit, and the gate of which is connected to a pull-up node, wherein the first clock signal line includes the first connection portion, and the first electrode of the third transistor includes the second connection portion.

[0005] Optionally, the array substrate includes: a gate metal layer located on the substrate; a gate insulating layer located on the side of the gate metal layer away from the substrate; a semiconductor material layer located on the side of the gate insulating layer away from the gate metal layer; an insulating layer located on the side of the semiconductor material layer away from the gate insulating layer; a signal line layer located on the side of the insulating layer away from the semiconductor material layer; a passivation layer located on the side of the signal line layer away from the insulating layer; and a connection layer located on the side of the passivation layer away from the signal line layer, wherein the second connection portion of the first electrode of the third transistor is connected to the first connection pad through a third via, and the first connection portion of the first clock signal line is connected to the first connection pad through a fourth via, wherein the first clock signal line is located on the gate metal layer, the first electrode of the third transistor is located on the signal line layer, the first connection pad is located on the connection layer, and the third via extends through the passivation layer, and the fourth via extends through the passivation layer, the insulating layer, and the gate insulating layer.

[0006] Optionally, the gate drive circuit includes multiple cascaded scanning units, each scanning unit including a control sub-circuit. The control sub-circuit includes: a fifth transistor, whose first electrode and gate are connected to a third clock signal line, and whose second electrode is connected to a pull-down node; and a sixth transistor, whose first electrode is connected to the pull-down node, whose second electrode is connected to a low-level signal line, and whose gate is connected to a pull-up node, wherein the third clock signal line includes the first connection portion, and the first electrode of the fifth transistor includes the second connection portion.

[0007] Optionally, the array substrate includes: a gate metal layer located on the substrate; a gate insulating layer located on the side of the gate metal layer away from the substrate; a semiconductor material layer located on the side of the gate insulating layer away from the gate metal layer; an insulating layer located on the side of the semiconductor material layer away from the gate insulating layer; a signal line layer located on the side of the insulating layer away from the semiconductor material layer; a passivation layer located on the side of the signal line layer away from the insulating layer; and a connection layer located on the side of the passivation layer away from the signal line layer, wherein the second connection portion of the first electrode of the fifth transistor is connected to the second connection pad through a fifth via, and the first connection portion of the third clock signal line is connected to the first connection pad through a sixth via, wherein the third clock signal line is located on the gate metal layer, the first electrode of the third transistor is located on the signal line layer, the first connection pad is located on the connection layer, and the fifth via extends through the passivation layer, and the sixth via extends through the passivation layer, the insulating layer, and the gate insulating layer.

[0008] Optionally, the first electrode of the third transistor in each scanning unit is connected to the first clock signal line, and the phase of the signal on the third clock signal line is opposite to the phase of the signal on the first clock signal line.

[0009] Optionally, the gate driving circuit includes a plurality of cascaded scanning units, wherein the orthographic projection of the output terminal of each scanning unit on the substrate and the orthographic projection of the input terminal of the corresponding gate line on the substrate overlap at least partially with each other along the first direction.

[0010] Optionally, the array substrate includes: a gate metal layer located on the substrate; a gate insulating layer located on the side of the gate metal layer away from the substrate; a semiconductor material layer located on the side of the gate insulating layer away from the gate metal layer; an insulating layer located on the side of the semiconductor material layer away from the gate insulating layer; a signal line layer located on the side of the insulating layer away from the semiconductor material layer; a passivation layer located on the side of the signal line layer away from the insulating layer; and a connection layer located on the side of the passivation layer away from the signal line layer. The output terminal of the scanning unit is connected to a third connection pad via a seventh via, and the input terminal of the gate line is connected to the third connection pad via an eighth via. The gate line is located on the gate metal layer, the output terminal of the scanning unit is located on the signal line layer, the third connection pad is located on the connection layer, and the seventh via extends through the passivation layer, and the eighth via extends through the passivation layer, the insulating layer, and the gate insulating layer.

[0011] Optionally, the seventh via and the eighth via are located on the side of the common electrode line closer to the scanning unit.

[0012] Optionally, the array substrate further includes a common electrode line, wherein the common electrode line and the gate line are located on different layers.

[0013] Optionally, the array substrate further includes common electrode lines, wherein the common electrode lines and data lines are located on the same layer.

[0014] Optionally, the array substrate further includes an adjacent ground line and a frame start signal line, wherein the distance between the ground line and the frame start signal line is greater than or equal to 5 μm and less than 20 μm.

[0015] Optionally, the gate driving circuit includes a plurality of cascaded scanning units, each scanning unit including: a capacitor having a key shape, the capacitor including a key handle portion and key teeth portion; and a fourth transistor having a first electrode connected to a pull-up node, a second electrode connected to a low-level signal line, and a gate connected to a pre-frame reset signal line; wherein the orthographic projection of the fourth transistor on the substrate and the orthographic projection of the key handle portion of the capacitor on the substrate at least partially overlap along the first direction.

[0016] Optionally, the orthographic projection of the fourth transistor on the substrate and the orthographic projection of the spoon portion of the capacitor on the substrate at least partially overlap along the second direction.

[0017] Optionally, the fourth transistor is located on the side of the key portion of the capacitor near the pre-frame reset signal line.

[0018] Optionally, the gate drive circuit includes a plurality of cascaded scanning units, each scanning unit including: a capacitor and a fourth transistor, wherein a first electrode is connected to a pull-up node, a second electrode is connected to a low-level signal line, and a gate is connected to a pre-frame reset signal line; wherein the capacitor has a tapered shape along the direction close to the fourth transistor, and the orthographic projection of the fourth transistor on the substrate and the orthographic projection of the capacitor on the substrate at least partially overlap along the first direction and at least partially overlap along the second direction.

[0019] Optionally, the gate driving circuit includes a plurality of cascaded scanning units, each scanning unit including a capacitor, the capacitor including a first electrode plate and a second electrode plate, the first electrode plate including a first electrode plate first portion and a first electrode plate second portion, wherein the first electrode plate first portion is connected to the first electrode plate through a ninth via.

[0020] Optionally, the second electrode plate is located between the first portion of the first electrode plate and the second portion of the first electrode plate.

[0021] Optionally, the array substrate includes: a gate metal layer located on the substrate; a gate insulating layer located on the side of the gate metal layer away from the substrate; a semiconductor material layer located on the side of the gate insulating layer away from the gate metal layer; an insulating layer located on the side of the semiconductor material layer away from the gate insulating layer; a signal line layer located on the side of the insulating layer away from the semiconductor material layer; a passivation layer located on the side of the signal line layer away from the insulating layer; and a connection layer located on the side of the passivation layer away from the signal line layer, wherein a first portion of the first electrode plate is located on the gate metal layer, a second electrode plate is located on the signal line layer, a second portion of the first electrode plate is located on the connection layer, and the ninth via extends through the passivation layer, the insulating layer, and the gate insulating layer.

[0022] Optionally, the gate drive circuit includes two adjacent scan units, the circuit structures of which are mirror images of each other about a straight line perpendicular to the clock signal line.

[0023] Optionally, the two adjacent scanning units share the same connection line, which is connected to a low-level signal line.

[0024] On the other hand, this disclosure provides a display panel, including: the array substrate described above; and a second substrate opposite to the array substrate, wherein the second substrate includes a black matrix, the black matrix including a black matrix main body located in the peripheral region of the display panel, and an extension extending from the black matrix main body to at least a portion of the edge of the display panel, the extension including a partially perforated pattern. Attached Figure Description

[0025] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0026] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0027] Figure 2 is a schematic diagram showing the structure of a gate drive circuit according to some embodiments of the present disclosure.

[0028] Figure 3 is a circuit diagram showing the structure of a scanning unit of a gate driving circuit according to some embodiments of the present disclosure.

[0029] Figure 4 is a timing diagram illustrating the operation of a gate drive circuit according to some embodiments of the present disclosure.

[0030] Figure 5A is a schematic diagram showing the structure of the gate drive circuit in region Z1 of Figure 1.

[0031] Figure 5B is a schematic diagram showing the arrangement of the drive circuit depicted in Figure 5A.

[0032] Figure 5C is a schematic diagram showing the structure of the gate metal layer of the gate drive circuit depicted in Figure 5A.

[0033] Figure 5D is a schematic diagram showing the structure of the semiconductor material layer of the gate drive circuit depicted in Figure 5A.

[0034] Figure 5E is a schematic diagram showing the structure of the signal line layer of the gate drive circuit depicted in Figure 5A.

[0035] Figure 5F is a schematic diagram showing the via through which the gate drive circuit depicted in Figure 5A extends through the passivation layer.

[0036] Figure 5G is a schematic diagram showing the structure of the connection layer of the gate drive circuit depicted in Figure 5A.

[0037] Figure 6 is a cross-sectional view along line I-I' in Figure 5A.

[0038] Figure 7 is a circuit diagram showing the structure of a scanning cell according to the gate drive circuit in Figure 5A.

[0039] Figure 8 is a schematic diagram showing the structure of a scanning circuit according to some embodiments of the present disclosure.

[0040] Figure 9 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0041] Figure 10 is a circuit diagram showing the structure of a scanning unit of a gate driving circuit according to some embodiments of the present disclosure.

[0042] Figure 11A is a timing diagram illustrating the operation of a gate drive circuit according to some embodiments of the present disclosure.

[0043] Figure 11B shows a simulation diagram of the signal waveforms according to the gate drive circuit in Figure 10.

[0044] Figure 12A is a schematic diagram showing the structure of the gate drive circuit in region Z2 of Figure 1.

[0045] Figure 12B is a schematic diagram showing the arrangement of the drive circuit depicted in Figure 12A.

[0046] Figure 12C is a schematic diagram showing the structure of the gate metal layer of the gate drive circuit depicted in Figure 12A.

[0047] Figure 12D is a schematic diagram showing the structure of the semiconductor material layer of the gate drive circuit depicted in Figure 12A.

[0048] Figure 12E is a schematic diagram showing the structure of the signal line layer of the gate drive circuit depicted in Figure 12A.

[0049] Figure 12F is a schematic diagram showing the via through which the gate drive circuit depicted in Figure 12A extends through the passivation layer.

[0050] Figure 12G is a schematic diagram showing the structure of the connection layer of the gate drive circuit depicted in Figure 12A.

[0051] Figure 13A is a cross-sectional view along line II-II' in Figure 12A.

[0052] Figure 13B is a cross-sectional view along line III-III' in Figure 12A.

[0053] Figure 13C is a cross-sectional view along line IV-IV' in Figure 12A.

[0054] Figure 13D is a cross-sectional view along line V-V' in Figure 12A.

[0055] Figure 14 shows a comparison of the signal sources of the 11T1C gate drive circuit in Figure 5A and the 8T1C gate drive circuit in Figure 12A.

[0056] Figure 15 shows a comparison of the connection methods of the 11T1C gate drive circuit in Figure 5A and the 8T1C gate drive circuit in Figure 12A with the clock signal line.

[0057] Figure 16 shows a comparison of the 11T1C gate drive circuit in Figure 5A and the 8T1C gate drive circuit in Figure 12A in terms of signal line width and spacing.

[0058] Figure 17 shows a comparison of the connection methods between the 11T1C gate drive circuit in Figure 5A and the 8T1C gate drive circuit in Figure 12A and the gate lines.

[0059] Figure 18 shows the layout of the capacitor and the fourth transistor in the 8T1C gate drive circuit of Figure 12A.

[0060] Figure 19 is a circuit diagram showing the structure of a scanning unit of a gate driving circuit according to some embodiments of the present disclosure.

[0061] Figure 20 is a schematic diagram illustrating the structure of a black matrix on a second substrate according to some embodiments of the present disclosure. Detailed Implementation

[0062] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0063] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure. Referring to Figure 1, the array substrate is bonded to a flexible printed circuit board (FPC). The array substrate includes a ground wire GND, one end of which is connected to the FPC. The ground wire GND extends around the display area of ​​the array substrate on three sides of the array substrate, excluding the side connected to the FPC, and the other end of which is connected to the FPC. In some embodiments, the ground wire GND can be connected to traces (e.g., data lines) in the array substrate via a structure such as an electrostatic ring to prevent electrostatic damage to the array substrate.

[0064] The array substrate also includes a common electrode line Com, which is a closed trace surrounding the display area of ​​the array substrate and connected to the flexible printed circuit board (FPC). The common electrode line Com is connected to the common electrode of the array substrate, providing a voltage signal to the common electrode.

[0065] In the region between the ground line GND and the common electrode line Com, the array substrate includes a gate drive circuit. The output of this gate drive circuit is connected to the gate lines, thereby outputting a gate scan signal to the gate lines. In the embodiment shown in FIG1, the array substrate includes a gate drive circuit GOA1 and a gate drive circuit GOA2 located on opposite sides of the array substrate. The output of the gate drive circuit GOA1 is connected to the odd-numbered row gate lines G1, G3, ..., G(2n-1), ..., thereby outputting a gate drive signal to the odd-numbered row gate lines G1, G3, ..., G(2n-1), ... The output of the gate drive circuit GOA2 is connected to the even-numbered row gate lines G2, G4, ..., G(2n), ..., thereby outputting a gate drive signal to the odd-numbered row gate lines G2, G4, ..., G(2n), ...

[0066] Gate drive circuits GOA1 and GOA2 are structurally symmetrical about the centerline of the array substrate, for example, they have symmetrical circuit structures and their connected signal lines are also symmetrical. Taking gate drive circuit GOA1 as an example, its connected signal lines include: a frame start signal line STV1, which is configured to provide an input signal to the first scan unit of gate drive circuit GOA1; and a clock signal line CLK, which is configured to provide a clock signal to gate drive circuit GOA1.

[0067] The circuit structure of the gate drive circuit will be described in detail below.

[0068] Figure 2 is a schematic diagram illustrating the structure of a gate driving circuit according to some embodiments of the present disclosure. Referring to Figure 2, in some embodiments, the scanning circuit includes N stages. Each of the N stages includes a corresponding scanning unit. As shown in Figure 2, the scanning circuit includes a first scanning unit, a second scanning unit, a third scanning unit, a fourth scanning unit, ..., an Nth scanning unit. The N scanning units are configured to provide N gate scan signals to N rows of sub-pixels. In Figure 2, the N gate scan signals are represented as Output1, Output2, Output3, Output4, ..., OutputN. The nth scanning unit is configured to receive a frame start signal STV1 or an output signal from the output of a preceding scanning unit (e.g., the (n-1)th scanning unit, the (n-2)th scanning unit, or the (n-3)th scanning unit). As used herein, the term "preceding scanning unit" is not limited to the immediately preceding scanning unit (e.g., the (n-1)th scanning unit), but includes any suitable preceding scanning unit (e.g., the (n-2)th scanning unit or the (n-3)th scanning unit). In Figure 2, the first scanning unit is configured to receive the frame start signal STV1 as an input signal, the second scanning unit is configured to receive the output signal from the first scanning unit as an input signal Input2, the third scanning unit is configured to receive the output signal from the second scanning unit as an input signal Input3, the fourth scanning unit is configured to receive the output signal from the third scanning unit as an input signal Input4, and the Nth scanning unit is configured to receive the output signal from the (N-1)th scanning unit as an input signal InputN.

[0069] Referring to Figure 2, the nth scan unit is configured to receive an output signal from a subsequent scan unit (e.g., the (n+1)th scan unit, the (n+2)th scan unit, or the (n+3)th scan unit) as a reset signal. As used herein, the term "subsequent scan unit" is not limited to the immediately following scan unit (e.g., the (n+1)th scan unit), but includes any suitable subsequent scan unit (e.g., the (n+2)th scan unit or the (n+3)th scan unit). In Figure 2, the first scan unit is configured to receive an output signal from the second scan unit as a reset signal Reset1, the second scan unit is configured to receive an output signal from the third scan unit as a reset signal Reset2, the third scan unit is configured to receive an output signal from the fourth scan unit as a reset signal Reset3, and the fourth scan unit is configured to receive an output signal from the fifth scan unit as a reset signal Reset4.

[0070] In some embodiments, the scanning circuit can be operated in both forward and reverse scanning modes. Figure 2 illustrates the forward scanning mode of the scanning circuit.

[0071] Figure 3 is a circuit diagram illustrating the structure of a scanning unit of a gate driving circuit according to some embodiments of the present disclosure. Referring to Figure 3, in some embodiments, the scanning unit circuit is an 11T1C (i.e., 11 transistors and 1 capacitor) circuit, including: a first transistor M1, whose first electrode and gate are connected to the input terminal INPUT, and whose second electrode is connected to the pull-up node pu; a second transistor M2, whose first electrode is connected to the pull-up node pu, whose second electrode is connected to the low-level signal line VGL, and whose gate is connected to the reset terminal RESET; a third transistor M3, whose first electrode is connected to the clock signal line CLK, whose second electrode is connected to the output terminal OUTPUT, and whose gate is connected to the pull-up node pu; a fourth transistor M4, whose first electrode is connected to the pull-up node pu, whose second electrode is connected to the low-level signal line VGL, and whose gate is connected to the pre-frame reset signal line STV0; a fifth transistor M5, whose first electrode is connected to the high-level signal line VGH, whose second electrode is connected to the pull-down node pd, and whose gate is connected to the first electrode of the eighth transistor M8 and the second electrode of the ninth transistor M9; and a sixth transistor M6, whose first electrode is connected to the pull-down node pd, and whose second electrode is connected to the low-level signal line OUTPUT. The first transistor is connected to the pull-up node pu; the second transistor is connected to the low-level signal line VGL, and its gate is connected to the pre-frame reset signal line STV0; the third transistor is connected to the pull-up node pu; the fourth transistor is connected to the pull-up node pd; the fifth transistor is connected to the pull-up node pu; the sixth transistor is connected to the pull-up node pu; the seventh transistor is connected to the output terminal OUTPUT, the second electrode is connected to the low-level signal line VGL, and its gate is connected to the pre-frame reset signal line STV0; the seventh transistor is connected to the pull-up node pu, the first electrode is connected to the second electrode of the ninth transistor M9 and the gate of the fifth transistor M5, the second electrode is connected to the low-level signal line VGL, and its gate is connected to the pull-up node pd; the eleventh transistor is connected to the output terminal OUTPUT, the second electrode is connected to the low-level signal line VGL, and its gate is connected to the pull-down node pd; the seventh transistor is connected to the pull-up node pu, the second electrode is connected to the output terminal OUTPUT.

[0072] In the circuit shown in Figure 3, the channel width-to-length ratio of the sixth transistor M6 is much greater than that of the fifth transistor M5.

[0073] The transistors in the gate drive circuit are implemented as various types of transistors, such as all p-type transistors, all n-type transistors, or a combination of p-type and n-type transistors. Referring to Figure 3, all transistors are n-type transistors, such as polysilicon transistors. For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0074] In the circuit structure shown in Figure 3, the first transistor M1 forms the pull-up sub-circuit SC-PU; the second transistor M2 forms the pull-down sub-circuit SC-PD; the third transistor M3 and capacitor C1 form the output sub-circuit SC-OUT; the fourth transistor M4 and the seventh transistor M7 form the noise reduction sub-circuit SC-DE; and the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 form the control sub-circuit SC-CON.

[0075] The pull-up sub-circuit SC-PU is configured to set the potential of the pull-up node pu to an effective potential when the input terminal INPUT is a valid control signal.

[0076] The pull-down sub-circuit SC-PD is configured to set the potential of the pull-down node pd to an effective potential when the RESET terminal is a valid control signal.

[0077] The output sub-circuit SC-OUT is configured to output a clock signal to the output terminal OUTPUT when the potential of the pull-up node pu is set to an effective potential.

[0078] The noise reduction sub-circuit SC-DE is configured to set the potentials of the output terminal OUTPUT and the pull-up node pu to invalid potentials when the signal of the pre-frame reset signal line STV0 is a valid control signal.

[0079] The control sub-circuit SC-CON is configured to: set the potential of the pull-up node pd to an invalid potential when the potential of the pull-up node pu is valid; and set the potential of the pull-up node pu to an invalid potential when the potential of the pull-up node pd is valid. The control sub-circuit SC-CON is essentially an inverter.

[0080] Figure 4 is a timing diagram illustrating the operation of a gate drive circuit according to some embodiments of the present disclosure. Referring to Figures 3 and 4, the operation of the gate drive circuit includes a first stage t1, a second stage t2, and a third stage t3.

[0081] In the first stage t1 (pre-charge stage), the output terminal of the previous stage scanning unit is connected to the input terminal INPUT of the current stage scanning unit. The output signal G(n-1) of the previous stage scanning unit is a turn-on control signal, provided to the gate and first electrode of the first transistor M1, thereby turning on the first reset transistor M1 and allowing the output signal G(n-1) of the previous stage scanning unit to be transmitted from the first electrode of the first transistor M1 to the second electrode of the first transistor M1, and then to the pull-up node pu. The potential of the pull-up node pu rises, charging the capacitor C1 and turning on the sixth transistor M6 and the eighth transistor M8. The high-level signal provided by the high-level signal line VGH keeps the fifth transistor M5 and the ninth transistor M9 in the on state. At this time, since the channel width-to-length ratio of the sixth transistor M6 is much larger than that of the fifth transistor M5, the strong discharge capability of the sixth transistor M6 causes the potential of the pull-down node pd to drop rapidly. After the potential of the pull-down node pd drops, the tenth transistor M10 and the eleventh transistor M11 change from on to off. The output of the next-stage scanning unit is connected to the reset terminal RESET of the current-stage scanning unit. At this time, the output signal G(n+1) of the next-stage scanning unit is a cutoff control signal and is provided to the gate of the second transistor M2 to turn off the second reset transistor M2. Meanwhile, the high potential of the pull-up node pu turns on the third transistor M3. Therefore, the low-level signal of the clock signal line CLK is output from the output terminal OUTPUT of the current-stage scanning unit, making the output signal G(n) low.

[0082] In the second stage t2 (output stage), the output signal G(n-1) of the previous stage scan unit is a cutoff control signal, which is provided to the gate and first electrode of the first transistor M1, thereby turning off the first reset transistor M1. At this time, the high potential of the pull-up node pu keeps the third transistor M3 on, so the high-level signal of the clock signal line CLK is output from the output terminal OUTPUT of this stage scan unit, making the output signal G(n) high. Due to the bootstrap effect of capacitor C1, the potential of the pull-up node pu is raised, keeping the sixth transistor M6 and the eighth transistor M8 on, the pull-down node pd at a low potential, and the tenth transistor M10 and the eleventh transistor M11 off. The output signal of the next stage scan unit is G(n+1), which is a cutoff control signal, and is provided to the gate of the second transistor M2, so that the second reset transistor M2 is turned off.

[0083] In the third stage t3 (reset stage), the output signal G(n-1) of the previous stage scan unit is a cutoff control signal, which is provided to the gate and first electrode of the first transistor M1, thereby turning off the first reset transistor M1. The output signal G(n+1) of the next stage scan unit is a turn-on control signal, which is provided to the gate of the second transistor M2, causing the second reset transistor M2 to change from cutoff to turn-on. At this time, the potential of the pull-up node pu rapidly drops to the low-level potential of the low-level signal line VGL, causing the sixth transistor M6 and the eighth transistor M8 to turn off. The high-level signal provided by the high-level signal line VGH keeps the fifth transistor M5 and the ninth transistor M9 in the on state, causing the pull-down node pd to change from a low-level potential to a high-level potential. After the potential of the pull-down node pd rises, the tenth transistor M10 changes from cutoff to turn-on, so the pull-up node pu is electrically connected to the low-level signal line VGL, maintaining a low potential. After the potential of the pull-down node pd rises, the eleventh transistor M11 changes from cutoff to conduction, so the potential of the output terminal OUTPUT drops to the low potential provided by the low-level signal line VGL.

[0084] It can be seen that the gate drive circuits shown in Figures 3 and 4 adopt the forward scanning mode shown in Figure 2.

[0085] Figure 5A is a schematic diagram showing the structure of the gate drive circuit in region Z1 of Figure 1. Figure 5B is a schematic diagram showing the arrangement of the drive circuit depicted in Figure 5A. Figures 5A and 5B depict portions of the gate drive circuit with two adjacent scan cells (including SC1 and SC2). The two adjacent scan cells (including SC1 and SC2) have the same layout.

[0086] Figure 5C is a schematic diagram showing the structure of the gate metal layer of the gate drive circuit depicted in Figure 5A. Figure 5D is a schematic diagram showing the structure of the semiconductor material layer of the gate drive circuit depicted in Figure 5A. Figure 5E is a schematic diagram showing the structure of the signal line layer of the gate drive circuit depicted in Figure 5A. Figure 5F is a schematic diagram showing the vias extending through the passivation layer of the gate drive circuit depicted in Figure 5A. Figure 5G is a schematic diagram showing the structure of the connection layer of the gate drive circuit depicted in Figure 5A. Figure 6 is a cross-sectional view along line I-I' in Figure 5A.

[0087] Referring to Figures 5A to 5G and Figure 6, in some embodiments, the array substrate includes: a substrate BS; a gate metal layer Gate located on the substrate BS; a gate insulating layer GI located on the side of the gate metal layer Gate away from the substrate BS; a semiconductor material layer SML located on the side of the gate insulating layer GI away from the gate metal layer Gate; an insulating layer IN located on the side of the semiconductor material layer SML away from the gate insulating layer GI; a signal line layer SD located on the side of the insulating layer IN away from the semiconductor material layer SML; a passivation layer PVX located on the side of the signal line layer SD away from the insulating layer IN; and a connection layer CL located on the side of the passivation layer PVX away from the signal line layer SD.

[0088] Referring to Figures 1, 5A, 5C, and 6, in some embodiments, the gate metal layer includes a ground line GND, a frame start signal line STV1, a high-level signal line VGH, a seventh clock signal line CLK7, a fifth clock signal line CLK5, a third clock signal line CLK3, a first clock signal line CLK1, the gate M1-G of the first transistor M1, the gate M2-G of the second transistor M2, the gate M3-G of the third transistor M3, the gate M4-G of the fourth transistor M4, the gate M7-G of the seventh transistor M7, the gate M5-G of the fifth transistor M5, the gate M6-G of the sixth transistor M6, the gate M8-G of the eighth transistor M8, the gate M9-G of the ninth transistor M9, the gate M10-G of the tenth transistor M10, the gate M11-G of the eleventh transistor M11, the first electrode plate C1-1 of the capacitor C1, a frame pre-reset signal line STV0, a ​​first-level signal line VDD, a second-level signal line VSS, and a low-level signal line VGL.

[0089] It should be noted that the gate drive circuit shown in Figure 5A adopts a structure with eight clock signal lines. On the other side of the array substrate symmetrical to the Z1 region, the gate metal layer includes the eighth clock signal line CLK8, the sixth clock signal line CLK6, the fourth clock signal line CLK4, and the second clock signal line CLK2.

[0090] Various suitable electrode materials and manufacturing methods can be used to fabricate the gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the ground line GND, frame start signal line STV1, high-level signal line VGH, seventh clock signal line CLK7, fifth clock signal line CLK5, third clock signal line CLK3, first clock signal line CLK1, gate M1-G of first transistor M1, gate M2-G of second transistor M2, gate M3-G of third transistor M3, gate M4-G of fourth transistor M4, gate M7-G of seventh transistor M7, gate M5-G of fifth transistor M5, gate M6-G of sixth transistor M6, gate M8-G of eighth transistor M8, gate M9-G of ninth transistor M9, gate M10-G of tenth transistor M10, gate M11-G of eleventh transistor M11, first electrode plate C1-1 of capacitor C1, frame reset signal line STV0, first-level signal line VDD, second-level signal line VSS, and low-level signal line VGL are located on the same layer.

[0091] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, when ground line GND and frame start signal line STV0 are formed due to one or more steps of the same patterning process performed in the same material layer, ground line GND and frame start signal line STV0 are located in the same layer. In another example, ground line GND and frame start signal line STV0 can be formed in the same layer by simultaneously performing the steps of forming ground line GND and forming frame start signal line STV0. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0092] Referring to Figure 5C, the gates M3-G of the third transistor M3, M6-G of the sixth transistor M6, M8-G of the eighth transistor M8, and the first electrode plate C1-1 of capacitor C1 are connected to each other, forming part of an integral structure. The gates M4-G of the fourth transistor M4, M7-G of the seventh transistor M7, and the pre-frame reset signal line STV0 are connected to each other, forming part of an integral structure. The gates M10-G of the tenth transistor M10 and M11-G of the eleventh transistor M11 are connected to each other, forming part of an integral structure.

[0093] Referring to Figures 1, 5A, 5D, and 6, in some embodiments, the semiconductor material layer SML includes at least the active layer ACT1 of the first transistor M1, the active layer ACT2 of the second transistor M2, the active layer ACT3 of the third transistor M3, the active layer ACT4 of the fourth transistor M4, the active layer ACT7 of the seventh transistor M7, the active layer ACT5 of the fifth transistor M5, the active layer ACT6 of the sixth transistor M6, the active layer ACT8 of the eighth transistor M8, the active layer ACT9 of the ninth transistor M9, the active layer ACT10 of the tenth transistor M10, and the active layer ACT11 of the eleventh transistor M11. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer SML. Examples of semiconductor materials used to fabricate the semiconductor material layer SML include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0094] In Figure 5D, the active layer corresponding to the scan unit SC2 in Figure 5B is labeled with numbers, which indicate components of each of the multiple transistors in the gate drive circuit.

[0095] Optionally, the active layer ACT1 of the first transistor M1, the active layer ACT2 of the second transistor M2, the active layer ACT3 of the third transistor M3, the active layer ACT4 of the fourth transistor M4, the active layer ACT7 of the seventh transistor M7, the active layer ACT5 of the fifth transistor M5, the active layer ACT6 of the sixth transistor M6, the active layer ACT8 of the eighth transistor M8, the active layer ACT9 of the ninth transistor M9, the active layer ACT10 of the tenth transistor M10, and the active layer ACT11 of the eleventh transistor M11 are located on the same layer.

[0096] Optionally, the active layer ACT1 of the first transistor M1, the active layer ACT2 of the second transistor M2, the active layer ACT3 of the third transistor M3, the active layer ACT4 of the fourth transistor M4, the active layer ACT7 of the seventh transistor M7, the active layer ACT5 of the fifth transistor M5, the active layer ACT6 of the sixth transistor M6, the active layer ACT8 of the eighth transistor M8, the active layer ACT9 of the ninth transistor M9, the active layer ACT10 of the tenth transistor M10, and the active layer ACT11 of the eleventh transistor M11 are independent parts that are separate from each other.

[0097] Referring to Figures 1, 5A, 5E, and 6, in some embodiments, the signal line layer SD includes the first electrode M1-S and the second electrode M1-D of the first transistor M1, the first electrode M2-S and the second electrode M2-D of the second transistor M2, the first electrode M3-S and the second electrode M3-D of the third transistor M3, the first electrode M4-S and the second electrode M4-D of the fourth transistor M4, the first electrode M7-S and the second electrode M7-D of the seventh transistor M7, the first electrode M5-S of the fifth transistor M5, and the second electrode M6-D of the third transistor M4. Two electrodes M5-D, the first electrode M6-S and the second electrode M6-D of the sixth transistor M6, the first electrode M8-S and the second electrode M8-D of the eighth transistor M8, the first electrode M9-S and the second electrode M9-D of the ninth transistor M9, the first electrode M10-S and the second electrode M10-D of the tenth transistor M10, the first electrode M11-S and the second electrode M11-D of the eleventh transistor M11, the second electrode plate C1-2 of capacitor C1, gate line G(2n-1) and gate line G(2n+1).

[0098] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate signal line layers. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating signal line layers include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the signal line layer comprises multiple sublayers stacked together. In one example, the signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0099] Optionally, the first electrode M1-S and the second electrode M1-D of the first transistor M1, the first electrode M2-S and the second electrode M2-D of the second transistor M2, the first electrode M3-S and the second electrode M3-D of the third transistor M3, the first electrode M4-S and the second electrode M4-D of the fourth transistor M4, the first electrode M7-S and the second electrode M7-D of the seventh transistor M7, the first electrode M5-S and the second electrode M5-D of the fifth transistor M5, the first electrode M6-S and the second electrode M6-D of the sixth transistor M6, the first electrode M8-S and the second electrode M8-D of the eighth transistor M8, the first electrode M9-S and the second electrode M9-D of the ninth transistor M9, the first electrode M10-S and the second electrode M10-D of the tenth transistor M10, the first electrode M11-S and the second electrode M11-D of the eleventh transistor M11, the second electrode plate C1-2 of the capacitor C1, the gate line G(2n-1) and the gate line G(2n+1) are located on the same layer.

[0100] In some embodiments, the second electrode M3-D of the third transistor M3, the first electrode M7-S of the seventh transistor M7, the first electrode M11-S of the eleventh transistor M11, the second electrode plate C1-2 of the capacitor C1, and the gate line G(2n-1) are connected to each other to form part of an integral structure. The first electrode M8-S of the eighth transistor M8 and the second electrode M9-D of the ninth transistor M9 are connected to each other to form part of an integral structure. The second electrode M5-D of the fifth transistor M5 and the first electrode M6-S of the sixth transistor M6 are connected to each other to form part of an integral structure. The second electrode M1-D of the first transistor M1, the first electrode M2-S of the second transistor M2, and the first electrode M4-S of the fourth transistor M4 are connected to each other to form part of an integral structure. The second electrode M4-D of the fourth transistor M4, the second electrode M7-D of the seventh transistor M7, the second electrode M6-D of the sixth transistor M6, the second electrode M8-D of the eighth transistor M8, the second electrode M10-D of the tenth transistor M10, and the second electrode M11-D of the eleventh transistor M11 are connected to each other to form part of the overall structure.

[0101] Figure 5F depicts vias extending through the passivation layer PVX, including a first via V1 and a second via V2.

[0102] Referring to Figures 1, 5A, 5G, and 6, in some embodiments, the interconnect layer CL includes a plurality of interconnect pads for connecting the first and / or second electrodes of transistors in the signal line layer to corresponding signal lines in the gate metal layer. In one example, the interconnect layer CL may be located on the same layer as the common electrode layer in the display area of ​​the array substrate. In another example, the interconnect layer CL may be located on the same layer as the pixel electrode layer in the display area of ​​the array substrate.

[0103] In some embodiments, the first connection pad PAD1 connects the first clock signal line CLK1 to the first electrode M3-S of the third transistor. Referring to FIG6, in the gate drive circuit, the first connection pad PAD1 is connected to the first clock signal line CLK1 through a second via V2 and to the first electrode M3-S of the third transistor M3 through a first via V1. In one example, the first via V1 extends through the passivation layer PVX. In another example, the second via V2 extends through the passivation layer PVX, the insulating layer IN, and the gate insulating layer GI.

[0104] Figure 7 is a circuit diagram showing the structure of a scanning unit according to the gate drive circuit in Figure 5A. Referring to Figure 7, in some embodiments, the scanning unit circuit is an 11T1C (i.e., 11 transistors and 1 capacitor) circuit, including: a first transistor M1, whose first electrode is connected to the first level signal line VDD, its gate is connected to the input terminal INPUT, and its second electrode is connected to the pull-up node pu; a second transistor M2, whose first electrode is connected to the pull-up node pu, its second electrode is connected to the second level signal line VSS, and its gate is connected to the reset terminal RESET; a third transistor M3, whose first electrode is connected to the clock signal line CLK, its second electrode is connected to the output terminal OUTPUT, and its gate is connected to the pull-up node pu; a fourth transistor M4, whose first electrode is connected to the pull-up node pu, its second electrode is connected to the low level signal line VGL, and its gate is connected to the pre-frame reset signal line STV0; a fifth transistor M5, whose first electrode is connected to the high level signal line VGH, its second electrode is connected to the pull-down node pd, and its gate is connected to the first electrode of the eighth transistor M8 and the second electrode of the ninth transistor M9; a sixth transistor M6, whose first electrode is connected to the pull-down node pd, its second electrode is connected to the second level signal line VSS, and its gate is connected to the reset terminal RESET; a third transistor M3, whose first electrode is connected to the clock signal line CLK, its second electrode is connected to the output terminal OUTPUT, and its gate is connected to the pull-up node pu; a fourth transistor M4, whose first electrode is connected to the pull-up node pu, its second electrode is connected to the low level signal line VGL, and its gate is connected to the pre-frame reset signal line STV0; a fifth transistor M5, whose first electrode is connected to the high level signal line VGH, its second electrode is connected to the pull-down node pd, and its gate is connected to the first electrode of the eighth The first electrode of the seventh transistor M7 is connected to the low-level signal line VGL, and its gate is connected to the pull-up node pu. The second electrode of the seventh transistor M7 is connected to the output terminal OUTPUT, and its gate is connected to the low-level signal line VGL. The gate of the seventh transistor M8 is connected to the pre-frame reset signal line STV0. The first electrode of the eighth transistor M8 is connected to the second electrode of the ninth transistor M9 and the gate of the fifth transistor M5. The second electrode of the eighth transistor M8 is connected to the low-level signal line VGL, and its gate is connected to the pull-up node pu. The first electrode and gate of the ninth transistor M9 are connected to the high-level signal line VGH, and its second electrode is connected to the first electrode of the eighth transistor M8 and the gate of the fifth transistor M5. The first electrode of the tenth transistor M10 is connected to the pull-up node pu, and its second electrode is connected to the low-level signal line VGL. The gate of the tenth transistor M10 is connected to the pull-up node pu, and its second electrode is connected to the low-level signal line VGL. The gate of the tenth transistor M10 is connected to the pull-up node pu, and its second electrode is connected to the pull-down node pd. The first electrode of the eleventh transistor M11 is connected to the output terminal OUTPUT, and its second electrode is connected to the low-level signal line VGL. The gate of the eleventh transistor M11 is connected to the pull-down node pd. The first electrode plate of the capacitor C1 is connected to the pull-up node pu, and its second electrode plate is connected to the output terminal OUTPUT.

[0105] In the circuit shown in Figure 7, the channel width-to-length ratio of the sixth transistor M6 is much greater than that of the fifth transistor M5.

[0106] In the circuit structure shown in Figure 7, the first transistor M1 forms the pull-up sub-circuit SC-PU; the second transistor M2 forms the pull-down sub-circuit SC-PD; the third transistor M3 and capacitor C1 form the output sub-circuit SC-OUT; the fourth transistor M4 and the seventh transistor M7 form the noise reduction sub-circuit SC-DE; and the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 form the control sub-circuit SC-CON.

[0107] The scanning unit shown in Figure 7 has two operating modes: forward scanning mode and reverse scanning mode. When the first level signal line VDD provides a high-level signal and the second level signal line VSS provides a low-level signal, the frame start signal STV1 is provided to the input terminal INPUT of the first scanning unit. The scanning unit shown in Figure 7 is in forward scanning mode, and its operating timing is exactly the same as that of the scanning unit shown in Figure 3. When the first level signal line VDD provides a low-level signal and the second level signal line VSS provides a high-level signal, the frame start signal STV1 is provided to the reset terminal RESET of the last scanning unit (e.g., the Nth scanning unit). The scanning unit shown in Figure 7 is in reverse scanning mode.

[0108] Figure 8 is a schematic diagram illustrating the structure of a scanning circuit according to some embodiments of the present disclosure. Figure 8 shows a reverse scanning mode of the scanning circuit. Referring to Figure 8, the nth scanning unit is configured to receive a start signal SS or an output signal from the output terminal of a subsequent scanning unit (e.g., the (n+1)th scanning unit, the (n+2)th scanning unit, or the (n+3)th scanning unit). In Figure 8, the Nth scanning unit is configured to receive the start signal SS as an input signal, the 4th scanning unit is configured to receive the output signal from the 5th scanning unit as an input signal Input4, the 3rd scanning unit is configured to receive the output signal from the 4th scanning unit as an input signal Input3, the 2nd scanning unit is configured to receive the output signal from the 3rd scanning unit as an input signal Input2, and the 1st scanning unit is configured to receive the output signal from the 2nd scanning unit as an input signal Input1.

[0109] Referring to Figure 8, in the reverse scan mode, the nth scan unit is configured to receive the output signal from the preceding scan unit (e.g., the (n-1)th scan unit, the (n-2)th scan unit, or the (n-3)th scan unit) as a reset signal. In Figure 8, the second scan unit is configured to receive the output signal from the first scan unit as a reset signal Reset2, the third scan unit is configured to receive the output signal from the second scan unit as a reset signal Reset3, the fourth scan unit is configured to receive the output signal from the third scan unit as a reset signal Reset4, and the fifth scan unit is configured to receive the output signal from the fourth scan unit as a reset signal Reset5.

[0110] In the aforementioned 11T1C gate drive circuit, the inventors of this disclosure have discovered the following problems: the aforementioned gate drive circuit is difficult to apply to extremely narrow bezel applications, such as wearable products; furthermore, the power consumption of the aforementioned gate drive circuit needs to be further reduced.

[0111] Therefore, this disclosure particularly provides an array substrate and display panel that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate comprising: a clock signal line having a clock signal line body extending along a first direction and a first connection portion extending away from the clock signal line body along a second direction, wherein the second direction intersects the first direction; and a gate driving circuit including a transistor connected to the clock signal line, wherein a connection electrode of the transistor connected to the clock signal line includes a second connection portion, wherein the orthographic projection of the first connection portion on a substrate and the orthographic projection of the second connection portion on the substrate at least partially overlap each other along the first direction.

[0112] Figure 9 is a plan view of an array substrate according to some embodiments of the present disclosure. Referring to Figure 9, the array substrate is bonded to a flexible printed circuit board (FPC). The array substrate includes a ground wire GND, one end of which is connected to the FPC. The ground wire GND extends around the display area of ​​the array substrate on three sides of the array substrate, excluding the side connected to the FPC, and the other end of which is connected to the FPC. In some embodiments, the ground wire GND can be connected to traces (e.g., data lines) in the array substrate via a structure such as an electrostatic ring to prevent electrostatic damage to the array substrate.

[0113] The array substrate also includes a common electrode line Com, which is a closed trace surrounding the display area of ​​the array substrate and connected to the flexible printed circuit board (FPC). The common electrode line Com is connected to the common electrode of the array substrate, providing a voltage signal to the common electrode.

[0114] In the region between the ground line GND and the common electrode line Com, the array substrate includes a gate drive circuit. The output of this gate drive circuit is connected to the gate lines, thereby outputting a gate scan signal to the gate lines. In the embodiment shown in FIG9, the array substrate includes a gate drive circuit GOA1 and a gate drive circuit GOA2 located on both sides of the array substrate. The output of the gate drive circuit GOA1 is connected to the odd-numbered row gate lines G1, G3, ..., G(2n-1), ..., thereby outputting a gate drive signal to the odd-numbered row gate lines G1, G3, ..., G(2n-1), ... The output of the gate drive circuit GOA2 is connected to the even-numbered row gate lines G2, G4, ..., G(2n), ..., thereby outputting a gate drive signal to the odd-numbered row gate lines G2, G4, ..., G(2n), ...

[0115] Gate drive circuits GOA1 and GOA2 are structurally symmetrical about the centerline of the array substrate, for example, they have symmetrical circuit structures and their connected signal lines are also symmetrical. Taking gate drive circuit GOA1 as an example, its connected signal lines include: a frame start signal line STV1, which is configured to provide an input signal to the first scan unit of gate drive circuit GOA1; and a clock signal line CLK, which is configured to provide a clock signal to gate drive circuit GOA1.

[0116] The circuit structure of the gate drive circuit will be described in detail below.

[0117] Figure 10 is a circuit diagram illustrating the structure of a scanning unit of a gate driving circuit according to some embodiments of the present disclosure. Referring to Figure 3, in some embodiments, the scanning unit circuit is an 8T1C (i.e., 8 transistors and 1 capacitor) circuit, including: a first transistor M1, whose first electrode and gate are connected to the input terminal INPUT, and whose second electrode is connected to the pull-up node PU; a second transistor M2, whose first electrode is connected to the pull-up node PU, whose second electrode is connected to the low-level signal line VGL, and whose gate is connected to the reset terminal RESET; a third transistor M3, whose first electrode is connected to the clock signal line CLK, whose second electrode is connected to the output terminal OUTPUT, and whose gate is connected to the pull-up node PU; and a fourth transistor M4, whose first electrode is connected to the pull-up node PU, whose second electrode is connected to the low-level signal line VGL, and whose gate is connected to the pre-frame reset signal line ST. V0; the fifth transistor M5, whose first electrode and gate are connected to the inverting clock signal line CLK_B, and whose second electrode is connected to the pull-down node PD; the sixth transistor M6, whose first electrode is connected to the pull-down node PD, whose second electrode is connected to the low-level signal line VGL, and whose gate is connected to the pull-up node PU; the tenth transistor M10, whose first electrode is connected to the pull-up node PU, whose second electrode is connected to the low-level signal line VGL, and whose gate is connected to the pull-down node PD; the eleventh transistor M11, whose first electrode is connected to the output terminal OUTPUT, whose second electrode is connected to the low-level signal line VGL, and whose gate is connected to the pull-down node PD; capacitor C0, whose first electrode plate is connected to the pull-up node PU, and whose second electrode plate is connected to the output terminal OUTPUT.

[0118] In the circuit shown in Figure 10, the channel width-to-length ratio of the sixth transistor M6 is much greater than that of the fifth transistor M5.

[0119] The transistors in the gate drive circuit are implemented as various types of transistors, such as all p-type transistors, all n-type transistors, or a combination of p-type and n-type transistors. Referring to Figure 3, all transistors are n-type transistors, such as polysilicon transistors. For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0120] In the circuit structure shown in Figure 10, the first transistor M1 forms the pull-up sub-circuit SC-PU; the second transistor M2 forms the pull-down sub-circuit SC-PD; the third transistor M3 and capacitor C0 form the output sub-circuit SC-OUT; the fourth transistor M4 forms the noise reduction sub-circuit SC-DE; and the fifth transistor M5, the sixth transistor M6, the tenth transistor M10, and the eleventh transistor M11 form the control sub-circuit SC-CON.

[0121] The pull-up sub-circuit SC-PU is configured to set the potential of the pull-up node PU to an effective potential when the input terminal INPUT is a valid control signal.

[0122] The pull-down sub-circuit SC-PD is configured to set the potential of the pull-down node PD to an effective potential when the RESET terminal is a valid control signal.

[0123] The output sub-circuit SC-OUT is configured to output a clock signal to the output terminal OUTPUT when the potential of the pull-up node PU is set to an effective potential.

[0124] The noise reduction sub-circuit SC-DE is configured to set the potentials of the output terminal OUTPUT and the pull-up node PU to invalid potentials when the signal of the pre-frame reset signal line STV0 is a valid control signal.

[0125] The control sub-circuit SC-CON is configured to: set the potential of the pull-up node PD to an invalid potential when the potential of the pull-up node PU is valid; and set the potential of the pull-up node PU to an invalid potential when the potential of the pull-up node PD is valid. The control sub-circuit SC-CON is essentially an inverter.

[0126] Figure 11A is a timing diagram illustrating the operation of a gate drive circuit according to some embodiments of the present disclosure. Referring to Figures 10 and 11A, the operation of the gate drive circuit includes a first stage t1, a second stage t2, and a third stage t3.

[0127] In the first stage t1 (pre-charge stage), the output of the previous stage scan unit is connected to the input INPUT of the current stage scan unit. The output signal G(n-1) of the previous stage scan unit is a turn-on control signal, provided to the gate and first electrode of the first transistor M1, thereby turning on the first reset transistor M1 and allowing the output signal G(n-1) of the previous stage scan unit to be transmitted from the first electrode of the first transistor M1 to the second electrode of the first transistor M1, and then to the pull-up node PU. The potential of the pull-up node PU rises, charging the capacitor C0 and turning on the sixth transistor M6. The high-level signal provided by the inverting clock signal line CLK_B turns on the fifth transistor M5. At this time, since the channel width-to-length ratio of the sixth transistor M6 is much larger than that of the fifth transistor M5, the strong discharge capability of the sixth transistor M6 causes the potential of the pull-down node pd to drop rapidly. After the potential of the pull-down node PD drops, the tenth transistor M10 and the eleventh transistor M11 change from being on to being off. The output of the next-stage scanning unit is connected to the reset terminal RESET of the current-stage scanning unit. At this time, the output signal G(n+1) of the next-stage scanning unit is a cutoff control signal and is provided to the gate of the second transistor M2 to turn off the second reset transistor M2. Meanwhile, the high potential of the pull-up node PU turns on the third transistor M3. Therefore, the low-level signal of the clock signal line CLK is output from the output terminal OUTPUT of the current-stage scanning unit, making the output signal G(n) low.

[0128] In the second stage t2 (output stage), the output signal G(n-1) of the previous stage scan unit is a cutoff control signal, provided to the gate and first electrode of the first transistor M1, thereby turning off the first reset transistor M1. At this time, the high potential of the pull-up node PU keeps the third transistor M3 on, so the high-level signal of the clock signal line CLK is output from the output terminal OUTPUT of this stage scan unit, making the output signal G(n) high. Due to the bootstrap effect of the capacitor C0, the potential of the pull-up node PU is raised, keeping the sixth transistor M6 on. The low-level signal provided by the inverted clock level signal line CLK_B turns off the fifth transistor M5. At this time, the pull-down node PD remains at a low potential, and the tenth transistor M10 and the eleventh transistor M11 remain off. The output signal G(n+1) of the next stage scan unit is a cutoff control signal, provided to the gate of the second transistor M2, so that the second reset transistor M2 turns off.

[0129] In the third stage t3 (reset stage), the output signal G(n-1) of the previous stage scan unit is a cutoff control signal, which is provided to the gate and first electrode of the first transistor M1, thereby turning off the first reset transistor M1. The output signal G(n+1) of the next stage scan unit is a turn-on control signal, which is provided to the gate of the second transistor M2, causing the second reset transistor M2 to change from cutoff to turn-on. At this time, the potential of the pull-up node PU rapidly decreases to the low-level potential of the low-level signal line VGL, causing the sixth transistor M6 to turn off. The high-level signal provided by the inverting clock signal line CLK_B turns on the fifth transistor M5, causing the pull-down node PD to change from a low-level potential to a high-level potential. After the potential of the pull-down node PD rises, the tenth transistor M10 changes from cutoff to turn-on, so the pull-up node PU is electrically connected to the low-level signal line VGL, maintaining a low potential. After the potential of the pull-down node PD rises, the eleventh transistor M11 changes from cutoff to turn-on, so the potential of the output terminal OUTPUT decreases to the low potential provided by the low-level signal line VGL.

[0130] It can be seen that the gate drive circuits shown in Figures 10 and 11A adopt the forward scanning mode shown in Figure 2.

[0131] Figure 11B shows a simulation of the signal waveforms based on the gate drive circuit in Figure 10. As shown in Figure 11B, the signal waveforms of the 8T1C gate drive circuit in Figure 10 are temperature-dependent. Figure 11B shows the waveforms of the pull-up node PU, pull-down node PD, and output terminal OUTPUT at high temperature, room temperature, and low temperature, respectively. From Figure 11B, it can be seen that the gate drive circuit operates more stably at high temperatures.

[0132] Figure 12A is a schematic diagram showing the structure of the gate drive circuit in region Z2 of Figure 1. Figure 12B is a schematic diagram showing the arrangement of the drive circuit depicted in Figure 12A. Figures 12A and 12B depict a portion of the gate drive circuit with two adjacent scan units (including SC1 and SC2). The layout of the two adjacent scan units (including SC1 and SC2) is mirror-symmetrical about a line perpendicular to the clock signal line.

[0133] Figure 12C is a schematic diagram showing the structure of the gate metal layer of the gate drive circuit depicted in Figure 12A. Figure 12D is a schematic diagram showing the structure of the semiconductor material layer of the gate drive circuit depicted in Figure 12A. Figure 12E is a schematic diagram showing the structure of the signal line layer of the gate drive circuit depicted in Figure 12A. Figure 12F is a schematic diagram showing the vias extending through the passivation layer of the gate drive circuit depicted in Figure 12A. Figure 12G is a schematic diagram showing the structure of the connection layer of the gate drive circuit depicted in Figure 12A. Figure 13A is a cross-sectional view along line II-II' in Figure 12A. Figure 13B is a cross-sectional view along line III-III' in Figure 12A. Figure 13C is a cross-sectional view along line IV-IV' in Figure 12A. Figure 13D is a cross-sectional view along line V-V' in Figure 12A.

[0134] Referring to Figures 12A to 12G and Figures 13A to 13D, in some embodiments, the array substrate includes: a substrate BS; a gate metal layer Gate located on the substrate BS; a gate insulating layer GI located on the side of the gate metal layer Gate away from the substrate BS; a semiconductor material layer SML located on the side of the gate insulating layer GI away from the gate metal layer Gate; an insulating layer IN located on the side of the semiconductor material layer SML away from the gate insulating layer GI; a signal line layer SD located on the side of the insulating layer IN away from the semiconductor material layer SML; a passivation layer PVX located on the side of the signal line layer SD away from the insulating layer IN; and a connection layer CL located on the side of the passivation layer PVX away from the signal line layer SD.

[0135] Referring to Figures 1, 12A, 12C, and 13A to 13D, in some embodiments, the gate metal layer includes a ground line GND, a frame start signal line STV1, a high-level signal line VGH, a third clock signal line CLK3, a first clock signal line CLK1, the gate M1-G of the first transistor M1, the gate M2-G of the second transistor M2, the gate M3-G of the third transistor M3, the gate M4-G of the fourth transistor M4, the gate M5-G of the fifth transistor M5, the gate M6-G of the sixth transistor M6, the gate M10-G of the tenth transistor M10, the gate M11-G of the eleventh transistor M11, the first portion C0-1a of the first electrode plate of capacitor C0, the frame pre-reset signal line STV0, the low-level signal line VGL, gate line G(2n-1), and gate line G(2n+1). Both gate line G(2n-1) and gate line G(2n+1) have input terminals, and the input terminal G-IN of gate line G(2n-1) is shown in Figure 12C.

[0136] It should be noted that the gate drive circuit shown in Figure 12A adopts a structure with four clock signal lines. On the other side of the array substrate symmetrical to the Z2 region, the gate metal layer includes a fourth clock signal line CLK4 and a second clock signal line CLK2.

[0137] Various suitable electrode materials and manufacturing methods can be used to fabricate the gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0138] Optionally, the ground line GND, frame start signal line STV1, high-level signal line VGH, third clock signal line CLK3, first clock signal line CLK1, gate M1-G of first transistor M1, gate M2-G of second transistor M2, gate M3-G of third transistor M3, gate M4-G of fourth transistor M4, gate M5-G of fifth transistor M5, gate M6-G of sixth transistor M6, gate M10-G of tenth transistor M10, gate M11-G of eleventh transistor M11, first electrode plate C0-1 of capacitor C0, frame reset signal line STV0, low-level signal line VGL, gate line G(2n-1), and gate line G(2n+1) are located on the same layer.

[0139] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, when ground line GND and frame start signal line STV0 are formed due to one or more steps of the same patterning process performed in the same material layer, ground line GND and frame start signal line STV0 are located in the same layer. In another example, ground line GND and frame start signal line STV0 can be formed in the same layer by simultaneously performing the steps of forming ground line GND and forming frame start signal line STV0. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0140] Referring to Figure 12C, the gate M3-G of the third transistor M3, the gate M6-G of the sixth transistor M6, and the first electrode plate C0-1 of the capacitor C0 are connected to each other, forming part of the overall structure. The gate M4-G of the fourth transistor M4 and the pre-frame reset signal line STV0 are connected to each other, forming part of the overall structure. The gate M10-G of the tenth transistor M10 and the gate M11-G of the eleventh transistor M11 are connected to each other, forming part of the overall structure.

[0141] In some embodiments, a clock signal line has a main body extending along a first direction and a protrusion extending away from the main body along a second direction, wherein the second direction intersects the first direction. Referring to FIG12C, a first clock signal line CLK1 has a main body extending along the first direction CLK1-B and a protrusion extending away from the main body CLK1-B along a second direction CLK1-T, wherein the second direction intersects the first direction. A third clock signal line CLK3 has a main body extending along the first direction CLK3-B and a protrusion extending away from the main body CLK3-B along a second direction CLK3-T.

[0142] Referring to Figures 1, 12A, 12D, and 13A to 13D, in some embodiments, the semiconductor material layer SML includes at least the active layer ACT1 of the first transistor M1, the active layer ACT2 of the second transistor M2, the active layer ACT3 of the third transistor M3, the active layer ACT4 of the fourth transistor M4, the active layer ACT5 of the fifth transistor M5, the active layer ACT6 of the sixth transistor M6, the active layer ACT10 of the tenth transistor M10, and the active layer ACT11 of the eleventh transistor M11. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer SML. Examples of semiconductor materials used to fabricate the semiconductor material layer SML include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0143] In Figure 12D, the active layer corresponding to the scan cell SC2 in Figure 12B is labeled with numbers, which indicate components of each of the multiple transistors in the gate drive circuit.

[0144] Optionally, the active layer ACT1 of the first transistor M1, the active layer ACT2 of the second transistor M2, the active layer ACT3 of the third transistor M3, the active layer ACT4 of the fourth transistor M4, the active layer ACT5 of the fifth transistor M5, the active layer ACT6 of the sixth transistor M6, the active layer ACT10 of the tenth transistor M10, and the active layer ACT11 of the eleventh transistor M11 are located on the same layer.

[0145] Optionally, the active layer ACT1 of the first transistor M1, the active layer ACT2 of the second transistor M2, the active layer ACT3 of the third transistor M3, the active layer ACT4 of the fourth transistor M4, the active layer ACT5 of the fifth transistor M5, the active layer ACT6 of the sixth transistor M6, the active layer ACT10 of the tenth transistor M10, and the active layer ACT11 of the eleventh transistor M11 are independent parts that are separate from each other.

[0146] Referring to Figures 1, 12A, 12E, and 13A to 13D, in some embodiments, the signal line layer SD includes the first electrode M1-S and the second electrode M1-D of the first transistor M1, the first electrode M2-S and the second electrode M2-D of the second transistor M2, the first electrode M3-S and the second electrode M3-D of the third transistor M3, the first electrode M4-S and the second electrode M4-D of the fourth transistor M4, the first electrode M5-S and the second electrode M5-D of the fifth transistor M5, the first electrode M6-S and the second electrode M6-D of the sixth transistor M6, the first electrode M10-S and the second electrode M10-D of the tenth transistor M10, the first electrode M11-S and the second electrode M11-D of the eleventh transistor M11, the second electrode plate C0-2 of the capacitor C0, and the common electrode line Com.

[0147] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate signal line layers. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating signal line layers include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the signal line layer comprises multiple sublayers stacked together. In one example, the signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0148] Optionally, the first electrode M1-S and the second electrode M1-D of the first transistor M1, the first electrode M2-S and the second electrode M2-D of the second transistor M2, the first electrode M3-S and the second electrode M3-D of the third transistor M3, the first electrode M4-S and the second electrode M4-D of the fourth transistor M4, the first electrode M5-S and the second electrode M5-D of the fifth transistor M5, the first electrode M6-S and the second electrode M6-D of the sixth transistor M6, the first electrode M10-S and the second electrode M10-D of the tenth transistor M10, the first electrode M11-S and the second electrode M11-D of the eleventh transistor M11, the second electrode plate C0-2 of the capacitor C0, and the common electrode line Com are located on the same layer.

[0149] In some embodiments, the second electrode M3-D of the third transistor M3, the first electrode M11-S of the eleventh transistor M11, and the second electrode plate C0-2 of the capacitor C0 are connected to each other to form part of an integral structure. The second electrode M5-D of the fifth transistor M5 and the first electrode M6-S of the sixth transistor M6 are connected to each other to form part of an integral structure. The second electrode M1-D of the first transistor M1, the first electrode M2-S of the second transistor M2, and the first electrode M4-S of the fourth transistor M4 are connected to each other to form part of an integral structure. The second electrodes M2-D of the second transistor M2, M4-D of the fourth transistor M4, M6-D of the sixth transistor M6, M10-D of the tenth transistor M10, and M11-D of the eleventh transistor M11 in two adjacent scanning units (i.e., SC1 and SC2 in FIG. 12B) are connected to each other to form part of an integral structure.

[0150] In some embodiments, as shown in FIG12E, the second electrode M3-D of the third transistor M3, the first electrode M11-S of the eleventh transistor M11, and the second electrode plate C0-2 of the capacitor C0 form an integral structure. The end of this integral structure near the common signal line Com is the output terminal OUTPUT of this scanning unit.

[0151] In some embodiments, as shown in FIG12E, the second electrode M2-D of the second transistor M2, the second electrode M4-D of the fourth transistor M4, the second electrode M6-D of the sixth transistor M6, the second electrode M10-D of the tenth transistor M10, and the second electrode M11-D of the eleventh transistor M11 in two adjacent scan units (i.e., SC1 and SC2 in FIG12B) are all connected to the same connection line C-Line, which is connected to the low-level signal line VGL. That is, the two adjacent scan units (including SC1 and SC2) share the same connection line C-Line. As shown in FIG12E, the structure of the two adjacent scan units (including SC1 and SC2) located in the signal line layer is mirror-symmetrical about the center line of the connection line C-Line.

[0152] In some embodiments, the layout of two adjacent scanning units (including SC1 and SC2) is mirror-symmetrical about the center line of the connecting line C-Line.

[0153] In some embodiments, the gate drive circuit includes a transistor connected to a clock signal line, and the connection electrode of the transistor connected to the clock signal line includes a second connection portion. As shown in FIG12E, the first electrode M3-D of the third transistor M3 has a connection portion M3-DC; the first electrode M5-D of the fifth transistor M5 has a connection portion M5-DC.

[0154] Figure 12F depicts vias extending through the passivation layer PVX, including via V3, V4, V5, V6, V7, V8, and V9.

[0155] Referring to Figures 1, 12A, 12G, and 13A to 13D, in some embodiments, the connection layer CL includes a plurality of connection pads for connecting the first and / or second electrodes of transistors in the signal line layer to corresponding signal lines in the gate metal layer. In one example, the connection layer CL may be located on the same layer as the common electrode layer in the display area of ​​the array substrate. In another example, the connection layer CL may be located on the same layer as the pixel electrode layer in the display area of ​​the array substrate. In the example shown in Figure 12G, the connection layer CL includes a first connection pad PAD1, a second connection pad PAD2, a third connection pad PAD3, and a second portion C0-2b of the capacitor first electrode plate.

[0156] In some embodiments, as shown in FIG13A, the first connection pad PAD1 connects the first clock signal line CLK1 to the first electrode M3-S of the third transistor. Referring to FIG13A, in the gate drive circuit, the first connection pad PAD1 is connected to the protrusion CLK1-T of the first clock signal line CLK1 through a fourth via V4, and to the connection portion M3-SC of the first electrode M3-S of the third transistor M3 through a third via V3. In one example, the third via V3 extends through the passivation layer PVX. In another example, the fourth via V4 extends through the passivation layer PVX, the insulating layer IN, and the gate insulating layer GI. As can be seen from FIG12A, the orthographic projection of the protrusion CLK1-T of the first clock signal line CLK1 on the substrate BS at least partially overlaps with the orthographic projection of the connection portion M3-SC of the first electrode M3-S of the third transistor M3 on the substrate BS along the extension direction (first direction) of the main body portion CLK1-B of the first clock signal line CLK1.

[0157] In some embodiments, as shown in FIG13B, the second connection pad PAD2 connects the third clock signal line CLK3 to the first electrode M5-S of the fifth transistor. Referring to FIG13A, in the gate drive circuit, the second connection pad PAD2 is connected to the protrusion CLK3-T of the third clock signal line CLK3 through a sixth via V6, and to the connection portion M3-SC of the first electrode M5-S of the fifth transistor M5 through a fifth via V5. In one example, the fifth via V5 extends through the passivation layer PVX. In another example, the sixth via V6 extends through the passivation layer PVX, the insulating layer IN, and the gate insulating layer GI. As can be seen from FIG12A, the orthographic projection of the protrusion CLK3-T of the third clock signal line CLK3 on the substrate BS at least partially overlaps with the orthographic projection of the connection portion M5-SC of the first electrode M5-S of the fifth transistor M5 on the substrate BS along the extension direction (first direction) of the main body portion CLK3-B of the third clock signal line CLK3.

[0158] In some embodiments, as shown in FIG13C, the third connection pad PAD1 connects the output terminal OUTPUT of the scanning unit to the input terminal G-IN of the corresponding gate line. Referring to FIG13A, in the gate drive circuit, the third connection pad PAD3 is connected to the input terminal G-IN of the gate line through the eighth via V8 and to the output terminal OUTPUT of the scanning unit through the seventh via V7. In one example, the seventh via V7 extends through the passivation layer PVX. In another example, the eighth via V8 extends through the passivation layer PVX, the insulating layer IN, and the gate insulating layer GI. As can be seen from FIG12A, the orthographic projection of the output terminal OUTPUT of the scanning unit on the substrate BS at least partially overlaps with the orthographic projection of the input terminal G-IN of the corresponding gate line on the substrate BS along the extension direction (first direction) of the main body portion CLK1-B of the first clock signal line CLK1 or the main body portion CLK3-B of the third clock signal line CLK3.

[0159] In some embodiments, as shown in FIG13D, capacitor C0 includes a first electrode plate, a first portion C0-1a, a second portion C0-1b, and a second electrode plate C0-2, wherein the second electrode plate C0-2 is located between the first portion C0-1a and the second portion C0-1b. Referring to FIG13A, in the gate drive circuit, the first portion C0-1a of the first electrode plate is connected to the second portion C0-1b of the first electrode plate through a ninth via V9, such that the first portion C0-1a and the second portion C0-1b together constitute the first electrode plate of capacitor C0. As can be seen from FIG13D, the first portion C0-1a of the first electrode plate is located in the gate metal layer Gate, the second electrode plate C0-2 is located in the signal line layer SD, the second portion C0-1b of the first electrode plate is located in the connection layer CL, and the ninth via V9 extends through the passivation layer PVX, the insulating layer IN, and the gate insulating layer GI.

[0160] The circuit diagram of a scanning unit of the gate drive circuit in Figure 12A is shown in Figure 10. It can be seen that the gate drive circuit in Figure 12A is a forward scanning circuit.

[0161] Figure 14 shows a comparison of the signal sources of the 11T1C gate drive circuit in Figure 5A and the 8T1C gate drive circuit in Figure 12A. As shown in Figure 14, compared to the 11T1C gate drive circuit, the 8T1C gate drive circuit reduces the number of high-level signal lines VGH in its input signal source. As shown in Figure 14, the high-level signal line VGH has rising and falling edges before and after the effective level of the pre-frame reset signal STV0. Therefore, reducing the number of high-level signal lines VGH can reduce the total number of signal source transitions. Since the power consumption of the gate drive circuit is positively correlated with the number of signal source transitions, the power consumption can be reduced.

[0162] Both the 11T1C gate drive circuit in Figure 3 and the 8T1C gate drive circuit in Figure 10 employ a forward scanning mode. Comparing the 11T1C gate drive circuit in Figure 3 and the 8T1C gate drive circuit in Figure 10, it can be found that: in the 11T1C gate drive circuit, the first electrode of the fifth transistor M5 is connected to the high-level signal line VGH; in the 8T1C gate drive circuit, the gate and first electrode of the fifth transistor M5 are connected to the inverting clock signal line CLK-B. Compared to the high-level signal line VGH, which remains high for one frame, the inverting clock signal line CLK-B alternates between high and low levels. Therefore, the forward bias time of the fifth transistor M5 is reduced by nearly half, which can improve the lifespan of the fifth transistor M5. Table 1 shows a comparison of the forward bias time of the fifth transistor M5 in the 11T1C gate drive circuit and the 8T1C gate drive circuit.

[0163] Table 1: Comparison of the forward bias time of the fifth transistor M5 in the 11T1C gate drive circuit and the 8T1C gate drive circuit

[0164] Figure 15 shows a comparison of the connection methods of the 11T1C gate drive circuit in Figure 5A and the 8T1C gate drive circuit in Figure 12A with the clock signal line. In the 8T1C gate drive circuit in Figure 12A, the clock signal line has a main body extending along a first direction DR1 and a first connection portion extending away from the main body along a second direction DR2, wherein the second direction DR2 intersects the first direction DR1. In some embodiments, the second direction DR2 is perpendicular to the first direction DR1. The gate drive circuit includes a transistor connected to the clock signal line, and the connection electrode of the transistor connected to the clock signal line includes a second connection portion, wherein the orthographic projection of the first connection portion on the substrate and the orthographic projection of the second connection portion on the substrate at least partially overlap each other along the first direction DR1.

[0165] As shown in Figure 15, the 11T1C gate drive circuit shown in Figure 5A employs a structure with eight clock signal lines, including four clock signal lines on one side, and the space occupied by these four clock signal lines is 59.25 μm. The gate drive circuit shown in Figure 12A employs a structure with four clock signal lines, including two clock signal lines on one side, and the space occupied by these two clock signal lines is 31 μm. By adopting the structure according to this disclosure, the bezel width of the array substrate is greatly reduced.

[0166] Figure 16 shows a comparison of the signal line width and spacing between the 11T1C gate drive circuit in Figure 5A and the 8T1C gate drive circuit in Figure 12A. As shown in Figure 16, in the 11T1C gate drive circuit shown in Figure 5A, the width of the ground line GND is 20 μm, and the spacing between the ground line GND and the adjacent frame start signal line STV1 is 20 μm; in the gate drive circuit shown in Figure 12A, the width of the ground line GND is 5 μm, and the spacing between the ground line GND and the adjacent frame start signal line STV1 is 5 μm. It has been verified that the width and spacing parameters in the gate drive circuit shown in Figure 12A also meet the same anti-static requirements. By adopting the structure according to this disclosure, the bezel width of the array substrate is significantly reduced.

[0167] In some embodiments, the distance between the ground line GND and the adjacent frame start signal line STV1 is greater than or equal to 5 μm and less than 20 μm.

[0168] Figure 17 shows a comparison of the connection methods between the 11T1C gate drive circuit in Figure 5A and the 8T1C gate drive circuit in Figure 12A with the gate lines. In the 11T1C gate drive circuit shown in Figure 5A, the common electrode line is located on the gate metal layer (Gate); in the gate drive circuit shown in Figure 12A, the common electrode line (Com) is located on the signal line layer (SD). The seventh via V7 and the eighth via V8, which connect the output terminal of the scanning unit to the input terminal of the corresponding gate line, can be set on the side of the common electrode line (Com) closer to the scanning unit.

[0169] Figure 18 shows the layout of the capacitor and the fourth transistor in the 8T1C gate drive circuit of Figure 12A. As shown in Figure 18, the capacitor C0 has a key shape, which includes a key handle portion C0-B and a key tooth portion C0-T.

[0170] In some embodiments, as shown in FIG18, the orthographic projection of the fourth transistor M4 on the substrate BS and the orthographic projection of the key handle portion CO-B on the substrate BS at least partially overlap along the first direction DR1.

[0171] In some embodiments, as shown in FIG18, the fourth transistor M4 is located on the side of the key portion C0-T near the pre-frame reset signal line STV0.

[0172] In some embodiments, as shown in FIG18, the orthographic projection of the fourth transistor M4 on the substrate BS and the orthographic projection of the key portion C0-T on the substrate BS at least partially overlap along the second direction DR2.

[0173] In some embodiments, as shown in FIG18, capacitor C0 has a tapered shape along the direction close to the fourth transistor M4. The orthographic projection of the fourth transistor M4 on the substrate BS and the orthographic projection of capacitor C0 on the substrate BS at least partially overlap along the first direction DR1 and at least partially overlap along the second direction DR2.

[0174] Figure 19 is a circuit diagram illustrating the structure of a scanning unit of a gate driving circuit according to some embodiments of the present disclosure. Referring to Figure 19, in some embodiments, the scanning unit circuit is an 11T1C (i.e., 11 transistors and 1 capacitor) circuit, including: a first transistor M1, whose first electrode is connected to a first-level signal line VDD, its gate is connected to the input terminal INPUT, and its second electrode is connected to a pull-up node PU; a second transistor M2, whose first electrode is connected to the pull-up node PU, its second electrode is connected to a second-level signal line VSS, and its gate is connected to the reset terminal RESET; a third transistor M3, whose first electrode is connected to the clock signal line CLK, its second electrode is connected to the output terminal OUTPUT, and its gate is connected to the pull-up node PU; and a fourth transistor M4, whose first electrode is connected to the pull-up node PU, its second electrode is connected to the low-level signal line VGL, and its gate is connected to... The first electrode of transistor M5 is connected to the high-level signal line VGH, and the second electrode is connected to the pull-down node PD. The second electrode of transistor M6 is connected to the pull-down node PD, the second electrode is connected to the low-level signal line VGL, and the gate is connected to the pull-up node PU. The third electrode of transistor M10 is connected to the pull-up node PU, the second electrode is connected to the low-level signal line VGL, and the gate is connected to the pull-down node PD. The fourth electrode of transistor M11 is connected to the output terminal OUTPUT, the second electrode is connected to the low-level signal line VGL, and the gate is connected to the pull-down node PD. The fifth transistor M5 has its first electrode plate connected to the pull-up node PU and its second electrode plate connected to the output terminal OUTPUT.

[0175] In the circuit shown in Figure 19, the channel width-to-length ratio of the sixth transistor M6 is much greater than that of the fifth transistor M5.

[0176] The scanning unit shown in Figure 19 has two operating modes: forward scanning mode and reverse scanning mode. When the first level signal line VDD provides a high-level signal and the second level signal line VSS provides a low-level signal, the frame start signal STV1 is provided to the input terminal INPUT of the first scanning unit. The scanning unit shown in Figure 19 is in forward scanning mode, and its operating timing is exactly the same as that of the scanning unit shown in Figure 10. When the first level signal line VDD provides a low-level signal and the second level signal line VSS provides a high-level signal, the frame start signal STV1 is provided to the reset terminal RESET of the last scanning unit (e.g., the Nth scanning unit). The scanning unit shown in Figure 19 is in reverse scanning mode.

[0177] On the other hand, the present invention provides a display panel including the array substrate described above; and a second substrate opposite to the array substrate, wherein the second substrate includes a black matrix, the black matrix including a black matrix body portion located in the peripheral region of the display panel, and an extension portion extending from the black matrix body portion to at least a portion of the edge of the display panel, the extension portion including a partially perforated pattern.

[0178] Figure 20 is a schematic diagram illustrating the structure of a black matrix on a second substrate according to some embodiments of the present disclosure. As shown in Figure 20, the black matrix includes a black matrix body BM-B and an extension BM-T extending from the black matrix body BM-B to at least a portion of the edge of the display panel, the extension BM-T including a partially perforated pattern. In the example shown in Figure 20, the extension BM-T extends to three sides of the display panel other than the side where the flexible circuit board (FPC) is bonded. As shown in Figure 20, the extension BM-T includes a plurality of black matrix blocks BLK spaced apart from each other, the spacing d between any two adjacent black matrix blocks BLK being between 10 μm and 15 μm, for example, 12 μm. As shown in Figure 20, on the side without the extension BM-T, the distance b between the black matrix body BM-B and the edge of the display panel is between 200 μm and 400 μm, for example, 300 μm. This structural design prevents light leakage from a large viewing angle due to the black matrix failing to block the backlight.

[0179] On the other hand, the present invention provides a display device comprising an array substrate manufactured as described herein or by the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo albums, GPS, etc. In one example, the display device is a wearable product. Optionally, the display device is a liquid crystal display device.

[0180] On the other hand, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a clock signal line and a gate driving circuit, wherein the clock signal line has a clock signal line body extending along a first direction and a first connection portion extending away from the clock signal line body along a second direction, wherein the second direction intersects the first direction; the gate driving circuit includes a transistor connected to the clock signal line, wherein a connection electrode of the transistor connected to the clock signal line includes a second connection portion, wherein the orthographic projection of the first connection portion on the substrate and the orthographic projection of the second connection portion on the substrate at least partially overlap each other along the first direction.

[0181] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to specific examples, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising: A clock signal line having a main body extending in a first direction and a first connecting portion extending in a second direction away from the main body, wherein the second direction intersects the first direction; and A gate drive circuit includes a transistor connected to the clock signal line, wherein the connection electrode of the transistor connected to the clock signal line includes a second connection portion. Wherein, the orthographic projection of the first connecting portion on the substrate and the orthographic projection of the second connecting portion on the substrate overlap each other at least partially along the first direction.

2. The array substrate according to claim 1, wherein, The gate drive circuit includes multiple cascaded scanning units, each scanning unit comprising: The third transistor has its first electrode connected to the first clock signal line, its second electrode connected to the output terminal of the scanning unit, and its gate connected to a pull-up node. The first clock signal line includes the first connection portion, and the first electrode of the third transistor includes the second connection portion.

3. The array substrate according to claim 2, comprising: A gate metal layer is located on the substrate. A gate insulating layer is located on the side of the gate metal layer away from the substrate. A semiconductor material layer is located on the side of the gate insulating layer away from the gate metal layer; An insulating layer is located on the side of the semiconductor material layer away from the gate insulating layer; A signal line layer, located on the side of the insulating layer away from the semiconductor material layer; A passivation layer is located on the side of the signal line layer away from the insulating layer; as well as A connection layer is located on the side of the passivation layer away from the signal line layer. Specifically, the second connection portion of the first electrode of the third transistor is connected to the first connection pad via a third via, and the first connection portion of the first clock signal line is connected to the first connection pad via a fourth via. Wherein, the first clock signal line is located on the gate metal layer, the first electrode of the third transistor is located on the signal line layer, and the first connection pad is located on the connection layer. The third via extends through the passivation layer, and the fourth via extends through the passivation layer, the insulating layer, and the gate insulating layer.

4. The array substrate according to claim 1, wherein, The gate driving circuit includes multiple cascaded scanning units, each scanning unit including a control sub-circuit, the control sub-circuit including: The fifth transistor has its first electrode and gate connected to the third clock signal line, and its second electrode connected to a pull-down node; and The sixth transistor has its first electrode connected to the pull-down node, its second electrode connected to the low-level signal line, and its gate connected to the pull-up node. The third clock signal line includes the first connection portion, and the first electrode of the fifth transistor includes the second connection portion.

5. The array substrate according to claim 4, comprising: A gate metal layer is located on the substrate. A gate insulating layer is located on the side of the gate metal layer away from the substrate. A semiconductor material layer is located on the side of the gate insulating layer away from the gate metal layer; An insulating layer is located on the side of the semiconductor material layer away from the gate insulating layer; A signal line layer, located on the side of the insulating layer away from the semiconductor material layer; A passivation layer is located on the side of the signal line layer away from the insulating layer; as well as A connection layer is located on the side of the passivation layer away from the signal line layer. Specifically, the second connection portion of the first electrode of the fifth transistor is connected to the second connection pad through a fifth via, and the first connection portion of the third clock signal line is connected to the first connection pad through a sixth via. Wherein, the third clock signal line is located on the gate metal layer, the first electrode of the third transistor is located on the signal line layer, and the first connection pad is located on the connection layer. The fifth via extends through the passivation layer, and the sixth via extends through the passivation layer, the insulating layer, and the gate insulating layer.

6. The array substrate according to claim 4, wherein, The first electrode of the third transistor in each scanning unit is connected to the first clock signal line, and The phase of the signal on the third clock signal line is opposite to the phase of the signal on the first clock signal line.

7. The array substrate according to claim 1, wherein, The gate driving circuit includes multiple cascaded scanning units, and the orthographic projection of the output terminal of each scanning unit on the substrate and the orthographic projection of the input terminal of the corresponding gate line on the substrate overlap at least partially with each other along the first direction.

8. The array substrate according to claim 7, comprising: A gate metal layer is located on the substrate. A gate insulating layer is located on the side of the gate metal layer away from the substrate. A semiconductor material layer is located on the side of the gate insulating layer away from the gate metal layer; An insulating layer is located on the side of the semiconductor material layer away from the gate insulating layer; A signal line layer, located on the side of the insulating layer away from the semiconductor material layer; A passivation layer is located on the side of the signal line layer away from the insulating layer; as well as A connection layer is located on the side of the passivation layer away from the signal line layer. The output of the scanning unit is connected to the third connecting pad via a seventh via, and the input of the grid line is connected to the third connecting pad via an eighth via. Wherein, the gate line is located in the gate metal layer, the output terminal of the scanning unit is located in the signal line layer, and the third connection pad is located in the connection layer. The seventh via extends through the passivation layer, and the eighth via extends through the passivation layer, the insulating layer, and the gate insulating layer.

9. The array substrate according to claim 8, wherein, The seventh and eighth vias are located on the side of the common electrode line closer to the scanning unit.

10. The array substrate according to claim 7, further comprising a common electrode line, wherein, The common electrode line and the gate line are located on different layers.

11. The array substrate according to claim 7, further comprising a common electrode line, wherein, The common electrode line and the data line are located on the same layer.

12. The array substrate according to claim 1, further comprising an adjacently disposed ground line and a frame start signal line, wherein, The distance between the grounding wire and the frame start signal line is greater than or equal to 5 μm and less than 20 μm.

13. The array substrate according to claim 1, wherein, The gate drive circuit includes multiple cascaded scanning units, each scanning unit comprising: A capacitor having a key shape, the capacitor including a handle portion and key teeth portions; and The fourth transistor has its first electrode connected to the pull-up node, its second electrode connected to the low-level signal line, and its gate connected to the pre-frame reset signal line. Wherein, the orthographic projection of the fourth transistor on the substrate and the orthographic projection of the key handle portion of the capacitor on the substrate at least partially overlap along the first direction.

14. The array substrate according to claim 13, wherein, The orthographic projection of the fourth transistor on the substrate and the orthographic projection of the key portion of the capacitor on the substrate at least partially overlap along the second direction.

15. The array substrate according to claim 13, wherein, The fourth transistor is located on the side of the key portion of the capacitor near the pre-frame reset signal line.

16. The array substrate according to claim 1, wherein, The gate drive circuit includes multiple cascaded scanning units, each scanning unit comprising: Capacitors, and The fourth transistor has its first electrode connected to the pull-up node, its second electrode connected to the low-level signal line, and its gate connected to the pre-frame reset signal line. The capacitor has a tapered shape along the direction close to the fourth transistor, and The orthographic projection of the fourth transistor on the substrate and the orthographic projection of the capacitor on the substrate overlap at least partially along the first direction and at least partially along the second direction.

17. The array substrate according to claim 1, wherein, The gate drive circuit includes multiple cascaded scanning units, each scanning unit including a capacitor. The capacitor includes a first electrode plate and a second electrode plate, wherein the first electrode plate includes a first portion and a second portion. The first portion of the first electrode plate is connected to the first electrode plate through the ninth through hole.

18. The array substrate according to claim 17, wherein, The second electrode plate is located between the first portion of the first electrode plate and the second portion of the first electrode plate.

19. The array substrate according to claim 17, comprising: A gate metal layer is located on the substrate. A gate insulating layer is located on the side of the gate metal layer away from the substrate. A semiconductor material layer is located on the side of the gate insulating layer away from the gate metal layer; An insulating layer is located on the side of the semiconductor material layer away from the gate insulating layer; A signal line layer, located on the side of the insulating layer away from the semiconductor material layer; A passivation layer is located on the side of the signal line layer away from the insulating layer; as well as A connection layer is located on the side of the passivation layer away from the signal line layer. Wherein, a first portion of the first electrode plate is located in the gate metal layer, a second electrode plate is located in the signal line layer, and a second portion of the first electrode plate is located in the interconnect layer. The ninth via extends through the passivation layer, the insulating layer, and the gate insulating layer.

20. The array substrate according to claim 1, wherein, The gate drive circuit includes two adjacent scan units, the circuit structures of which are mirror images of each other about a straight line perpendicular to the clock signal line.

21. The array substrate according to claim 20, wherein, The two adjacent scanning units share the same connection line, which is connected to a low-level signal line.

22. A display panel, comprising: The array substrate according to claim 1; and A second substrate opposite to the array substrate. The second substrate includes a black matrix, which includes a black matrix body located in the peripheral region of the display panel and an extension portion extending from the black matrix body to at least a portion of the edge of the display panel, the extension portion including a partially perforated pattern.

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