Integrated circuit delay determination method and apparatus, and device, medium and product

Abstract

An integrated circuit delay determination method and apparatus, and a device, a medium and a product. The method comprises: acquiring a directed acyclic graph of a clock net of a target integrated circuit, a preset timing path set and a preset timing exception rule set, wherein the timing exception rule set comprises a sub-graph rule corresponding to at least one timing exception rule (S202); on the basis of a plurality of key nodes in the sub-graph rule, determining an affected region corresponding to each timing exception rule, and on the basis of a preset microinstruction compiling method, determining microinstructions of a plurality of affected nodes within the affected regions (S204); on the basis of the microinstructions, performing classified discussion on each affected node, and on the basis of classified discussion results, determining one or more tags corresponding to each affected node, so as to obtain a timing exception tag graph on the basis of the tags and the affected regions (S206); and on the basis of a GPU platform and the timing exception tag graph, determining a delay corresponding to each timing path in the preset timing path set, so as to determine the maximum delay value and the minimum delay value of the target integrated circuit (S208).

Description

Integrated circuit delay determination methods, apparatus, equipment, media and products

[0001] This application claims priority to Chinese Patent Application No. 202411597634.X, filed on November 11, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the technical field of integrated circuit design automation, and for example to an integrated circuit delay determination method, apparatus, device, medium, and product. Background Technology

[0003] Current timing analysis tools mostly employ the technique of "timing exception analysis" to compensate for the shortcomings of static timing analysis. Timing exception analysis requires chip design engineers to specify a series of timing exception rules so that timing analysis tools can better understand the chip design engineer's intentions, thereby performing reasonable verification of the chip circuit and achieving better consistency between timing analysis results and the chip's functional objectives.

[0004] In related technologies, to reduce the cost of timing exception analysis, methods such as graph analysis and path analysis are commonly used to accelerate various tasks in timing analysis by leveraging heterogeneous GPU platforms. However, due to the wide variety of timing exceptions and the highly complex data structures resulting from classification and discussion, GPU memory pressure increases. This makes it difficult for timing exception analysis methods in related technologies to fully utilize heterogeneous GPU platforms for high-speed timing exception analysis, thus resulting in low efficiency of integrated circuit delay determination methods in related technologies. Summary of the Invention

[0005] This application provides a method, apparatus, device, medium, and product for determining the delay of an integrated circuit, so as to improve the efficiency of the method for determining the delay of an integrated circuit.

[0006] In a first aspect, this application provides a method for determining the delay of an integrated circuit, comprising:

[0007] Obtain the directed acyclic graph of the clock net of the target integrated circuit, a preset set of timing paths, and a preset set of timing exception rules. The set of timing exception rules includes at least one subgraph rule corresponding to a timing exception rule, and the subgraph rule includes multiple key nodes.

[0008] Based on multiple key nodes, determine the affected area corresponding to each timing exception rule, and determine the micro-instructions of multiple affected nodes within the affected area according to the preset micro-instruction compilation method;

[0009] Each affected node is classified and discussed according to the micro-instructions, and one or more labels corresponding to each affected node are determined based on the results of the classification and discussion. Based on the labels and the affected area, a time-series exception label map is obtained. The labels store the behavioral characteristics of the corresponding affected node and the delay corresponding to the behavioral characteristics.

[0010] Based on the GPU platform and timing exception labeling graph, the latency corresponding to each timing path in the preset timing path set is determined in order to determine the minimum and maximum latency of the target integrated circuit.

[0011] Secondly, this application also provides an integrated circuit delay determination apparatus, the apparatus comprising:

[0012] The circuit data acquisition module is configured to acquire the directed acyclic graph of the clock net of the target integrated circuit, a preset timing path set, and a preset timing exception rule set. The timing exception rule set includes at least one subgraph rule corresponding to a timing exception rule, and the subgraph rule includes multiple key nodes.

[0013] The microinstruction determination module is configured to determine the affected area corresponding to each timing exception rule based on multiple key nodes, and determine the microinstructions of multiple affected nodes within the affected area according to a preset microinstruction compilation method.

[0014] The label graph generation module is configured to classify and discuss each affected node according to the microinstruction, and determine one or more labels corresponding to each affected node based on the results of the classification and discussion, so as to obtain a time-series exception label graph based on the labels and the affected area. The labels store the behavioral characteristics of the corresponding affected node and the delay corresponding to the behavioral characteristics.

[0015] The circuit delay determination module is set to be based on the GPU platform and timing exception label map to determine the delay corresponding to each timing path in the preset timing path set, so as to determine the minimum and maximum delay of the target integrated circuit.

[0016] Thirdly, this application also provides a computer device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the aforementioned integrated circuit delay determination method.

[0017] Fourthly, this application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the aforementioned integrated circuit delay determination method.

[0018] Fifthly, this application also provides a computer program product comprising a computer program that, when executed by a processor, implements the aforementioned integrated circuit delay determination method. Attached Figure Description

[0019] Figure 1 is an application environment diagram of an integrated circuit delay determination method in one embodiment;

[0020] Figure 2 is a flowchart of an integrated circuit delay determination method in one embodiment;

[0021] Figure 3 is a schematic diagram of each timing exception rule and its corresponding subgraph rule in one embodiment;

[0022] Figure 4 is a flowchart of determining the target influence area based on the target key nodes in one embodiment;

[0023] Figure 5 is an example diagram of the influence area of ​​a timing exception rule in one embodiment;

[0024] Figure 6 is a flowchart of determining the minimum boundary point of a timing exception rule in one embodiment;

[0025] Figure 7 is a flowchart of determining the microinstructions corresponding to a node in one embodiment;

[0026] Figure 8 is a schematic diagram of a timing exception label diagram in one embodiment;

[0027] Figure 9 is a structural block diagram of an integrated circuit delay determination device in one embodiment;

[0028] Figure 10 is an internal structure diagram of a computer device in one embodiment;

[0029] Figure 11 is an internal structural diagram of a computer device in another embodiment. Detailed Implementation

[0030] Static Timing Analysis (STA) is a crucial step in the integrated circuit chip design process, playing a decisive role in verifying and optimizing circuit functionality and performance. A standard STA procedure typically uses timing propagation to simulate and calculate signal propagation along the topological order of each type of component on the circuit diagram, thereby evaluating the circuit's timing. However, the circuit diagram's topology cannot fully reflect the actual operation of the chip design. For example, the topology may incorrectly introduce spurious timing paths that are logically impossible to trigger. Furthermore, the topology cannot reflect the interaction of multiple clock domains within the chip or logic paths spanning multiple clock cycles. Therefore, timing analysis based solely on simple topology propagation can lead to inaccuracies, negatively impacting chip optimization.

[0031] To accurately analyze chip timing, current timing analysis tools employ a technique called "timing exception analysis." Timing exception analysis requires chip design engineers to specify a series of timing exception rules, including ignoring timing paths that conform to specific patterns, treating timing paths that conform to specific patterns as paths spanning multiple clock cycles, and so on. These timing exception rules enable timing analysis tools to better understand the chip design engineer's intent, thereby allowing for reasonable verification of the chip circuitry and resulting in better consistency between timing analysis results and the chip's functional objectives.

[0032] However, timing exception analysis is very costly. If analysis methods such as graph analysis and path analysis are used to accelerate multiple tasks in timing analysis by utilizing the heterogeneous platform of GPU, it will increase the GPU memory pressure and make it difficult to fully utilize the GPU to achieve high-speed analysis of timing exceptions, resulting in low efficiency of integrated circuit delay determination methods in related technologies.

[0033] To address the inefficiency of existing integrated circuit delay determination methods, this application provides a method for determining integrated circuit delay, applicable to the environment shown in Figure 1. In this method, terminal 102 communicates with server 104 via a network. A data storage system stores the data that server 104 needs to process. This data storage system can be integrated onto server 104 or hosted on a cloud or other network server. Terminal 102 can be, but is not limited to, any type of personal computer, laptop, smartphone, tablet, IoT device, or portable wearable device. IoT devices can include smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, etc. Portable wearable devices can include smartwatches, smart bracelets, head-mounted devices, etc. Server 104 can be implemented using a standalone server or a server cluster consisting of multiple servers.

[0034] This method utilizes GPU acceleration for integrated circuit timing exception analysis, primarily comprising three steps: limiting the impact region of timing exceptions, compiling timing exception micro-instructions, and propagating timing exception label graphs. The timing exception impact region limiting step aims to precisely narrow the actual impact range of each timing exception rule on the circuit diagram, avoiding unnecessary classification discussions outside the actual impact range, thus simplifying the circuit diagram and saving storage. This step includes sub-steps: forward traversal, backward traversal, and construction of the minimum boundary point set. The timing exception micro-instruction compilation step aims to break down each timing exception rule into multiple micro-instructions according to a matching subgraph pattern (also known as a subgraph rule). Each micro-instruction defines the classification discussion behavior of a single node on the circuit diagram, effectively reducing the complexity of modeling the mutual influence between timing exceptions and simplifying the implementation of timing analysis tools. The timing exception label graph propagation step aims to automatically classify and discuss the microinstructions stored on each node according to the topological order of the circuit diagram. Using a hash algorithm, nodes on the circuit diagram are split into one or more labels, constructing a timing exception label graph. The final timing exception label graph is the result of timing exception analysis. Furthermore, on the final timing exception label graph, the fastest arrival time and slowest arrival time of the signal for each node label can be obtained through graph traversal algorithms. Based on the fastest and slowest arrival times, the chip's maximum operating frequency can be calculated, thus completing the chip performance analysis. Furthermore, by searching for the signal transmission paths corresponding to the fastest and slowest arrival times, the chip's performance bottlenecks can be identified, guiding automated chip design algorithms to perform targeted performance optimizations.

[0035] In one embodiment, as shown in Figure 2, the method is illustrated using a computer or other terminal as an example. It is understood that the method can also be applied to a server, and further to a system including both a terminal and a server, and is implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0036] Step 202: Obtain the directed acyclic graph of the clock net of the target integrated circuit, a preset timing path set, and a preset timing exception rule set. The timing exception rule set includes at least one subgraph rule corresponding to a timing exception rule, and the subgraph rule includes multiple key nodes.

[0037] The target integrated circuit is the one to be subjected to timing analysis. In integrated circuit design, timing refers to the time relationship between signal propagation and processing in a circuit, including the delay time for a signal to travel from one point to another. The goal of timing analysis is to ensure that these signals meet predetermined timing requirements during transmission and processing, thereby guaranteeing the normal operation and performance of the circuit.

[0038] A directed acyclic graph (DAG) consists of multiple nodes and multiple directed edges. Nodes represent multiple electrical components in an integrated circuit, such as clock sources, buffers, gating units, and registers. Directed edges represent the propagation path of the clock signal from one node to another. The preset timing path set is a set of timing detection paths used to verify chip performance. These paths are used to ensure the timing accuracy of the chip under different operating conditions.

[0039] Subgraph rules describe the specific location and scope of influence of timing exception rules within the clock net. Each subgraph rule typically includes multiple matching critical nodes. Furthermore, subgraph rules can be pre-defined based on the performance testing requirements of the target integrated circuit. The critical nodes in a subgraph rule are typically the start, intermediate, and end points of the path matched by the timing exception rule, and each subgraph rule must include at least one start and one end point.

[0040] For example, as shown in Figure 3, the types of timing exceptions mainly include spurious paths (a), multi-cycle paths (b), paths across synchronous clock domains (c), path fine-tuning (d), and local delay constraints (e). Each type of timing exception corresponds to a specific subgraph rule, i.e., an expression method. The rules for timing exceptions are usually given using the Synopsys Design Constraint (SDC) format, but other formats can also be used. In this embodiment, the SDC format is adopted, and the rules for each type of timing exception are given as shown in Figures (a)-(e) of Figure 3. For example, the general format of a false path is "set_false_path-from X-through Y-to Z", where set_false_path is the type of time-series exception, -from, -through, and -to represent the source node, the node passed through, and the destination node, respectively. -from-through-to together constitute a subgraph rule of a time-series exception. -from, -through, and -to are all optional, and each can give a set of nodes. -through can also have multiple stages, such as -through{AB}-through{CD}, which means passing through one of the two nodes A and B first, and then passing through one of the two nodes C and D. As shown in Figure 3, the subgraph rule for the false path (a) is set_false_path-through MUX0 / in0-through MUX1 / in1; the subgraph rule for the multicycle path (b) is set_multicycle_path-setup2-from FF0-to FF1; the subgraph rule for the cross-synchronous clock domain path (c) is create_generated_clock-divide_by 2[get_pins DIV2 / out]create_generated_clock-divide_by 3[get_pins DIV3 / out]; the subgraph rule for path fine-tuning (d) is set_path_margin 10-through NOR1 / a-through AND 2 / o; and the subgraph rule for local delay constraint (e) is set_max_delay200-from NOR3 / a-to AND 4 / o.

[0041] For example, the subgraph rule corresponding to a certain multicycle path is "set_multicycle_path-setup 2-from FF0-to FF1" in Figure 3(b), where "-setup" is used to specify the timing check of the path setup. For example, "-setup 2" indicates that the timing check of the path setup is completed within 2 clock cycles; "-from FF0" indicates that the starting point of the path is flip-flop FF0; and "to FF1" indicates that the ending point of the path is flip-flop FF1.

[0042] Step 204: Based on multiple key nodes, determine the affected area corresponding to each timing exception rule, and based on the preset micro-instruction compilation method, determine the micro-instructions of multiple affected nodes within the affected area.

[0043] In this context, the affected region is the circuit segment that a specific timing exception rule can influence, and the affected nodes are the nodes within that circuit segment. The affected region is related to the regions containing critical nodes and nodes associated with those critical nodes. In the entire circuit, a timing exception rule may only affect a small subset of paths, while most paths still follow regular timing rules. Therefore, by first analyzing the affected region of the timing exception rule, we can clarify which paths require special handling and which paths can be analyzed according to regular timing rules. This narrowing process avoids unnecessary global analysis, thereby improving the efficiency of timing analysis.

[0044] The pre-defined microinstruction compilation method aims to compile timing exception information, path classification, and other information in circuit design into a set of automatically executable microinstructions. Microinstructions act on a single circuit diagram node, determining the subsequent classification and discussion behavior of that node. They are instruction labels that do not require further splitting, including "immediately terminate timing propagation", "terminate timing propagation after the current label is completed", "create a label with signal delay starting from 0", "start matching the i-th timing exception", "abandon the i-th timing exception currently being matched", and "make the i-th timing exception effective and clean up invalid rules according to priority". Here, i represents the number of a timing exception. These microinstructions can be used to automatically handle tasks such as classification and discussion in timing analysis, so that the combined effect of any path passing through all microinstructions is equivalent to the behavior that the timing exception rule design should have.

[0045] Step 206: Classify and discuss each affected node according to the micro-instructions, and determine one or more labels corresponding to each affected node based on the classification and discussion results, so as to obtain a time-series exception label map based on the labels and the affected area. The labels store the behavioral characteristics of the corresponding affected nodes and the delays corresponding to the behavioral characteristics.

[0046] The purpose of the classification discussion is to correctly handle timing exceptions when checking path delays. Since the paths matched by timing exception rules are handled differently than normal paths, these paths need to be classified and labeled (tagged) for accurate timing analysis, and microinstruction compilation can automate this process. Tags are used to characterize the signal arrival time and the matching status of timing exceptions in different classification states. Therefore, the behavioral features in this embodiment are used to characterize the matching status of influencing nodes and timing exceptions, and delay is the time required for a signal to travel from one node to another. The timing exception tag graph, based on the directed acyclic graph, stores tag information on each node, but during data storage, it is still stored through the topological connections between nodes.

[0047] Step 208: Based on the GPU platform and timing exception label map, determine the latency corresponding to each timing path in the preset timing path set, so as to determine the minimum and maximum latency of the target integrated circuit.

[0048] The GPU platform, with its powerful computing capabilities, can perform parallel task processing. Based on the GPU platform and the timing exception labeling graph, the speed of timing path analysis can be accelerated, thereby improving the efficiency of timing analysis. As mentioned above, each node in the timing exception labeling graph stores latency data, including minimum and maximum latency. Based on this latency data, the minimum and maximum latency of the target integrated circuit can be determined, facilitating the subsequent calculation of the chip's maximum operating frequency and completing the chip's performance analysis.

[0049] In the aforementioned method for determining integrated circuit delay, each preset timing exception rule is represented as a subgraph rule. Then, based on the key nodes in each subgraph rule, the influence region corresponding to the timing exception rule where the key node is located is determined. This precisely narrows the actual influence range of each timing exception rule on the circuit diagram, avoiding unnecessary classification discussions outside the actual influence range. Furthermore, a preset microinstruction compilation method defines the classification discussion behavior of multiple influence nodes within each influence region. This ensures that the combined effect of all microinstructions traversed by any timing path is equivalent to the behavior that should be present in the timing exception design. It also effectively reduces the complexity of modeling the mutual influence between timing exceptions, thereby improving the efficiency of timing analysis. In addition, the final obtained timing exception label diagram allows for the accurate calculation of the minimum and maximum delay values ​​of the integrated circuit, ensuring the accuracy and reliability of calculating the impact of timing exceptions on signal propagation.

[0050] In one embodiment, as shown in Figure 4, multiple key nodes in each subgraph rule are sorted according to the topological order of the directed acyclic graph.

[0051] Based on multiple key nodes, the affected area corresponding to each time-series exception rule is determined, including:

[0052] Step 402: Based on the multiple target key nodes in the target subgraph rules, determine the path affected by the corresponding target time-series exception rules.

[0053] The target subgraph rule is any one of multiple subgraph rules, and the target key node is the key node in the target subgraph rule. Connecting the target key node and the associated nodes in sequence according to the topological order yields the path affected by the corresponding target temporal exception rule.

[0054] For example, as shown in Figure 5, Figure 5 is an example diagram of determining the corresponding affected area according to the subgraph rule "-from 1-through{4,5}-to 8". In this subgraph rule, nodes 1, 4, 5 and 8 are key nodes. Since node 1 must pass through node 3 to reach nodes 4 and 5 in sequence, and nodes 4 and 5 must pass through node 7 to reach node 8, nodes 3 and 7 are associated nodes related to the key nodes. The path formed by nodes 1, 3, 4, 7 and 8, as well as the path formed by nodes 1, 3, 5, 7 and 8, are the temporal paths affected by this subgraph rule.

[0055] Step 404: Determine the minimum boundary point of the target temporal exception rule according to the preset minimum boundary point determination method, and determine the target influence area corresponding to the target subgraph rule based on the minimum boundary point and the target graph node on the target temporal exception rule.

[0056] The target graph node is the target critical node on the target timing exception rule. Determining the minimum boundary point of the timing exception rule helps to further limit the scope of its influence in the integrated circuit, thereby avoiding unnecessary classification discussions outside the actual scope of influence, and achieving the purpose of simplifying the circuit diagram and saving storage.

[0057] For example, taking the example graph in Figure 5 above, it can be seen from Figure 5 that the minimum boundary points are nodes 2, 6 and 9. That is to say, when any temporal path passes through any of the nodes 2, 6 and 9, it is impossible to match the subgraph rule "-from 1-through{4,5}-to8". Therefore, the influence of the temporal exception corresponding to this subgraph rule on this temporal path can be excluded. The influence area corresponding to this subgraph rule is the area formed by nodes 1-9 and the directed edges between them.

[0058] In this embodiment, a set of minimum boundary points corresponding to each timing exception rule is constructed by using a preset minimum boundary point determination method, thereby determining the influence area corresponding to each timing exception rule. This helps to further limit the influence range of the timing exception rule in the integrated circuit, so as to avoid unnecessary classification discussions outside the actual influence range, thereby achieving the purpose of simplifying the circuit diagram and saving storage.

[0059] In one embodiment, as shown in Figure 6, the minimum boundary point of the target temporal exception rule is determined according to a preset minimum boundary point determination method, including:

[0060] Step 602: Based on the target key nodes, the directed acyclic graph containing the target time-series exception rules is layered to obtain a layered directed acyclic graph.

[0061] This application breaks down sequential exceptions into micro-instructions according to the hierarchy of subgraph rules, so that the combined effect of all micro-instructions traversed by any path is equivalent to the behavior that the sequential exception rules should possess when they are designed.

[0062] For example, as shown in Figure 5, the subgraph rules can be divided into 3 layers based on key nodes 1, 4, 5 and 8, where node 1 is in the first layer, nodes 4 and 5 are in the second layer and node 8 is in the third layer.

[0063] Step 604: Traverse the target graph nodes forward in the hierarchical directed acyclic graph to determine the candidate nodes of the previous level of each target graph node, and store the first traversal information on the target graph node and the candidate nodes respectively. The first traversal information is used to characterize whether the corresponding node can be accessed forward through multiple levels.

[0064] After obtaining the hierarchical directed acyclic graph, a graph search algorithm is used to perform a forward traversal from the i-th layer to the (i+1)-th layer, marking the nodes visited during the forward traversal, where i = 1, 2, ..., N-1. Candidate nodes are the predecessor nodes obtained during the forward traversal; therefore, some nodes are both graph nodes and candidate nodes.

[0065] For example, as shown in Figure 5, traversing forward from node 1 in the first layer can reach candidate nodes, namely nodes 2 and 3. Traversing forward from node 3 can reach candidate nodes in the second layer, namely nodes 4 and 5. Traversing forward from nodes 4 and 5 can reach node 7, and traversing forward from node 4 can also reach node 6. Traversing forward from node 7 can reach nodes 8 and 9 in the third layer. The first traversal information of nodes 1-9 can be expressed in the form of tags, as shown in Figure 5. Each node is marked with a tag B: X1X2X3, where X1, X2, and X3 are 0 or 1, indicating whether the node can be reached by traversing forward from the first, second, and third layers, respectively. 1 indicates yes, and 0 indicates no. For example, in Figure 5, node 1 in the first layer can be obtained by forward traversal of the first layer, but it cannot be obtained by forward traversal of the second and third layers. Therefore, the label B of node 1 is 100. Node 8 can be obtained by forward traversal of all three layers, so the label B of node 8 is 111. That is to say, the first traversal information of node 1 is 100, and the first traversal information of node 8 is 111.

[0066] Step 606: Traverse the target graph nodes and candidate nodes backward in the hierarchical directed acyclic graph, and store the second traversal information on the target graph nodes and candidate nodes respectively. The second traversal information is used to characterize whether the corresponding node can be accessed backward through multiple levels.

[0067] In the backward traversal, the process starts from the (i+1)th layer of the hierarchical subgraph rules and proceeds backward to the ith layer, using a graph search algorithm to perform a backward traversal on the circuit graph, marking the nodes visited during the backward traversal. Backward traversal refers to traversing the circuit graph in topological order in its reverse graph, where the reverse graph is obtained by reversing each edge of the directed acyclic graph (DAG), where i = 1, 2, ..., N-1.

[0068] For example, as shown in Figure 5, traversing backwards from node 8 in the third layer leads to node 7. Traversing backwards from node 7 leads to nodes 4 and 5 in the second layer, but node 7 cannot reach node 9. Traversing backwards from nodes 4 and 5 leads to node 3. Traversing backwards from node 3 leads to node 1 in the first layer, but node 3 cannot reach node 2. Similarly, the second traversal information for nodes 1-9 can also be expressed using labels, as shown in Figure 5. Each node is labeled F: Y1Y2Y3, where Y1, Y2, and Y3 are 0 or 1, indicating whether the node can be reached from the first, second, and third layers via reverse traversal, respectively. 1 indicates yes, and 0 indicates no. For example, in Figure 5, node 8 in the third layer can be obtained by traversing backward from the third layer, but it cannot be obtained by traversing backward from the second and first layers. Therefore, the label F of node 8 is 001. Node 1 can be obtained by traversing backward from the first to the third layer, so the label F of node 1 is 111. That is to say, the second traversal information of node 8 is 001, and the second traversal information of node 1 is 111.

[0069] Step 608: Determine the minimum boundary point of the target temporal exception rule based on the first traversal information and the second traversal information.

[0070] By comparing the information from the first and second traversals, we can identify nodes that are not visited by the backward traversal but are accessible by the forward traversal. These nodes can be defined as boundary points. A boundary point signifies that when a temporal path reaches a boundary point, it means that the temporal path can no longer satisfy the rule for that temporal exception, thus eliminating the need for further classification. Furthermore, we apply the simplification rule: if a boundary point A already has a predecessor node B that is also a boundary point, then point A can be removed from the list of boundary points. This is because when a path reaches boundary point A, the need for classification is eliminated. Applying this simplification rule to the set of all boundary points yields the minimum set of boundary points.

[0071] For example, taking the example graph in Figure 5, the minimum boundary point set consists of nodes 2, 6, and 9. This means that any path that passes through any of the nodes 2, 6, or 9 cannot match the subgraph rule "-from 1-through{4,5}-to 8". Therefore, the influence of the temporal exception rule corresponding to this subgraph rule on this path can be excluded.

[0072] In this embodiment, the minimum boundary point of the temporal exception rule is determined by forward and backward traversal, which helps to improve the efficiency and reliability of constructing the minimum boundary point set.

[0073] In one embodiment, determining the minimum boundary point of the target temporal exception rule based on the first traversal information and the second traversal information includes:

[0074] By comparing the information from the first traversal and the information from the second traversal, the candidate nodes that can be accessed forward but not backward are determined as the minimum boundary points of the target temporal exception rules.

[0075] As can be seen from the above, by comparing the labels B and F of the affected nodes within the affected area, the minimum boundary point corresponding to each time-series exception rule can be quickly determined, thereby enabling the rapid construction of the corresponding minimum boundary point set.

[0076] In one embodiment, as shown in Figure 7, the micro-instructions for multiple affected nodes within the affected area are determined according to a preset micro-instruction compilation method, including:

[0077] Step 702: In the preset mapping table between microinstruction compilation strategies and timing exception rule types, find and determine the target microinstruction compilation strategy corresponding to the type of the target timing exception rule. The target microinstruction compilation strategy includes the microinstruction compilation sub-strategy of each level of the affected nodes in the target timing exception rule.

[0078] The pre-defined mapping table between microinstruction compilation strategies and timing exception rule types can be preset according to the actual timing detection requirements of the target integrated circuit. Each microinstruction compilation sub-strategy specifies the instructions that need to be executed independently for each affected node.

[0079] Table 1

[0080] For example, the mapping relationship between the preset microinstruction compilation strategy and the timing exception rule type in this embodiment is shown in Table 1 above.

[0081] Step 704: Determine and store the micro-instructions corresponding to each affected node based on the level at which each affected node is located.

[0082] For example, as shown in Figure 8, which is a schematic diagram of a timing exception label graph, the subgraph rule corresponding to this timing exception rule is "e1:set_multicycle_path-through 1-through 4". That is, this subgraph rule corresponds to the multicycle path timing exception e1. According to this subgraph rule, it can be determined that nodes 1 and 4 are the key nodes corresponding to this subgraph rule. Node 1 is located in the first layer, and node 4 is located in the second layer. The micro-instruction of node 1 is "start matching the e1st timing exception", and the corresponding label is {e1:1}, which means that the current state is "timing exception e1 has been matched to the first stage". Node 2 has no timing exception associated with it, so the timing exception number set RuleSet of node 2 is an empty set {}. Node 3 has two predecessor nodes, namely node 1. Since Node 2 and Node 3 have different RuleSets, they need to be discussed separately. Two time exception labels are created: {e1:1} and {}. Node 4 executes the microinstruction on Node 4, "advance the matching status of the e1th time exception rule by one level", based on Node 3. Therefore, the label {e1:1} is updated to {e1:2}, which means that the matching status of e1 has advanced by one level, while {} remains unchanged. Since Node 5 is one of the smallest boundary points of time exception e1, the microinstruction on Node 5 is "abandon the e1th time exception that is being matched", and the label is {}.

[0083] In addition, each tag stores the corresponding delay time, which is the propagation time from a predecessor node to that node. For example, if node 3 has predecessor nodes 1 and 2, the time from node 1 to node 3 is 15 ps. Based on the tag of each node, the signal transmission path corresponding to the fastest and slowest times can be searched, which facilitates the identification of chip performance bottlenecks and guides the automated chip design algorithm to perform targeted performance optimization.

[0084] In this embodiment, by setting microinstructions for each node, the subsequent classification and discussion process can be accelerated, thereby helping to speed up the analysis of time-series exceptions.

[0085] In one embodiment, after determining one or more labels corresponding to each affected node based on the results of the classification discussion, the method further includes: merging labels of the same type among the multiple labels of each affected node.

[0086] During the classification discussion, a hash algorithm is used to merge identical categories. Two categories are considered identical if and only if their signal arrival times are defined in the same clock domain (denoted as ClockSet) and they have the same set of timing exception numbers currently in the matching process (denoted as RuleSet). The hash value for each category is calculated as Digest(ClockSet, RuleSet), where the result of Digest is an integer or other digest that can be quickly compared. When the digests of two categories are identical, they are considered equivalent and merged into a single category, reducing the number of categories in the final classification discussion result.

[0087] During the matching of new category summaries with existing category summaries, the GPU's storage hierarchy is utilized to allocate a software cache in local memory, caching recently occurring category summaries for fast matching. When ClockSet and RuleSet remain essentially unchanged, pointer techniques are used to avoid unnecessary copy operations, performing copies only when modifications to the two sets are required.

[0088] For each category obtained, a tag is created. A directed edge is established between tags a and b of each pair of adjacent nodes A->B on the circuit diagram. Specifically, if tag b can be obtained from tag a through classification discussion, then a directed edge is established from a to b. The resulting timing exception tag graph is shown in Figure 8. The final timing exception tag graph can provide a foundation for further timing exception analysis.

[0089] For example, as shown in Figure 8, node 5 in Figure 8 has two predecessor nodes, namely node 3 and node 2. Therefore, the labels of the two predecessor nodes are {e1:1} and {}, respectively. Since node 5 is one of the smallest boundary points of timing exception e1, the label on node 5 is the state of abandoning the timing exception e1 that is being matched. Therefore, the labels of the two predecessor nodes, {e1:1} and {}, will be transformed into {}. Since the two categories are the same, they are merged, leaving only the unique label {}. The resulting timing exception label map, when combined with timing analysis tools in related technologies, can be used to independently maintain the signal arrival time of each label during timing propagation, and take the maximum or minimum value according to the analysis mode when the classification is merged. This allows for the rapid acquisition of the minimum and maximum delay values ​​of the target integrated circuit.

[0090] This embodiment employs the above-described method, which precisely analyzes the impact range of timing exception rules, breaks down complex timing exception types into simple micro-instructions for simplified processing, and uses hash algorithms, copy-on-write, and other techniques to significantly reduce the time and memory usage for classification discussions, thus achieving a timing exception analysis computation mode that is friendly to heterogeneous GPU platforms. In addition, the efficiency of timing exception analysis completed by this application can be improved by more than 10 times, saving the computational cost of static timing analysis of integrated circuits and facilitating a more efficient automated chip design process.

[0091] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. There is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0092] This application also provides an integrated circuit delay determination apparatus for implementing the integrated circuit delay determination method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the integrated circuit delay determination apparatus provided below can be found in the limitations of the integrated circuit delay determination method described above, and will not be repeated here.

[0093] In one embodiment, as shown in FIG9, an integrated circuit delay determination device is provided, comprising: a circuit data acquisition module 902, a microinstruction determination module 904, a tag map generation module 906, and a circuit delay determination module 908, wherein:

[0094] The circuit data acquisition module 902 is configured to acquire the directed acyclic graph of the clock net of the target integrated circuit, a preset timing path set, and a preset timing exception rule set. The timing exception rule set includes at least one subgraph rule corresponding to a timing exception rule, and the subgraph rule includes multiple key nodes.

[0095] The microinstruction determination module 904 is configured to determine the affected area corresponding to each timing exception rule based on multiple key nodes, and determine the microinstructions of multiple affected nodes within the affected area according to a preset microinstruction compilation method.

[0096] The label graph generation module 906 is configured to classify and discuss each affected node according to the microinstruction, and determine one or more labels corresponding to each affected node based on the results of the classification and discussion, so as to obtain a time-series exception label graph based on the labels and the affected area. The labels store the behavioral characteristics of the corresponding affected node and the delay corresponding to the behavioral characteristics.

[0097] The circuit delay determination module 908 is configured to determine the delay corresponding to each timing path in the preset timing path set based on the GPU platform and timing exception label map, so as to determine the minimum and maximum delay values ​​of the target integrated circuit.

[0098] In one embodiment, the micro-instruction determination module 904 is configured to determine the influence area corresponding to each time-series exception rule in the following manner: based on multiple target key nodes in the target subgraph rule, determine the path affected by the corresponding target time-series exception rule; based on a preset minimum boundary point determination method, determine the minimum boundary point of the target time-series exception rule; and based on the minimum boundary point and the target graph nodes on the target time-series exception rule, determine the target influence area corresponding to the target subgraph rule.

[0099] In one embodiment, the microinstruction determination module 904 is configured to determine the minimum boundary point of the target temporal exception rule in the following manner: based on the target key node, the directed acyclic graph in which the target temporal exception rule is located is layered to obtain a layered directed acyclic graph; the target graph nodes are traversed forward in the layered directed acyclic graph to determine the candidate node of the previous level of each target graph node, and the first traversal information is stored on the target graph node and the candidate node respectively. The first traversal information is used to characterize whether the corresponding node can be accessed forward through multiple levels; the target graph nodes and candidate nodes are traversed backward in the layered directed acyclic graph, and the second traversal information is stored on the target graph node and the candidate node respectively. The second traversal information is used to characterize whether the corresponding node can be accessed backward through multiple levels; the minimum boundary point of the target temporal exception path is determined based on the first traversal information and the second traversal information.

[0100] In one embodiment, the microinstruction determination module 904 is configured to determine the minimum boundary point of the target timing exception rule based on the first traversal information and the second traversal information in the following manner: by comparing the first traversal information and the second traversal information, candidate nodes that can be accessed forward but not backward are determined as the minimum boundary point of the target timing exception rule.

[0101] In one embodiment, the microinstruction determination module 904 is configured to determine the microinstructions of multiple affected nodes within the affected area according to a preset microinstruction compilation method in the following manner: In a preset mapping table between microinstruction compilation strategies and time-series exception rule types, a target microinstruction compilation strategy corresponding to the type of the target time-series exception rule is searched and determined, wherein the target microinstruction compilation strategy includes microinstruction compilation sub-strategies for each level of affected nodes in the target time-series exception rule; and the microinstructions corresponding to each affected node are determined and stored according to the level at which each affected node is located.

[0102] In one embodiment, the label graph generation module 906 is further configured to merge labels of the same type when there are multiple labels of the same type among the multiple labels of each affected node.

[0103] The multiple modules in the aforementioned integrated circuit delay determination device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0104] In one embodiment, a computer device, which may be a server, is provided, and its internal structure is shown in Figure 10. The computer device includes a processor, memory, and a network interface connected via a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database of the computer device is configured to store data such as the identifier and latency of each node in the target integrated circuit. The network interface of the computer device is configured to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements an integrated circuit latency determination method.

[0105] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in Figure 11. The computer device includes a processor, memory, communication interface, display screen, and input device connected via a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is configured to communicate with an external terminal via wired or wireless means. Wireless communication can be achieved through Wireless Fidelity (WIFI), mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements an integrated circuit delay determination method. The display screen of the computer device may be a liquid crystal display (LCD) or an e-ink display. The input device of the computer device may be a touch layer covering the display screen, or buttons, a trackball, or a touchpad located on the casing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0106] Those skilled in the art will understand that the structures shown in Figures 10 and 11 are merely block diagrams of some structures related to the present application and do not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than shown in the figures, or combine certain components, or have different component arrangements.

[0107] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiment.

[0108] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.

[0109] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the method embodiments described above.

[0110] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by multiple parties.

[0111] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0112] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for determining the delay of an integrated circuit, comprising: Obtain the directed acyclic graph of the clock net of the target integrated circuit, a preset set of timing paths, and a preset set of timing exception rules, wherein the set of timing exception rules includes at least one subgraph rule corresponding to a timing exception rule, and the subgraph rule includes multiple key nodes; Based on the multiple key nodes, the affected area corresponding to each timing exception rule is determined, and the micro-instructions of multiple affected nodes within the affected area are determined according to the preset micro-instruction compilation method. Each affected node is classified and discussed according to the micro-instruction, and one or more labels corresponding to each affected node are determined according to the classification and discussion results. A time-series exception label map is obtained according to the labels and the affected area. The labels store the behavioral characteristics of the corresponding affected node and the delay corresponding to the behavioral characteristics. Based on the graphics processing unit (GPU) platform and the timing exception label map, the latency corresponding to each timing path in the preset timing path set is determined, so as to determine the minimum and maximum latency of the target integrated circuit.

2. The method according to claim 1, wherein, Multiple key nodes in each of the subgraph rules are sorted according to the topological order of the directed acyclic graph; The step of determining the affected area corresponding to each time-series exception rule based on the multiple key nodes includes: Based on multiple key nodes of the target subgraph rules, determine the paths affected by the corresponding target time-series exception rules; According to the preset minimum boundary point determination method, the minimum boundary point of the target temporal exception rule is determined, and based on the minimum boundary point and the target graph node on the target temporal exception rule, the target influence area corresponding to the target subgraph rule is determined. The target graph node is the target key node on the target time-series exception rule.

3. The method according to claim 2, wherein, The step of determining the minimum boundary point of the target temporal exception rule according to the preset minimum boundary point determination method includes: Based on the target key nodes, the directed acyclic graph containing the target temporal exception rules is layered to obtain a layered directed acyclic graph; In the hierarchical directed acyclic graph, the target graph nodes are traversed forward to determine the candidate nodes of the previous level of each target graph node, and the first traversal information is stored on the target graph nodes and the candidate nodes respectively. The first traversal information is used to characterize whether the corresponding node can be accessed forward through multiple levels. In the hierarchical directed acyclic graph, the target graph nodes and the candidate nodes are traversed backward, and second traversal information is stored on the target graph nodes and the candidate nodes respectively. The second traversal information is used to characterize whether the corresponding node can be accessed backward through multiple levels. Based on the first traversal information and the second traversal information, determine the minimum boundary point of the target temporal exception rule.

4. The method according to claim 3, wherein, The step of determining the minimum boundary point of the target temporal exception rule based on the first traversal information and the second traversal information includes: By comparing the first traversal information and the second traversal information, candidate nodes that can be accessed forward but not backward are determined as the minimum boundary points of the target temporal exception rules.

5. The method according to claim 3, wherein, The step of determining the micro-instructions of multiple affected nodes within the affected area according to a preset micro-instruction compilation method includes: In the preset mapping table between microinstruction compilation strategies and timing exception rule types, the target microinstruction compilation strategy corresponding to the type of the target timing exception rule is found and determined. The target microinstruction compilation strategy includes the microinstruction compilation sub-strategy of each level of the affected nodes in the target timing exception rule. Based on the level at which each affected node is located, determine and store the micro-instructions corresponding to each affected node.

6. The method of claim 5, further comprising, after determining one or more labels corresponding to each of the influencing nodes based on the results of the classification discussion: If there are tags of the same type among the multiple tags of each affected node, the tags of the same type are merged.

7. An integrated circuit delay determination apparatus, comprising: The circuit data acquisition module is configured to acquire the directed acyclic graph of the clock net of the target integrated circuit, a preset timing path set, and a timing exception rule set, wherein the timing exception rule set includes at least one subgraph rule corresponding to a timing exception rule, and the subgraph rule includes multiple key nodes; The microinstruction determination module is configured to determine the affected area corresponding to each timing exception rule based on the multiple key nodes, and determine the microinstructions of multiple affected nodes within the affected area according to a preset microinstruction compilation method. The label graph generation module is configured to classify and discuss each of the affected nodes according to the microinstructions, and determine one or more labels corresponding to each of the affected nodes according to the results of the classification and discussion, so as to obtain a time-series exception label graph based on the labels and the affected areas. The labels store the behavioral characteristics of the corresponding affected nodes and the delays corresponding to the behavioral characteristics. The circuit delay determination module is configured to determine the delay corresponding to each timing path in the preset timing path set based on the graphics processing unit (GPU) platform and the timing exception label map, so as to determine the minimum and maximum delay values ​​of the target integrated circuit.

8. A computer device comprising a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1 to 6.

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