Analog computing in-memory architecture design method and apparatus

The ACiM architecture design method enhances neural network accelerators by optimizing tile sizes and searches to improve latency, energy efficiency, and resource utilization while maintaining accuracy.

WO2026121373A1PCT designated stage Publication Date: 2026-06-11SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION +1
View PDF 0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
Filing Date
2024-12-06
Publication Date
2026-06-11

AI Technical Summary

⚠Technical Problem

Traditional Von Neumann architectures face performance bottlenecks in memory data processing and computation, leading to inefficiencies in energy consumption and data movement, which are addressed by Analog Computing in Memory (ACiM) technology for neural network accelerators.

⚗Method used

A method for designing an analog in-memory computing architecture involves obtaining tile size candidates, performing evaluations for performance and accuracy, and using multi-objective and evolutionary searches to optimize the architecture, incorporating hardware simulators for verification.

🎯Benefits of technology

The method optimizes ACiM architectures for improved latency, energy efficiency, and resource utilization by minimizing accuracy loss and addressing heterogeneous model structures.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure KR2024019970_11062026_PF_FP_ABST
    Figure KR2024019970_11062026_PF_FP_ABST
Patent Text Reader

Abstract

In an analog in-memory computing architecture design method and apparatus according to an embodiment, multiple setting values and at least one model may be obtained, and one or more first tile size candidates may be generated on the basis of the setting values. In the design method and apparatus, with respect to the at least one model, a first evaluation based on multiple performance prediction models of the first tile size candidates may be performed so as to obtain a performance prediction value for each layer of the corresponding model, and with respect to the at least one model, a second evaluation based on accuracy measurement of the first tile size candidates may be performed so as to obtain an accuracy-related value for each layer of the corresponding model. In the design method and apparatus, a multi-purpose search method may be performed on the basis of the performance prediction value for each layer and the accuracy-related value for each layer so as to obtain multiple second tile size candidates from among the first tile size candidates, and simulation based on the multiple second tile size candidates may be performed so as to output an analog in-memory computing architecture.
Need to check novelty before this filing date? Find Prior Art