Electronic device for resetting processor using pulse signals received from external electronic device, and method for operating same

Abstract

According to an embodiment, an electronic device may comprise: a wired interface including a terminal; a detection circuit configured to detect a pulse signal having a frequency higher than a designated frequency received through the wired interface; a processor; and a memory storing instructions. According to one embodiment, the instructions, when collectively or individually executed by the processor, may cause the electronic device to receive a pulse signal from an external electronic device through the wired interface while communicating with the external electronic device through the wired interface. According to an embodiment, the instructions, when collectively or individually executed by the processor, may cause the electronic device to identify whether the frequency of the pulse signal remains higher than the designated frequency for a designated time, by using the detection circuit. According to an embodiment, the instructions, when collectively or individually executed by the processor, may cause the electronic device to apply a first signal of a first level output from the detection circuit to the processor or a charger included in the electronic device, upon confirming that the frequency of the pulse signal remains higher than the designated frequency for the designated time. According to an embodiment, the instructions, when executed collectively or individually by the processor, may cause the electronic device to reset the processor on the basis of application of the first signal to the processor or the charger.

Description

Electronic device for resetting a processor using pulse signals received from an external electronic device and method of operation thereof

[0001] The present disclosure relates to an electronic device that resets a processor using pulse signals received from an external electronic device, and a method of operating the same.

[0002] Recently, along with electronic devices such as smartphones, the use of wearable electronic devices (e.g., wireless earphones) is increasing. Wearable electronic devices (e.g., wireless earphones) can be charged by being placed in a charging case (e.g., a cradle). Wearable electronic devices can be charged by contacting a connector (e.g., at least one pin) of the charging case. Wearable electronic devices (e.g., wireless earphones) can establish a communication connection with the charging case by contacting the connector of the charging case (e.g., a cradle). For example, wearable electronic devices can transmit and receive various data with the charging case through the communication connection.

[0003] According to one embodiment, the electronic device may include a wired interface comprising a terminal, a detection circuit configured to detect a pulse signal of a frequency greater than a specified frequency received through the wired interface, a processor, and a memory for storing instructions. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the electronic device to receive a pulse signal from the external electronic device through the wired interface while communicating with the external electronic device through the wired interface. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the electronic device to use the detection circuit to determine whether the frequency of the pulse signal maintains a frequency higher than the specified frequency for a specified time. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause a first signal of a first level output from the detection circuit to be applied to the processor or a charger included in the electronic device if it is determined that the frequency of the pulse signal maintains a frequency higher than the specified frequency for the specified time. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the processor to be reset based on the application of the first signal to the processor or the charger.

[0004] According to one embodiment, the method of operating an electronic device may include receiving a pulse signal from an external electronic device through a wired interface while communicating with an external electronic device through a wired interface. According to one embodiment, the method of operating the electronic device may include checking whether the frequency of the pulse signal maintains a frequency higher than the specified frequency for a specified time using a detection circuit included in the electronic device. According to one embodiment, if it is confirmed that the frequency of the pulse signal maintains a frequency higher than the specified frequency for the specified time, the method of operating the electronic device may include applying a first signal of a first level output from the detection circuit to a processor included in the electronic device or a charger included in the electronic device. According to one embodiment, the method of operating the electronic device may include resetting the processor based on applying the first signal to the processor or the charger.

[0005] According to one embodiment, the electronic device may include a wired interface comprising a terminal, a detection circuit configured to detect a pulse signal of a frequency greater than a specified frequency received from the wired interface, a processor, and a memory for storing instructions. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the electronic device to receive a pulse signal from an external electronic device through the wired interface while communicating with an external electronic device through the wired interface. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the electronic device to use the detection circuit to determine whether the frequency of the pulse signal is higher than the specified frequency. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the electronic device to apply a first signal of a first level output from the detection circuit to the processor or a charger included in the electronic device if it is determined that the frequency of the pulse signal is higher than the specified frequency. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the processor to be reset based on applying the first signal to the processor or the charger.

[0006] FIG. 1 is a block diagram of an electronic device in a network environment according to various embodiments.

[0007] FIG. 2 is a drawing for explaining a method for resetting a processor in a conventional electronic device according to one embodiment and a method for resetting a processor in an electronic device of the present invention.

[0008] FIG. 3 is a block diagram showing the schematic configuration of an electronic device and an external electronic device according to one embodiment.

[0009] FIG. 4 is a flowchart illustrating a method for an electronic device to reset a processor according to one embodiment.

[0010] FIGS. 5a, 5b, and 5c are drawings for illustrating a detection circuit of an electronic device according to one embodiment.

[0011] FIG. 6 is a flowchart illustrating the operation of a detection circuit of an electronic device according to one embodiment.

[0012] FIGS. 7a, 7b, and 7c are drawings for illustrating a detection circuit of an electronic device according to one embodiment.

[0013] FIG. 8 is a flowchart illustrating the operation of a detection circuit of an electronic device according to one embodiment.

[0014] FIGS. 9a and FIGS. 9b are drawings for explaining the operation of a detection circuit of an electronic device according to one embodiment.

[0015] FIG. 10 is a flowchart illustrating a method for an electronic device to reset a processor according to one embodiment.

[0016] FIGS. 11a and FIGS. 11b are drawings for explaining a detection circuit of an electronic device according to one embodiment.

[0017] FIGS. 12a and FIGS. 12b are drawings for explaining a detection circuit of an electronic device according to one embodiment.

[0018] FIG. 13 is a flowchart illustrating the operation of a detection circuit of an electronic device according to one embodiment.

[0019] FIG. 1 is a block diagram of an electronic device (101) in a network environment (100) according to various embodiments. Referring to FIG. 1, in the network environment (100), the electronic device (101) may communicate with an electronic device (102) through a first network (198) (e.g., a short-range wireless communication network) or may communicate with at least one of an electronic device (104) or a server (108) through a second network (199) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (101) may communicate with the electronic device (104) through a server (108). According to one embodiment, the electronic device (101) may include a processor (120), memory (130), input module (150), sound output module (155), display module (160), audio module (170), sensor module (176), interface (177), connection terminal (178), haptic module (179), camera module (180), power management module (188), battery (189), communication module (190), subscriber identification module (196), or antenna module (197). In some embodiments, at least one of these components (e.g., connection terminal (178)) may be omitted from the electronic device (101), or one or more other components may be added. In some embodiments, some of these components (e.g., sensor module (176), camera module (180), or antenna module (197)) may be integrated into a single component (e.g., display module (160)).

[0020] The processor (120) can control at least one other component (e.g., hardware or software component) of the electronic device (101) connected to the processor (120) by executing software (e.g., program (140)), for example, and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (120) can store commands or data received from other components (e.g., sensor module (176) or communication module (190)) in volatile memory (132), process the commands or data stored in volatile memory (132), and store the resulting data in non-volatile memory (134). According to one embodiment, the processor (120) may include a main processor (121) (e.g., central processing unit or application processor) or an auxiliary processor (123) that can operate independently or together with it (e.g., graphics processing unit, neural processing unit (NPU), image signal processor, sensor hub processor, or communication processor). For example, if the electronic device (101) includes a main processor (121) and an auxiliary processor (123), the auxiliary processor (123) may be configured to use lower power than the main processor (121) or to be specialized for a designated function. The auxiliary processor (123) may be implemented separately from the main processor (121) or as part thereof.

[0021] The auxiliary processor (123) may control at least some of the functions or states associated with at least one component of the electronic device (101) (e.g., display module (160), sensor module (176), or communication module (190)) on behalf of the main processor (121) while the main processor (121) is in an inactive (e.g., sleep) state, or together with the main processor (121) while the main processor (121) is in an active (e.g., application execution) state. According to one embodiment, the auxiliary processor (123) (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module (180) or communication module (190)). According to one embodiment, the auxiliary processor (123) (e.g., neural network processing unit) may include a hardware structure specialized for processing an artificial intelligence model. The artificial intelligence model may be generated through machine learning. Such learning may be performed, for example, on the electronic device (101) itself where the artificial intelligence is performed, or through a separate server (e.g., server (108)). The learning algorithm may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model may include a plurality of artificial neural network layers.An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially.

[0022] The memory (130) can store various data used by at least one component of the electronic device (101) (e.g., processor (120) or sensor module (176)). The data may include, for example, input data or output data for software (e.g., program (140)) and related commands. The memory (130) may include volatile memory (132) or non-volatile memory (134).

[0023] The program (140) may be stored as software in memory (130) and may include, for example, an operating system (142), middleware (144), or an application (146).

[0024] The input module (150) can receive commands or data to be used for a component of the electronic device (101) (e.g., processor (120)) from outside the electronic device (101) (e.g., user). The input module (150) may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0025] The sound output module (155) can output a sound signal to the outside of the electronic device (101). The sound output module (155) may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as multimedia playback or recording playback. The receiver may be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part thereof.

[0026] The display module (160) can visually provide information to an external (e.g., user) of the electronic device (101). The display module (160) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling said device. According to one embodiment, the display module (160) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of the force generated by said touch.

[0027] The audio module (170) can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module (170) can acquire sound through the input module (150) or output sound through the sound output module (155) or an external electronic device (e.g., electronic device (102)) (e.g., speaker or headphones) connected directly or wirelessly to the electronic device (101).

[0028] The sensor module (176) can detect the operating state of the electronic device (101) (e.g., power or temperature) or the external environmental state (e.g., user state) and generate an electrical signal or data value corresponding to the detected state. According to one embodiment, the sensor module (176) may include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0029] The interface (177) may support one or more specified protocols that can be used for the electronic device (101) to be connected directly or wirelessly to an external electronic device (e.g., electronic device (102)). According to one embodiment, the interface (177) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0030] The connection terminal (178) may include a connector through which the electronic device (101) can be physically connected to an external electronic device (e.g., electronic device (102)). According to one embodiment, the connection terminal (178) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0031] The haptic module (179) can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that the user can perceive through tactile or kinesthetic senses. According to one embodiment, the haptic module (179) may include, for example, a motor, a piezoelectric element, or an electric stimulation device.

[0032] The camera module (180) can capture still images and video. According to one embodiment, the camera module (180) may include one or more lenses, image sensors, image signal processors, or flashes.

[0033] The power management module (188) can manage the power supplied to the electronic device (101). According to one embodiment, the power management module (188) can be implemented, for example, as at least part of a power management integrated circuit (PMIC).

[0034] The battery (189) can supply power to at least one component of the electronic device (101). According to one embodiment, the battery (189) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0035] The communication module (190) can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between an electronic device (101) and an external electronic device (e.g., electronic device (102), electronic device (104), or server (108)), and the performance of communication through the established communication channel. The communication module (190) may include one or more communication processors that operate independently of the processor (120) (e.g., application processor) and support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (190) may include a wireless communication module (192) (e.g., cellular communication module, short-range wireless communication module, or GNSS (global navigation satellite system) communication module) or a wired communication module (194) (e.g., LAN (local area network) communication module, or power line communication module). The corresponding communication module among these communication modules can communicate with an external electronic device (104) through a first network (198) (e.g., a short-range communication network such as Bluetooth, WiFi (wireless fidelity) direct, or IrDA (infrared data association)) or a second network (199) (e.g., a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (192) can identify or authenticate the electronic device (101) within a communication network such as the first network (198) or the second network (199) using subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module (196).

[0036] The wireless communication module (192) can support 5G networks and next-generation communication technologies following 4G networks, for example, new radio access technology. NR access technology can support high-speed transmission of high-capacity data (enhanced mobile broadband (eMBB)), minimization of terminal power and connection of multiple terminals (massive machine type communications (mMTC)), or high reliability and low latency (ultra-reliable and low-latency communications (URLLC)). The wireless communication module (192) can support a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate, for example. The wireless communication module (192) can support various technologies for securing performance in the high-frequency band, such as beamforming, massive MIMO (multiple-input and multiple-output), full-dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large-scale antenna. The wireless communication module (192) can support various requirements specified in the electronic device (101), external electronic device (e.g., electronic device (104)), or network system (e.g., second network (199)). According to one embodiment, the wireless communication module (192) can support a Peak data rate (e.g., 20 Gbps or more) for realizing eMBB, loss coverage (e.g., 164 dB or less) for realizing mMTC, or U-plane latency (e.g., downlink (DL) and uplink (UL) each 0.5 ms or less, or round trip 1 ms or less) for realizing URLLC.

[0037] An antenna module (197) can transmit a signal or power to or from an external source (e.g., an external electronic device). According to one embodiment, the antenna module (197) may include an antenna comprising a radiator made of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (197) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as a first network (198) or a second network (199), may be selected from the plurality of antennas, for example, by a communication module (190). A signal or power may be transmitted or received between the communication module (190) and an external electronic device through the selected at least one antenna. According to some embodiments, in addition to the radiator, other components (e.g., a radio frequency integrated circuit (RFIC)) may be additionally created as part of the antenna module (197).

[0038] According to one embodiment, the antenna module (197) can create a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., bottom surface) of the printed circuit board and capable of supporting a specified high frequency band (e.g., mmWave band), and a plurality of antennas (e.g., array antennas) disposed on or adjacent to a second surface (e.g., top surface or side surface) of the printed circuit board and capable of transmitting or receiving a signal of the specified high frequency band.

[0039] At least some of the above components can be connected to each other via a communication method between peripheral devices (e.g., bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)) and exchange signals (e.g., commands or data) with each other.

[0040] According to one embodiment, commands or data may be transmitted or received between an electronic device (101) and an external electronic device (104) through a server (108) connected to a second network (199). Each of the external electronic devices (102, or 104) may be the same or a different type of device as the electronic device (101). According to one embodiment, all or part of the operations performed on the electronic device (101) may be performed on one or more of the external electronic devices (102, 104, or 108). For example, if the electronic device (101) needs to perform a function or service automatically or in response to a request from a user or another device, the electronic device (101) may request one or more external electronic devices to perform at least part of the function or service instead of performing the function or service itself or additionally. One or more external electronic devices that receive the above request may execute at least part of the requested function or service, or additional function or service related to the request, and transmit the result of the execution to the electronic device (101). The electronic device (101) may provide the result as is or additionally processed as at least part of the response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device (101) may provide ultra-low latency services using, for example, distributed computing or mobile edge computing. In another embodiment, the external electronic device (104) may include an Internet of Things (IoT) device. The server (108) may be an intelligent server using machine learning and / or neural networks. According to one embodiment, the external electronic device (104) or the server (108) may be included within a second network (199).The electronic device (101) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0041] Meanwhile, terms related to 'identify' in the present disclosure may be replaced with 'detect', 'recognize', 'determine', and / or 'sense'.

[0042] FIG. 2 is a drawing for explaining a method for resetting a processor in a conventional electronic device according to one embodiment and a method for resetting a processor in an electronic device of the present invention.

[0043] Referring to FIG. 2(a), according to a comparative embodiment, a conventional electronic device (209) can form a communication connection with an external electronic device (208) through a wired interface (205). The electronic device (209) can receive power from the external electronic device (208) through the wired interface (205) and can transmit and receive communication signals with the external electronic device (208) through the wired interface (205). For example, the electronic device (209) can receive power or transmit and receive communication signals with the external electronic device (208) using a single signal line.

[0044] Referring to FIG. 2(b), according to one embodiment, an electronic device (201) can form a communication connection with an external electronic device (202) through a wired interface (205). The electronic device (201), like a conventional electronic device (209), can receive power from the external electronic device (202) through the wired interface (205) and can transmit and receive communication signals with the external electronic device (202) through the wired interface (205).

[0045] Referring to FIG. 2(a), according to a comparative embodiment, the conventional electronic device (209) cannot perform normal communication functions through the wired interface (205) when the processor (292) operates abnormally. For example, the conventional electronic device (209) cannot transmit a response to a communication signal to the processor (291) of the external electronic device (208) through the wired interface (205) when the processor (292) operates abnormally. At this time, the conventional electronic device (209) can reset (or initialize) the processor (292) based on an external signal directly applied from the outside (e.g., based on the detection circuit (293) detecting the external signal). In order to reset the processor (292), the conventional electronic device (209) may require a path (e.g., a path through a separate external terminal) to apply a separate external signal in addition to the wired interface (205). Additionally, the existing electronic device (209) may require a separate configuration (e.g., a button-type switch or a Hall sensor capable of detecting magnetic force) to detect an external signal through the path. In this case, a miniaturized electronic device (e.g., earbuds) using a wired interface (205) may find it difficult to provide a separate path to reset the processor (292), and problems such as increased production costs, lack of space, and increased product weight may occur.

[0046] Referring to FIG. 2(b), according to one embodiment, the electronic device (201) can reset the processor (220) without having a path for applying a separate external signal other than the wired interface (205) and a detection circuit (293) corresponding to the path, unlike the conventional electronic device (209). For example, the electronic device (201) can detect a high-frequency pulse signal higher than a specified frequency from an external electronic device (202) through the wired interface (205) and reset the processor (220) based on the detection result. To this end, the electronic device (201) can detect the high-frequency pulse signal through a detection circuit (250) that includes a relatively simple circuit configuration.

[0047] Based on the method described above, the electronic device (201) according to one embodiment may not have a separate path for resetting the processor (220), and may reduce production costs compared to the existing electronic device (209) and enable product miniaturization and weight reduction.

[0048] FIG. 3 is a block diagram showing the schematic configuration of an electronic device and an external electronic device according to one embodiment.

[0049] Referring to FIG. 3, according to one embodiment, the electronic system may include an electronic device (201) and an external electronic device (202). The electronic device (201) may be identical or similar to the electronic device (101) of FIG. 1, and the external electronic device (202) may be identical or similar to the electronic device (102) of FIG. 1. For example, the external electronic device (202) may include at least some of the components included in the electronic device (101) of FIG. 1. For example, the electronic device (201) may include a wearable electronic device (e.g., wireless earphones) that can be worn on a user's ear, and the external electronic device (202) may include a charging case (or charging cradle) of the wearable electronic device.

[0050] According to one embodiment, an electronic device (201) can form a communication connection with an external electronic device (202) through a wired interface (205). For example, the wired interface (205) (e.g., POGO interface) may include at least one terminal (e.g., VBUS terminal and ground terminal). For example, a communication connection may be formed by contact between at least one terminal (207) of the electronic device (201) and at least one terminal (206) of the external electronic device (202). The electronic device (201) may receive power from the external electronic device (202) through the wired interface (205) and may transmit and receive communication signals with the external electronic device (202) through the wired interface (205). Meanwhile, various communication methods (e.g., time division method, or PLC method) may be applied to the communication method through the wired interface (205), and may not be limited to any one communication method.

[0051] According to one embodiment, the external electronic device (202) may include a processor (210), a charger (212), a battery (214), a port (216), and / or a coil (218).

[0052] According to one embodiment, an external electronic device (201) may receive power from an external power transmitter via a wired or wireless connection through a port (216) (e.g., a USB port) or a coil (218). A charger (212) may store the power received via a wired or wireless connection in a battery (214). Alternatively, a charger (210) may provide the received power and / or the power stored in the battery (214) to a processor (210).

[0053] According to one embodiment, the processor (210) can control the overall operation of an external electronic device (202). For example, the processor (210) can be implemented identically or similarly to the processor (120) of FIG. 1. For example, the processor (210) can be implemented as a microcontroller unit (MCU) and can perform communication functions.

[0054] According to one embodiment, the processor (210) can receive a communication signal from an electronic device (201) through a wired interface (205) and transmit a communication signal to the electronic device (201).

[0055] According to one embodiment, the processor (210) can transmit power to the electronic device (201) through a wired interface (205). For example, the processor (210) can control the components of the electronic device (201) to transmit power stored in the battery (214) to the electronic device (201).

[0056] According to one embodiment, the processor (210) can control the switch (211) to connect the wired interface (205) to a communication line (e.g., a line connecting the processor (210) and the wired interface (205)) or a power transmission line (e.g., a line connecting the charger (212) and the wired interface (205). For example, the processor (210) can control the switch (211) so that the processor (210) and the wired interface (205) are connected to each other when transmitting and receiving a communication signal to and from the electronic device (201). For example, the processor (210) can control the switch (211) so that the charger (212) and the wired interface (205) are connected to each other when transmitting power to the electronic device (201).

[0057] According to one embodiment, the processor (210) can determine whether the electronic device (201) is in an abnormal state while communicating with the electronic device (201). For example, the processor (210) can determine that the electronic device (201) is in an abnormal state when it does not receive a response to a communication signal from the electronic device (201) within a specific time.

[0058] According to one embodiment, if the processor (210) determines that the electronic device (201) is in an abnormal state while communicating with the electronic device (201), it can transmit a pulse signal having a frequency higher than a specified frequency to the electronic device (201) through a wired interface (205).

[0059] According to one embodiment, the electronic device (201) may include a processor (220), a charger (230), a battery (240), and a detection circuit (250).

[0060] According to one embodiment, the electronic device (201) can receive power from an external electronic device (202) through a wired interface (205). The charger (230) can charge the battery (240) using the power received through the wired interface (205) or supply the power charged in the battery (240) to the processor (220).

[0061] According to one embodiment, the processor (220) can control the overall operation of the electronic device (201). For example, the processor (220) may be implemented identically or similarly to the processor (120) of FIG. 1. According to one embodiment, the processor (220) can control at least one other component (e.g., hardware or software component) of the electronic device (201) connected to the processor (220) by executing software (e.g., program (140) of FIG. 1), and can perform data processing or operations based on instructions. According to one embodiment, the instructions may include instructions implemented in machine language that can be processed by the electronic device (201) or the processor (220). For example, the instructions may include instructions corresponding to operation instructions used in the program.

[0062] Meanwhile, although FIG. 2 illustrates that the electronic device (201) includes one processor (220), this is exemplary and the technical concept of the present invention may not be limited thereto. For example, the electronic device (201) may include at least one processor (e.g., CPU, DSP, GPU, and / or NPU). For example, the processor (220) may be implemented as at least one processor.

[0063] According to one embodiment, a memory (not shown) (e.g., memory (130) of FIG. 1) may store at least one instruction (or instruction) that causes at least one operation of an electronic device (201). When executed collectively or individually by a processor (220), the at least one instruction may cause the electronic device (201) to perform the corresponding operation.

[0064] According to one embodiment, the processor (220) may be implemented as a microcontroller unit (MCU) and may perform communication functions. The processor (220) may receive a communication signal from an external electronic device (202) via a wired interface (205) and transmit a communication signal to the external electronic device (202). For example, the communication signal may be implemented as a pulse signal having a frequency within a frequency range for communication. For example, the communication signal may include information for receiving power, information indicating the remaining battery level of a battery (240) included in the electronic device (201), and / or information indicating whether a terminal of the wired interface (205) (e.g., a POGO interface terminal) is in contact.

[0065] According to one embodiment, the processor (220) can control the switch (222) to connect the wired interface (205) to a communication line (e.g., a line connecting the processor (220) and the wired interface (205)) or a power transmission line (e.g., a line connecting the charger (230) and the wired interface (205). For example, the processor (220) can control the switch (222) so that the processor (220) and the wired interface (205) are connected to each other when transmitting and receiving a communication signal with an external electronic device (202). For example, the processor (220) can control the switch (222) so that the charger (230) and the wired interface (205) are connected to each other when receiving power from the external electronic device (202).

[0066] According to one embodiment, the processor (220) may be in an abnormal state while communicating with an external electronic device (202). In the abnormal state, the processor (210) cannot normally transmit or receive communication signals with the external electronic device (202). For example, in the abnormal state, the processor (210) may not be able to transmit a response to the communication signal to the external electronic device (202) within a specific time.

[0067] According to one embodiment, the detection circuit (250) can detect a pulse signal of a frequency greater than a specified frequency received from an external electronic device (202) through a wired interface (205). For example, the detection circuit (250) can receive a pulse signal from the external electronic device (202) through a first signal line branched from a signal line connected from the wired interface (205) to a charger (230) or a processor (202).

[0068] According to one embodiment, the detection circuit (250) may provide (or apply) a first signal (RST) of a level determined based on the detection result to the processor (220) and / or charger (230). For example, the specified frequency may be a reference frequency for determining a frequency range for resetting the processor (220). Additionally, the specified frequency may be a reference for distinguishing from the frequency of a signal for communication. For example, a frequency higher than the specified frequency may be different from the frequency of a communication signal (e.g., a pulse signal for communication) received through the wired interface (205).

[0069] According to one embodiment, when the external electronic device (202) fails to receive a communication signal normally from the electronic device (201), a pulse signal of a frequency higher than a specified frequency can be transmitted from the external electronic device (202) to the electronic device (201) through a wired interface (205).

[0070] According to one embodiment, the detection circuit (250) can determine whether the frequency of a pulse signal (e.g., a pulse signal received from an external electronic device (202) via a wired interface (205)) maintains a frequency higher than a specified frequency for a specified time. If the detection circuit (250) determines that the pulse signal maintains a frequency higher than a specified frequency for a specified time, it can output a first signal (RST) of a first level. If the detection circuit (250) determines that the pulse signal does not maintain a frequency higher than a specified frequency for a specified time, it can output a first signal of a second level (e.g., low level) different from the first level. For example, if the detection circuit (250) detects a pulse signal of a frequency greater than a specified frequency from the external electronic device (202) continuously for a specified time, it can output a first signal (RST) of a first level (e.g., high level). Additionally, the detection circuit (250) can output a first signal (RST) of a second level (e.g., low level) if a pulse signal of a frequency greater than the specified frequency is not detected from an external electronic device (202) continuously for a specified time.

[0071] According to another embodiment, the detection circuit (250) can determine whether the frequency of a pulse signal (e.g., a pulse signal received from an external electronic device (202) via a wired interface (205) is higher than a specified frequency. If the detection circuit (250) determines that the frequency of the pulse signal is higher than the specified frequency, it can output a first signal (RST) of a first level (e.g., high level). Alternatively, if the detection circuit (250) determines that the frequency of the pulse signal is not higher than the specified frequency, it can output a first signal (RST) of a second level (e.g., low level).

[0072] According to one embodiment, the processor (220) may be reset (or initialized) based on a first signal (RST) of a first level (e.g., high level) being provided (or applied) from the detection circuit (250).

[0073] According to one embodiment, the charger (230) may be reset (or initialized) based on a first signal (RST) of a first level (e.g., high level) being provided (or applied) from the detection circuit (250). Power may not be supplied to the battery (240) or the processor (220) until the charger (230) returns to a normal state after being reset (or initialized). At this time, the processor (220) may be reset (or initialized) based on the interruption of power supply to the processor (220).

[0074] Based on the method described above, the electronic device (201) can reset the processor (220) so that the processor (220) exits an abnormal state while the electronic device (201) is communicating with an external electronic device (202). Through this, the electronic device (201) can effectively reset the processor (220) without having a path for receiving a separate external signal to reset the processor (220).

[0075] At least some of the operations of the electronic device (201) described below may be performed by the processor (220). However, for the convenience of explanation, it will be described that the electronic device (201) performs the operations.

[0076] FIG. 4 is a flowchart illustrating a method for an electronic device to reset a processor according to one embodiment.

[0077] Referring to FIG. 4, according to one embodiment, in operation 401, an electronic device (e.g., electronic device (201) of FIG. 3) can receive a pulse signal from an external electronic device (e.g., external electronic device (202) of FIG. 3) through a wired interface (e.g., wired interface (205) of FIG. 3). According to various embodiments, the electronic device (201) can receive various types of signals (e.g., triangular pulse wave signal, square pulse wave signal, sine wave signal, or pulse signal) from the external electronic device (202) through the wired interface (205).

[0078] According to one embodiment, in operation 403, the electronic device (201) can determine, through a detection circuit (e.g., detection circuit (250) of FIG. 3), whether a signal applied through a wired interface (205) maintains a frequency higher than a specified frequency for a specified time. For example, it can determine whether the frequency of a pulse signal maintains a frequency higher than a specified frequency for a specified time.

[0079] According to one embodiment, if it is determined that the frequency of the pulse signal does not maintain a frequency higher than the specified frequency for a specified time (No in operation 403), the electronic device (201) may not reset the processor (e.g., the processor (220) of FIG. 3). Additionally, the electronic device (201) may perform operations 401 to 403 again.

[0080] According to one embodiment, if it is confirmed that the frequency of the pulse signal maintains a frequency higher than the specified frequency for a specified time (e.g., operation 403), in operation 405, the electronic device (201) may apply a first signal of a first level (e.g., high level) output from the detection circuit (250) to a processor (e.g., processor (220) of FIG. 3) or a charger (e.g., charger (230) of FIG. 3).

[0081] According to one embodiment, in operation 407, the electronic device (201) can reset the processor (220) based on the first signal of a first level (e.g., high level) being applied to the processor (220) or charger (230).

[0082] Based on the method described above, the electronic device (201) can reset the processor (220) so that the processor (220) exits an abnormal state while the electronic device (201) is communicating with an external electronic device (202). Through this, the electronic device (201) can effectively reset the processor (220) without having a path for receiving a separate external signal to reset the processor (220).

[0083] Meanwhile, for convenience of explanation, the electronic device (201) is described in this specification as receiving a pulse signal from an external electronic device (202), but the technical features of the present invention may not be limited thereto. For example, the electronic device (201) may receive various types of signals (e.g., a triangular pulse signal, a square pulse signal, a sine wave signal, or a pulse signal), and various types of signals may be used in the detection circuit (250).

[0084] FIGS. 5a, 5b, and 5c are drawings for illustrating a detection circuit of an electronic device according to one embodiment.

[0085] Referring to FIG. 5a, according to one embodiment, the detection circuit (501) may be implemented as an analog circuit of the detection circuit (250) of FIG. 2.

[0086] According to one embodiment, the detection circuit (501) may include a D-flip-flop (510), an OR gate (520), a first switch (SW1), a comparator (530), a second switch (SW2), and / or a capacitor (C2). For example, the detection circuit (501) may further include a plurality of resistors (R1, R2, R3, R4) and a capacitor (C1).

[0087] According to one embodiment, the D-flip-flop (510) may be configured to output a first output signal (Q) and a second output signal (QB) in which the first output signal (Q) is inversely inversely in accordance with a pulse signal (VPOGO) received through a wired interface (205). For example, the D-flip-flop (510) may receive a specified voltage (VDD) as a first input, and the pulse signal (VPOGO) may be received as a clock signal. For example, the first output signal (Q) may have a voltage corresponding to the specified voltage (VDD) when the pulse signal (VPOGO) is at a high level. For example, referring to FIG. 5c, the D-flip-flop (510) may transition the first output signal (Q) to a high level based on the rising edge of the pulse signal (VPOGO). For example, the rising edge of the graph (565) of the pulse signal (VPOGO) can correspond to the rising edge of the graph (559) of the first output signal (Q).

[0088] According to one embodiment, the OR gate (520) can output a first control signal that determines the on / off of the first switch (SW1) based on the signal in which the second output signal (QB) and the pulse signal (VPOGO) are inversely connected.

[0089] Referring to FIG. 5a and FIG. 5c, according to one embodiment, the comparator (530) may be configured to output a reset signal (CRL) for resetting the D-flip-flop (510) based on a first voltage (CLRP) based on a first output signal (Q) input to a first input terminal (e.g., positive input terminal) and a reference voltage (CLRN) input to a second input terminal (e.g., negative input terminal).

[0090] According to one embodiment, the first voltage (CLRP) can be determined (or increased) as in Equation 1 when the first output signal (Q) is 1. Here, R1 represents the resistance value of the first resistor (R1), C1 represents the capacitance value of the capacitor (C1), VDD may represent the voltage value of a specified voltage, and t may represent time.

[0091]

[0092] For example, the reference voltage (CRLN) can be determined as shown in Equation 2. Here, R3 represents the resistance value of the third resistor (R3), R4 represents the resistance value of the fourth resistor (R4), and VDD represents the voltage value of the specified voltage.

[0093]

[0094] At this time, the voltage of the first signal (RST) can be determined (or increased) as in Equation 3. Here, R2 represents the resistance value of the first resistor (R2), C2 represents the capacitance value of the capacitor (C2), VDD can represent the voltage value of a specified voltage, and t can represent time. For example, if the resistance values ​​and capacitance values ​​are designed such that R2*C2 is greater than R1*C1 (e.g., R2*C2 > R1*C1), the voltage of the first voltage (CRLP) can be increased sufficiently quickly.

[0095]

[0096] When the first voltage (CRLP) increases above the second voltage (CRPN), the comparator (530) can output a high-level reset signal (CRL) of the D-flip-flop (510). At this time, the D-flip-flop (510) can output a low-level first output signal (Q) and a high-level second output signal (QB). When the second output signal (QB) is at a high level, the second switch (SW2) is short-circuited, and as a result, the voltage of the first signal (RST) can be discharged to zero. For example, as the output terminal of the detection circuit (501) is short-circuited to ground, the voltage of the first signal (RST) can be discharged to zero.

[0097] According to one embodiment, when the frequency of the pulse signal is greater than a specified frequency, the pulse signal (VPOGO) may transition to a second level (e.g., low level) before the first voltage (CRLP) increases above the second voltage (CRPN). At this time, the OR gate (520) may output a first control signal of a high level based on the fact that the signal inverse of the pulse signal (VPOGO) is at a high level. The first switch (SW1) may be short-circuited based on the first control signal of a high level. As the first switch (SW1) is short-circuited, the first input terminal of the comparator (530) is connected to ground, and the first voltage (CRLP) may be discharged to O. As the first voltage (CRLP) is discharged, the reset signal (CLR) of the D-flip-flop (510) may be at a low level, and the D-flip-flop (510) may not be reset. Accordingly, the first output signal (Q) of the D-flip-flop (510) may continue to maintain a high level, and the voltage of the first signal (RST) may be increased until it is recognized as a first level (e.g., a high level). For example, the capacitor (C2) may increase the voltage of the first signal (RST) as power is charged based on the first output signal. When the voltage of the first signal (RST) is increased to a voltage corresponding to the first level, the processor (220) may be reset.

[0098] According to one embodiment, the level of the first signal may be determined as a first level or a second level based on a voltage corresponding to the power charged in the capacitor (C2). For example, the first level may be a level (e.g., a high level) for resetting the processor (220) (or charger (230)), and the second level may be a level different from the first level (e.g., a low level).

[0099] FIG. 5b may show graphs representing signals associated with a detection circuit (501) according to one embodiment.

[0100] Referring to FIG. 5b, according to one embodiment, the first graph (551) may represent the reset signal (CLR) of the D-flip-flop (510). The second graph (553) may represent the first voltage (CRLP) input to the first input terminal (e.g., positive input terminal) of the comparator (530). The third graph (555) may represent the reference voltage (CRLN) input to the second input terminal (e.g., negative input terminal) of the comparator (530). The fourth graph (557) may represent the frequency of the pulse signal (VPOGO). The fifth graph (559) may represent the first output signal (Q) of the D-flip-flop (510). The sixth graph (561) may represent the second output signal (QB) of the D-flip-flop (510). The seventh graph (563) may represent the first signal (RST) output from the detection circuit (501). The eighth graph (565) may represent the pulse signal (VPOGO). For example, the shaded portion may represent multiple pulse signals.

[0101] According to one embodiment, the first section (580) may represent a section in which the pulse signal (VPOGO) is not received. The second section (585) may represent a section in which the frequency of the pulse signal (VPOGO) is not higher than a specified frequency (e.g., 0.8 MHz). The third section (590) may represent a section in which the frequency of the pulse signal (VPOGO) becomes higher than the specified frequency. The fourth section (595) may represent a section in which the frequency of the pulse signal (VPOGO) becomes lower than the specified frequency (e.g., 0.8 MHz).

[0102] FIG. 5c may show graphs representing signals associated with a detection circuit (501) according to one embodiment.

[0103] Referring to FIG. 5c, according to one embodiment, when a pulse signal (VPOGO) is applied, the level of the first signal (RST) (563) may be changed from a second level to a first level (e.g., corresponding to a high level voltage above a specified voltage between about 1.2V and 1.4V). For example, the first voltage (CRLP) may be increased but may be reset before reaching a reference voltage (CRLN). Accordingly, the voltage of the first signal (RST) may be changed or increased to a voltage corresponding to the first level. When the pulse signal (VPOGO) is not applied, the level of the first signal (RST) may be changed from the first level to the second level. For example, the detection circuit (501) may output a first signal of the first level when a pulse signal above a specified frequency (e.g., 0.7MHz) is applied. For example, the detection circuit (501) can output a first signal (RST) (563) of a first level when a pulse signal of a specified frequency band (e.g., 0.7 MHz to 2 MHz) is applied. The processor (220) can perform a reset operation based on the first signal (RST) (563).

[0104] According to one embodiment, for example, a first signal (RST) (563) may be applied to a processor (220), and the level of the first signal (RST) (563) applied to the processor (220) may also be changed by changing the frequency of the pulse signal. For example, in the third section (590), the level of the first signal (RST) (563) may be changed from a second level to a first level (e.g., corresponding to a high level voltage above a specified voltage between about 1.2V and 1.4V). In the fourth section (595), the level of the first signal (RST) may be changed from a first level to a second level. For example, the detection circuit (501) may output a first signal of a first level from the third section (590) to the fourth section (595). For example, the processor (220) may perform a reset operation in the section between the third section (590) and the fourth section (595). Depending on the implementation, even if no frequency swing operation occurs, such as in the third section (590) and the fourth section (595), the processor (220) can perform a reset operation based on the first signal (RST) (563).

[0105] FIG. 6 is a flowchart illustrating the operation of a detection circuit of an electronic device according to one embodiment.

[0106] Referring to FIG. 6, according to one embodiment, in operation 601, a detection circuit (e.g., detection circuit (250) of FIG. 2 or detection circuit (501) of FIG. 5) can detect a pulse signal (e.g., VPOGO of FIG. 5) received from an external electronic device (e.g., external electronic device (202) of FIG. 3) through a wired interface (e.g., wired interface (205) of FIG. 3).

[0107] According to one embodiment, in operation 603, the detection circuit (501) can determine whether the frequency of the pulse signal (VPOGO) is higher than a specified frequency.

[0108] According to one embodiment, if it is confirmed that the frequency of the pulse signal (VPOGO) is not higher than the specified frequency (No in operation 603), in operation 605, the detection circuit (501) can discharge the first signal (RST in FIG. 5) to 0V. At this time, the processor (220) may not be reset.

[0109] According to one embodiment, if it is confirmed that the frequency of the pulse signal (VPOGO) is higher than the specified frequency (e.g., operation 603), in operation 607, the detection circuit (501) can increase the voltage of the first signal (RST). For example, if the detection circuit (501) continuously confirms that the pulse signal (VPOGO) is higher than the specified frequency, it can continuously maintain the voltage of the first signal (RST) in an increased state.

[0110] According to one embodiment, in operation 609, a processor (e.g., processor (220) of FIG. 3) can determine whether the voltage of the first signal (RST) output from the detection circuit (501) corresponds to a voltage corresponding to a first level (e.g., a high level). For example, the first level may represent a voltage level that the processor (220) can identify as a high level.

[0111] According to one embodiment, if it is determined that the voltage of the first signal (RST) is lower than the voltage corresponding to the first level (e.g., high level) (No in operation 609), the processor (220) may not be reset. If it is determined that the voltage of the first signal (RST) is lower than the voltage corresponding to the first level (e.g., high level) (No in operation 609), the processor (220) may perform operation 603.

[0112] According to one embodiment, if it is confirmed that the voltage of the first signal (RST) is a voltage corresponding to a first level (e.g., high level) (e.g., operation 609), in operation 611, the processor (220) can perform a reset operation based on the first signal of the first level (e.g., high level).

[0113] Based on the method described above, the electronic device (201) can reset the processor (220) so that the processor (220) exits an abnormal state while the electronic device (201) is communicating with an external electronic device (202). Through this, the electronic device (201) can effectively reset the processor (220) without having a path for receiving a separate external signal to reset the processor (220).

[0114] FIGS. 7a, 7b, and 7c are drawings for illustrating a detection circuit of an electronic device according to one embodiment.

[0115] FIGS. 7a and FIGS. 7b, according to one embodiment, may show that the detection circuit (701 or 702) is implemented as a filter circuit (710) and a comparator (720) of FIG. 2.

[0116] Referring to FIG. 7a, according to one embodiment, the detection circuit (701) may include a filter circuit (710), a comparator (720), a third capacitor (C6), and a fourth capacitor (C5).

[0117] According to one embodiment, the filter circuit (710) may be configured to pass signals in a frequency band higher than a specified frequency band. For example, the filter circuit (710) may be implemented as a high pass filter (HPF) or a rectifier circuit including a plurality of diodes.

[0118] According to one embodiment, the third capacitor (C6) may be configured to charge power based on a second signal output from the filter circuit (710). A voltage corresponding to the power charged in the third capacitor (C6) may be input to the first input terminal (e.g., positive input terminal) of the comparator (720).

[0119] According to one embodiment, the comparator (720) can output a second voltage (Vrect) based on a second signal output from the filter circuit (710) input to the first input terminal (e.g., positive input terminal) and a third signal based on a reference voltage (VREF) input to the second input terminal (e.g., negative input terminal). For example, if pulse signals (VPOGO) having a frequency higher than a specified frequency are continuously received, the filter circuit (710) can pass the corresponding pulse signals (VPOGO). Through this, a second voltage (Vrect) higher than the reference voltage can be input to the first input terminal of the comparator (720) through the third capacitor (C3). At this time, the comparator (720) can continuously output a high-level third signal.

[0120] According to one embodiment, the fourth capacitor (C5) may be configured to charge power based on a third signal. For example, the level of the first signal (RST) output from the detection circuit (701) may be determined based on a voltage corresponding to the power charged in the third capacitor (C5). For example, the level of the first signal (RST) may be determined as a first level (e.g., high level) or a second level (e.g., low level).

[0121] According to one embodiment, when pulse signals (VPOGO) having a frequency higher than a specified frequency are continuously received, a voltage corresponding to a first level (e.g., high level) can be applied to the fourth capacitor (C5). Through this, the detection circuit (701) can output a first signal of a first level (e.g., high level).

[0122] Referring to FIG. 7b, the detection circuit (702) may have an additional resistor (R5) compared to the detection circuit (701) of FIG. 7a. For example, the filter circuit (710) may be implemented as a high-pass filter (HPF) or rectifier circuit including a plurality of diodes (712, 713).

[0123] According to one embodiment, the resistor (R5) can discharge the second voltage (Vrect) input to the first input terminal of the comparator (720) when a pulse signal (VPOGO) of a frequency higher than the specified frequency is not continuously received. Through this, the voltage of the first signal (RST) can also be reduced when a pulse signal (VPOGO) of a frequency higher than the specified frequency is not continuously received. Depending on the implementation, the resistor (R5) may be omitted as in the detection circuit (701) of FIG. 7a.

[0124] In addition, the detection circuit (702) of FIG. 7b may operate in the same or similar manner as the detection circuit (701) of FIG. 7a.

[0125] Referring to FIG. 7c, the detection circuit (702) can output a first signal of a first level when a pulse signal (VPOGO) of a specified frequency band is applied, for example, when a pulse signal of a frequency higher than a specified frequency (e.g., 0.7 MHz) is applied. For example, the detection circuit (702) can output a first signal (RST) (757) of a first level when a pulse signal of a specified frequency band (e.g., 0.7 MHz to 2 MHz) is applied.

[0126] According to one embodiment, the first graph (751) may represent the frequency of the pulse signal (VPOGO). The second graph (753) may represent the pulse signal (VPOGO). The third graph (755) may represent the second voltage (Vrect). The fourth graph (757) may represent the first signal (RST) output from the detection circuit (701).

[0127] According to one embodiment, when pulse signals of a frequency higher than a specified frequency (e.g., 0.8 MHz) are continuously received, the level of the first signal (RST) may be changed from a second level to a first level. For example, the detection circuit (701 or 702) may output a first signal of a first level (e.g., a high level) in a corresponding section (e.g., a section where the voltage of the first signal (RST) is 1.2 V or higher). For example, the processor (220) may perform a reset operation in that section.

[0128] FIG. 8 is a flowchart illustrating the operation of a detection circuit of an electronic device according to one embodiment.

[0129] Referring to FIG. 8, according to one embodiment, in operation 801, a detection circuit (e.g., the detection circuit (250) of FIG. 3 or the detection circuit (701, 702) of FIG. 7a and 7b) can detect a pulse signal (VPOGO).

[0130] According to one embodiment, in operation 803, the detection circuit (701 or 702) can determine whether the frequency of the pulse signal (VPOGO) is higher than a specified frequency.

[0131] According to one embodiment, if it is determined that the frequency of the pulse signal (VPOGO) is not higher than a specified frequency (No in operation 803), in operation 805, the detection circuit (701 or 702) can reduce the voltage of the first signal (RST in FIG. 5).

[0132] According to one embodiment, if it is confirmed that the frequency of the pulse signal (VPOGO) is higher than the specified frequency (e.g., operation 803), in operation 807, the detection circuit (701 or 702) may increase the voltage of the first signal (RST). For example, if the detection circuit (701 or 702) continuously confirms that the pulse signal (VPOGO) is higher than the specified frequency, it may continuously increase the voltage of the first signal (RST).

[0133] According to one embodiment, in operation 809, a processor (e.g., processor (220) of FIG. 3) can determine whether the voltage of a first signal (RST) output from a detection circuit (701 or 702) is greater than or equal to a voltage corresponding to a first level (e.g., a high level). For example, the first level may represent a voltage level that the processor (220) can identify as a high level.

[0134] According to one embodiment, if it is determined that the voltage of the first signal (RST) is lower than the voltage corresponding to the first level (e.g., a voltage corresponding to a high level above a specified voltage between about 1.2V and 1.4V) (No in operation 809), the processor (220) may not be reset. For example, if a pulse signal (VPOGO) higher than the specified frequency is not continuously applied, the voltage of the first signal (RST) may not increase to the voltage corresponding to the first level. If it is determined that the voltage of the first signal (RST) is lower than the voltage corresponding to the first level (e.g., a high level) (No in operation 809), the processor (220) may perform operation 803.

[0135] According to one embodiment, if it is confirmed that the voltage of the first signal (RST) is greater than or equal to the voltage corresponding to the first level (e.g., high level) (e.g., operation 809), in operation 811, the processor (220) can perform a reset operation based on the first signal of the first level (e.g., high level).

[0136] Depending on the implementation, a detection circuit (701 or 702) including a filter circuit (710) compared to a detection circuit (501) implemented as an analog circuit of FIG. 6 may apply (or provide) a first signal of a first level (e.g., high level) to a processor (220) even if the frequency of the pulse signal (VPOGO) is not continuously received at a frequency greater than a specified frequency.

[0137] Based on the method described above, the electronic device (201) can reset the processor (220) so that the processor (220) exits an abnormal state while the electronic device (201) is communicating with an external electronic device (202). Through this, the electronic device (201) can effectively reset the processor (220) without having a path for receiving a separate external signal to reset the processor (220).

[0138] FIGS. 9a and FIGS. 9b are drawings for explaining the operation of a detection circuit of an electronic device according to one embodiment.

[0139] Referring to FIG. 9a, according to one embodiment, the detection circuit (901) may include a filter circuit (910) and a counter (920).

[0140] According to one embodiment, the filter circuit (910) may be implemented in the same or similar way as the filter circuit (710) described in FIG. 7a and FIG. 7b.

[0141] According to one embodiment, the counter (920) can count pulse signals higher than a specified frequency that are passed (or output) from the filter circuit (910).

[0142] According to one embodiment, the counter (920) may output a first signal (RST) of a first level (e.g., high level) when the number of times counted through the counter (920) during a specified time is greater than the specified number. Additionally, the counter (920) may output a first signal (RST) of a second level (e.g., low level) when the number of times counted through the counter (920) during a specified time is not greater than the specified number. For example, the level of the first signal (RST) may be determined based on the number of times counted through the counter (920).

[0143] Referring to FIG. 9b, according to one embodiment, in operation 951, a detection circuit (e.g., detection circuit (250) of FIG. 3 or detection circuit (901) of FIG. 9a) can detect a pulse signal (VPOGO) received from an external electronic device (e.g., external electronic device (202) of FIG. 3) through a wired interface (e.g., wired interface (205) of FIG. 3).

[0144] According to one embodiment, in operation 953, the detection circuit (901) can determine whether the frequency of the pulse signal (VPOGO) is higher than a specified frequency.

[0145] According to one embodiment, if it is determined that the frequency of the pulse signal (VPOGO) is not higher than the specified frequency (No of operation 953), the detection circuit (901) can continue to detect the received pulse signal (VPOGO) without counting the corresponding pulse signal. At this time, the processor (220) may not be reset.

[0146] According to one embodiment, if it is confirmed that the frequency of the pulse signal (VPOGO) is higher than the specified frequency (e.g., operation 953), in operation 955, the detection circuit (901) can count the corresponding pulse signal (VPOGO) through the counter (920).

[0147] According to one embodiment, in operation 957, the detection circuit (901) can determine whether the counted number is greater than the specified number. For example, the specified number may represent the number of times to confirm that a frequency higher than the specified frequency is received continuously. For example, the specified number may be set to correspond to the debounce time. For example, the specified number may be determined according to the conditions for resetting the processor (220). For example, if the conditions for resetting are relaxed, the specified number may be set to a small number, and if the conditions for resetting are strengthened, the specified number may be set to a large number.

[0148] According to one embodiment, if it is confirmed that the counted number is less than the specified number (No of operation 957), the detection circuit (901) can detect the continuously received pulse signal (VPOGO). At this time, the processor (220) may not be reset.

[0149] According to one embodiment, if it is confirmed that the counted number is greater than or equal to a specified number (e.g., operation 957), the detection circuit (901) may reset the processor (220) by applying a first signal of a first level (e.g., high level) to the processor (220) in operation 959.

[0150] Based on the method described above, the electronic device (201) can reset the processor (220) so that the processor (220) exits an abnormal state while the electronic device (201) is communicating with an external electronic device (202). Through this, the electronic device (201) can effectively reset the processor (220) without having a path for receiving a separate external signal to reset the processor (220).

[0151] FIG. 10 is a flowchart illustrating a method for an electronic device to reset a processor according to one embodiment.

[0152] Referring to FIG. 10, according to one embodiment, in operation 1001, an electronic device (e.g., electronic device (201) of FIG. 3) can receive a pulse signal from an external electronic device (e.g., external electronic device (202) of FIG. 3) through a wired interface (e.g., wired interface (205) of FIG. 3) while communicating with an external electronic device (e.g., external electronic device (202) of FIG. 3) through a wired interface (205).

[0153] According to one embodiment, in operation 1003, the electronic device (201) can determine whether the frequency of the pulse signal is higher than a specified frequency through a detection circuit (e.g., the detection circuit (250) of FIG. 3).

[0154] According to one embodiment, if it is determined that the frequency of the pulse signal is not higher than a specified frequency (No in operation 1003), the electronic device (201) may not reset the processor (e.g., the processor (220) of FIG. 3). Additionally, the electronic device (201) may perform operations 1001 to 1003 again for subsequent received pulse signals.

[0155] According to one embodiment, if it is confirmed that the frequency of the pulse signal is higher than a specified frequency (e.g., operation 1003), in operation 1005, the electronic device (201) may apply a first signal of a first level (e.g., high level) output from the detection circuit (250) to a processor (e.g., processor (220) of FIG. 3) or a charger (e.g., charger (230) of FIG. 3).

[0156] According to one embodiment, in operation 1007, the electronic device (201) can reset the processor (220) based on a first signal of a first level (e.g., high level) being applied to the processor (220) or charger (230).

[0157] Based on the method described above, the electronic device (201) can reset the processor (220) so that the processor (220) exits an abnormal state while the electronic device (201) is communicating with an external electronic device (202). Through this, the electronic device (201) can effectively reset the processor (220) without having a path for receiving a separate external signal to reset the processor (220).

[0158] FIGS. 11a and FIGS. 11b are drawings for explaining a detection circuit of an electronic device according to one embodiment.

[0159] Referring to FIG. 11a, the detection circuit (1101) may indicate that the detection circuit (1101) of FIG. 3 is implemented as an analog circuit.

[0160] According to one embodiment, the detection circuit (1101) may further include an AND gate (1140) compared to the detection circuit (501) of FIG. 5a, and may not include a second switch (SW2) and a capacitor (C2). For example, the detection circuit (1101) may include a D-flip-flop (510), an OR gate (520), a comparator (530), and a first switch (SW1), similar to the detection circuit (501) of FIG. 5a. For example, the D-flip-flop (510), the OR gate (520), the comparator (530), and the first switch (SW1) may be implemented in the same or similar manner as described in FIG. 5a.

[0161] According to one embodiment, the AND gate (1140) can output a first signal based on the first output signal (Q) of the D-flip-flop (510) and the pulse signal (VPOGO) being inversely signaled.

[0162] According to one embodiment, when a pulse signal (VPOGO) is received, the D-flip-flop (510) can output a first output signal (Q) of a first level (e.g., high level). At this time, if the frequency of the pulse signal (VPOGO) is higher than a specified frequency, the pulse signal (VPOGO) can be polled before the D-flip-flop (510) is reset. At this time, the AND gate (1140) can output a first signal of a first level (e.g., high level).

[0163] FIG. 11b may show graphs representing signals associated with a detection circuit (1101), according to one embodiment.

[0164] Referring to FIG. 11b, according to one embodiment, the first graph (1151) may represent the reset signal (CLR) of the D-flip-flop (510). The second graph (1153) may represent the first voltage (CRLP) input to the first input terminal (e.g., positive input terminal) of the comparator (530). The third graph (1155) may represent the reference voltage (CRLN) input to the second input terminal (e.g., negative input terminal) of the comparator (530). The fourth graph (1157) may represent the frequency of the pulse signal (VPOGO). The fifth graph (1159) may represent the first output signal (Q) of the D-flip-flop (510). The sixth graph (1161) may represent the second output signal (QB) of the D-flip-flop (510). The seventh graph (1163) may represent the first signal (RST) output from the detection circuit (1101). The eighth graph (1165) may represent the pulse signal (VPOGO). For example, the shaded portion may represent multiple pulse signals.

[0165] According to one embodiment, when the frequency of the pulse signal is higher than a specified frequency (e.g., 0.8 MHz), the pulse signal (VPOGO) may be polled before the D-flip-flop (510) is reset. For example, the first voltage (CRLP) may be increased but may be reset before reaching the reference voltage (CRLN). Accordingly, the pulse signal (VPOGO) may be polled before the D-flip-flop (510) is reset. At this time, as shown in the seventh graph (1165), the level of the first signal (RST) may be changed from a second level to a first level (e.g., corresponding to a voltage of 1.2 V or higher). For example, the processor (220) may perform a reset operation based on the application of the first signal (RST) of the first level.

[0166] According to one embodiment, when a pulse signal (VPOGO) higher than a specified frequency is applied, the detection circuit (1101) may output a first signal (RST) containing a voltage corresponding to a first level (e.g., a voltage higher than a high level of about 1.0V). For example, when a pulse signal higher than a specified frequency (e.g., 0.8MHz) is applied, the detection circuit (1101) may output a first signal (RST) in which the first level and the second level alternate. The processor (220) may perform an operation to reset the processor (220) based on the first signal (RST).

[0167] According to one embodiment, when a pulse signal (VPOGO) that is not higher than a specified frequency is applied, the detection circuit (1101) may output a first signal (RST) containing a voltage corresponding to a second level (e.g., a voltage of about 0V). Alternatively, the detection circuit (1101) may not output a separate signal.

[0168] Based on the method described above, the electronic device (201) can use the detection circuit (1101) to reset the processor (220) so that the processor (220) is out of an abnormal state while the electronic device (201) is communicating with an external electronic device (202).

[0169] FIGS. 12a and FIGS. 12b are drawings for explaining a detection circuit of an electronic device according to one embodiment.

[0170] Referring to FIG. 12a, according to one embodiment, the detection circuit (1201) may include a filter circuit (1210).

[0171] According to one embodiment, the filter circuit (1210) may be the same or similar to the filter circuit (710) described in FIG. 7a and 7b.

[0172] According to one embodiment, the filter circuit (1210) can pass a signal of a frequency band higher than the specified frequency band among the pulse signals. The detection circuit (1201) can determine the signal output from the filter circuit (1210) as a first signal (RST) of a first level. For example, if a signal higher than the specified frequency passes through the filter circuit (1210), the detection circuit (1201) can apply the first signal (RST) of a first level to the processor (220).

[0173] Referring to FIG. 12b, according to one embodiment, the first graph (1251) may represent the frequency of the pulse signal (VPOGO). The second graph (1253) may represent the pulse signal (VPOGO). The third graph (1257) may represent the first signal (RST) output from the detection circuit (1201).

[0174] According to one embodiment, when a pulse signal of a frequency higher than a specified frequency (e.g., 0.8 MHz) is received, the level of the first signal (RST) may be changed from a first level to a second level. For example, the detection circuit (1201) may output a first signal of a first level (e.g., a high level) in a corresponding section (e.g., a section where the voltage of the first signal (RST) is 1.2 V or higher). For example, the processor (220) may perform a reset operation in that section.

[0175] Based on the method described above, the electronic device (201) can use the detection circuit (1201) to reset the processor (220) so that the processor (220) is out of an abnormal state while the electronic device (201) is communicating with an external electronic device (202).

[0176] FIG. 13 is a flowchart illustrating the operation of a detection circuit of an electronic device according to one embodiment.

[0177] Referring to FIG. 13, according to one embodiment, in operation 1301, a detection circuit (e.g., the detection circuit (1101) of FIG. 11a or the detection circuit (1201) of FIG. 12a) can detect a pulse signal (VPOGO).

[0178] According to one embodiment, in operation 1303, the detection circuit (1101 or 1201) can determine whether the frequency of the pulse signal (VPOGO) is higher than a specified frequency.

[0179] According to one embodiment, if it is determined that the frequency of the pulse signal (VPOGO) is not higher than a specified frequency (No in operation 1303), in operation 1305, the detection circuit (1101 or 1201) may output a first signal of a second level (e.g., low level) to a processor (e.g., processor (220) of FIG. 3) or a charger (e.g., charger (230) of FIG. 3). At this time, the processor (220) may not be reset.

[0180] According to one embodiment, if it is confirmed that the frequency of the pulse signal (VPOGO) is higher than a specified frequency (e.g., operation 1303), in operation 1307, the detection circuit (1101 or 1201) may output a first signal of a first level (e.g., high level) to the processor (220) or charger (230).

[0181] According to one embodiment, in operation 1309, the processor (220) may perform a reset operation based on a first signal of a first level (e.g., high level) being output to the processor (220) or the charger (230).

[0182] Based on the method described above, the electronic device (201) can reset the processor (220) so that the processor (220) exits an abnormal state even if a pulse signal of a frequency higher than the specified frequency is not continuously received for a specified time.

[0183] According to one embodiment, an electronic device (201) may include a wired interface (205) including a terminal, a detection circuit (250, 501, 701, 702, 901) configured to detect a pulse signal of a frequency greater than a specified frequency received through the wired interface, a processor (220), and a memory (130) for storing instructions. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the electronic device to receive a pulse signal from the external electronic device through the wired interface while communicating with the external electronic device (202) through the wired interface. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the electronic device to use the detection circuit to determine whether the frequency of the pulse signal maintains a frequency higher than the specified frequency for a specified time. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause a first signal of a first level output from the detection circuit to be applied to the processor or a charger included in the electronic device if it is determined that the frequency of the pulse signal maintains a frequency higher than the specified frequency for the specified time. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the processor to be reset based on the application of the first signal to the processor or the charger.

[0184] According to one embodiment, the detection circuit may be configured to receive the pulse signal through a first signal line branched from a signal line connected from the wired interface to the charger or the processor.

[0185] According to one embodiment, when the external electronic device fails to normally receive a communication signal from the electronic device, a pulse signal of a frequency higher than the specified frequency may be transmitted from the external electronic device to the electronic device through the wired interface.

[0186] According to one embodiment, a frequency higher than the specified frequency may be different from the frequency of the communication signal received through the wired interface.

[0187] According to one embodiment, the detection circuit may include a D-flip-flop (510) configured to output a first output signal and a second output signal in which the first output signal is inversely inversely in accordance with the pulse signal received through the wired interface; a comparator (530) configured to output a reset signal for resetting the D-flip-flop based on a first voltage from the first output signal input to the first input terminal and a reference voltage input to the second input terminal; an OR gate (520) configured to output a first control signal for determining the on / off of the first switch based on the signal inversely inversely in the pulse signal and the second output signal; a first switch (SW1) configured to connect the first input terminal of the comparator to ground based on the first control signal output from the OR gate; a second switch (SW2) configured to connect the output terminal of the detection signal to ground based on the second output signal; and a first capacitor configured to charge power based on the first output signal. According to one embodiment, the level of the first signal may be determined as the first level for resetting the processor based on a voltage corresponding to the power charged in the first capacitor, or as a second level different from the first level.

[0188] According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the first switch to be controlled so that the first input terminal of the comparator is connected to ground based on the first control signal when a pulse signal higher than the specified frequency is received during the specified time. According to one embodiment, when the first input terminal of the comparator is connected to ground, a high-level voltage may be provided to the output terminal of the detection circuit through the first capacitor based on the high-level first output signal output from the D-flip-flop. According to one embodiment, based on the high-level voltage being provided to the output terminal of the detection circuit, the first signal of the first level may be applied to the processor or the charger.

[0189] According to one embodiment, the detection circuit may include a filter circuit configured to pass a signal of a frequency higher than a specified frequency, a second capacitor configured to charge power based on the second signal output from the filter circuit, a comparator configured to output a third signal based on a voltage corresponding to the power charged in the second capacitor input to a first input terminal and a reference voltage input to a second input terminal, and a third capacitor configured to charge power based on the third signal. According to one embodiment, the level of the first signal may be determined as the first level or a second level different from the first level for resetting the processor based on the voltage corresponding to the power charged in the third capacitor.

[0190] According to one embodiment, when the voltage charged in the second capacitor is not higher than the reference voltage, the voltage corresponding to the power charged in the third capacitor may be reduced. According to one embodiment, when the voltage signal charged in the second capacitor is higher than the reference voltage, the voltage corresponding to the power charged in the third capacitor may be increased.

[0191] According to one embodiment, the detection circuit may include a filter circuit configured to pass a pulse signal of a frequency higher than the specified frequency and a counter configured to count pulse signals of a frequency higher than the specified frequency output from the filter circuit. According to one embodiment, the level of the first signal may be determined as the first level for resetting the processor based on the number of times counted through the counter or as a second level different from the first level.

[0192] According to one embodiment, when the number of times counted through the counter during the specified time is greater than or equal to the reference number, the level of the first signal may be determined to the first level. According to one embodiment, when the number of times counted during the specified time is less than the reference number, the level of the first signal may be determined to the second level.

[0193] According to one embodiment, the method of operation of an electronic device (201) may include receiving a pulse signal from an external electronic device (202) through a wired interface while communicating with the external electronic device (202) through a wired interface. According to one embodiment, the method of operation of the electronic device may include checking whether the frequency of the pulse signal maintains a frequency higher than the specified frequency for a specified time using a detection circuit (250, 501, 701, 702, 901) included in the electronic device. According to one embodiment, the method of operation of the electronic device may include applying a first signal of a first level output from the detection circuit to a processor included in the electronic device or a charger included in the electronic device when it is confirmed that the frequency of the pulse signal maintains a frequency higher than the specified frequency for the specified time. According to one embodiment, the method of operation of the electronic device may include resetting the processor based on applying the first signal to the processor or the charger.

[0194] According to one embodiment, an electronic device (201) may include a wired interface (205) including a terminal, a detection circuit (250, 1101, 1201) configured to detect a pulse signal of a frequency greater than a specified frequency received from the wired interface, a processor (220), and a memory (130) for storing instructions. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the electronic device to receive a pulse signal from an external electronic device through the wired interface while communicating with an external electronic device (202) through the wired interface. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the electronic device to use the detection circuit to determine whether the frequency of the pulse signal is higher than the specified frequency. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause a first signal of a first level output from the detection circuit to be applied to the processor or a charger included in the electronic device if it is determined that the frequency of the pulse signal is higher than the specified frequency. According to one embodiment, when the instructions are executed collectively or individually by the processor, the electronic device may cause the processor to be reset based on the application of the first signal to the processor or the charger.

[0195] According to one embodiment, the detection circuit may include a D-flip-flop (510) configured to output a first output signal and a second output signal in which the first output signal is inversely

[0196] According to one embodiment, the detection circuit may include a filter circuit configured to pass a first signal having a frequency higher than the specified frequency among the pulse signals.

[0197] The electronic device according to the various embodiments disclosed in this document may be of various forms. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device according to the embodiments of this document is not limited to the devices described above.

[0198] The various embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of said embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of said items unless the relevant context clearly indicates otherwise. In this document, phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B, or C" may each include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used simply to distinguish said components from other said components and do not limit said components in any other aspect (e.g., importance or order). Where any (e.g., 1st) component is referred to as “coupled” or “connected” to another (e.g., 2nd) component, with or without the terms “functionally” or “communicationly,” it means that said any component may be connected to said other component directly (e.g., via a wire), wirelessly, or through a third component.

[0199] The term “module” as used in the various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A module may be a component formed integrally, or a minimum unit of said component or a part thereof that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0200] Various embodiments of the present document may be implemented as software (e.g., program (140)) comprising one or more instructions stored in a storage medium (e.g., internal memory (136) or external memory (138)) readable by a machine (e.g., electronic device (101)). For example, a processor (e.g., processor (120)) of the machine (e.g., electronic device (101)) may call at least one of the one or more instructions stored in the storage medium and execute it. This enables the machine to be operated to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The storage medium readable by the machine may be provided in the form of a non-transitory storage medium. Here, 'non-temporary' simply means that the storage medium is a tangible device and does not contain a signal (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily.

[0201] According to one embodiment, the method according to the various embodiments disclosed herein may be provided by being included in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or distributed online (e.g., download or upload) through an application store (e.g., Play Store™) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0202] According to various embodiments, each component (e.g., module or program) of the components described above may include a singular or multiple entities, and some of the multiple entities may be separated and placed in other components. According to various embodiments, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Generally or additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the corresponding component among the multiple components prior to integration. According to various embodiments, operations performed by the module, program, or other components may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

1. In an electronic device (201), Wired interface (205) including a terminal; A detection circuit (250, 501, 701, 702, 901) configured to detect a pulse signal of a frequency greater than a specified frequency received through the wired interface; processor (220); and The electronic device includes a memory (130) for storing instructions, and when the instructions are executed collectively or individually by the processor, the electronic device, While communicating with an external electronic device (202) through the wired interface, a pulse signal is received from the external electronic device through the wired interface, Using the above detection circuit, check whether the frequency of the pulse signal maintains a frequency higher than the specified frequency for a specified time, and If it is confirmed that the frequency of the pulse signal maintains a frequency higher than the specified frequency during the specified time, a first signal of a first level output from the detection circuit is applied to the processor or a charger included in the electronic device, and An electronic device that causes the processor to be reset based on applying the first signal to the processor or the charger.

2. In Paragraph 1, The above detection circuit is an electronic device configured to receive the pulse signal through a first signal line branched from a signal line connected from the wired interface to the charger or the processor.

3. In any one of paragraphs 1 to 2, An electronic device in which, when the external electronic device fails to normally receive a communication signal from the electronic device, a pulse signal of a frequency higher than the specified frequency is transmitted from the external electronic device to the electronic device through the wired interface.

4. In any one of paragraphs 1 through 3, An electronic device characterized in that a frequency higher than the specified frequency is different from the frequency of a communication signal received through the wired interface.

5. In any one of paragraphs 1 to 4, the detection circuit is, A D-flip-flop configured to output a first output signal and a second output signal in which the first output signal is inversely inverse, based on the pulse signal received through the wired interface; A comparator configured to output a reset signal for resetting the D-flip-flop based on a first voltage from the first output signal input to the first input terminal and a reference voltage input to the second input terminal; An OR gate configured to output a first control signal that determines the on / off of the first switch based on the inverse signal of the pulse signal and the second output signal; A first switch configured to connect the first input terminal of the comparator to ground based on the first control signal output from the OR gate; A second switch configured to connect the output terminal of the detection signal to ground based on the second output signal; and It includes a first capacitor configured to charge power based on the first output signal, and An electronic device in which the level of the first signal is determined as the first level or a second level different from the first level for resetting the processor based on a voltage corresponding to the power charged in the first capacitor.

6. In any one of claims 1 to 5, when the instructions are executed collectively or individually by the processor, the electronic device, If a pulse signal higher than the specified frequency is received during the specified time, the first switch is controlled to be connected to the first input terminal of the comparator and ground based on the first control signal, and When the first input terminal of the comparator is connected to ground, a high-level voltage is provided to the output terminal of the detection circuit through the first capacitor based on the high-level first output signal output from the D-flip-flop, and An electronic device in which the first signal of the first level is applied to the processor or the charger based on the above high-level voltage being provided to the output terminal of the detection circuit.

7. In any one of paragraphs 1 to 6, the detection circuit, A filter circuit configured to pass signals of a frequency higher than a specified frequency; A second capacitor configured to charge power based on the second signal output from the filter circuit; A comparator configured to output a third signal based on a voltage corresponding to the power charged in the second capacitor input to the first input terminal and a reference voltage input to the second input terminal; and It includes a third capacitor configured to charge power based on the third signal, and An electronic device in which the level of the first signal is determined as the first level or a second level different from the first level for resetting the processor based on a voltage corresponding to the power charged in the third capacitor.

8. In any one of paragraphs 1 through 7, When the voltage charged in the second capacitor is not higher than the reference voltage, the voltage corresponding to the power charged in the third capacitor is reduced, and An electronic device in which, when the voltage signal charged in the second capacitor is higher than the reference voltage, the voltage corresponding to the power charged in the third capacitor is increased.

9. In any one of claims 1 to 8, the detection circuit is, A filter circuit configured to pass a pulse signal with a frequency higher than the specified frequency; and It includes a counter configured to count pulse signals higher than the specified frequency output from the filter circuit, and An electronic device in which the level of the first signal is determined as the first level or a second level different from the first level for resetting the processor based on the number of times counted through the counter.

10. In any one of paragraphs 1 through 9, When the number of times counted through the counter during the specified time is greater than or equal to the reference number, the level of the first signal is determined to be the first level, and An electronic device in which the level of the first signal is determined to be the second level when the number of times counted during the specified time is less than the reference number.

11. In the method of operating the electronic device (201), While communicating with an external electronic device (202) through a wired interface (205), the operation of receiving a pulse signal from the external electronic device through the wired interface; An operation to determine whether the frequency of the pulse signal maintains a frequency higher than the specified frequency for a specified time using a detection circuit (250, 501, 701, 702, 901) included in the electronic device; If it is confirmed that the frequency of the pulse signal maintains a frequency higher than the specified frequency during the specified time, the operation of applying a first signal of a first level output from the detection circuit to a processor (220) included in the electronic device or a charger (230) included in the electronic device; and A method of operation of an electronic device comprising an operation to reset the processor based on applying the first signal to the processor or the charger.

12. In Paragraph 11, The above detection circuit is a method of operation of an electronic device configured to receive the pulse signal through a first signal line branched from a signal line connected to the charger or the processor from the wired interface.

13. In any one of paragraphs 11 to 12, A method of operation of an electronic device characterized in that a frequency higher than the specified frequency is different from the frequency of a communication signal received through the wired interface.

14. In any one of claims 11 to 13, the detection circuit is, A D-flip-flop configured to output a first output signal and a second output signal in which the first output signal is inversely inverse, based on the pulse signal received through the wired interface; A comparator configured to output a reset signal for resetting the D-flip-flop based on a first voltage from the first output signal input to the first input terminal and a reference voltage input to the second input terminal; An OR gate configured to output a first control signal that determines the on / off of the first switch based on the inverse signal of the pulse signal and the second output signal; A first switch configured to connect the first input terminal of the comparator to ground based on the first control signal output from the OR gate; A second switch configured to connect the output terminal of the detection signal to ground based on the second output signal; and It includes a first capacitor configured to charge power based on the first output signal, and A method of operation of an electronic device in which the level of the first signal is determined as the first level or a second level different from the first level for resetting the processor based on a voltage corresponding to the power charged in the first capacitor.

15. In any one of claims 11 to 14, the detection circuit is, A filter circuit configured to pass signals of a frequency higher than a specified frequency; A second capacitor configured to charge power based on the second signal output from the filter circuit; A comparator configured to output a third signal based on a voltage corresponding to the power charged in the second capacitor input to the first input terminal and a reference voltage input to the second input terminal; and It includes a third capacitor configured to charge power based on the third signal, and A method of operation of an electronic device in which the level of the first signal is determined as the first level or a second level different from the first level for resetting the processor based on a voltage corresponding to the power charged in the third capacitor.

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