Heterogeneous inference acceleration
WO2026122331A1PCT designated stage Publication Date: 2026-06-11ATI TECHNOLOGIES ULC +1
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- ATI TECHNOLOGIES ULC
- Filing Date
- 2025-11-21
- Publication Date
- 2026-06-11
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Figure US2025056539_11062026_PF_FP_ABST
Abstract
The embodiments herein describe techniques for performing ML compilation using a unified interface that combines different processors in a heterogeneous processing system which allows for intelligent partitioning of a ML model. Unlike prior solutions which rely on user preferences to assign the ML model, the unified interface can violate or break the user preferences when partitioning the ML model. The unified interface can receive information from the processors (e.g., a NPU, CPU, GPU, etc.) and determine the capabilities, current workload, power metrics, subgraphs of the ML model they can execute, and the like. With this information, the unified interface can intelligently choose when to violate or break the user-entered priority based instructions.
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