Chip package

Abstract

The present application discloses a chip package. The chip package comprises: a base circuit board, a chip unit, an encapsulation layer, and a plurality of connecting members. The chip unit is fixedly mounted in a corresponding mounting through slot. A chip of the chip unit is fixedly connected to a first side of a metal substrate. The encapsulation layer is attached to a first side of the base circuit board. One end of each connecting member is connected to a corresponding electrode of the chip, and the other end of each connecting member extends to a first side of the encapsulation layer to be exposed. The connecting members comprise a first connecting member. One end of the first connecting member is connected to a second side of the metal substrate to connect the chip, and the other end of the first connecting member extends to a board edge region along a second side of the base circuit board and then vertically extends to the side of the encapsulation layer distant from the base circuit board to be exposed. In this way, the present application can take both internal electrical insulation of the connecting members of the chip package and internal wiring of the chip package into consideration.

Description

Chip package [Technical Field]

[0001] This application relates to the field of chip packaging technology, and in particular to chip packages. [Background Technology]

[0002] With the ongoing transformation of the global energy structure, electricity has become an increasingly important form of energy. Power chips are characterized by high conversion efficiency, but current packaging methods have excessively large parasitic parameters, which affect the switching frequency of power chips.

[0003] Embedding power chips into printed circuit boards is one of the best solutions for reducing integration parameters.

[0004] However, after the power chip is embedded in the printed circuit board, the chip's connectors need to be internally electrically insulated to prevent leakage or electrical breakdown between different transmission networks. The internal electrical insulation setting requires a certain amount of space, which can easily conflict with the internal wiring of the chip package. [Summary of the Invention]

[0005] This application provides a chip package to address the compatibility issues between internal electrical insulation settings and internal traces within the chip package.

[0006] To address the aforementioned technical problems, this application provides a chip package comprising: a base circuit board, at least one chip unit, a molding compound, and multiple connectors. At least one mounting slot is formed on the base circuit board, and the chip unit is fixedly mounted within a corresponding mounting slot. Each chip unit includes at least one metal substrate and at least one chip, with the chip fixedly connected to a first side of the metal substrate. A second side of the metal substrate is flush with a second side of the base circuit board, and the second side of the base circuit board is opposite to the first side of the base circuit board. The molding compound is bonded to the first side of the base circuit board and fills the gap between the base circuit board and the at least one chip unit. One end of each connector is connected to a corresponding electrode of the chip, and the other end of each connector extends to the first side of the molding compound for exposure. Each connector includes a first connector, one end of which connects to the chip via a connection to the second side of the metal substrate, and the other end of the first connector extends along the second side of the base circuit board to the edge region of the board, and then extends vertically to the side of the molding compound away from the base circuit board for exposure.

[0007] The first connector includes a first extension and a first vertical member connected in sequence; one end of the first extension is connected to the second side of the metal substrate, and the other end of the first extension extends along the second side of the base circuit board to the edge region of the board; the first vertical member is located in the edge region of the board, one end of the first vertical member is connected to the other end of the first extension, and the other end of the first vertical member extends vertically to the side of the molding layer away from the base circuit board for exposure.

[0008] The molding layer includes a filler layer, a first layer, and a second layer. The filler layer is disposed in the mounting slot. The second layer is stacked and bonded to the first side of the base circuit board, and the first layer and the second layer are stacked and bonded to the side away from the base circuit board.

[0009] The first vertical component includes a first conductive component, a second connecting hole, and a first connecting hole connected in sequence; the first conductive component is disposed in the base circuit board, the first connecting hole is disposed in the first layer, and the second connecting hole is disposed in the second layer; one end of the first conductive component is connected to the other end of the first extension component, the other end of the first conductive component is connected to one end of the second connecting hole, and the end of the first connecting hole away from the second connecting hole is exposed on the side of the first layer away from the base circuit board.

[0010] The connector further includes a second connector; the second connector includes a cross member, a second extension member, and a second vertical member connected in sequence; one end of the cross member is connected to the first side of the chip, and the other end of the cross member extends on the side of the second layer away from the base circuit board to reach the first side of the base circuit board; one end of the first extension member is connected to the other end of the cross member, and the other end of the first extension member extends along the first side of the base circuit board to the edge area of ​​the board; the first vertical member is disposed in the molding layer and located in the edge area of ​​the board, one end of the first vertical member is connected to the other end of the first extension member, and the other end of the first vertical member penetrates the second layer and the first layer until it is exposed on the first side of the molding layer.

[0011] The connector further includes a second connector; the second connector includes a cross member, a second conductive member, a third extension member, and a third vertical member connected in sequence; one end of the cross member is connected to the first side of the chip, and the other end of the cross member extends on the side of the second layer away from the base circuit board to reach the first side of the base circuit board; the second conductive member is disposed within the base circuit board, one end of the second conductive member is connected to the other end of the cross member on the first side of the base circuit board, and the other end of the second conductive member extends vertically to the second side of the base circuit board; the third extension member is disposed on the second side of the base circuit board, one end of the third extension member is connected to the other end of the second conductive member, and the other end of the third extension member extends along the second side of the base circuit board to the edge area of ​​the board; the third vertical member is disposed within the base circuit board, the second layer, and the first layer, one end of the third vertical member is connected to the other end of the third extension member in the edge area of ​​the board on the second side of the base circuit board, and the other end of the third vertical member extends vertically to the side of the first layer away from the second layer for exposure.

[0012] The connector also includes a third connector; the third connector is disposed in the first layer and the second layer, one end of the third connector is connected to the first side of the chip, and the other end of the third connector is exposed on the side of the first layer away from the second layer.

[0013] The chip package also includes conductive lines; the conductive lines are arranged in one or more of the following areas: the side of the second layer away from the base circuit board, the side of the first layer away from the base circuit board, and the first side of the base circuit board; wherein the conductive lines are connected to a third connector, and the distance between the conductive lines and other connectors is greater than 0.3 mm.

[0014] The chip package further includes: a heat dissipation device; the heat dissipation device is attached to the second side of the base circuit board, the second side of the base circuit board being the opposite side of the first side of the base circuit board; the heat dissipation device includes an insulating plate and a heat sink; the insulating plate is fixed and attached to the second side of the base circuit board, and the heat sink is fixed and attached to the side of the insulating plate away from the base circuit board.

[0015] The insulating board includes a first metal layer, an insulating layer, and a second metal layer that are stacked and bonded together in sequence. The second metal layer is also bonded to the side of the heat sink near the metal substrate. The first metal layer is also bonded to the second side of the base circuit board and the second side of the metal substrate. The length of the side connection path between the side of the first metal layer and the heat sink is greater than 0.3 mm.

[0016] To address the aforementioned technical problems, the chip package of this application connects to the chip via a first connector, one end of which is connected to the second side of a metal substrate. The other end of the first connector extends along the second side of the base circuit board to the edge region of the board, and then extends vertically to the side of the molding compound away from the base circuit board for exposure. This allows for the extraction of the second-side electrode signals of the chip through the first connector, while providing a larger space on the side of the first connector near the molding compound for conductive wiring and increased insulation spacing between the first connector and other connection networks, thereby increasing the wiring freedom of the chip package. In other words, this application provides a connection structure that is compatible with the internal electrical insulation and internal wiring of the chip package's connectors. [Attached Image Description]

[0017] Figure 1 is a schematic diagram of the structure of the first embodiment of the chip package provided in this application;

[0018] Figure 2 is a schematic diagram of the structure of the second embodiment of the chip package provided in this application;

[0019] Figure 3 is an enlarged schematic diagram of the first connector in Figure 2;

[0020] Figure 4 is an enlarged schematic diagram of the second connector in Figure 2;

[0021] Figure 5 is a partial structural diagram of the metal substrate and the heat sink;

[0022] Figure 6 is a structural schematic diagram of the third embodiment of the chip package provided in this application;

[0023] Figure 7 is a structural schematic diagram of the fourth embodiment of the chip package provided in this application;

[0024] Figure 8 is an enlarged schematic diagram of the second connector in Figure 7. 【Detailed Implementation Methods】

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0027] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0028] Please refer to Figure 1, which is a schematic diagram of the structure of the first embodiment of the chip package provided in this application.

[0029] The chip package 100 of this embodiment includes: a base circuit board 110, at least one chip unit 112, a molding layer 140, and a plurality of connectors 150.

[0030] The base circuit board 110 is a pre-fabricated PCB (Printed Circuit Board) that serves as the basic framework for embedding the chip 130; the circuitry within the base circuit board 110 is patterned. The base circuit board 110 can be a multilayer board with only through-hole interconnects, or an HDI (High Density Interconnect) board with blind via interconnects. The specific structure of the base circuit board 110 is determined based on actual requirements (not shown in the figure). At least one mounting slot 111 is formed on the base circuit board 110, and the number of mounting slots 111 corresponds to the number of chip units 112.

[0031] The chip unit 112 is fixedly installed in the corresponding mounting slot 111. The chip unit 112 includes at least one metal substrate 120 and at least one chip 130. The chip 130 may include a power chip, such as an IGBT (Insulated-Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or other devices such as diodes, electron tubes, electromechanical components, etc., which are not specifically limited here. The metal substrate 120 may be made of copper, molybdenum copper, tungsten copper, etc., to conduct heat and electricity to the chip 130. Its coefficient of thermal expansion (CTE) is 5 to 20 ppm / ℃. This range of CTE matches the expansion coefficient of the chip 130, thereby maintaining structural stability between the thermal expansion of the chip 130 and the metal substrate 120, reducing stress caused by the difference in thermal expansion, and improving the connection stability between the chip 130 and the metal substrate 120.

[0032] The chip package 100 may include multiple chip units 112, and each chip unit 112 may include multiple chips 130, depending on actual needs.

[0033] The chip unit 112 is fixedly installed in the corresponding mounting slot 111. One or more chip units 112 can be disposed on a base circuit board 110. The first side 117 of the base circuit board 110, the first side 121 of the metal substrate 120, and the first side of the chip 130 are on the same side.

[0034] Chip 130 is fixedly connected to the first side 121 of metal substrate 120; in this embodiment, the first side 121 of metal substrate 120 is a planar base. The second side 122 of metal substrate 120 is flush with the second side 116 of base circuit board 110, and the second side 116 of base circuit board 110 is the opposite side of the first side 117 of base circuit board 110. The first side of chip 130 is flush with the first side 117 of base circuit board 110 so that the connector 150 can lead out signals from the first side of chip 130. In this embodiment, the flush alignment is not required to be absolutely perfect; in actual operation, the error can be within ±20%.

[0035] The molding compound 140 is bonded to the first side 117 of the base circuit board 110 and fills the gap between the base circuit board 110 and at least one chip unit 112 for insulating encapsulation and device fixation. The molding compound 140 includes, but is not limited to, one or more insulating materials such as epoxy resin, polyester resin (PET), polyimide, polyimide, polycarbonate (PC), bismaleimide triazine (BT), Ajinomoto build film (ABF), FR4 resin, and ceramic matrix.

[0036] One end of each connector 150 is connected to the corresponding electrode of the chip 130, and the other end of each connector 150 extends to the first side of the molding layer 140 for exposure, so as to bring out the signal of the chip 130 to the outside.

[0037] The connector 150 includes a first connector 151. One end of the first connector 151 is connected to the second side 122 of the metal substrate 120 to connect to the chip 130. The other end of the first connector 151 extends along the second side 116 of the base circuit board 110 to the board edge region 190, and then extends vertically to the side of the molding compound 140 away from the base circuit board 110 for exposure. The board edge region 190 is a region with a certain width at the edge of the entire chip package 100. When the connector 150 is located in the board edge region 190, it does not mean that it is exposed outside the edge. The board edge region 190 is arranged around the chip package 100.

[0038] The chip package 100 needs to guide the signals of the chip 130 to the edge region 190 of the board for connection with external devices. The chip package 100 may include multiple chips 130. When guiding the signals of multiple chips 130 to the edge region 190 of the board, lateral traces are often required. However, these lateral traces are prone to routing conflicts with other conductive lines within the chip package 100. Therefore, in this embodiment, the first connector 151 is disposed on the second side 122 of the metal substrate 120. The electrode signals of the second side of the chip 130 are led out from below, and after being transmitted to the edge region 190 of the board, they are vertically led upward to the edge of the molding compound 140 on the side away from the base circuit board 110. This allows the side of the first connector 151 near the molding compound 140 to have a larger space for conductive line routing and to increase the insulation distance between the first connector 151 and other connection networks.

[0039] The second side 116 of the base circuit board 110 can be insulated from the outside world by means of pressing an insulating layer or setting other insulating structures, which is not limited here.

[0040] With the above structure, in this embodiment, the chip package connects to the chip via one end of the first connector, which is connected to the second side of the metal substrate. The other end of the first connector extends along the second side of the base circuit board to the edge region of the board, and then extends vertically to the side of the molding compound away from the base circuit board for exposure. This allows for the extraction of the second-side electrode signal of the chip through the first connector, while providing a larger space on the side of the first connector near the molding compound for conductive wiring and insulation spacing between the first connector and other connection networks, increasing the wiring freedom of the chip package. In other words, this application provides a connection structure that is compatible with the internal electrical insulation and internal wiring of the chip package's connectors.

[0041] Please refer to Figure 2, which is a schematic diagram of the structure of the second embodiment of the chip package provided in this application.

[0042] The positions and connections between the base circuit board 210, at least one chip unit, molding layer L, and multiple connectors in the chip package 200 of this embodiment are the same as in the previous embodiment. Furthermore, this embodiment also includes:

[0043] In some embodiments, the first connector 270 includes a first extension 271 and a first vertical member 272 connected in sequence.

[0044] One end of the first extension member 271 is connected to the second side of the metal substrate 230, and the other end of the first extension member 271 extends along the second side of the base circuit board 210 to the edge region of the board. The directional positions of the first side, the second side, and the edge region of the board in this embodiment are similar to those in the previous embodiments and will not be described again.

[0045] The first vertical member 272 is located in the edge area of ​​the board. One end of the first vertical member 272 is connected to the other end of the first extension member 271. The other end of the first vertical member 272 extends vertically to the side of the molding layer L away from the base circuit board 210 for exposure.

[0046] The aforementioned structure transmits the signal from the second side of chip 220 through the metal substrate 220 to its second side. The first extension 271 then laterally guides the signal to the edge region of the board, and the first vertical member 272 leads the signal upwards within the edge region to the side of the molding compound L away from the base circuit board 210, facilitating external connections. This connector structure provides ample space on the side of the first connector 270 near the molding compound L for wiring of the conductive lines 290 and for increasing insulation distance between the first connector 270 and other connection networks.

[0047] In some embodiments, the molding compound L includes a filler layer L0, a first layer L1, and a second layer L2. The filler layer L0 is disposed within the mounting slot 211, filling the gap between the mounting slot 211 and the chip unit. The second layer L2 is stacked and bonded to a first side of the base circuit board 210, and the first layer L1 and the second layer L2 are stacked and bonded to the side of the base circuit board 210 away from the base circuit board 210. The filler layer L0, the first layer L1, and the second layer L2 are fused together after being pressed.

[0048] Please refer to Figure 3 for further details. Figure 3 is an enlarged schematic diagram of the first connector in Figure 2.

[0049] In some embodiments, the first vertical member 272 includes a first conductive member 2723, a second connecting hole 2722, and a first connecting hole 2721 connected in sequence.

[0050] The first conductive element 2723 is disposed within the base circuit board 210, the first connecting hole 2721 is disposed within the first layer L1, and the second connecting hole 2722 is disposed within the second layer L2.

[0051] One end of the first conductive member 2723 is connected to the other end of the first extension member 271, and the other end of the first conductive member 2723 is connected to one end 2722 of the second connecting hole. The end of the first connecting hole 2721 away from the second connecting hole 2722 is exposed on the side of the first layer L1 away from the base circuit board 210.

[0052] In a specific application scenario, the second connecting hole 2722 and the first conductive member 2723 can be connected in a staggered manner, that is, the end of the second connecting hole 2722 away from the first layer L1 and the end of the first conductive member 2723 away from the first extension member 271 are connected by a staggered member 2724. In another specific application scenario, the second connecting hole 2722 and the first conductive member 2723 can also be connected perpendicularly, that is, without the staggered member 2724. The specific configuration is based on the process or actual requirements.

[0053] In this embodiment, the first conductive element 2723 is a metallized through-hole on the base circuit board 210, and the second connecting hole 2722 and the first connecting hole 2721 are metallized blind holes in the second layer L2 and the first layer L1, respectively, and have corresponding electrical conductivity. If the first layer L1 and the second layer L2 are laminated in one step, the metallized blind holes in the first layer L1 and the second layer L2 may not be fully filled by electroplating due to the excessive thickness of the single lamination. Therefore, by using a dual configuration of the first layer L1 and the second layer L2, and a double-stacked hole design corresponding to the second connecting hole 2722 and the first connecting hole 2721, the thickness of the molding layer L on the first side of the base circuit board 210 and the conductivity of the first vertical element 272 are simultaneously ensured.

[0054] In some embodiments, the connector further includes a second connector 250, which includes a transverse member 251, a second extension member 252, and a second vertical member 253 connected in sequence.

[0055] One end of the cross member 251 is connected to the first side of the chip 220, specifically to the transmission electrode on that side. The other end of the cross member 251 extends on the side of the second layer L2 away from the base circuit board 210 to reach the first side of the base circuit board 210. The cross member 251 is used to transmit the signal from the transmission electrode on the first side of the chip 220 to the first side of the base circuit board 210.

[0056] One end of the second extension 252 is connected to the other end of the cross member 251, and the other end of the second extension 252 extends along the first side of the base circuit board 210 to the edge region of the board. The second extension 252 is used to transmit the signal of the transmission electrode on the first side of the chip 220 to the edge of the first side of the base circuit board 210.

[0057] The second vertical member 253 is disposed in the edge region of the board within the molding layer L. One end of the second vertical member 253 is connected to the other end of the second extension member 252, and the other end of the second vertical member 253 penetrates through the second layer L2 and the first layer L1 until the first side of the molding layer L is exposed. The second vertical member 253 is used to vertically transmit signals from the edge of the first side of the base circuit board 210 to the outer edge of the first layer L1 for external connection.

[0058] The end of the second connector 250 away from the chip 220 extends horizontally on the side of the second layer L2 away from the base circuit board 210 to the first side of the base circuit board 210. This results in a distance equal to the thickness of the second layer L2 + the fill layer L0 between this part of the second connector 250 and the first side of the metal substrate 230, thereby increasing the distance between the second connector 250 and the metal substrate 230. The molding layer L provides insulation, thereby reducing the occurrence of leakage or electrical breakdown between the second connector 250 and the metal substrate 230. This ensures the electrical insulation characteristics between the metal substrate 230 and the second connector 250. Furthermore, the portion of the second connector 250 spanning the metal substrate 230 is sandwiched between the first layer L1 and the second layer L2, which further reduces leakage or electrical breakdown between the second connector 250 and the outside world, further improving the overall insulation effect, safety, and reliability of the chip package 200.

[0059] The above structure, by combining the transverse member 251 with the metal substrate 230 disposed on the first side plane, increases the vertical distance between the second connector 250 and the metal substrate 230, another transmission network at the bottom of the chip 220, reducing the occurrence of leakage or electrical breakdown between the second connector 250 and the metal substrate 230, and ensuring the electrical insulation characteristics between the metal substrate 230 and the second connector 250. The second extension member 252 extends towards the edge on the first side of the base circuit board 210, freeing up space between the first layer L1 and the second layer L2 on the second extension member 252 to facilitate wiring of the conductive lines 290. Furthermore, the second connector 250 vertically guides the signal from the first side edge of the base circuit board 210 to the edge of the first layer L1 away from the base circuit board 210, thereby facilitating external connections.

[0060] In some embodiments, the thickness of the lines and connectors disposed on the first side of the base circuit board 210 can be greater than or equal to 100 micrometers to meet the conduction requirements of various connectors and lines.

[0061] Please refer to Figure 4 for further details. Figure 4 is an enlarged schematic diagram of the second connector in Figure 2.

[0062] In some embodiments, the span 251 includes a third connecting hole 2511, a span portion 2512, and a fourth connecting hole 2513 connected in sequence; wherein, each connecting hole in this embodiment is a metallized hole with conductive capability.

[0063] The third connection hole 2511 and the fourth connection hole 2513 are disposed in the second layer L2, and the transverse portion 2512 is attached to the side of the second layer L2 away from the base circuit board 210; one end of the third connection hole 2511 is connected to the first side of the chip 220, the other end of the third connection hole 2511 is connected to one end of the transverse portion 2512, the other end of the transverse portion 2512 is connected to one end of the fourth connection hole 2513, and the other end of the fourth connection hole 2513 is connected to one end of the second extension 252 on the first side of the base circuit board 210.

[0064] The third connecting hole 2511, the cross section 2512 and the fourth connecting hole 2513 form a bridge structure. The cross section 251 is first led up to the second layer L2 through the third connecting hole 2511, crosses the second surface 232 and then led down to the first side of the base circuit board 210, thereby increasing the distance upward. The metal substrate 230 is provided in the mounting slot 211 to increase the distance downward, thereby doubly increasing the distance between the second connecting member 250 and the metal substrate 230.

[0065] The second vertical member 253 includes a fifth connecting hole 2531 and a sixth connecting hole 2532 connected in sequence. The fifth connecting hole 2531 is disposed in the second layer L2, and the sixth connecting hole 2532 is disposed in the first layer L1. One end of the fifth connecting hole 2531 is connected to the other end of the second extension member 252, and the end of the sixth connecting hole 2532 away from the fifth connecting hole 2531 is exposed on the first side of the molding layer L. The fifth connecting hole 2531 and the sixth connecting hole 2532 form a vertical stacked hole to guide the signal upward. In order to prevent the second connector 250 from leaking electricity to the outside, a sufficient thickness needs to be set on the molding layer L on the first side of the base circuit board 210. However, if the first layer L1 and the second layer L2 are pressed together at once, the second vertical component 253 will not be able to be fully electroplated due to the excessive thickness of the single pressing. Therefore, by setting the first layer L1 and the second layer L2 and the corresponding double stacked hole design of the second vertical component 253, the thickness of the molding layer L on the first side of the base circuit board 210 and the conductivity of the second vertical component 253 are ensured at the same time.

[0066] In some embodiments, a gate and a transmission electrode are disposed on a first side of the chip 220, and another transmission electrode is disposed on a second side of the chip 220. A metal substrate 230 is connected to a transmission electrode on the second side of the chip 220, and a first connector 270 is connected to the second side of the metal substrate 230, thereby guiding the signal from the transmission electrode on the second side of the chip 220 to the exposed molding layer through the metal substrate 230 and the first connector 270 for interfacing with external devices.

[0067] Chip 220 includes power chips such as insulated gate bipolar transistors (IGBT chips) or metal-oxide-semiconductor field-effect transistors (MOS chips).

[0068] The transfer electrode (not shown) includes a current input stage and a current output stage. When chip 220 is an insulated-gate bipolar transistor, the transfer electrode can be the emitter or collector; when chip 220 is a metal-oxide-semiconductor field-effect transistor, the transfer electrode can be the source or drain. The specific types of the transfer electrode connected to the second connector 250 and the other transfer electrode connected to the metal substrate 230 can be arbitrarily set or interchanged based on the chip type and actual needs, and are not limited here. For example, when chip 220 is a metal-oxide-semiconductor field-effect transistor, the electrode connected to the second connector 250 can be the source and the electrode connected to the metal substrate 230 can be the drain; or the electrode connected to the second connector 250 can be the drain and the electrode connected to the metal substrate 230 can be the source.

[0069] Please refer back to Figure 2. In some embodiments, the chip package 200 further includes a third connector 280; one end of the third connector 280 is connected to the gate on the first side of the chip 220, and the other end of the third connector 280 passes through the molding compound L and is exposed on the first side of the molding compound L.

[0070] In a specific application scenario, the third connector 280 may include a ninth connector hole (not shown in the figure) and a tenth connector hole (not shown in the figure) that are stacked together. One end of the ninth connector hole is connected to the gate on the first side of the chip 220, and the end of the tenth connector hole away from the ninth connector hole is exposed on the first layer L1.

[0071] In a specific application scenario, the third connector 280 may include a metal base, which is inserted into the first layer L1 and the second layer L2 to connect with the gate of the chip 220. The specific structure of the third connector 280 is not limited here.

[0072] The third connector 280 can extend to the edge area of ​​the first layer L1 after the first layer L1 is exposed, so as to connect to the external structure.

[0073] In some embodiments, the chip package 200 further includes: conductive lines 290; the conductive lines 290 are basic circuits on the chip package 200 used to implement electrical functions, and are low-voltage connection networks.

[0074] The area where the conductive line 290 is laid includes one or more of the following: the side of the second layer L2 away from the base circuit board 210, the side of the first layer L1 away from the base circuit board 210, and the first side of the base circuit board 210; the specific layout is based on actual needs.

[0075] The conductive line 290 can be connected to the third connector 280. Since the third connector 280 is connected to the gate of the chip 220 and belongs to a low-voltage connection network, it can be connected to the conductive line 290. However, the first connector 270 and the second connector 250 are connected to the transmission electrodes of the chip 220 and belong to a high-voltage connection network. Therefore, the first connector 270 and the second connector 250 need to be internally insulated from the conductive line 290. That is, the distance between the conductive line 290 and other connectors is greater than 0.3 mm to standardize the minimum distance between different connection networks in the chip package 200 and ensure the electrical insulation characteristics between the connection networks.

[0076] The specific spacing between different connection networks may include, but is not limited to, 0.3 mm, 0.4 mm, 0.5 mm, 0.8 mm, 1.0 mm, 2.0 mm, or 3.0 mm, etc.

[0077] The thickness of the base circuit board 210, the spacing between each connector and the metal substrate 230, and the spacing between the lateral trace area of ​​the connector connected to the transmission electrode of the chip 220 and the outside world can all be greater than 0.3 mm, so as to further improve the internal electrical insulation effect of the chip package 200.

[0078] In some embodiments, the chip package 200 further includes: a heat dissipation device 267; the heat dissipation device 267 is attached to a second side of the base circuit board 210, the second side of the base circuit board 210 being the opposite side of the first side of the base circuit board 210; the second side of the metal substrate 230 is in the same direction as the second side of the base circuit board 210 and the second side of the chip 220.

[0079] The heat dissipation device 267 includes an insulating plate 260 and a heat sink 264; the insulating plate 260 is fixed and attached to the second side of the base circuit board 210, and the heat sink 264 is fixed and attached to the side of the insulating plate 260 away from the base circuit board 210.

[0080] The heat dissipation device 267 in this embodiment can be obtained by welding an insulating plate 260 onto the heat sink 264. The welding can include tin reflow soldering, silver sintering, etc. The heat sink 264 includes a metal heat sink, an air-cooled heat sink, or a liquid-cooled heat sink.

[0081] In a specific application scenario, the heat sink 264 may include a protruding heat dissipation structure 266 and a main body plate 265. The main body plate 265 is fixed and attached to the side of the insulating plate 260 away from the base circuit board 210. The protruding heat dissipation structure 266 is fixedly disposed on the side of the main body plate 265 away from the insulating plate 260. The shape of the protruding heat dissipation structure 266 may include, but is not limited to, one or more of the following: columnar, corrugated, finned, and slatted. The material of the heat sink 264 may include, but is not limited to, copper, aluminum, and stainless steel. The heat sink 264 may be a metal heat sink, an air-cooled heat sink, or a liquid-cooled heat sink, etc., and the specific type is not limited here.

[0082] By fixing and attaching the insulating plate 260 to the second side of the base circuit board 210, the insulating plate 260 can be used to insulate and protect the second side of the base circuit board 210, preventing leakage of current from the second side of the base circuit board 210 to the heat sink 264 or the outside world.

[0083] In some embodiments, the insulating plate 260 includes a first metal layer 261, an insulating layer 263, and a second metal layer 262 that are sequentially stacked and bonded together. The first metal layer 261 is also bonded to a second side of the base circuit board 210, and the second metal layer 262 is also bonded to the side of the heat sink 264 near the metal substrate 230. When the first metal layer 261 is bonded to the second side of the base circuit board 210, it may also be bonded to the first extension member 271.

[0084] The first metal layer 261 is used to weld and fix the metal substrate 230 to the insulating layer 263, and the second metal layer 262 is used to weld and fix the insulating layer 263 to the heat sink 264. The insulating plate 260 stacked as described above achieves the positional fixation of the insulating layer 263 and the heat sink 264.

[0085] The first metal layer 261 and the second metal layer 262 can be bonded and fixed by direct bonding or welding.

[0086] The thickness of both the first metal layer 261 and the second metal layer 262 ranges from 0.01 mm to 1.00 mm, specifically 0.05 mm, 0.11 mm, 0.17 mm, 0.25 mm, 0.3 mm, 0.45 mm, 0.52 mm, 0.63 mm, 0.75 mm, 0.8 mm, 0.95 mm, or 1.00 mm. The first metal layer 261 and the second metal layer 262 may have the same or different thicknesses, and the material includes one or more of copper, aluminum, silver, titanium, tin, molybdenum, and tungsten.

[0087] In this embodiment, the insulating board 260 can be pre-prepared and then welded to the base circuit board 210 to independently achieve high-temperature welding between the first metal layer 261 and the second metal layer 262 and the insulating layer 263, and to avoid the high temperature affecting the reliability of the base circuit board 210.

[0088] In some embodiments, the first metal layer 261 is bonded to the second side of the base circuit board 210 and the second side of the metal substrate 230.

[0089] The length of the lateral connection path between the side of the first metal layer 261 and the heat sink 264 is greater than 0.3 mm. Since the first metal layer 261 is connected to the metal substrate 230, it also belongs to the connection network. Therefore, the length of the lateral connection path between the side of the first metal layer 261 and the heat sink 264 is limited to be greater than 0.3 mm. That is, the sum of the distance from the side edge of the first metal layer 261 to the side edge of the insulating layer 263 and the thickness of the insulating layer 263 must be at least greater than 0.3 mm. This distance limitation can be achieved by recessing the first metal layer 261. The recessed area of ​​the first metal layer 261 is filled with the molding compound on the base circuit board 210.

[0090] Please refer to Figure 5, which is a partial structural diagram of the metal substrate and the heat sink.

[0091] The lateral connection path S between the metal substrate 230 and the heat sink 264 is composed of the sum of the distance between the edge of the connection network where the metal substrate 230 is located and the edge of the insulating plate 260, and the thickness X of the insulating plate 260. That is, S = P + X; that is, the minimum path length that may cause current breakdown needs to be greater than 0.3 mm to prevent electrical breakdown and improve the external insulation effect on the metal substrate 230.

[0092] In this embodiment, the side connection path S can be the distance between the edge of the first metal layer 261 and the edge of the insulating plate 260. The edge of the first extension 271 does not protrude from the corresponding edge of the first metal layer 261. The same applies to the third extension 553 in Figure 8.

[0093] The structure of the chip package 200 described above can use the first metal layer 261 to fix the metal substrate 230 and the insulating layer 263, and use the second metal layer 262 to fix the insulating layer 263 and the heat sink 264. The arrangement of the metal substrate 230 can also improve the heat dissipation efficiency of the chip package 200.

[0094] In some embodiments, the insulating layer 263 of the insulating plate 260 includes a ceramic layer and / or a resin layer.

[0095] When the insulating layer 263 is a ceramic layer, the thickness of the ceramic layer is greater than 0.05 mm; specifically, it can be 0.05 mm, 0.10 mm, 0.16 mm, 0.25 mm, 0.32 mm, 0.45 mm, 0.52 mm, 0.68 mm, 0.71 mm, 0.8 mm, 0.95 mm, or 1.00 mm, etc. Within this range, the insulating layer 263 can provide insulating protection for the bottom of the base circuit board 210.

[0096] The insulating layer 263 can be one or more of aluminum oxide, silicon nitride, aluminum nitride, beryllium oxide, diamond, etc. The above-mentioned ceramic materials can not only achieve insulation protection, but also ensure the thermal conductivity of the insulating layer 263, which can reach 80W / mK or even 1200W / mK, far exceeding materials such as silicone grease and resin, thus achieving a significant improvement in heat dissipation efficiency.

[0097] In some embodiments, when the insulating layer 263 is a ceramic layer, the first metal layer 261 is bonded to the second side of the metal substrate 230 and the first extension 271 via a solder layer (not shown); this solder layer may include a solder layer near the first metal layer 261 and a soldering auxiliary metal layer covering the second side surfaces of the metal substrate 230 and the base circuit board 210. The ceramic layer is larger than the metal substrate 230 but not larger than the base circuit board 210.

[0098] When the insulating layer 263 is a resin layer, the thickness of the resin layer is greater than 0.3 mm. Specifically, it may include, but is not limited to, 0.3 mm, 0.5 mm, 0.6 mm, 0.8 mm, 1.0 mm, or 1.5 mm.

[0099] The resin layer includes, but is not limited to, one or more of the following insulating materials: prepreg, epoxy resin, polyester resin (PET), polyimide, polyimide, polycarbonate (PC), bismaleimide triazine (BT), Ajinomoto build film (ABF), FR4 resin, and ceramic-based materials.

[0100] In some implementations, when the insulating layer 263 is a resin layer, the first metal layer 261 may not be necessary, and the insulating layer 263 may be directly bonded to the second side of the metal substrate 230 by resin bonding.

[0101] Please refer to Figure 6, which is a structural schematic diagram of the third embodiment of the chip package provided in this application.

[0102] In the chip package 400 of this embodiment, a lamination insulating layer 420 can be added between the base circuit board 410 and the heat dissipation device 465 to form a symmetrical lamination with the first layer and the second layer, thereby mitigating the internal stress of the upper single-area layer and reducing product warpage. The thickness of the lamination insulating layer 420 is preferably the same as or close to the sum of the thickness of the first layer and the second layer. Specifically, one side of the lamination insulating layer 420 is bonded to the second side of the base circuit board 410, and the other side of the lamination insulating layer 420 is bonded to the first metal layer 461.

[0103] Electrical wiring or heat sinks can also be installed within the laminated insulating layer 420, depending on actual needs. Other conductive lines can also be installed on the second side of the base circuit board 410.

[0104] Other features of the chip package 400 in this embodiment can be the same as those in the previous embodiments. Please refer to the previous text for details, which will not be repeated here.

[0105] Please refer to Figures 7 and 8. Figure 7 is a structural schematic diagram of the fourth embodiment of the chip package provided in this application. Figure 8 is an enlarged schematic diagram of the second connector in Figure 7.

[0106] In some embodiments, the second connector 550 includes a transverse member 551, a second conductive member 552, a third extension member 553, and a third vertical member 554 connected in sequence.

[0107] One end of the transverse member 551 is connected to the first side of the chip 520, and the other end of the transverse member 551 extends on the second layer away from the base circuit board 510 to reach the first side of the base circuit board 510. The specific structure of the transverse member 551 is similar to that of the transverse member 251 in the previous embodiment in terms of structure and connection relationship, as described above, and will not be repeated here.

[0108] The second conductive element 552 is disposed within the base circuit board 510. One end of the second conductive element 552 is connected to the other end of the cross member 551 on the first side of the base circuit board 510, and the other end of the second conductive element 552 extends vertically to the second side of the base circuit board 510. The second conductive element 552 is a metallized hole within the base circuit board 510, used to lead down the signal from the cross member 551.

[0109] The third extension 553 is disposed on the second side of the base circuit board 510. One end of the third extension 553 is connected to the other end of the second conductor 552, and the other end of the third extension 553 extends along the second side of the base circuit board 510 to the edge area of ​​the board.

[0110] The third vertical member 554 is disposed in the base circuit board 510, the second layer and the first layer. One end of the third vertical member 554 is connected to the other end of the third extension member 553 in the board edge area on the second side of the base circuit board 510. The other end of the third vertical member 554 extends vertically to the side of the first layer away from the second layer for exposure.

[0111] The structure of the third vertical member 554 is similar to that of the first vertical member 272 in the aforementioned embodiment. Please refer to the previous text for further details.

[0112] In this embodiment, by sequentially setting a second conductive member 552, a third extension member 553, and a third vertical member 554, the signal from the first side of the chip 520 is led down from the first side of the base circuit board 510 to the second side of the base circuit board 510 through the second conductive member 552, then extended from the second side of the base circuit board 510 to the edge area of ​​the board, and then led up to the first exposed layer through the third vertical member 554. In this way, while realizing the signal lead-out of the transmission electrode on the first side of the chip 520, the relevant space on the first side of the base circuit board 510 is avoided, so that conductive lines 590 can be set in this part. That is, the setting of the second connector 550 in this embodiment increases the wiring space of the conductive lines 590, while ensuring the insulation distance between the second connector 550 and other connection networks.

[0113] Other features of the chip package 500 in this embodiment can be the same as those in the previous embodiments. Please refer to the previous text for details, which will not be repeated here.

[0114] With the above structure, in this embodiment, the chip package connects to the chip via one end of the first connector, which is connected to the second side of the metal substrate. The other end of the first connector extends along the second side of the base circuit board to the edge area of ​​the board, and then extends vertically to the side of the molding layer away from the base circuit board for exposure. This allows for the extraction of the second-side electrode signal of the chip through the first connector, while providing a larger space on the side of the first connector near the molding layer for conductive line routing and increased insulation distance between the first connector and other connection networks, thereby increasing the routing freedom of the chip package. In other words, this application provides a connection structure that is compatible with the internal electrical insulation and internal wiring of the chip package's connector, reserving more wiring space for other conductive lines and increasing the routing freedom of the chip package. Furthermore, this embodiment can also use a second connector, which includes a transverse member, a second conductive member, a third extension member, and a second vertical member connected in sequence, to avoid the relevant space on the first side of the base circuit board. This allows conductive lines to be installed in this area, providing more wiring space for the conductive lines while simultaneously ensuring the insulation distance between the second connector and other connection networks. This application specifies the shape of the metal substrate in the module and the layout methods of various lines, ensuring the electrical insulation characteristics of the high-voltage lines and avoiding the risk of electrical aging and insulation failure of the module under high voltage and high switching frequency conditions.

[0115] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A chip package, wherein, The chip package includes: A base circuit board having at least one mounting slot formed thereon; At least one chip unit is fixedly installed in a corresponding mounting slot. The chip unit includes at least one metal substrate and at least one chip. The chip is fixedly connected to a first side of the metal substrate. The second side of the metal substrate is flush with the second side of the base circuit board, and the second side of the base circuit board is the opposite side of the first side of the base circuit board. A molding layer is attached to a first side of the base circuit board and fills the gap between the base circuit board and at least one of the chip units; Multiple connectors, one end of each connector is connected to a corresponding electrode of the chip, and the other end of each connector extends to the first side of the molding compound for exposure; The connector includes a first connector, one end of which is connected to the second side of the metal substrate to connect to the chip, and the other end of the first connector extends along the second side of the base circuit board to the edge area of ​​the board, and then extends vertically to the side of the molding layer away from the base circuit board for exposure.

2. The chip package according to claim 1, wherein, The first connector includes a first extension and a first vertical member connected in sequence; One end of the first extension is connected to the second side of the metal substrate, and the other end of the first extension extends along the second side of the base circuit board to the edge region of the board. The first vertical member is located in the edge region of the board, one end of the first vertical member is connected to the other end of the first extension member, and the other end of the first vertical member extends vertically to the side of the molding layer away from the base circuit board for exposure.

3. The chip package according to claim 2, wherein, The molding layer includes a filler layer, a first layer, and a second layer. The filler layer is disposed within the mounting slot. The second layer is stacked and bonded to a first side of the base circuit board, and the first layer and the second layer are stacked and bonded to the side of the second layer away from the base circuit board.

4. The chip package according to claim 3, wherein, The first vertical member includes a first conductive member, a second connecting hole, and a first connecting hole connected in sequence; The first conductive element is disposed within the base circuit board, the first connecting hole is disposed within the first layer, and the second connecting hole is disposed within the second layer; One end of the first conductive member is connected to the other end of the first extension member, and the other end of the first conductive member is connected to one end of the second connecting hole. The end of the first connecting hole away from the second connecting hole is exposed on the side of the first layer away from the base circuit board.

5. The chip package according to claim 4, wherein, The second connecting hole is misaligned with the first conductive member, wherein the misaligned member connects the end of the second connecting hole away from the first layer and the end of the first conductive member away from the first extension member.

6. The chip package according to claim 3, wherein, The connector further includes a second connector; The second connector includes a transverse member, a second extension member, and a second vertical member connected in sequence; One end of the cross member is connected to the first side of the chip, and the other end of the cross member extends on the second layer away from the base circuit board to reach the first side of the base circuit board. One end of the first extension is connected to the other end of the cross member, and the other end of the first extension extends along the first side of the base circuit board to the edge region of the board. The first vertical member is disposed within the molding layer and located in the edge region of the board. One end of the first vertical member is connected to the other end of the first extension member, and the other end of the first vertical member penetrates through the second layer and the first layer until it is exposed on the first side of the molding layer.

7. The chip package according to claim 3, wherein, The connector further includes a second connector; The second connector includes a transverse member, a second conductive member, a third extension member, and a third vertical member connected in sequence. One end of the cross member is connected to the first side of the chip, and the other end of the cross member extends on the second layer away from the base circuit board to reach the first side of the base circuit board. The second conductive element is disposed within the base circuit board, one end of the second conductive element is connected to the other end of the cross member on the first side of the base circuit board, and the other end of the second conductive element extends vertically to the second side of the base circuit board. The third extension is disposed on the second side of the base circuit board, one end of the third extension is connected to the other end of the second conductive member, and the other end of the third extension extends along the second side of the base circuit board to the edge area of ​​the board. The third vertical member is disposed within the base circuit board, the second layer, and the first layer. One end of the third vertical member is connected to the other end of the third extension member in the board edge region on the second side of the base circuit board. The other end of the third vertical member extends vertically to the side of the first layer away from the second layer for exposure.

8. The chip package according to claim 3, wherein, The connector also includes a third connector; The third connector is disposed within the first layer and the second layer. One end of the third connector is connected to the first side of the chip, and the other end of the third connector is exposed on the side of the first layer away from the second layer.

9. The chip package according to claim 8, wherein, The third connector includes a ninth connector and a tenth connector that are stacked together. One end of the ninth connector is connected to the gate on the first side of the chip, and the end of the tenth connector away from the ninth connector is exposed in the first layer.

10. The chip package according to claim 8, wherein, The chip package also includes: conductive lines; The area where the conductive lines are laid includes one or more of the following: the side of the second layer away from the base circuit board, the side of the first layer away from the base circuit board, and the first side of the base circuit board. The conductive line is connected to the third connector, and the distance between the conductive line and other connectors is greater than 0.3 mm.

11. The chip package according to claim 1, wherein, The chip package also includes: A heat dissipation device; the heat dissipation device is attached to the second side of the base circuit board, the second side of the base circuit board being the opposite side of the first side of the base circuit board; the heat dissipation device includes an insulating plate and a heat sink; the insulating plate is fixed and attached to the second side of the base circuit board, and the heat sink is fixed and attached to the side of the insulating plate away from the base circuit board.

12. The chip package according to claim 11, wherein, The heat sink includes a protruding heat dissipation structure and a main plate. The main plate is fixed and attached to the side of the insulating plate away from the base circuit board. The protruding heat dissipation structure is fixedly disposed on the side of the main plate away from the insulating plate.

13. The chip package according to claim 12, wherein, The shape of the protruding heat dissipation structure includes one or more of the following: columnar, corrugated, finned, and slatted.

14. The chip package according to claim 11, wherein, The insulating plate includes a first metal layer, an insulating layer, and a second metal layer that are stacked and bonded together in sequence. The second metal layer is also bonded to the side of the heat sink that is close to the metal substrate. The first metal layer is also bonded to the second side of the base circuit board and the second side of the metal substrate; Wherein, the length of the side connection path between the side of the first metal layer and the heat sink is greater than 0.3 mm.

15. The chip package according to claim 14, wherein, The thickness of both the first metal layer and the second metal layer ranges from 0.01 mm to 1.00 mm.

16. The chip package according to claim 14, wherein, The insulating layer includes a ceramic layer and / or a resin layer; When the insulating layer is a ceramic layer, the thickness of the ceramic layer is greater than 0.05 mm; when the insulating layer is a resin layer, the thickness of the resin layer is greater than 0.3 mm.

17. The chip package according to claim 1, wherein, The thickness of the lines and connectors on the first side of the base circuit board is greater than or equal to 100 micrometers.

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