Display panel and detection method therefor, and display device

Abstract

A display panel, comprising a plurality of sub-pixels, gate lines, data lines, a control circuit, a first data connection line, a second data connection line and gate connection lines. The plurality of sub-pixels are divided into a plurality of pixel units, and each pixel unit comprises a first pixel and a second pixel. Each of the first pixel and the second pixel comprises a plurality of sub-pixels arranged in a column direction and emitting light of different colors. In the first pixel and the second pixel, the sub-pixels emitting light of the same color are connected to different gate lines. A first data line is connected to the sub-pixels of the first pixel, and a second data line is connected to the sub-pixels of the second pixel. The first data connection line is connected to the first data line by means of the control circuit. The second data connection line is connected to the second data line by means of the control circuit. The gate connection lines are connected to the gate lines by means of the control circuit. In one of the pixel units, gate lines connected to sub-pixels emitting light of at least one color in the first pixel and gate lines connected to sub-pixels emitting light of different colors in the second pixel are connected to the same gate connection line.

Description

Display panel and its testing method, display device

[0001] This application claims priority to Chinese patent application No. 202411815418.8, filed on December 09, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a display panel and its testing method and display device. Background Technology

[0003] With the rapid development of display technology, display panels are being used more and more widely, and all kinds of display devices have become ubiquitous in people's lives. For example, depending on the application scenario, smartphones, wearable watches, televisions, laptops and in-vehicle displays have gradually become commonplace in people's lives. Summary of the Invention

[0004] On one hand, a display panel is provided. The display panel includes multiple sub-pixels, gate lines, data lines, control circuitry, a first data connection line, a second data connection line, and gate connection lines. The multiple sub-pixels are arranged in multiple rows and columns. The multiple sub-pixels are divided into multiple pixel units, each pixel unit including a first pixel and a second pixel arranged along a row direction, and the first pixel and the second pixel each including multiple sub-pixels arranged along a column direction with different emission colors. The gate lines are connected to a row of sub-pixels. Furthermore, in the first pixel and the second pixel, sub-pixels with the same emission color are connected to different gate lines. The data lines are connected to a column of sub-pixels. The data lines include a first data line and a second data line, the first data line being connected to the sub-pixels of the first pixel, and the second data line being connected to the sub-pixels of the second pixel.

[0005] The control circuit is disposed on at least one side of the plurality of sub-pixels. The first data connection line is connected to the first data line through the control circuit. The second data connection line is connected to the second data line through the control circuit. The gate connection line is connected to the gate line through the control circuit. In a pixel unit, the gate lines connected to sub-pixels of at least one emission color of the first pixel and sub-pixels of different emission colors of the second pixel are connected to the same gate connection line.

[0006] In some embodiments, the number of the first pixels in the pixel unit is the same as the number of the second pixels.

[0007] In some embodiments, in a pixel unit, the gate lines connected to at least two sub-pixels of the first pixel with the same emission color as the two sub-pixels of the second pixel are connected to different gate connection lines.

[0008] In some embodiments, the plurality of gate lines includes N first gate lines, where N is greater than or equal to 3 and is an integer. Along the direction of the gate lines near the first data connection line, the plurality of first gate lines in the gate line group are sequentially the 1st first gate line, the 2nd first gate line, the 3rd first gate line, ..., the Nth first gate line. The plurality of gate connection lines include a first gate connection line, a second gate connection line, and a third gate connection line. The first gate connection line is connected to the (3M+1)th first gate line via the control circuit; M is greater than or equal to 0 and is an integer, and 3M+3 is less than or equal to N. The second gate connection line is connected to the (3M+2)th first gate line via the control circuit. The third gate connection line is connected to the (3M+3)th first gate line via the control circuit.

[0009] In some embodiments, within the same pixel unit, multiple sub-pixels emit the same color along the row direction.

[0010] In some embodiments, the plurality of gate lines further includes a second gate line located on the side of the N first gate lines that is close to or far from the first data connection line.

[0011] In some embodiments, a row of sub-pixels is located between two adjacent gate lines, and sub-pixels in the first pixel are connected to a gate line adjacent to and close to the first data connection line; sub-pixels in the second pixel are connected to a gate line adjacent to and away from the first data connection line. The second gate line is located on the side of the N first gate lines away from the first data connection line; the first gate connection line is also connected to the second gate line.

[0012] In some embodiments, a row of sub-pixels is located between two adjacent gate lines, and sub-pixels in the first pixel are connected to a gate line adjacent to and away from the first data connection line; sub-pixels in the second pixel are connected to a gate line adjacent to and close to the first data connection line. The second gate line is located on the side of the N first gate lines closest to the first data connection line; the third gate connection line is also connected to the second gate line.

[0013] In some embodiments, the data line includes connected data lead segments and fan-out lead segments. The data lead segments are connected to a column of sub-pixels, and the data lead segments are connected to the first data connection line or the second data connection line via the fan-out lead segments. The display panel includes multiple conductive layers, the pixel unit includes a first pixel and a second pixel, and the fan-out lead segments of multiple data lines are located in the same conductive layer. Alternatively, the fan-out lead segments of two data lines connected to the same pixel unit are located in the same conductive layer, and the fan-out lead segments of two data lines connected to adjacent and different pixel units are located in different conductive layers.

[0014] In some embodiments, the fan-out leads of two data lines connected to the same pixel unit are located in the same conductive layer, while the fan-out leads of data lines connected to adjacent and different pixel units are located in different conductive layers. The fan-out leads of two data lines connected to adjacent and different pixel units bend toward each other and overlap.

[0015] In some embodiments, within the same pixel unit, the emission color of at least one row of sub-pixels of the first pixel is different from the emission color of sub-pixels of the second pixel.

[0016] In some embodiments, the plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels. Within the same pixel unit, the red sub-pixels of the first pixel and the green sub-pixels of the second pixel are located in the same row, the green sub-pixels of the first pixel and the blue sub-pixels of the second pixel are located in the same row, and the blue sub-pixels of the first pixel and the red sub-pixels of the second pixel are located in the same row.

[0017] In some embodiments, the plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels. Within the same pixel unit, the red sub-pixels of the first pixel and the blue sub-pixels of the second pixel are located in the same row, the green sub-pixels of the first pixel and the green sub-pixels of the second pixel are located in the same row, and the blue sub-pixels of the first pixel and the red sub-pixels of the second pixel are located in the same row.

[0018] In some embodiments, the data line includes connected data lead segments and fan-out lead segments. The data lead segments are connected to a column of sub-pixels, and the data lead segments are connected to the first data connection line or the second data connection line via the fan-out lead segments. The display panel includes multiple conductive layers, the pixel unit includes a first pixel and a second pixel, and the fan-out lead segments of multiple data lines are located in the same conductive layer.

[0019] In some embodiments, the data line includes connected data lead segments and fan-out lead segments. The data lead segments are connected to a column of sub-pixels, and the data lead segments are connected to the first data connection line or the second data connection line via the fan-out lead segments. The display panel includes multiple conductive layers, and the pixel unit includes a plurality of first pixels and a plurality of second pixels. Along the row direction, the sub-pixels of the plurality of first pixels have the same emission color, and the sub-pixels of the plurality of second pixels have the same emission color. The fan-out lead segments of the plurality of first data lines connected to a pixel unit are located in different conductive layers, and the fan-out lead segments of the plurality of second data lines connected to a pixel unit are located in different conductive layers.

[0020] In some embodiments, the pixel unit includes two first pixels and two second pixels, with the two first pixels located on one side of the two second pixels along the row direction. The multilayer conductive layer includes a first conductive layer and a second conductive layer, with fan-out lead segments of multiple data lines alternately located in the first conductive layer and the second conductive layer along the row direction.

[0021] In some embodiments, the display panel includes a plurality of the gate connection lines, wherein the number of the gate connection lines is greater than or equal to 3.

[0022] In some embodiments, the display panel includes a display area and a fan-out area, with a plurality of sub-pixels located in the display area along the column direction, and the fan-out area located on one side of the display area. The data line includes connected data lead segments and fan-out lead segments. The data lead segments are connected to a column of sub-pixels, and the data lead segments are connected to the first data connection line or the second data connection line via the fan-out lead segments. The data lead segments are located in the display area, and the fan-out lead segments are located in the fan-out area, with one end extending into the display area and connecting to the data lead segment, and the other end connected to the first data connection line or the second data connection line.

[0023] In some embodiments, the control circuit includes a first control circuit and a second control circuit. The first data connection line and the second data connection line are respectively connected to the data line through the first control circuit, and the gate connection line is connected to the gate line through the second control circuit. Along the column direction, the first control circuit and the second control circuit are located on the same side of the plurality of sub-pixels.

[0024] In some embodiments, the display panel further includes a first control line, the control circuit being connected to the first control line and configured to be turned on or off in response to a control signal transmitted via the first control line. The first control line, the first data connection line, and the second data connection line are sequentially located away from the plurality of sub-pixels. The display panel further includes a chip output bonding portion, a chip input bonding portion, and a source driver chip. The chip output bonding portion is disposed on the side of the first control line away from the first data connection line. The chip input bonding portion is disposed on the side of the second data connection line away from the first data connection line. The source driver chip is connected to the chip output bonding portion and the chip input bonding portion.

[0025] In some embodiments, the display panel further includes a circuit board bonding portion located on the side of the chip input bonding portion away from the chip output bonding portion and connected to the chip input bonding portion.

[0026] On the other hand, a display device is provided. The display device includes a display panel and a driving circuit board as described in any of the above embodiments, wherein the driving circuit board is connected to the display panel.

[0027] In another aspect, a method for detecting a display panel is provided. The detection method is applied to a display panel as described in any of the above embodiments. The detection method includes: in a first detection stage, providing a plurality of gate test signals, a first data test signal, and a second data test signal to a plurality of gate lines, a first data line, and a second data line, respectively. The first data test signal is at a working level, at least a portion of the gate test signal is at a working level, and the remaining portion of the gate test signal and the second data test signal are at a non-working level. In response to the gate test signal, the first data test signal, and the second data test signal, the sub-pixel connected to the gate line transmitting the working-level gate test signal and the first data line emits light of a first color. When the first data line and the second data line are not short-circuited, the other sub-pixels in the pixel unit do not emit light. When the first data line and the second data line are short-circuited, at least one sub-pixel connected to the second data line short-circuited to the first data line emits light of a second color, and the first color is different from the second color.

[0028] In some embodiments, the detection method further includes: in a second detection phase, providing a plurality of gate test signals, a first data test signal, and a second data test signal to the plurality of gate lines, the first data line, and the second data line, respectively. At least a portion of the gate test signal is at a working level, while the remaining gate test signal, the first data test signal, and the second data test signal are at a non-working level. In response to the gate test signal, the first data test signal, and the second data test signal, the sub-pixels in the pixel unit do not emit light. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0030] Figure 1 is a structural diagram of a display device according to some embodiments;

[0031] Figure 2 is a cross-sectional view along section line AA' in Figure 1;

[0032] Figure 3 is a schematic diagram of the stacked structure of a display device according to some embodiments;

[0033] Figure 4 is a top view of a display panel according to some embodiments;

[0034] Figure 5 is a structural diagram of the display area of ​​a display panel according to some embodiments;

[0035] Figure 6 is a structural diagram of the common electrode of the display panel shown in Figure 5;

[0036] Figure 7 is a structural diagram of the display panel shown in Figure 5 after the common electrode has been removed;

[0037] Figure 8 is a structural diagram of a display panel according to some embodiments;

[0038] Figure 9 is a structural diagram of another display panel according to some embodiments;

[0039] Figure 10 is a structural diagram of another display panel according to some embodiments;

[0040] Figure 11 shows the detection results of lighting up the red sub-pixel when the first data line and the second data line in Figure 9 are not short-circuited;

[0041] Figure 12 shows the detection results of lighting up the red sub-pixel when one of the first data lines and one of the second data lines in Figure 9 are short-circuited.

[0042] Figure 13 shows the detection results of lighting up the green sub-pixel when the first data line and the second data line in Figure 9 are not short-circuited;

[0043] Figure 14 shows the detection results of lighting up the green sub-pixel when one of the first data lines and one of the second data lines in Figure 9 are short-circuited.

[0044] Figure 15 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 9 are short-circuited.

[0045] Figure 16 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 9 are short-circuited.

[0046] Figure 17 shows the detection results of lighting up the red sub-pixel when the first data line and the second data line in Figure 8 are not short-circuited;

[0047] Figure 18 shows the detection results of lighting up the red sub-pixel when one of the first data lines and one of the second data lines in Figure 8 are short-circuited.

[0048] Figure 19 shows the detection results of lighting up the green sub-pixel when the first data line and the second data line in Figure 8 are not short-circuited;

[0049] Figure 20 shows the detection results of lighting up the green sub-pixel when one of the first data lines and one of the second data lines in Figure 8 are short-circuited.

[0050] Figure 21 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 8 are short-circuited.

[0051] Figure 22 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 8 are short-circuited.

[0052] Figure 23 shows the detection results of lighting up the red sub-pixel when the first data line and the second data line in Figure 10 are not short-circuited;

[0053] Figure 24 shows the detection results of lighting up the red sub-pixel when one of the first data lines and one of the second data lines in Figure 10 are short-circuited.

[0054] Figure 25 shows the detection results of lighting up the green sub-pixel when the first data line and the second data line in Figure 10 are not short-circuited;

[0055] Figure 26 shows the detection results of lighting up the green sub-pixel when one of the first data lines and one of the second data lines in Figure 10 are short-circuited.

[0056] Figure 27 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 10 are short-circuited.

[0057] Figure 28 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 10 are short-circuited.

[0058] Figure 29 is a structural diagram of another display panel according to some embodiments;

[0059] Figure 30 is a structural diagram of another display panel according to some embodiments;

[0060] Figure 31 is a structural diagram of another display panel according to some embodiments;

[0061] Figure 32 shows the detection results of lighting up the red sub-pixel when one of the first data lines and one of the second data lines in Figure 29 are short-circuited.

[0062] Figure 33 shows the detection results of lighting up the green sub-pixel when one of the first data lines and one of the second data lines in Figure 29 are short-circuited.

[0063] Figure 34 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 29 are short-circuited.

[0064] Figure 35 shows the detection results of lighting up the red sub-pixel when one of the first data lines and one of the second data lines in Figure 30 are short-circuited.

[0065] Figure 36 shows the detection results of lighting up the green sub-pixel when one of the first data lines and one of the second data lines in Figure 30 are short-circuited.

[0066] Figure 37 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 30 are short-circuited.

[0067] Figure 38 shows the detection results of lighting up the red sub-pixel when one of the first data lines and one of the second data lines in Figure 31 are short-circuited.

[0068] Figure 39 shows the detection results of lighting up the green sub-pixel when one of the first data lines and one of the second data lines in Figure 31 are short-circuited.

[0069] Figure 40 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 31 are short-circuited.

[0070] Figure 41 is a structural diagram of another display panel according to some embodiments;

[0071] Figure 42 is a structural diagram of another display panel according to some embodiments;

[0072] Figure 43 is a structural diagram of another display panel according to some embodiments;

[0073] Figure 44 is a structural diagram of another display panel according to some embodiments;

[0074] Figure 45 shows the detection results of lighting up the red sub-pixel when the first data line and the second data line in Figure 41 are not short-circuited.

[0075] Figure 46 shows the detection results of lighting up the red sub-pixel when one of the first data lines and one of the second data lines in Figure 41 are short-circuited.

[0076] Figure 47 shows the detection results of lighting up the green sub-pixel when the first data line and the second data line in Figure 41 are not short-circuited;

[0077] Figure 48 shows the detection results of lighting up the green sub-pixel when one of the first data lines and one of the second data lines in Figure 41 are short-circuited.

[0078] Figure 49 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 41 are short-circuited.

[0079] Figure 50 shows the detection result of lighting up the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 41 are short-circuited.

[0080] Figure 51 shows the detection results of lighting up the red sub-pixel when the first data line and the second data line in Figure 42 are not short-circuited;

[0081] Figure 52 shows the detection results of lighting up the red sub-pixel when one of the first data lines and one of the second data lines in Figure 42 are short-circuited.

[0082] Figure 53 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 42 are short-circuited.

[0083] Figure 54 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 42 are short-circuited.

[0084] Figure 55 shows the detection results of lighting up the red sub-pixel when the first data line and the second data line in Figure 43 are not short-circuited;

[0085] Figure 56 shows the detection results of lighting up the red sub-pixel when one of the first data lines and one of the second data lines in Figure 43 are short-circuited.

[0086] Figure 57 shows the detection results of lighting up the green sub-pixel when the first data line and the second data line in Figure 43 are not short-circuited;

[0087] Figure 58 shows the detection results of lighting up the green sub-pixel when one of the first data lines and one of the second data lines in Figure 43 are short-circuited.

[0088] Figure 59 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 43 are short-circuited.

[0089] Figure 60 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 43 are short-circuited.

[0090] Figure 61 shows the detection results of lighting up the red sub-pixel when the first data line and the second data line in Figure 44 are not short-circuited;

[0091] Figure 62 shows the detection results of lighting up the red sub-pixel when one of the first data lines and one of the second data lines in Figure 44 are short-circuited.

[0092] Figure 63 shows the detection result of lighting up the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 44 are short-circuited.

[0093] Figure 64 shows the detection results of illuminating the blue sub-pixel when one of the first data lines and one of the second data lines in Figure 44 are short-circuited.

[0094] Figure 65 is a magnified view of a portion of region D1 in Figure 4;

[0095] Figure 66 is a magnified view of a portion of region D2 in Figure 4;

[0096] Figure 67 is a magnified view of a portion of region D3 in Figure 4;

[0097] Figure 68 is a timing diagram of a display panel according to some embodiments, when testing the illumination of a red sub-pixel.

[0098] Figure 69 is a timing diagram of a display panel according to some embodiments, when testing the lighting of a green sub-pixel.

[0099] Figure 70 is a timing diagram of a display panel according to some embodiments, during a test of lighting up the blue sub-pixel. Detailed Implementation

[0100] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0101] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0102] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0103] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a mechanical connection or an electrical connection; it can be a fixed connection or a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art will understand the specific meaning of the above terms herein based on the specific circumstances.

[0104] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0105] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0106] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0107] As used herein, “vertical” includes the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “vertical” includes absolute verticality and approximate verticality, where an acceptable range of deviation for approximate verticality could, for example, be within 5°.

[0108] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0109] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0110] As shown in FIG1, some embodiments of the present disclosure provide a display device 1000, which can be any device that displays text or images, whether moving (e.g., video) or fixed (e.g., still images).

[0111] For example, referring to FIG1, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, in-vehicle display, in-flight display, wearable device, virtual reality (VR) device, signboard, electronic billboard, and shopping mall display. For example, the display device 1000 can be the laptop computer shown in FIG1.

[0112] Regarding the type of light emission of the display device 1000, the display device 1000 can be a liquid crystal display (LCD), or it can be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a mini / micro light-emitting diode (MLED), etc. Regarding the shape of the display device 1000, the display device 1000 can be rectangular or circular, etc., and the embodiments disclosed herein do not specifically limit this.

[0113] The following uses a rectangular and planar liquid crystal display device as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure is not limited to this, and any other display device can be considered as long as the same technical concept is applied.

[0114] In some embodiments, referring to FIG2, the display device 1000 includes a display panel 100 and a driving circuit board 200. The driving circuit board 200 may include, for example, a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistor voltage divider circuit (generating Vcom), etc. Of course, the driving circuit board 200 may also include other circuit structures, which will not be listed here. The driving circuit board 200 is connected to the display panel 100 and is used to transmit control signals to the display panel 100 to drive the display panel 100 to display images. Exemplarily, the display panel 100 includes a circuit board mounting portion 110, and the driving circuit board 200 is connected to the circuit board mounting portion 110 to transmit control signals to the display panel 100.

[0115] Referring again to Figure 2, the display device 1000 may also include a frame 300 and a cover plate 400. The longitudinal section of the frame 300 is, for example, U-shaped. The display panel 100 and the driving circuit board 200 may be disposed within the frame 300, and the cover plate 400 is disposed at the opening of the frame 300.

[0116] Referring again to Figure 2, when the display device 1000 is a liquid crystal display device, the display device 1000 may further include a backlight module 500 disposed on the backlight side of the display panel 100. The backlight module 500 may, for example, be disposed on the side of the display panel 100 away from the cover plate 400, and the driving circuit board 200 may be disposed on the side of the backlight module 500 away from the cover plate 400. The backlight module 500 may be a direct-lit backlight module or an edge-lit backlight module, etc., and is used to provide a light source for the display panel 100. The display panel 100 adjusts the amount of light passing through it to display different gray levels, thereby achieving the purpose of image display.

[0117] In some embodiments, as shown in FIG2, the display panel 100 may include an array substrate 10 and a color filter substrate 20 disposed opposite to each other, and a liquid crystal layer 15 disposed between the array substrate 10 and the color filter substrate 20. The array substrate 10 and the color filter substrate 20 are joined together by an adhesive sealant 350, thereby confining the liquid crystal layer 15 within the area enclosed by the adhesive sealant 350. The color filter substrate 20 may also be referred to as an opposing substrate or an encapsulation substrate. The color filter substrate 20 can filter the light incident on it to emit light of various colors (such as red, green, or blue) to achieve color display.

[0118] As shown in Figure 3, the array substrate 10 includes a first substrate 11, and pixel electrodes 120 and a common electrode 130 disposed on the first substrate 11. The common electrode 130 is disposed on the side of the pixel electrodes 120 away from the first substrate 11, and multiple pixel electrodes 120 are spaced apart. The common electrode 130 is a single-piece structure, and multiple slits S can be formed on the common electrode 130, exposing portions of the pixel electrodes 120. In this case, a multidimensional electric field is formed by the electric field generated at the edge of the slits of the common electrode 130 in the same plane, and the electric field generated between the common electrode 130 and the pixel electrodes 120. This allows all oriented liquid crystal molecules in the liquid crystal layer 15 to rotate, thereby improving the liquid crystal working efficiency and increasing the light transmittance. Of course, the structure of the pixel electrode 120 and the common electrode 130 is not limited to this. For example, the pixel electrode 120 and the common electrode 130 are disposed in the same layer, or the pixel electrode 120 is located on the side of the common electrode 130 away from the first substrate 11, the pixel electrode 120 is provided with multiple slits, and the common electrode 130 is a continuous whole-surface structure (i.e., the common electrode 130 does not have slits) or the common electrode 130 is provided with multiple slits. These will not be listed one by one here.

[0119] As shown in Figure 3, the color filter substrate 20 includes a second substrate 21 and a color filter layer 220 disposed on the second substrate 21. The color filter layer 220 includes a plurality of filter portions 221, which include red, green, and blue filter portions. The red, green, and blue filter portions are respectively configured to transmit red, green, and blue light, thereby achieving color display. Furthermore, the color filter substrate 20 may also include, for example, a black matrix pattern 230 disposed on the second substrate 21, which is used to space the different filter portions 221.

[0120] In some embodiments, referring to FIG4, the display panel 100 may include a display area A and a peripheral area B disposed on at least one side of the display area A. FIG4 shows an example where the peripheral area B surrounds the display area A. The display area A is the area for displaying images and is configured to have multiple sub-pixels P, where each sub-pixel P can be understood as the smallest light-emitting unit in the display panel 100. The peripheral area B may contain circuit structures.

[0121] As shown in Figures 4 and 5, the display area A includes multiple sub-pixels P. These sub-pixels P can be arranged in multiple rows and columns in the display area A. Each column includes at least two sub-pixels P arranged along a first direction X, and each row includes at least two sub-pixels P arranged along a second direction Y. The first direction X intersects the second direction Y; for example, the first direction X is perpendicular to the second direction Y.

[0122] Based on this, referring to Figures 5, 6, and 7, the display panel 100 may further include multiple data lines 30 and multiple gate lines 40. The multiple data lines 30 are spaced apart along a first direction X and extend generally along a second direction Y. For example, one data line 30 may be connected to a column of sub-pixels P. The multiple gate lines 40 are spaced apart along the second direction Y and extend generally along the first direction X. For example, one gate line 40 may be connected to one or more rows of sub-pixels P. The multiple data lines 30 and multiple gate lines 40 intersect to form a grid structure, each grid structure defining a pixel area, and one sub-pixel P is disposed in one pixel area.

[0123] It should be noted that the data line 30 can be a straight line or a broken line in its extension direction, and the gate line 40 can be a straight line or a broken line in its extension direction. This disclosure does not specifically limit this aspect.

[0124] Furthermore, the sub-pixel P may include a pixel circuit, a pixel electrode 120, and a filter section 221. The pixel circuit includes a thin-film transistor 12, which includes an active layer 121, a source 122, a drain 123, a gate 124, and a gate insulating layer 125. The source 122 and the drain 123 are respectively in contact with the active layer 121, and the pixel electrode 120 is connected to the drain 123 of the thin-film transistor 12. At this time, multiple openings H may also be provided on the aforementioned common electrode 130, with each opening H exposing one thin-film transistor 12 to reduce parasitic capacitance.

[0125] In this article, referring to Figures 3 and 8, the sub-pixel P including the red filter is called the red sub-pixel R, the sub-pixel P including the green filter is called the green sub-pixel G, and the sub-pixel P including the blue filter is called the blue sub-pixel B.

[0126] In this document, the connection of data line 30 to sub-pixel P means that data line 30 is connected to the source 122 of thin-film transistor 12. The connection of gate line 40 to sub-pixel P means that gate line 40 is connected to the gate 124 of thin-film transistor 12 of sub-pixel P.

[0127] As shown in Figure 4, the peripheral area B includes a fan-out area B1, which is located on one side of the display area A and coincides with the edge of the display area A near the fan-out area B1. For example, along the second direction Y, the fan-out area B1 is located on one side of the display area A. The fan-out area B1 can be used to shrink the circuit traces (e.g., data line 30) of the display area A and lead them out to the source driver chip 600 or the driver circuit board 200, thereby reducing the bezel of the display panel 100.

[0128] For example, as shown in Figure 8, the data line 30 includes a connected data lead segment 31 and a fan-out lead segment 32. The data lead segment 31 is connected to a column of sub-pixels P, and the data lead segment 31 is connected to the auxiliary circuit 50 through the fan-out lead segment 32. The data lead segment 31 is located in the display area A, and the fan-out lead segment 32 is located in the fan-out area B1. One end of the fan-out lead segment 32 extends to the display area A and connects to the data lead segment 31, while the other end extends to the source driver chip 600 (see Figure 4) or the circuit board bonding portion 110 (see Figure 4).

[0129] However, in related technologies, the risk of short circuits is relatively high for fan-out lead segments arranged on the same layer. Furthermore, during the production process of display panels, short circuits between fan-out lead segments arranged on the same layer cannot be detected, and defective products cannot be intercepted in time, resulting in material waste in subsequent processes, a decrease in the yield of display devices, and an increase in production costs.

[0130] To address the aforementioned technical problems, referring to FIG8, in some embodiments of the present disclosure, a display panel 100 includes multiple sub-pixels P divided into multiple pixel units P10. Each pixel unit P10 includes a first pixel P11 and a second pixel P12 arranged along a row direction (first direction X), and the first pixel P11 and the second pixel P12 each include multiple sub-pixels P arranged along a column direction (second direction Y) and emitting different colors. For example, the first pixel P11 and the second pixel P12 each include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B located in the same column. The following description uses the example of the first pixel P11 and the second pixel P12 each including a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B located in the same column to illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

[0131] In a pixel unit P10, the number of first pixels P11 can be the same as the number of second pixels P12, resulting in a regular pixel arrangement that is easy to design and improves display quality. For example, a pixel unit P10 may include one first pixel P11 and one second pixel P12. Alternatively, a pixel unit P10 may include two first pixels P11 and two second pixels P12. Of course, a pixel unit P10 may also include three, four, or more first pixels P11 and second pixels P12; this embodiment does not impose a specific limitation.

[0132] Furthermore, in the first pixel P11 and the second pixel P12, sub-pixels P with the same emission color are connected to different gate lines 40. The data line 30 includes a first data line 310 and a second data line 320. The first data line 310 is connected to the sub-pixel P of the first pixel P11, and the second data line 320 is connected to the sub-pixel P of the second pixel P12.

[0133] Furthermore, the display panel 100 also includes an auxiliary circuit 50, which is disposed on at least one side of a plurality of sub-pixels P and connected to the gate line 40 and the data line 30. At this time, one end of the aforementioned fan-out lead segment 32 is connected to the data lead segment 31, and the other end is connected to the auxiliary circuit 50. The auxiliary circuit 50 is configured to provide a gate test signal, a first data test signal, and a second data test signal to the gate line 40, the first data line 310, and the second data line 320, respectively. Simultaneously, in response to the gate test signal, the first data test signal, and the second data test signal, one sub-pixel P in the pixel unit P10, either the first pixel P11 or the second pixel P12, emits light of a first color. When the first data line 310 and the second data line 320 are not short-circuited, the other sub-pixels P in the pixel unit P10 do not emit light. When the first data line 310 and the second data line 320 are short-circuited, at least one sub-pixel P connected to the second data line 320 short-circuited to the first data line 310 emits light of a second color, which is different from the first color.

[0134] In other words, when the first data line 310 and the second data line 320 are not short-circuited, the detection screen displays multiple vertical stripes of the first color. When the first data line 310 and the second data line 320 are short-circuited, a vertical stripe of the second color appears between the multiple vertical stripes of the first color in the detection screen. Based on this, when the first data line 310 and the second data line 320 are short-circuited, the human eye can directly identify it through the detection screen, thereby promptly rejecting display panels 100 with short circuits in the first data line 310 and the second data line 320, intercepting defective products, reducing material waste in subsequent processes, improving the yield of the display device 1000, and reducing production costs.

[0135] In some embodiments, referring to FIG8, the auxiliary circuit 50 includes a first control line 510, a control circuit 520, a first data connection line 530, a second data connection line 540, and a gate connection line 550. The first control line 510, the first data connection line 530, and the second data connection line 540 may, for example, be sequentially located away from a plurality of sub-pixels P.

[0136] As shown in Figure 8, the control circuit 520 is connected to the first control line 510, and the control circuit 520 is configured to be turned on or off in response to a control signal transmitted through the first control line 510. For example, the control circuit 520 may include a switching transistor 5211, the control electrode of which is connected to the first control line 510, and is turned on or off under the control of the first control line 510.

[0137] As shown in Figure 8, the first data connection line 530 is connected to the first data line 310 via the control circuit 520. The second data connection line 540 is connected to the second data line 320 via the control circuit 520. Here, the data lead segment 31 of the data line 30 of the first data line 310 can be connected to the first data connection line 530 via the fan-out lead segment 32, and the data lead segment 31 of the data line 30 of the second data line 320 can be connected to the second data connection line 540 via the fan-out lead segment 32. The control circuit 520 can be disposed between the fan-out lead segment 32 and the first data connection line 530 and the second data connection line 540. For example, the first data line 310 is connected to the first terminal of the switching transistor 5211, and the second terminal of the switching transistor 5211 is connected to the first data connection line 530. The second data line 320 is connected to the first terminal of the switching transistor 5211, and the second terminal of the switching transistor 5211 is connected to the second data connection line 540.

[0138] As shown in Figure 8, the gate connection line 550 is connected to the gate line 40 through the control circuit 520. Here, the gate connection line 550 can be directly connected to the control circuit 520, and the control circuit 520 can be directly connected to the gate line 40; or, the gate connection line 550 can be directly connected to the gate line 40, and the control circuit 520 can be located on the trace of the gate connection line 550 to control the on / off state of the gate connection line 550.

[0139] In this configuration, by inputting a first control signal to the first control line 510, the control circuit 520 can be turned on or off, thereby enabling the first data connection line 530 and the second data connection line 540 to be connected or disconnected from the first data line 310 and the second data line 320, respectively, and the gate connection line 550 to be connected or disconnected from the gate line 40. This controls whether a lighting test is performed, preventing interference with the normal display of the display panel 100. Furthermore, by inputting a first data test signal, a second data test signal, and a gate test signal to the first data connection line 530, the second data connection line 540, and the gate connection line 550, respectively, the light emission or non-light emission of the sub-pixel P connected to the first data line 310 and the second data line 320 can be controlled, realizing the detection of whether there is a short circuit between the first data line 310 and the second data line 320. The circuit structure is simple and easy to configure.

[0140] In some embodiments, referring to FIG8, in a pixel unit P10, the gate lines 40 connecting at least one emission color sub-pixel P of the first pixel P11 and the sub-pixel P of a different emission color from the second pixel P12 are connected to the same gate connection line 550. That is, the gate lines 40 connecting at least one emission color sub-pixel P and the sub-pixel P of a different emission color are connected to the same gate connection line 550.

[0141] In a pixel unit P10, the two sub-pixels P connected to the first pixel P11 and the second pixel P12 that transmit the same gate test signal but have different emission colors are respectively the first target sub-pixel and the second target sub-pixel. For example, in the first pixel P11 and the second pixel P12, each sub-pixel P with a different emission color has the same gate test signal transmitted by the gate line 40 connected to it.

[0142] At this time, by inputting the gate test signal, the first data test signal, and the second data test signal, it is expected that, without short-circuiting the first data line 310 and the second data line 320, one of the first target sub-pixels and the second target sub-pixel will emit light while the other does not. Thus, after short-circuiting the first data line 310 and the second data line 320, the second target sub-pixel connected to the shorted second data line 320 will emit light, causing a vertical stripe of a different color to appear in the detection image.

[0143] In some embodiments, referring to Figures 8 to 49, in a pixel unit P10, the gate lines 40 connecting the two sub-pixels P of the first pixel P11 with the same emission color as the two sub-pixels P of the second pixel P12 are connected to different gate connection lines 550.

[0144] For example, referring to Figures 8 to 49, the multiple gate lines 40 include N first gate lines 41, where N is greater than or equal to 3 and is an integer. Along the direction of the gate lines 40 near the first data connection line 530, the N first gate lines 41 are sequentially the first first gate line 41-1, the second first gate line 41-2, the third first gate line 41-3, ... the Nth first gate line 41-N.

[0145] Based on this, the auxiliary circuit 50 also includes a first gate connection line 551, a second gate connection line 552, and a third gate connection line 553. The first gate connection line 551 is connected to the 3M+1th first gate line 41 via the control circuit 520. The second gate connection line 552 is connected to the 3M+2th first gate line 41 via the control circuit 520. The third gate connection line 553 is connected to the 3M+3th first gate line 41 via the control circuit 520. M is greater than or equal to 0 and is an integer, and 3M+3 is less than or equal to N. In this configuration, when the control circuit 520 is turned on, the first data connection line 530, the second data connection line 540, the first gate connection line 551, the second gate connection line 552, and the third gate connection line 553 can all receive corresponding test signals. The auxiliary circuit 50 has a simple structure and is easy to manufacture and test.

[0146] The number of gate connection lines 550 is greater than or equal to three. For example, the gate connection line 550 includes a first gate connection line 551, a second gate connection line 552, and a third gate connection line 553. In this way, the three gate connection lines 550 transmit the corresponding gate test signal to all gate lines 40, which is beneficial for the narrow bezel design of the display panel 100. Of course, the number of gate connection lines 550 can also be four, five, six, or more, and this embodiment does not specifically limit this.

[0147] In some embodiments, referring to Figures 8 to 49, in the same pixel unit P10, multiple sub-pixels P emit the same color along the row direction. This arrangement makes the sub-pixels P more regularly arranged, which is beneficial for the fabrication of the multiple filter portions 221 of the color filter layer 220.

[0148] In addition, the multiple gate lines 40 also include a second gate line 42, which is located on the side of the N first gate lines 41 that is close to or far from the first data connection line 530, so as to transmit gate test signals to some sub-pixels P in the first row or the last row.

[0149] In some examples, as shown in Figures 8, 9, and 10, a row of sub-pixels P is located between two adjacent gate lines 40, and the sub-pixel P in the first pixel P11 is connected to the adjacent gate line 40 that is close to the first data connection line 530. The sub-pixel P in the second pixel P12 is connected to the adjacent gate line 40 that is far from the first data connection line 530. Furthermore, the second gate line 42 is located on the side of the N first gate lines 41 that is far from the first data connection line 530, and the first gate connection line 551 is also connected to the second gate line 42.

[0150] At this time, as shown in Figures 8 and 9, pixel unit P10 may include a first pixel P11 and a second pixel P12, or, as shown in Figure 10, pixel unit P10 may include multiple first pixels P11 and multiple second pixels P12, and along the row direction, the light emission colors of the sub-pixels P of the multiple first pixels P11 are the same, and the light emission colors of the sub-pixels P of the multiple second pixels P12 are the same.

[0151] Example 1, as shown in Figure 9, pixel unit P10 includes a first pixel P11 and a second pixel P12. The display panel 100 includes multiple conductive layers 60, with multiple fan-out lead segments 32 located within the same conductive layer 60. For example, the multiple conductive layers 60 include a first conductive layer 610 and a second conductive layer 620. Gate lines 40, first control lines 510, first gate connection lines 551, second gate connection lines 552, and third gate connection lines 553 are located in the first conductive layer 610, while data lead segments 31, first data connection lines 530, and second data connection lines 540 are located in the second conductive layer 620. In this case, the multiple fan-out lead segments 32 can be located in the first conductive layer 610; however, the fan-out lead segments 32 can also be located in other conductive layers 60, and this embodiment is not limited to this.

[0152] When testing the illumination of the red sub-pixel R, the detection screen is shown in Figure 11 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 12 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the green sub-pixel G, the detection screen is shown in Figure 13 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 14 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the blue sub-pixel B, the detection screen is shown in Figure 15 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 16 when the first data line 310 and the second data line 320 are short-circuited. In Figures 11-16, the white area represents sub-pixel P not emitting light. As can be seen from Figures 11-16, a short circuit between the first data line 310 and the second data line 320 can be identified.

[0153] Example 2, as shown in Figure 8, shows that pixel unit P10 includes a first pixel P11 and a second pixel P12. The display panel 100 includes multiple conductive layers 60. The fan-out lead segments 32 of two data lines 30 connected to the same pixel unit P10 are located in the same conductive layer 60, while the fan-out lead segments 32 of data lines 30 connected to adjacent and different pixel units P10 are located in different conductive layers 60. For example, the multiple conductive layers 60 include a first conductive layer 610 and a second conductive layer 620. Gate lines 40, first control lines 510, first gate connection lines 551, second gate connection lines 552, and third gate connection lines 553 are located in the first conductive layer 610, while data lead segments 31, first data connection lines 530, and second data connection lines 540 are located in the second conductive layer 620. At this time, the fan-out lead segments 32 of the two data lines 30 connected to the same pixel unit P10 are located in the first conductive layer 610 or the second conductive layer 620. The fan-out lead segments 32 of the two data lines 30 connected to adjacent and different pixel units P10 are located in the first conductive layer 610 and the second conductive layer 620, respectively. Here, the fan-out lead segments 32 of the two data lines 30 connected to adjacent and different pixel units P10 can be bent in a direction closer to each other and overlap, which can increase the distance between the fan-out lead segments 32 in the same layer and reduce the risk of short circuit of the fan-out lead segments 32 in the same layer. Furthermore, the fan-out lead segments 32 of the two data lines 30 connected to adjacent and different pixel units P10 are located in the first conductive layer 610 and the other in the second conductive layer 620. That is, the fan-out lead segments 32 of the data lines 30 connected to adjacent pixel units P10 are alternately arranged in the first conductive layer 610 and the second conductive layer 620. The fan-out lead segments 32 of multiple data lines 30 can be arranged more compactly, which is beneficial to reducing the bezel of the display panel 100.

[0154] When testing the illumination of the red sub-pixel R, the detection screen is shown in Figure 17 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 18 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the green sub-pixel G, the detection screen is shown in Figure 19 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 20 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the blue sub-pixel B, the detection screen is shown in Figure 21 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 22 when the first data line 310 and the second data line 320 are short-circuited. In Figures 17-22, the white area represents sub-pixel P not emitting light. As can be seen from Figures 17-22, a short circuit between the first data line 310 and the second data line 320 can be identified.

[0155] Example 3, as shown in Figure 10, a pixel unit P10 may include multiple first pixels P11 and multiple second pixels P12. The fan-out leads 32 of multiple first data lines 310 connected to a pixel unit P10 are located in different conductive layers 60, and the fan-out leads 32 of multiple second data lines 320 connected to a pixel unit P10 are located in different conductive layers 60. For example, a pixel unit P10 may include two first pixels P11 and two second pixels P12, with the two first pixels P11 located on one side of the two second pixels P12 along the row direction. The multilayer conductive layer 60 includes a first conductive layer 610 and a second conductive layer 620, with the fan-out leads 32 of the multiple data lines 30 alternately located in the first conductive layer 610 and the second conductive layer 620 along the row direction. Furthermore, the gate line 40, the first control line 510, the first gate connection line 551, the second gate connection line 552, and the third gate connection line 553 may be located in the first conductive layer 610, for example, and the data lead segment 31, the first data connection line 530, and the second data connection line 540 may be located in the second conductive layer 620, for example.

[0156] When testing the illumination of the red sub-pixel R, the detection screen is shown in Figure 23 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 24 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the green sub-pixel G, the detection screen is shown in Figure 25 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 26 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the blue sub-pixel B, the detection screen is shown in Figure 27 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 28 when the first data line 310 and the second data line 320 are short-circuited. In Figures 23-28, the white area represents sub-pixel P not emitting light. As can be seen from Figures 23-28, a short circuit between the first data line 310 and the second data line 320 can be identified.

[0157] In other examples, as shown in Figures 29, 30, and 31, a row of sub-pixels P is located between two adjacent gate lines 40, and the sub-pixel P in the first pixel P11 is connected to the adjacent gate line 40 that is far from the first data connection line 530. The sub-pixel P in the second pixel P12 is connected to the adjacent gate line 40 that is close to the first data connection line 530. The second gate line 42 is located on the side of the N first gate lines 41 close to the first data connection line 530, and the third gate connection line 553 is also connected to the second gate line 42.

[0158] At this time, as shown in Figures 29 and 30, pixel unit P10 may include a first pixel P11 and a second pixel P12, or, as shown in Figure 31, pixel unit P10 may include multiple first pixels P11 and multiple second pixels P12, and along the row direction, the light emission colors of the sub-pixels P of the multiple first pixels P11 are the same, and the light emission colors of the sub-pixels P of the multiple second pixels P12 are the same.

[0159] Example 1, as shown in Figure 29, pixel unit P10 includes a first pixel P11 and a second pixel P12. The display panel 100 includes multiple conductive layers 60, with multiple fan-out lead segments 32 located within the same conductive layer 60. For example, the multiple conductive layers 60 include a first conductive layer 610 and a second conductive layer 620. Gate lines 40, first control lines 510, first gate connection lines 551, second gate connection lines 552, and third gate connection lines 553 are located in the first conductive layer 610, while data lead segments 31, first data connection lines 530, and second data connection lines 540 are located in the second conductive layer 620. In this case, the multiple fan-out lead segments 32 can be located in the first conductive layer 610; however, the fan-out lead segments 32 can also be located in other conductive layers 60, and this embodiment is not limited to this.

[0160] When testing the illumination of the red sub-pixel R, the detection screen is shown in Figure 11 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 32 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the green sub-pixel G, the detection screen is shown in Figure 13 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 33 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the blue sub-pixel B, the detection screen is shown in Figure 15 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 34 when the first data line 310 and the second data line 320 are short-circuited. In Figures 11, 13, 15 and 32-34, the white area represents that the sub-pixel P does not emit light. As can be seen from Figures 11, 13, 15 and 32-34, the first data line 310 and the second data line 320 can be shorted to identify this.

[0161] Example 2, as shown in Figure 30, shows that pixel unit P10 includes a first pixel P11 and a second pixel P12. The display panel 100 includes multiple conductive layers 60. The fan-out lead segments 32 of two data lines 30 connected to the same pixel unit P10 are located in the same conductive layer 60, while the fan-out lead segments 32 of data lines 30 connected to adjacent and different pixel units P10 are located in different conductive layers 60. For example, the multiple conductive layers 60 include a first conductive layer 610 and a second conductive layer 620. Gate lines 40, first control lines 510, first gate connection lines 551, second gate connection lines 552, and third gate connection lines 553 are located in the first conductive layer 610, while data lead segments 31, first data connection lines 530, and second data connection lines 540 are located in the second conductive layer 620. At this time, the fan-out lead segments 32 of the two data lines 30 connected to the same pixel unit P10 are located in the first conductive layer 610 or the second conductive layer 620. The fan-out lead segments 32 of the two data lines 30 connected to adjacent and different pixel units P10 are located in the first conductive layer 610 and the second conductive layer 620, respectively. Here, the fan-out lead segments 32 of the two data lines 30 connected to adjacent and different pixel units P10 can be bent in a direction closer to each other and overlap, which can increase the distance between the fan-out lead segments 32 in the same layer and reduce the risk of short circuit of the fan-out lead segments 32 in the same layer.

[0162] When testing the illumination of the red sub-pixel R, the detection screen is shown in Figure 17 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 35 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the green sub-pixel G, the detection screen is shown in Figure 19 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 36 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the blue sub-pixel B, the detection screen is shown in Figure 21 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 37 when the first data line 310 and the second data line 320 are short-circuited. In Figures 17, 19, 21 and 35-37, the white area represents that the sub-pixel P does not emit light. As can be seen from Figures 17, 19, 21 and 35-37, the first data line 310 and the second data line 320 can be shorted to identify this.

[0163] Example 3, as shown in Figure 31, a pixel unit P10 may include multiple first pixels P11 and multiple second pixels P12. The fan-out leads 32 of multiple first data lines 310 connected to a pixel unit P10 are located in different conductive layers 60, and the fan-out leads 32 of multiple second data lines 320 connected to a pixel unit P10 are located in different conductive layers 60. For example, a pixel unit P10 may include two first pixels P11 and two second pixels P12, with the two first pixels P11 located on one side of the two second pixels P12 along the row direction. The multilayer conductive layer 60 includes a first conductive layer 610 and a second conductive layer 620, with the fan-out leads 32 of the multiple data lines 30 alternately located in the first conductive layer 610 and the second conductive layer 620 along the row direction. Furthermore, the gate line 40, the first control line 510, the first gate connection line 551, the second gate connection line 552, and the third gate connection line 553 may be located in the first conductive layer 610, for example, and the data lead segment 31, the first data connection line 530, and the second data connection line 540 may be located in the second conductive layer 620, for example.

[0164] When testing the illumination of the red sub-pixel R, the detection screen is shown in Figure 23 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 38 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the green sub-pixel G, the detection screen is shown in Figure 25 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 39 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the blue sub-pixel B, the detection screen is shown in Figure 27 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 40 when the first data line 310 and the second data line 320 are short-circuited. In Figures 23, 25, 27 and 38-40, the white area represents that the sub-pixel P does not emit light. As can be seen from Figures 23, 25, 27 and 38-40, the first data line 310 and the second data line 320 can be shorted to identify this.

[0165] In other embodiments, referring to Figures 41-44, in the same pixel unit P10, the emission color of the sub-pixels P of at least one row of the first pixel P11 is different from the emission color of the sub-pixels P of the second pixel P12. This arrangement results in more uniform light mixing among multiple sub-pixels P with different emission colors.

[0166] Based on this, all sub-pixels P in a row can be connected to the same gate line 40 adjacent to the first data connection line 530, or all sub-pixels P in a row can be connected to the same gate line 40 adjacent to the first data connection line 530. This disclosure does not specifically limit this. The following example, where all sub-pixels P in a row are connected to the same gate line 40 adjacent to the first data connection line 530, illustrates some embodiments of this disclosure. However, this disclosure is not limited to these embodiments.

[0167] At this time, as shown in Figures 41 and 43, in the same pixel unit P10, the red sub-pixel R of the first pixel P11 and the green sub-pixel G of the second pixel P12 are in the same row, the green sub-pixel G of the first pixel P11 and the blue sub-pixel B of the second pixel P12 are in the same row, and the blue sub-pixel B of the first pixel P11 and the red sub-pixel R of the second pixel are in the same row.

[0168] Alternatively, as shown in Figures 42 and 44, in the same pixel unit P10, the red sub-pixel R of the first pixel P11 and the blue sub-pixel B of the second pixel P12 are located in the same row, the green sub-pixel G of the first pixel P11 and the green sub-pixel G of the second pixel P12 are located in the same row, and the blue sub-pixel B of the first pixel P11 and the red sub-pixel R of the second pixel P12 are located in the same row.

[0169] Furthermore, as shown in Figures 41 and 42, pixel unit P10 may include a first pixel P11 and a second pixel P12, or, as shown in Figures 43 and 44, pixel unit P10 may include multiple first pixels P11 and multiple second pixels P12, and along the row direction, the sub-pixels P of the multiple first pixels P11 have the same emission color, and the sub-pixels P of the multiple second pixels P12 have the same emission color.

[0170] Example 1, as shown in Figure 41, in the same pixel unit P10, the red sub-pixel R of the first pixel P11 and the green sub-pixel G of the second pixel P12 are located in the same row; the green sub-pixel G of the first pixel P11 and the blue sub-pixel B of the second pixel P12 are located in the same row; and the blue sub-pixel B of the first pixel P11 and the red sub-pixel R of the second pixel are located in the same row. Furthermore, pixel unit P10 may include one first pixel P11 and one second pixel P12.

[0171] The display panel 100 includes multiple conductive layers 60, with multiple fan-out lead segments 32 located on the same conductive layer 60. For example, the multiple conductive layers 60 include a first conductive layer 610 and a second conductive layer 620. The gate line 40, the first control line 510, the first gate connection line 551, the second gate connection line 552, and the third gate connection line 553 are located on the first conductive layer 610, while the data lead segment 31, the first data connection line 530, and the second data connection line 540 are located on the second conductive layer 620. In this case, the multiple fan-out lead segments 32 can be located on the first conductive layer 610. Of course, the fan-out lead segments 32 can also be located on other conductive layers 60, and the embodiments disclosed herein are not limited to this.

[0172] When testing the illumination of the red sub-pixel R, the detection screen is shown in Figure 45 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 46 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the green sub-pixel G, the detection screen is shown in Figure 47 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 48 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the blue sub-pixel B, the detection screen is shown in Figure 49 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 50 when the first data line 310 and the second data line 320 are short-circuited. In Figures 45-50, the white area represents sub-pixel P not emitting light. As can be seen from Figures 45-50, a short circuit between the first data line 310 and the second data line 320 can be identified.

[0173] Example 2, as shown in Figure 42, in the same pixel unit P10, the red sub-pixel R of the first pixel P11 and the blue sub-pixel B of the second pixel P12 are located in the same row; the green sub-pixel G of the first pixel P11 and the green sub-pixel G of the second pixel P12 are located in the same row; and the blue sub-pixel B of the first pixel P11 and the red sub-pixel R of the second pixel P12 are located in the same row. Furthermore, pixel unit P10 may include one first pixel P11 and one second pixel P12.

[0174] The display panel 100 includes multiple conductive layers 60, with multiple fan-out lead segments 32 located on the same conductive layer 60. For example, the multiple conductive layers 60 include a first conductive layer 610 and a second conductive layer 620. The gate line 40, the first control line 510, the first gate connection line 551, the second gate connection line 552, and the third gate connection line 553 are located on the first conductive layer 610, while the data lead segment 31, the first data connection line 530, and the second data connection line 540 are located on the second conductive layer 620. In this case, the multiple fan-out lead segments 32 can be located on the first conductive layer 610. Of course, the fan-out lead segments 32 can also be located on other conductive layers 60, and the embodiments disclosed herein are not limited to this.

[0175] When testing the illumination of the red sub-pixel R, the detection screen is shown in Figure 51 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 52 when the first data line 310 and the second data line 320 are short-circuited. Similarly, when testing the illumination of the blue sub-pixel B, the detection screen is shown in Figure 53 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 54 when the first data line 310 and the second data line 320 are short-circuited. In Figures 51-54, the white area represents sub-pixel P not emitting light. As can be seen from Figures 51-54, a short circuit between the first data line 310 and the second data line 320 can be identified.

[0176] Example 3, as shown in Figure 43, in the same pixel unit P10, the red sub-pixel R of the first pixel P11 and the green sub-pixel G of the second pixel P12 are located in the same row; the green sub-pixel G of the first pixel P11 and the blue sub-pixel B of the second pixel P12 are located in the same row; and the blue sub-pixel B of the first pixel P11 and the red sub-pixel R of the second pixel are located in the same row. Furthermore, pixel unit P10 may include multiple first pixels P11 and multiple second pixels P12. The fan-out lead segments 32 of multiple first data lines 310 connected to a pixel unit P10 are located in different conductive layers 60, and the fan-out lead segments 32 of multiple second data lines 320 connected to a pixel unit P10 are located in different conductive layers 60.

[0177] For example, pixel unit P10 includes two first pixels P11 and two second pixels P12, with the two first pixels P11 located on one side of the two second pixels P12 along the row direction. Multilayer conductive layer 60 includes a first conductive layer 610 and a second conductive layer 620, with fan-out lead segments 32 of multiple data lines 30 alternately located in the first conductive layer 610 and the second conductive layer 620 along the row direction. Furthermore, gate lines 40, first control lines 510, first gate connection lines 551, second gate connection lines 552, and third gate connection lines 553 may, for example, be located in the first conductive layer 610, and data lead segments 31, first data connection lines 530, and second data connection lines 540 may, for example, be located in the second conductive layer 620.

[0178] When testing the illumination of the red sub-pixel R, the detection screen is shown in Figure 55 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 56 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the green sub-pixel G, the detection screen is shown in Figure 57 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 58 when the first data line 310 and the second data line 320 are short-circuited. When testing the illumination of the blue sub-pixel B, the detection screen is shown in Figure 59 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 60 when the first data line 310 and the second data line 320 are short-circuited. In Figures 55-60, the white area represents sub-pixel P not emitting light. As can be seen from Figures 55-60, a short circuit between the first data line 310 and the second data line 320 can be identified.

[0179] Example 4, as shown in Figure 44, in the same pixel unit P10, the red sub-pixel R of the first pixel P11 and the blue sub-pixel B of the second pixel P12 are located in the same row; the green sub-pixel G of the first pixel P11 and the green sub-pixel G of the second pixel P12 are located in the same row; and the blue sub-pixel B of the first pixel P11 and the red sub-pixel R of the second pixel P12 are located in the same row. Furthermore, pixel unit P10 may include multiple first pixels P11 and multiple second pixels P12. The fan-out lead segments 32 of multiple first data lines 310 connected to a pixel unit P10 are located in different conductive layers 60, and the fan-out lead segments 32 of multiple second data lines 320 connected to a pixel unit P10 are located in different conductive layers 60.

[0180] For example, pixel unit P10 includes two first pixels P11 and two second pixels P12, with the two first pixels P11 located on one side of the two second pixels P12 along the row direction. Multilayer conductive layer 60 includes a first conductive layer 610 and a second conductive layer 620, with fan-out lead segments 32 of multiple data lines 30 alternately located in the first conductive layer 610 and the second conductive layer 620 along the row direction. Furthermore, gate lines 40, first control lines 510, first gate connection lines 551, second gate connection lines 552, and third gate connection lines 553 may, for example, be located in the first conductive layer 610, and data lead segments 31, first data connection lines 530, and second data connection lines 540 may, for example, be located in the second conductive layer 620.

[0181] When testing the illumination of the red sub-pixel R, the detection screen is shown in Figure 61 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 62 when the first data line 310 and the second data line 320 are short-circuited. Similarly, when testing the illumination of the blue sub-pixel B, the detection screen is shown in Figure 63 when the first data line 310 and the second data line 320 are not short-circuited; the detection screen is shown in Figure 64 when the first data line 310 and the second data line 320 are short-circuited. In Figures 61-64, the white area represents sub-pixel P not emitting light. As can be seen from Figures 61-64, a short circuit between the first data line 310 and the second data line 320 can be identified.

[0182] In any of the above embodiments, referring to Figures 8-10, 29-31 and 41-44, the control circuit 520 may include, for example, a first control circuit 521 and a second control circuit 522, a first data connection line 530 and a second data connection line 540, which are respectively connected to the data line 30 through the first control circuit 521, and a first gate connection line 551, a second gate connection line 552 and a third gate connection line 553, which are respectively connected to the gate line 40 through the second control circuit 522.

[0183] In this configuration, along the column direction, the first control circuit 521 and the second control circuit 522 are located on the same side of the plurality of sub-pixels P; that is, along the second direction Y, the first control circuit 521 and the second control circuit 522 are located on one side of the display area A. This arrangement, with the first control circuit 521 and the second control circuit 522 positioned along the extension direction of the data line 30, facilitates reducing the bezel in the row direction of the display panel 100. Of course, the first control circuit 521 and the second control circuit 522 can also be located on different sides of the plurality of sub-pixels P; this embodiment does not specifically limit this arrangement.

[0184] Here, the first control circuit 521 and the second control circuit 522 can be arranged, for example, along the first direction X. For instance, the switching transistors 5211 of the first control circuit 521 and the second control circuit 522 can be arranged along a row direction, making the circuit layout more regular and facilitating the routing design of each signal line (such as the first control line 510). Furthermore, along the first direction X, the first control circuit 521 can be located only on one side of the second control circuit 522, or, along the first direction X, a portion of the first control circuit 521 can be located on the first side of the second control circuit 522, and another portion can be located on the second side of the second control circuit 522. The first side and the second side are opposite sides of the second control circuit 522 in the first direction X. This embodiment of the present disclosure does not specifically limit this arrangement.

[0185] Furthermore, on at least one side of the first direction X of the display area A, the first gate connection line 551, the second gate connection line 552, and the third gate connection line 553 can, for example, be connected to the corresponding gate line 40 respectively, and extend to one side of the second direction Y of the display area A to connect to the second control circuit 522. In the orthographic projection onto the first substrate 11, two adjacent gate connection lines (including the first gate connection line 551, the second gate connection line 552, and the third gate connection line 553) can be located in different conductive layers 60. This helps to reduce the area occupied by the gate connection lines on the first substrate 11, thereby reducing the bezel of the display panel 100. For example, one of the two adjacent gate connection lines may be located in the first conductive layer 610, and the other in the second conductive layer 620. Of course, they can also be disposed in other conductive layers 60; this embodiment does not specifically limit this.

[0186] It should be noted that when two adjacent gate lines 40 are connected to the same gate connection line, the two adjacent gate lines 40 can extend to one side of the display area A, and the two gate lines 40 are directly connected and connected to the same gate connection line on one side of the display area A, and connected to the second control circuit 522 through a gate connection line.

[0187] In any of the above embodiments, the connection between circuit structures located in different conductive layers 60 can be achieved through a transition block 710. For example, referring to FIG65, the fan-out lead segment 32 located in the first conductive layer 610 and the data lead segment 31 located in the second conductive layer 620 can be connected through the transition block 710. The transition block 710 can, for example, be made of the same material as the pixel electrode 120 and disposed in the same layer.

[0188] In any of the above embodiments, referring to FIG4, the peripheral area B may further include, for example, a chip setting area B2 and a circuit board bonding area B3. The chip setting area B2 is located on the side of the fan-out area B1 away from the display area A, and the circuit board bonding area B3 is located on the side of the chip setting area B2 away from the display area A. The chip setting area B2 is used to set the source driver chip 600, and the circuit board bonding area B3 is used to set the circuit board bonding part 110 to connect the driver circuit board 200.

[0189] For example, as shown in Figures 4, 65, 66, and 67, the display panel 100 further includes a chip input bonding portion 61 and a chip output bonding portion 62, which are disposed in the chip setting area B2, and a circuit board bonding portion 110 is disposed in the circuit board bonding area B3. The chip input bonding portion 61 is located on the side of the chip output bonding portion 62 away from the display area A, and the circuit board bonding portion 110 is located on the side of the chip input bonding portion 61 away from the chip output bonding portion 62. In this case, the display panel 100 also includes a source driver chip 600, which is connected to the chip input bonding portion 61 and the chip output bonding portion 62, and a drive circuit board 200 is connected to the circuit board bonding portion 110.

[0190] The chip input bonding section 61 includes multiple chip input pins 611, the chip output bonding section 62 includes multiple chip output pins 621, and the circuit board bonding section 110 includes multiple bonding pins 111. The chip input pins 611, chip output pins 621, and bonding pins 111 can all, for example, be made of the same material as the pixel electrode 120 and disposed on the same layer; however, this embodiment is not limited to this. Furthermore, the chip input pins 611 and bonding pins 111 can be connected via a first connecting line 810. The first connecting line 810 can, for example, be located on the first conductive layer 610; however, the first connecting line 810 can also be located on other conductive layers 60, and this embodiment does not specifically limit this.

[0191] Based on this, the chip output bonding portion 62 can be located, for example, on the side of the first control line 510 away from the first data connection line 530, and the chip input bonding portion 61 can be located, for example, on the side of the second data connection line 540 away from the first data connection line 530. In this case, by positioning the chip output bonding portion 62 on the side of the first control line 510 away from the first data connection line 530, some connection traces can overlap with the area occupied by the chip output bonding portion 62, which helps to reduce the bezel size. Furthermore, the circuit board bonding portion 110 can be located, for example, on the side of the chip input bonding portion 61 away from the chip output bonding portion 62, and connected to the chip input bonding portion 61 to transmit control signals to the source driver chip 600.

[0192] Figure 68 is a timing diagram of a display panel according to some embodiments for testing the illumination of a red sub-pixel; Figure 69 is a timing diagram of a display panel according to some embodiments for testing the illumination of a green sub-pixel; Figure 70 is a timing diagram of a display panel according to some embodiments for testing the illumination of a blue sub-pixel.

[0193] Some embodiments of this disclosure also provide a method for detecting a display panel 100, applicable to the display panel 100 as described in any of the above embodiments. Referring to Figures 68, 69, and 70, the detection method includes:

[0194] In the first detection phase T1, multiple gate test signals, first data test signals, and second data test signals are provided to the multiple gate lines 40, the first data line 310, and the second data line 320, respectively. During the first detection phase T1, the first data test signal is at a working level, and at least a portion of the time period of one gate test signal is at a working level, while the remaining time periods of the gate test signal and the second data test signal are at a non-working level. For example, the first detection phase T1 includes a first sub-segment T11, in which one gate test signal is at a working level, and the time interval between the first sub-segment T11 and the start point of the first detection phase T1 can be, for example, greater than or equal to 5 ms. Furthermore, the duration of the first sub-segment T11 can be, for example, greater than or equal to 2 ms.

[0195] In this document, "operating level" refers to the voltage level that enables the operated transistors included in a sub-pixel to be turned on, and correspondingly, "non-operating level" refers to the voltage level that prevents the operated transistors included in a sub-pixel from being turned on (i.e., the transistor is turned off). Depending on factors such as the type of transistor (N-type or P-type), the operating level may be higher or lower than the non-operating level. This embodiment illustrates an example where the operating level is higher than the non-operating level, but the embodiments disclosed herein are not limited to this.

[0196] At this time, in response to the gate test signal, the first data test signal, and the second data test signal, the sub-pixel P connected to the gate line 40 transmitting the gate test signal at the working level and the first data line 310 emits light of a first color. When the first data line 310 and the second data line 320 are not short-circuited, the other sub-pixels P in the pixel unit P10 do not emit light. When the first data line 310 and the second data line 320 are short-circuited, at least one sub-pixel P connected to the second data line 320 short-circuited to the first data line 310 emits light of a second color, and the first color is different from the second color. The detection method for the display panel provided in this disclosure embodiment has the same beneficial technical effects as the display panel provided in the above embodiment, and will not be repeated here.

[0197] For example, as shown in Figures 8, 68, 69 and 70, in the first detection stage T1, a first control signal is transmitted through the first control line 510. In response to the first control signal, the control circuit 520 is turned on so that the first gate connection line 551, the second gate connection line 552 and the third gate connection line 553 respectively provide multiple gate test signals to the multiple gate lines 40, and the first data connection line 530 and the second data connection line 540 respectively provide the first data test signal and the second data test signal to the first data line 310 and the second data line 320.

[0198] As shown in Figures 8 and 68, in the first sub-segment T11, the gate test signal transmitted by the first gate connection line 551 is at the working level, while the gate test signals transmitted by the second gate connection line 552 and the third gate connection line 553 are at the non-working level. At this time, the red sub-pixel P emits light. When the first data line 310 and the second data line 320 are not short-circuited, other color sub-pixels P do not emit light. When the first data line 310 and the second data line 320 are short-circuited, at least one green sub-pixel G or blue sub-pixel B emits light.

[0199] Alternatively, as shown in Figures 8 and 69, in the first sub-segment T11, the gate test signal transmitted by the second gate connection line 552 is at a working level, while the gate test signals transmitted by the first gate connection line 551 and the third gate connection line 553 are at a non-working level. In this case, the green sub-pixel G emits light, and when the first data line 310 and the second data line 320 are not short-circuited, other color sub-pixels P do not emit light. When the first data line 310 and the second data line 320 are short-circuited, at least one red sub-pixel R or blue sub-pixel B emits light.

[0200] Alternatively, as shown in Figures 8 and 70, in the first sub-segment T11, the gate test signal transmitted by the third gate connection line 553 is at a working level, while the gate test signals transmitted by the first gate connection line 551 and the second gate connection line 552 are at a non-working level. In this case, the blue sub-pixel B emits light, and when the first data line 310 and the second data line 320 are not short-circuited, other color sub-pixels P do not emit light. When the first data line 310 and the second data line 320 are short-circuited, at least one red sub-pixel R or green sub-pixel G emits light.

[0201] In some embodiments, referring to Figures 68, 69 and 70, the above detection method further includes:

[0202] In the second detection phase T2, multiple gate test signals, first data test signals, and second data test signals are provided to the multiple gate lines 40, the first data line 310, and the second data line 320, respectively. At least a portion of the time period of one gate test signal is at a working level, while the remaining time periods of the gate test signal, the first data test signal, and the second data test signal are at a non-working level. For example, the second detection phase T2 includes a second sub-segment T21, in which one gate test signal is at a working level. The time interval between the second sub-segment T21 and the start point of the second detection phase T2 can, for example, be greater than or equal to 5 ms. Furthermore, the duration of the second sub-segment T21 can, for example, be greater than or equal to 2 ms. The second detection phase T2 is located after the first detection phase T1.

[0203] In response to the gate test signal, the first data test signal, and the second data test signal, none of the sub-pixels P in pixel unit P10 emit light. In this case, during the second detection stage T2, the liquid crystal molecules in the liquid crystal layer can be reset, which reduces the risk of the preceding first detection stage T1 interfering with the display of the subsequent first detection stage T1.

[0204] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0205] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: Multiple sub-pixels, arranged in multiple rows and columns; The multiple sub-pixels are divided into multiple pixel units. Each pixel unit includes a first pixel and a second pixel arranged along the row direction, and the first pixel and the second pixel each include multiple sub-pixels arranged along the column direction and having different emission colors. A gate line is connected to a row of sub-pixels; and, in the first pixel and the second pixel, sub-pixels with the same emission color are connected to different gate lines; A data line is connected to a column of said sub-pixels; and the data line includes a first data line and a second data line, the first data line being connected to the sub-pixels of the first pixel, and the second data line being connected to the sub-pixels of the second pixel; The control circuit is disposed on at least one side of the plurality of sub-pixels; The first data connection line is connected to the first data line through the control circuit; The second data connection line is connected to the second data line through the control circuit; A gate connection line is connected to the gate line via the control circuit; in a pixel unit, the gate lines connected to the sub-pixels of at least one emission color of the first pixel and the sub-pixels of different emission colors of the second pixel are connected to the same gate connection line.

2. The display panel according to claim 1, wherein, In the pixel unit, the number of the first pixel is the same as the number of the second pixel.

3. The display panel according to claim 1 or 2, wherein, In one pixel unit, the gate lines connecting at least two sub-pixels of the first pixel with the same emission color as the two sub-pixels of the second pixel with the same emission color are connected to different gate connection lines.

4. The display panel according to claim 3, wherein, The plurality of gate lines includes N first gate lines, where N is greater than or equal to 3 and is an integer; along the direction of the gate lines close to the first data connection line, the plurality of first gate lines in the gate line group are sequentially the 1st first gate line, the 2nd first gate line, the 3rd first gate line... the Nth first gate line; The plurality of gate connection lines include: The first gate connection line is connected to the 3M+1th first gate line through the control circuit; M is greater than or equal to 0 and is an integer, and 3M+3 is less than or equal to N; The second gate connection line is connected to the 3M+2th first gate line through the control circuit; The third gate connection line is connected to the 3M+3rd first gate line through the control circuit.

5. The display panel according to claim 4, wherein, Within the same pixel unit, along the row direction, multiple sub-pixels emit the same color.

6. The display panel according to claim 5, wherein, The plurality of gate lines also includes a second gate line located on the side of the N first gate lines that is close to or far from the first data connection line.

7. The display panel according to claim 6, wherein, The sub-pixels in a row are located between two adjacent gate lines, and the sub-pixels in the first pixel are connected to the gate line adjacent to and close to the first data connection line; the sub-pixels in the second pixel are connected to the gate line adjacent to and far from the first data connection line; the second gate line is located on the side of the N first gate lines away from the first data connection line; the first gate connection line is also connected to the second gate line.

8. The display panel according to claim 6, wherein, The sub-pixels in a row are located between two adjacent gate lines, and the sub-pixels in the first pixel are connected to the adjacent gate line that is far away from the first data connection line; the sub-pixels in the second pixel are connected to the adjacent gate line that is close to the first data connection line; the second gate line is located on the side of the N first gate lines that is close to the first data connection line; the third gate connection line is also connected to the second gate line.

9. The display panel according to any one of claims 5 to 8, wherein, The data line includes connected data lead segments and fan-out lead segments. The data lead segments are connected to a column of the sub-pixels, and the data lead segments are connected to the first data connection line or the second data connection line through the fan-out lead segments. The display panel includes multiple conductive layers, and the pixel unit includes a first pixel and a second pixel. The fan-out leads of multiple data lines are located in the same conductive layer; or, the fan-out leads of two data lines connected to the same pixel unit are located in the same conductive layer, and the fan-out leads of two data lines connected to adjacent and different pixel units are located in different conductive layers.

10. The display panel according to claim 9, wherein, The fan-out lead segments of two data lines connected to the same pixel unit are located in the same conductive layer, and the fan-out lead segments of data lines connected to adjacent and different pixel units are located in different conductive layers; The fan-out lead segments of the two data lines connected to adjacent and different pixel units bend toward each other and overlap.

11. The display panel according to claim 4, wherein, In the same pixel unit, the emission color of at least one row of sub-pixels of the first pixel is different from the emission color of the sub-pixels of the second pixel.

12. The display panel according to claim 11, wherein, The plurality of said sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels; In the same pixel unit, the red sub-pixel of the first pixel and the green sub-pixel of the second pixel are located in the same row, the green sub-pixel of the first pixel and the blue sub-pixel of the second pixel are located in the same row, and the blue sub-pixel of the first pixel and the red sub-pixel of the second pixel are located in the same row.

13. The display panel according to claim 11, wherein, The plurality of said sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels; In the same pixel unit, the red sub-pixel of the first pixel and the blue sub-pixel of the second pixel are located in the same row, the green sub-pixel of the first pixel and the green sub-pixel of the second pixel are located in the same row, and the blue sub-pixel of the first pixel and the red sub-pixel of the second pixel are located in the same row.

14. The display panel according to any one of claims 11 to 13, wherein, The data line includes connected data lead segments and fan-out lead segments. The data lead segments are connected to a column of the sub-pixels, and the data lead segments are connected to the first data connection line or the second data connection line through the fan-out lead segments. The display panel includes multiple conductive layers, the pixel unit includes a first pixel and a second pixel, and the fan-out lead segments of multiple data lines are located in the same conductive layer.

15. The display panel according to any one of claims 5-8 and 11-13, wherein, The data line includes connected data lead segments and fan-out lead segments. The data lead segments are connected to a column of the sub-pixels, and the data lead segments are connected to the first data connection line or the second data connection line through the fan-out lead segments. The display panel includes multiple conductive layers, and the pixel unit includes multiple first pixels and multiple second pixels. Along the row direction, the sub-pixels of the multiple first pixels have the same emission color, and the sub-pixels of the multiple second pixels have the same emission color. The fan-out lead segments of multiple first data lines connected to one pixel unit are located in different conductive layers, and the fan-out lead segments of multiple second data lines connected to one pixel unit are located in different conductive layers.

16. The display panel according to claim 15, wherein, The pixel unit includes two first pixels and two second pixels, and along the row direction, the two first pixels are located on one side of the two second pixels; The multilayer conductive layer includes a first conductive layer and a second conductive layer. Along the row direction, fan-out lead segments of multiple data lines are alternately located in the first conductive layer and the second conductive layer.

17. The display panel according to any one of claims 1 to 16, comprising a plurality of the gate connecting lines, wherein the number of the gate connecting lines is greater than or equal to 3.

18. The display panel according to any one of claims 1 to 17, comprising a display area and a fan-out area, wherein a plurality of said sub-pixels are located in the display area and along the column direction, and the fan-out area is located on one side of the display area; The data line includes connected data lead segments and fan-out lead segments. The data lead segments are connected to a column of sub-pixels, and the data lead segments are connected to the first data connection line or the second data connection line through the fan-out lead segments. The data lead segments are located in the display area, and the fan-out lead segments are located in the fan-out area, with one end extending into the display area and connecting to the data lead segments, and the other end connecting to the first data connection line or the second data connection line.

19. The display panel according to any one of claims 1 to 18, wherein, The control circuit includes a first control circuit and a second control circuit. The first data connection line and the second data connection line are respectively connected to the data line through the first control circuit. The gate connection line is connected to the gate line through the second control circuit. Along the column direction, the first control circuit and the second control circuit are located on the same side of the plurality of sub-pixels.

20. The display panel of claim 19, further comprising a first control line, the control circuit being connected to the first control line and configured to be turned on or off in response to a control signal transmitted by the first control line; the first control line, the first data connection line, and the second data connection line being sequentially moved away from the plurality of sub-pixels; The display panel also includes: The chip output bonding section is located on the side of the first control line away from the first data connection line; The chip input bonding section is located on the side of the second data connection line away from the first data connection line; The source driver chip is connected to the chip output bonding part and the chip input bonding part.

21. The display panel according to claim 20, further comprising: The circuit board bonding part is located on the side of the chip input bonding part away from the chip output bonding part, and is connected to the chip input bonding part.

22. A display device, comprising: The display panel as described in any one of claims 1 to 21; The driver circuit board is connected to the display panel.

23. A method for detecting a display panel, applied to the display panel as described in any one of claims 1 to 21, comprising: In the first detection phase, multiple gate test signals, first data test signals, and second data test signals are provided to multiple gate lines, the first data line, and the second data line, respectively. The first data test signal is at the working level, at least a portion of the gate test signal is at the working level, and the remaining portion of the gate test signal and the second data test signal are at the non-working level. In response to the gate test signal, the first data test signal, and the second data test signal, the sub-pixel connected to the gate line transmitting the gate test signal of the working level and the first data line emits light of a first color; When the first data line and the second data line are not short-circuited, the other sub-pixels in the pixel unit do not emit light; when the first data line and the second data line are short-circuited, at least one sub-pixel connected to the second data line that is short-circuited to the first data line emits light of a second color, and the first color is different from the second color.

24. The detection method according to claim 23, further comprising: In the second detection phase, multiple gate test signals, first data test signals, and second data test signals are provided to the multiple gate lines, the first data line, and the second data line, respectively. At least a portion of the gate test signal is at the working level, while the remaining portion of the gate test signal, the first data test signal, and the second data test signal are at the non-working level. In response to the gate test signal, the first data test signal, and the second data test signal, none of the sub-pixels in the pixel unit emit light.

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