Photoelectric packaging structure and manufacturing method therefor

Abstract

The present invention provides a photoelectric packaging structure and a manufacturing method therefor. During packaging, an optical chip is connected to micro solder bumps within a pad area of an image sensor by means of a fan-out process, thereby achieving large-scale and high-density photoelectric co-packaging of the optical chip and the image sensor. A distance between an image area of the image sensor and a grating coupling-out area of the optical chip is controlled to be within 30 μm, so that it can be ensured that the image sensor is closely aligned with the optical chip to receive an optical signal of the optical chip, and an electric signal from the image sensor is led out to a substrate by means of a second lead, thereby effectively reducing the difficulty of signal transmission between the optical chip and the image sensor and other devices. In addition, the photoelectric packaging structure is simple and has low manufacturing costs, thereby improving the yield and prolonging the service life of a finished product of the photoelectric packaging structure.

Description

A photoelectric packaging structure and its fabrication method Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to an optoelectronic packaging structure and its fabrication method. Background Technology

[0002] Image sensors, as core components for photoelectric conversion, play a vital role in machine vision, communication, and medical fields. Optical chips, as key components for light sources or optical signal processing, are crucial for improving system performance when integrated with image sensors. However, the problem of electrical signal extraction is becoming increasingly prominent during the integration of image sensors and optical chips.

[0003] Currently, image sensor designs on the market generally employ a highly integrated layout, placing the image area and electrical signal window on the same plane. This design is relatively simple to manufacture and has low cost, thus gaining widespread use in many application areas. However, with continuous technological advancements and increasingly diverse application requirements, this design has gradually revealed some limitations. The problem is particularly pronounced when the image sensor needs to be closely bonded to an optical chip to receive the light signals emitted by the chip. Because the image area and electrical signal window are on the same plane, the signal extraction path is severely restricted when they are closely bonded. When the distance between them is greater, the number of pixels occupied by the light spot increases, resulting in higher noise levels, and overlap between adjacent light spots can cause crosstalk between channels. Furthermore, it can also lead to signal interference and attenuation, severely affecting the performance and stability of the image sensor.

[0004] Therefore, it is necessary to improve the existing bonding and packaging process of image sensors and optical chips.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an optoelectronic packaging structure and its preparation method, which solves the problem in the prior art where image sensors and optical chips are bonded and co-packaged to receive optical signals emitted by the optical chip at close range, resulting in severely limited output paths for electrical signals, which leads to increased signal transmission difficulty and potential signal interference and attenuation, seriously affecting the performance of the image sensor.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating an optoelectronic packaging structure, the method comprising the following steps:

[0008] An optical chip is provided, the surface of which has a grating coupling-in region and a grating coupling-out region;

[0009] A first electrical pin and a second electrical pin are formed on the surface of the optical chip, and the first electrical pin and the second electrical pin are connected by a first lead.

[0010] A solder resist layer is formed on the surface of the optical chip, the solder resist layer exposing the grating coupling region, the grating coupling out region, the first electrical pin and the second electrical pin;

[0011] An image sensor is provided, the image sensor having an image region located at a central position and a pad region distributed circumferentially along the image region, the pad region being electrically connected to the optical chip;

[0012] A substrate is provided, and a first gap is formed between the optical chip and the substrate. The first gap is filled with curing adhesive, and the curing adhesive is cured at high temperature to achieve the connection and fixation between the optical chip and the substrate.

[0013] A cover plate is provided, the cover plate having a light window facing the grating coupling area, and the cover plate is fixed to the substrate to complete the encapsulation of the optical chip and the image sensor.

[0014] Optionally, a micro solder bump is formed between the pad area of ​​the image sensor and the first electrical pin to achieve electrical connection between the optical chip and the image sensor through the micro solder bump. The formation process of the micro solder bump includes one of laser ball-mounting technology, ultrasonic soldering ball-mounting technology, solder paste printing ball-mounting technology, electroplating bump technology, or vapor deposition bump technology.

[0015] Optionally, the shape of the micro solder bumps can be one of sphere, cylinder, cone, frustum, or cuboid.

[0016] Optionally, the first electrical pin is distributed circumferentially along the edge of the grating coupling region, and the second electrical pin is distributed circumferentially along the edge of the optical chip.

[0017] Optionally, a second lead that is insensitive to thermal mismatch of materials is provided between the substrate and the second electrical pin, so as to achieve electrical connection between the optical chip and the substrate by welding.

[0018] Optionally, the substrate includes one of a glass substrate, a semiconductor substrate, a polymer substrate, or a ceramic substrate that is thermally adapted to the optical chip.

[0019] The present invention also provides an optoelectronic packaging structure, the optoelectronic packaging structure comprising:

[0020] The substrate, located at the bottom of the co-package structure, is used to provide mechanical strength support;

[0021] A cover plate, wherein the cover plate is provided with a light window, and the cover plate is connected to the substrate and together with the substrate form an accommodating space;

[0022] An optical chip is located within the accommodating space and forms a first gap with the substrate. The surface of the optical chip has a grating coupling-in region and a grating coupling-out region, and the grating coupling-in region is positioned directly opposite the optical window.

[0023] A curing adhesive is used to fill the first gap so as to fix the optical chip to the substrate.

[0024] A solder resist layer is located on the optical chip, and the solder resist layer exposes the grating coupling-in region and the grating coupling-out region;

[0025] An image sensor is located above and electrically connected to the optical chip. The image sensor has an image area located at the center and a pad area distributed circumferentially along the image area. The image area is positioned opposite the grating coupling area.

[0026] Optionally, the surface of the optical chip is further provided with a first electrical pin and a second electrical pin. The first electrical pin is distributed circumferentially along the edge of the grating coupling region, and the second electrical pin is distributed circumferentially along the edge of the optical chip. The first electrical pin and the second electrical pin are connected by a first lead.

[0027] Optionally, the solder mask layer further exposes the first electrical pin and the second electrical pin, and a micro solder bump is provided between the first electrical pin and the pad area of ​​the image sensor to realize the electrical connection between the optical chip and the image sensor. A second lead is provided between the second electrical pin and the substrate to realize the electrical connection between the optical chip and the substrate.

[0028] Optionally, the micro solder bumps include one of gold balls, copper balls, tin balls, or tin-silver-copper alloy solder balls, and the diameter of the micro solder bumps ranges from 18 to 30 μm.

[0029] Optionally, the micro solder bumps include one of gold pillars, copper pillars, indium pillars, tin pillars, or tin-silver-copper alloy pillars, and the height of the micro solder bumps is less than 30 μm.

[0030] This invention also provides another method for fabricating an optoelectronic packaging structure, the method comprising the following steps:

[0031] An optical chip is provided, the surface of which has a grating coupling-in region and a grating coupling-out region;

[0032] A temporary carrier and a second wafer are provided. The second wafer includes a plurality of image sensor chips, each of which has an image area and a pad area. The second wafer and the temporary carrier are bonded together by a release layer.

[0033] A first etching process is performed to etch the second wafer to form a first via, the first via exposing a portion of the pad area;

[0034] A metal wiring layer and a solder mask layer are sequentially formed in the first through-hole. One end of the metal wiring layer is connected to the pad area, and the other end of the metal wiring layer covers the back side of the second wafer. The solder mask layer completely covers the second wafer and the metal wiring layer.

[0035] Photolithography is used to form solder resist openings in the solder resist layer, which expose the metal wiring layer covering the back side of the second wafer.

[0036] A substrate is provided, the optical chip is bonded to the substrate, and the image sensor chip is bonded to the optical chip. A first curing adhesive is filled between the optical chip and the substrate, and a second curing adhesive is filled between the image sensor chip and the optical chip, thereby realizing the connection and fixation of the image sensor chip, the optical chip and the substrate.

[0037] A cover plate is provided, the cover plate having a light window, the cover plate covering the substrate to complete the packaging of the optical chip and the image sensor chip.

[0038] Optionally, the light window is positioned opposite the grating coupling area of ​​the optical chip, and the image sensor chip is positioned opposite the grating coupling area of ​​the optical chip.

[0039] Optionally, the second cured adhesive is a non-conductive epoxy resin adhesive with high light transmittance.

[0040] Optionally, the image region is located at the center of the image sensor chip, and the pad region is distributed circumferentially along the edge of the image sensor chip.

[0041] Optionally, before bonding the optical chip to the substrate, the method further includes forming a groove in the substrate to accommodate the optical chip and the image sensor chip through the groove, wherein the method of forming the groove includes a laser drilling process.

[0042] Optionally, the process further includes cutting the wafer according to a preset dicing groove on the second wafer, cutting the second wafer into individual image sensor chips, and performing a debonding process on the image sensor chips to remove the temporary carrier and release layer.

[0043] Optionally, a first lead that is insensitive to thermal mismatch of materials is provided between the substrate and the metal wiring layer exposed by the solder mask opening, so as to realize the electrical connection between the image sensor chip and the substrate by soldering.

[0044] Optionally, the substrate includes one of a metal substrate, a glass substrate, a semiconductor substrate, a polymer substrate, or a ceramic substrate that is thermally adapted to the optical chip.

[0045] The present invention also provides another optoelectronic packaging structure, the optoelectronic packaging structure comprising:

[0046] The substrate, located at the bottom layer of the optoelectronic packaging structure, is used to provide mechanical strength support;

[0047] A cover plate, wherein the cover plate is provided with a light window, the cover plate is connected to the substrate and together with the groove of the substrate to form an accommodating space;

[0048] An optical chip is located within the accommodating space and is filled with a first curing adhesive between itself and the substrate. The surface of the optical chip has a grating coupling-in region and a grating coupling-out region.

[0049] An image sensor chip is located above an optical chip and a second curing adhesive is filled between the two chips. The image sensor chip has an image area located at the center and a pad area distributed circumferentially along the edge of the image sensor chip. A first through-hole is formed in the image sensor chip to expose the pad area.

[0050] A metal wiring layer is located within the first via and on the back side of the image sensor chip to electrically lead the pad area to the back side of the image sensor chip.

[0051] A solder resist layer is located on the back side of the image sensor chip. The solder resist layer has a solder resist window to expose the metal wiring layer, and a first lead is disposed in the solder resist window. The two ends of the first lead are electrically connected to the metal wiring layer exposed by the solder resist window and the substrate, respectively.

[0052] Optionally, the light window is positioned opposite the grating coupling area of ​​the optical chip, and the image sensor chip is positioned opposite the grating coupling area of ​​the optical chip.

[0053] As described above, the optoelectronic packaging structure and its fabrication method of the present invention have the following advantages compared with the prior art: The fan-out process is used to complete the micro solder bump connection between the optical chip and the image sensor, achieving large-scale, high-density optoelectronic co-packaging of the optical chip and the image sensor. Furthermore, the distance between the image area of ​​the image sensor and the grating coupling area of ​​the optical chip can be controlled to be within 30 μm. This ensures that while the image sensor and the optical chip are in close contact to receive the optical signal from the optical chip, the electrical signal of the image sensor can also be led out to the substrate through the second lead, effectively reducing the signal transmission difficulty between the optical chip, the image sensor, and other devices. Further, by forming a... A first through-hole is formed, and a metal wiring layer and a solder mask layer are formed on the back of the first through-hole and the image sensor chip, thereby leading the electrical signal of the image sensor chip from the front to the back. This ensures that the distance between the image sensor chip and the grating coupling surface of the optical chip can be controlled within 10μm. This allows for close-range reception of the optical signal from the optical chip, while the electrical signal of the image sensor chip can also be led to the substrate through the metal wiring layer on the back of the image sensor chip via the formed solder mask opening. This effectively reduces the signal transmission difficulty between the optical chip, the image sensor chip, and other devices. This optoelectronic packaging structure is relatively simple, has a low manufacturing cost, and can improve the yield and service life of the finished optoelectronic packaging structure. Attached Figure Description

[0054] Figure 1 shows a process flow diagram of the preparation method of the optoelectronic packaging structure in Embodiment 1 of the present invention.

[0055] Figure 2 shows a top view of the optical chip in the optoelectronic packaging structure of Embodiment 1 of the present invention.

[0056] Figure 3 shows a top view of the optoelectronic packaging structure in Embodiment 1 of the present invention, illustrating the formation of the first electrical pin and the second electrical pin.

[0057] Figure 4 shows a top view of the optoelectronic packaging structure after the solder resist layer is formed in Embodiment 1 of the present invention.

[0058] Figure 5 shows a top view of the image sensor in the optoelectronic packaging structure of Embodiment 1 of the present invention.

[0059] Figure 6 shows a cross-sectional view of the coupling between the image sensor and the optical chip in the optoelectronic packaging structure of Embodiment 1 of the present invention.

[0060] Figure 7 shows a schematic diagram of the coupling between the optical chip and the substrate in the optoelectronic packaging structure of Embodiment 1 of the present invention.

[0061] Figure 8 shows a cross-sectional schematic diagram of the optoelectronic packaging structure formed in Embodiment 1 and Embodiment 2 of the present invention.

[0062] Figure 9 shows a process flow diagram of the preparation method of the optoelectronic packaging structure in Embodiment 3 of the present invention.

[0063] Figure 10 shows a top view of the optical chip provided in the optoelectronic packaging structure of Embodiment 3 of the present invention.

[0064] Figure 11 shows a schematic cross-sectional view of the temporary carrier and the second wafer provided in the optoelectronic packaging structure of Embodiment 3 of the present invention.

[0065] Figure 12 shows a schematic cross-sectional view of the second wafer after grinding in the optoelectronic packaging structure of Embodiment 3 of the present invention.

[0066] Figure 13 shows a cross-sectional view of the optoelectronic packaging structure after the first through-hole is formed in Embodiment 3 of the present invention.

[0067] Figure 14 shows a cross-sectional view of the optoelectronic packaging structure after the metal wiring layer and solder mask layer are formed in Embodiment 3 of the present invention.

[0068] Figure 15 shows a cross-sectional view of the optoelectronic packaging structure after the solder resist window is formed in Embodiment 3 of the present invention.

[0069] Figure 16 shows a top view of the image sensor chip formed after cutting the second wafer in the optoelectronic packaging structure of Embodiment 3 of the present invention.

[0070] Figure 17 shows a schematic diagram of the structure after the optical chip is coupled to the substrate in the optoelectronic packaging structure of Embodiment 3 of the present invention.

[0071] Figure 18 shows a cross-sectional view of the image sensor chip and the optical chip coupled in the optoelectronic packaging structure of Embodiment 3 of the present invention.

[0072] Figure 19 shows a cross-sectional schematic diagram of the optoelectronic packaging structure in Embodiments 3 and 4 of the present invention.

[0073] Component Labeling Explanation: 10. Optical Chip; 101. Grating Coupled-in Region; 102. Grating Coupled-out Region; 11. First Electrical Pin; 12. Second Electrical Pin; 13. First Lead; 14. Image Sensor; 141. Image Area; 142. Micro Solder Bump; 15. Substrate; 16. Second Lead; 17. Curing Adhesive; 18. Cover Plate; 181. Light Window; 19. Solder Mask Layer; S1-S6, Steps; 20. Optical Chip; 201. Grating Coupled-in Region; 20 2. Grating coupling area; 21. Second wafer; 22. Image sensor chip; 221. Image area; 222. Pad area; 23. Temporary carrier; 24. Release layer; 251. First via; 252. Solder resist window; 26. Metal wiring layer; 27. Solder resist layer; 28. Substrate; 281. Accommodating space; 291. First curing adhesive; 292. Second curing adhesive; 30. First lead; 31. Cover plate; 311. Light window; S11~S17, Steps. Detailed Implementation

[0074] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0075] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0076] Please refer to Figures 1 to 19. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and are not intended to limit the scope of the invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of the invention, should still fall within the scope of the technical content disclosed in this invention. Furthermore, the terms such as "upper," "lower," "left," "right," "middle," "first," and "second" used in this specification are merely for clarity and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention.

[0077] Example 1

[0078] This embodiment provides a method for fabricating an optoelectronic packaging structure, as shown in Figure 1, which is a flowchart of the fabrication process, including the following steps:

[0079] S1: Provide an optical chip 10, the surface of which has a grating coupling-in region 101 and a grating coupling-out region 102;

[0080] S2: A first electrical pin 11 and a second electrical pin 12 are formed on the surface of the optical chip 10, and the first electrical pin 11 and the second electrical pin 12 are connected by a first lead 13.

[0081] S3: A solder resist layer 19 is formed on the surface of the optical chip 10, the solder resist layer 19 exposing the grating coupling region 101, the grating coupling region 102, the first electrical pin 11 and the second electrical pin 12;

[0082] S4: An image sensor 14 is provided, the image sensor 14 having an image region 141 located at a central position and a pad region distributed circumferentially along the image region 141, the pad region being electrically connected to the optical chip 10;

[0083] S5: A substrate 15 is provided, a first gap is formed between the optical chip 10 and the substrate 15, the first gap is filled with curing adhesive 17, and the curing adhesive 17 is cured and heated at high temperature to realize the connection and fixation between the optical chip 10 and the substrate 15.

[0084] S6: A cover plate 18 is provided, the cover plate 18 is provided with a light window 181, the light window 181 is directly opposite the grating coupling area 101, and the cover plate 18 is fixed on the substrate 15 to complete the encapsulation of the optical chip 10 and the image sensor 14.

[0085] The fabrication method of the aforementioned optoelectronic packaging structure is further described below with reference to the accompanying drawings:

[0086] In step S1, referring to Figures 1 and 2, an optical chip 10 is provided, the surface of which has a grating coupling region 101 and a grating coupling out region 102.

[0087] In this embodiment, the semiconductor wafer is cut along the dicing groove area on the semiconductor wafer to separate several optical chip 10 areas to form several individual optical chips 10. In the above process, the individual separation of the optical chips 10 is achieved and it can be ensured that the optical chips 10 are not contaminated by contaminants generated during the dicing process. It can also ensure the integrity and reliability of the circuit function of the optical chips 10.

[0088] Specifically, as shown in Figure 2, which is a top view of the optical chip 10, the surface of the optical chip 10 has a grating coupling region 101 and a grating coupling region 102. The grating coupling region 101 is used to couple light into the optical chip 10, and the grating coupling region 102 is used to couple the image light transmitted within the optical chip 10 to the image sensor 14. An optical waveguide formed by optical wire bonding technology is disposed between the grating coupling region 101 and the grating coupling region 102, so that the signal transmission path between adjacent grating coupling regions 101 and grating coupling regions 102 is no longer metal, but an optical waveguide. Optionally, the shape of the optical waveguide can be linear, curved, or other shapes.

[0089] In step S2, referring to Figures 1 and 3, a first electrical pin 11 and a second electrical pin 12 are formed on the surface of the optical chip 10, and the first electrical pin 11 and the second electrical pin 12 are connected by a first lead 13.

[0090] Specifically, as shown in Figure 3, in this embodiment, a first electrical pin 11 and a second electrical pin 12 adapted to and electrically connected to the first electrical pin 11 are formed along the surface of the optical chip 10. Both the first electrical pin 11 and the second electrical pin 12 are fabricated using thin-film technology, and a first lead 13 is provided on the first electrical pin 11 and the second electrical pin 12. The first lead 13 is used to electrically connect the first electrical pin 11 and the second electrical pin 12. This connection utilizes the mature wire bonding technology, saving packaging costs, and also avoids packaging problems caused by material thermal mismatch. Optionally, the first electrical pin 11 and the second electrical pin 12 are made of materials with excellent conductivity. In this embodiment, the first electrical pin 11 and the second electrical pin 12 are made of copper alloy. Of course, in other embodiments, other suitable metal materials can be selected for the first electrical pin 11 and the second electrical pin 12.

[0091] In other embodiments, the first electrical pin 11 is distributed circumferentially along the edge of the grating coupling region 102, and the second electrical pin 12 is distributed circumferentially along the edge of the optical chip 10. This arrangement allows for a shorter distance between the pad area of ​​the image sensor 14 and the first electrical pin 11 of the optical chip 10 during subsequent bonding processes, thereby improving signal transmission speed and reducing the size of the package structure.

[0092] In step S3, referring to Figures 1 and 4, a solder resist layer 19 is formed on the surface of the optical chip 10, the solder resist layer 19 exposing the grating coupling region 101, the grating coupling region 102, the first electrical pin 11 and the second electrical pin 12.

[0093] As shown in Figure 4, a solder resist layer 19 is formed on the surface of the optical chip 10, exposing a grating coupling region 101, a grating coupling out region 102, a first electrical pin 11, and a second electrical pin 12. In this embodiment, the process for forming the solder resist layer 19 includes one of a liquid sealant curing process, a vacuum lamination process, and a spin coating process; the solder resist layer 19 includes one of an epoxy resin layer, a polyimide layer, and a silicone layer. Optionally, after forming the solder resist layer 19, a planarization process is also included. The planarization process can maintain a suitable thickness for the package structure, which is beneficial for reducing the volume of the package structure and improving the package quality.

[0094] Specifically, in this embodiment, the process of forming the solder resist layer 19 is as follows: after screen printing solder resist ink on the surface of the optical chip 10, it is sequentially subjected to pre-curing, exposure, development and thermal curing treatments to cure the solder resist ink into the solder resist layer 19. This coats a layer on the lines and pins that do not need to be soldered, preventing bridging between lines during soldering, providing a permanent electrical environment and chemical corrosion resistance, and also enhancing the appearance.

[0095] In step S4, referring to Figures 1, 5 and 6, an image sensor 14 is provided. The image sensor 14 has an image region 141 located at the center and a pad region distributed circumferentially along the image region 141. The pad region is electrically connected to the optical chip 10.

[0096] Specifically, as shown in Figure 5, which is a top view of the image sensor 14, the surface of the image sensor 14 has an image area 141 and a pad area. After packaging, the image area 141 is positioned directly opposite the grating coupling area 102, so that the image sensor 14 can receive image light received from the grating coupling area 101 and transmitted to the grating coupling area 102. The image area 141 is located at the center of the image sensor 14. The pad area is distributed circumferentially along the image area 141 and is positioned corresponding to the first pin. Micro solder bumps 142 are formed on the pad area using laser ball bonding technology, ultrasonic soldering ball bonding technology, solder paste printing ball bonding technology, electroplating bump technology, or vapor deposition bump technology. After all the micro solder bumps 142 are formed, as shown in Figure 6, the pad area forms an electrical connection with the first electrical pin 11 through the micro solder bumps 142, thereby realizing the electrical connection between the optical chip 10 and the image sensor 14.

[0097] As an example, the shape of the micro solder bump 142 is one of sphere, cylinder, cone, frustum, or cuboid.

[0098] Specifically, as shown in Figure 6, the shape of the micro solder bumps 142 formed on the pad area can be one of sphere, cylinder, cone, frustum, or cuboid. By creating various irregular bumps, a structural basis is provided for researching and developing new bonding methods between the optical chip 10 and the image sensor 14.

[0099] In step S5, referring to Figures 1 and 7, a substrate 15 is provided, and a first gap is formed between the optical chip 10 and the substrate 15. The first gap is filled with curing adhesive 17, and the curing adhesive 17 is cured and heated at high temperature to achieve the connection and fixation between the optical chip 10 and the substrate 15.

[0100] As an example, the substrate 15 includes one of a glass substrate 15, a semiconductor substrate 15, a polymer substrate 15, or a ceramic substrate 15 that is thermally adapted to the optical chip 10.

[0101] Specifically, as shown in Figure 7, the substrate 15 can be a glass substrate 15, a semiconductor substrate 15, a polymer substrate 15, or a ceramic substrate 15. The present invention does not particularly limit its material, properties, or internal structure. Preferably, in this embodiment, the substrate 15 is a ceramic substrate 15 that is thermally compatible with the optical chip 10. The accommodating space formed by the substrate 15 and the cover plate 18 can protect the packaging structure, prevent it from being affected by the external environment during use, prevent damage to the packaging structure, and improve the service life of the packaging structure.

[0102] As shown in Figure 7, during the bonding process between the optical chip 10 and the substrate 15, a first gap is formed between the optical chip 10 and the substrate 15. In order to improve the strength of the packaging structure, the first gap needs to be filled with curing adhesive 17, and the curing adhesive 17 is subjected to high-temperature curing heating. The technical principle of high-temperature curing heating is to use high-temperature hot air to heat the curing adhesive 17, so that the curing adhesive 17 in the first gap is fused under the action of high-temperature hot air, thereby forming a larger contact area to realize the connection and fixation between the optical chip 10 and the substrate 15.

[0103] As an example, a second lead 16 that is insensitive to thermal mismatch of materials is provided between the substrate 15 and the second electrical pin 12, so as to realize the electrical connection between the optical chip 10 and the substrate 15 by welding.

[0104] Specifically, in order to lead the electrical signal of the image sensor 14 to an external device, a second lead 16 is provided between the substrate 15 and the second electrical pin 12. The second lead 16 is made of a material that is not sensitive to thermal mismatch. Then, one end of the second lead 16 is soldered to the second electrical pin 12 and the other end of the second lead 16 is soldered to the substrate 15 to achieve electrical connection between the optical chip 10 and the substrate 15, thereby avoiding thermal mismatch problems in the packaging structure.

[0105] In step S6, referring to Figures 1 and 8, a cover plate 18 is provided, on which a light window 181 is provided. The light window 181 faces the grating coupling area 101. The cover plate 18 is fixed on the substrate 15 to complete the encapsulation of the optical chip 10 and the image sensor 14.

[0106] Specifically, as shown in Figure 8, a light window 181 is provided on the cover plate 18, and the light window 181 is positioned directly opposite the grating coupling region 101, so that light is coupled into the grating coupling region 101 of the optical chip 10 through the light window 181. After the optical chip 10 and the substrate 15 are bonded, the cover plate 18 is fixed on the substrate 15, thereby completing the optoelectronic co-packaging of the optical chip 10 and the image sensor 14.

[0107] In the method for fabricating an optoelectronic packaging structure in this embodiment, a fan-out process is used to connect the micro solder bumps 142 of the optical chip 10 and the image sensor 14, thereby achieving large-scale, high-density optoelectronic co-packaging of the optical chip 10 and the image sensor 14. The distance between the image area 141 of the image sensor 14 and the grating coupling area 102 of the optical chip 10 can be controlled. This ensures that the image sensor 14 and the optical chip 10 are in close contact to receive the optical signal of the optical chip 10, and also ensures that the electrical signal of the image sensor 14 is led out to the substrate 15 through the second lead 16, thereby effectively reducing the signal transmission difficulty between the optical chip 10, the image sensor 14, and other devices.

[0108] Example 2

[0109] This embodiment provides an optoelectronic packaging structure, as shown in Figure 8, which is a cross-sectional schematic diagram of the optoelectronic packaging structure. The optoelectronic packaging structure includes: a substrate 15, located at the bottom layer of the co-packaging structure, used to provide mechanical strength support; a cover plate 18, on which a light window 181 is provided, the cover plate 18 being connected to the substrate 15 and forming an accommodating space with the substrate 15; and an optical chip 10, located within the accommodating space and forming a first gap with the substrate 15, the surface of the optical chip 10 having a grating coupling-in region 101 and a grating coupling-out region 102, the grating coupling-in region 101 being positioned directly opposite the light window 181. The optical chip 10 is fixedly connected to the substrate 15 by: a curing adhesive 17 filling the first gap; a solder resist layer 19 located on the optical chip 10, exposing the grating coupling-in region 101 and the grating coupling-out region 102; and an image sensor 14 located above and electrically connected to the optical chip 10, the image sensor 14 having an image region 141 located at the center and pad regions distributed circumferentially along the image region 141, the image region 141 being positioned directly opposite the grating coupling-out region 102.

[0110] As an example, the surface of the optical chip 10 is also provided with a first electrical pin 11 and a second electrical pin 12. The first electrical pin 11 is distributed circumferentially along the edge of the grating coupling region 102, and the second electrical pin 12 is distributed circumferentially along the edge of the optical chip 10. The first electrical pin 11 and the second electrical pin 12 are connected by a first lead 13.

[0111] Optionally, the first electrical pin 11 and the second electrical pin 12 are made of a material with excellent electrical conductivity. In this embodiment, the first electrical pin 11 and the second electrical pin 12 are made of copper alloy. Of course, in other embodiments, the first electrical pin 11 and the second electrical pin 12 can also be made of other suitable metal materials.

[0112] In this embodiment, the first electrical pin 11 is distributed circumferentially along the edge of the grating coupling region 102, and the second electrical pin 12 is distributed circumferentially along the edge of the optical chip 10. This arrangement allows for a shorter distance between the pad area of ​​the image sensor 14 and the first electrical pin 11 of the optical chip 10 during subsequent bonding processes, thereby improving signal transmission speed and reducing the size of the package structure.

[0113] As an example, the solder mask layer 19 also exposes the first electrical pin 11 and the second electrical pin 12, and a micro solder bump 142 is provided between the first electrical pin 11 and the pad area of ​​the image sensor 14 to realize the electrical connection between the optical chip 10 and the image sensor 14. A second lead 16 is provided between the second electrical pin 12 and the substrate 15 to realize the electrical connection between the optical chip 10 and the substrate 15.

[0114] Specifically, in addition to exposing the grating coupling-in region 101 and the grating coupling-out region 102, the solder mask layer 19 also exposes the first electrical pin 11 and the second electrical pin 12, so that the first electrical pin 11 can be electrically connected to the pad area of ​​the image sensor 14. The planarized solder mask layer 19 also allows the package structure to maintain a suitable thickness, which is beneficial to reducing the volume of the package structure and improving the package quality. Micro solder bumps 142 are also provided on the pad area to achieve electrical connection between the image sensor 14 and the optical chip 10 through the micro solder bumps 142. In order to lead the electrical signal of the image sensor 14 to an external device, a second lead 16 is provided between the substrate 15 and the second electrical pin 12. The second lead 16 is made of a material that is not sensitive to thermal mismatch. Then, one end of the second lead 16 is soldered to the second electrical pin 12 and the other end of the second lead 16 is soldered to the substrate 15 to realize the electrical connection between the optical chip 10 and the substrate 15 and avoid thermal mismatch problems in the packaging structure.

[0115] As an example, the micro solder bumps include one of gold balls, copper balls, tin balls, or tin-silver-copper alloy solder balls, and the diameter of the micro solder bumps ranges from 18 to 30 μm.

[0116] Optionally, the micro solder bump 142 includes one of gold ball, copper ball, tin ball or tin-silver-copper alloy solder ball, and its diameter ranges from 18 to 30 μm, for example: 18 μm, 24 μm or 30 μm, to achieve better electrical connection between the first electrical pin 11 and the pad area.

[0117] As an example, the micro solder bump 142 includes one of gold pillars, copper pillars, indium pillars, tin pillars, or tin-silver-copper alloy pillars, and the height of the micro solder bump 142 is less than 30 μm.

[0118] Optionally, the micro solder bump 142 includes one of gold pillars, copper pillars, indium pillars, tin pillars, or tin-silver-copper alloy pillars. Specifically, in this embodiment, the micro solder bump 142 formed on the pad area is cylindrical in shape and its height is less than 30 μm, for example, 8 μm, 18 μm, or 28 μm, so as to achieve better electrical connection between the first electrical pin 11 and the pad area.

[0119] Example 3

[0120] This embodiment provides a method for fabricating an optoelectronic packaging structure, as shown in Figure 9, which is a flowchart of the fabrication process, including the following steps:

[0121] S11: Provide an optical chip 20, the surface of which has a grating coupling-in region 201 and a grating coupling-out region 202;

[0122] S12: A temporary carrier 23 and a second wafer 21 are provided. The second wafer 21 includes a plurality of image sensor chips 22. Each image sensor chip 22 is provided with an image area 221 and a pad area 222. The second wafer 21 and the temporary carrier 23 are bonded together through a release layer 24.

[0123] S13: Perform a first etching process to etch the second wafer 21 to form a first through-hole 251, the first through-hole 251 exposing a portion of the pad area 222;

[0124] S14: A metal wiring layer 26 and a solder mask layer 27 are sequentially formed in the first through hole 251. One end of the metal wiring layer 26 is connected to the pad area 222, and the other end of the metal wiring layer 26 covers the back side of the second wafer 21. The solder mask layer 27 completely covers the second wafer 21 and the metal wiring layer 26.

[0125] S15: Photolithography is used to form a solder resist window 252 on the solder resist layer 27, the solder resist window 252 exposes the metal wiring layer 26 covering the back side of the second wafer 21.

[0126] S16: A substrate 28 is provided, the optical chip 20 is bonded to the substrate 28, and the image sensor chip 22 is bonded to the optical chip 20. A first curing adhesive 291 is filled between the optical chip 20 and the substrate 28, and a second curing adhesive 292 is filled between the image sensor chip 22 and the optical chip 20, thereby realizing the connection and fixation of the image sensor chip 22, the optical chip 20 and the substrate 28.

[0127] S17: A cover plate 31 is provided, the cover plate 31 is provided with a light window 311, the cover plate 31 covers the substrate 28 to complete the encapsulation of the optical chip 20 and the image sensor chip 22.

[0128] The fabrication method of the aforementioned optoelectronic packaging structure is further described below with reference to the accompanying drawings:

[0129] In step S11, referring to Figures 9 and 10, an optical chip 20 is provided, the surface of which has a grating coupling region 201 and a grating coupling out region 202.

[0130] In this embodiment, a first semiconductor wafer is provided, which includes a plurality of optical chip 20 regions. The first semiconductor wafer is diced along a dicing groove region to separate the plurality of optical chip 20 regions, thereby forming a plurality of individual optical chips 20. This process achieves individual separation of the optical chips 20, ensures that the optical chips 20 are not contaminated by pollutants generated during the dicing process, and also guarantees the integrity and reliability of the circuit functions of the optical chips 20.

[0131] Specifically, as shown in Figure 10, which is a top view of the optical chip 20 in this embodiment, the surface of the optical chip 20 has a grating coupling region 201 and a grating coupling region 202. The grating coupling region 201 is used to couple light into the optical chip 20, and the grating coupling region 202 is used to couple the image light transmitted within the optical chip 20 to the image sensor chip 22. An optical waveguide formed by optical wire bonding technology is disposed between the grating coupling region 201 and the grating coupling region 202, so that the signal transmission path between adjacent grating coupling regions 201 and grating coupling regions 202 is no longer metal, but an optical waveguide. Optionally, the shape of the optical waveguide can be linear, curved, or other shapes.

[0132] In step S12, referring to Figures 9 and 11, a temporary carrier 23 and a second wafer 21 are provided. The second wafer 21 includes a plurality of image sensor chips 22. Each image sensor chip 22 is provided with an image area 221 and a pad area 222. The second wafer 21 and the temporary carrier 23 are bonded together through a release layer 24.

[0133] Optionally, the temporary carrier 23 may be one of the following non-metallic materials: silicon oxide carrier, glass carrier, ceramic carrier, polymer carrier, etc. Its shape may be circular, square or any other desired shape. There are no special restrictions here, and the specific selection is made according to the needs.

[0134] Specifically, in this embodiment, the temporary carrier 23 is coated with a release layer 24, which has the characteristic of being able to adhere to other components and cure after being heated at high temperature, thereby enabling the fixation of the second wafer 21.

[0135] Specifically, in this embodiment, the temporary carrier 23 is a glass carrier with a low coefficient of thermal expansion. On the one hand, the glass carrier substrate 28 has a low coefficient of thermal expansion, which can reduce the warping generated during the cutting of the second wafer 21. On the other hand, the glass carrier has a low cost, and it is easy to form a release layer 24 on its surface, which reduces the difficulty of subsequent removal processes.

[0136] Optionally, the release layer 24 may include a polymer layer or a strip adhesive layer.

[0137] Specifically, the material of the release layer 24 can be selected from adhesive tapes with adhesive on both sides (such as chip attachment films or non-conductive films, etc.) or adhesives made by spin coating processes; preferably, in this embodiment, the release layer 24 is preferably a UV adhesive, which has the characteristic of easily undergoing denaturation and peeling after UV light (ultraviolet light) irradiation; of course, in other examples, the release layer 24 can also be other material layers formed by physical vapor deposition, chemical vapor deposition, screen printing or spraying methods, such as epoxy resin, silicone rubber, polyimide, etc., and the release layer 24 can be removed by wet etching, chemical mechanical polishing or other methods when separating the temporary carrier 23.

[0138] In this embodiment, a second wafer 21 is provided, which includes a plurality of image sensor chips 22, and each image sensor chip 22 is provided with an image area 221 and a pad area 222. Specifically, as shown in FIG11, after the second wafer 21 is bonded to the temporary carrier 23 through the release layer 24, the back side of the second wafer 21 is exposed.

[0139] In step S13, referring to Figures 9, 12 and 13, a first etching process is performed to etch the second wafer 21 to form a first via 251, which exposes a portion of the pad area 222.

[0140] As an example, as shown in Figure 12, after bonding the second wafer 21 to the temporary carrier 23, the process also includes grinding and planarizing the second wafer 21 to maintain a suitable thickness, which helps to reduce the volume of the subsequently formed optoelectronic packaging structure and improve the packaging quality of the optoelectronic packaging structure.

[0141] Specifically, in this embodiment, as shown in FIG13, a first etching process is performed to form a photoresist mask layer on the back side of the second wafer 21. The photoresist mask layer is then exposed and developed to form a patterned photoresist mask layer. Based on the patterned photoresist mask layer, the second wafer 21 is etched to form a first via 251 on the back side of the second wafer 21. The first via 251 exposes the pad area 222 in the image sensor chip 22. The photoresist mask layer is then removed. The composition, flow rate, and process conditions of the etching gas used in the first etching process are well known in the art, and those skilled in the art can select and adjust them according to actual needs; further details are omitted here.

[0142] In step S14, referring to Figures 9 and 14, a metal wiring layer 26 and a solder mask layer 27 are sequentially formed in the first through-hole 251. One end of the metal wiring layer 26 is connected to the pad area 222, and the other end of the metal wiring layer 26 covers the back side of the second wafer 21. The solder mask layer 27 completely covers the second wafer 21 and the metal wiring layer 26.

[0143] As shown in Figure 14, a metal wiring layer 26 is formed by physical vapor deposition within the first via 251, extending to the back side of the second wafer 21, thereby guiding the electrical signals of the image sensor chip 22 from the front to the back. Optionally, the material of the metal wiring layer 26 is one or a combination of copper, aluminum, nickel, gold, silver, and titanium. Specifically, in this embodiment, the material of the metal wiring layer 26 is preferably copper, because copper not only has good conductivity but also very good ductility. Placing copper between the pad area 222 and the solder mask layer 27 helps to improve the electrical conductivity of the optoelectronic packaging structure. After forming the metal wiring layer 26, a chemical mechanical polishing process is used for planarization to give the top of the metal wiring layer 26 a flat surface, allowing the metal wiring layer 26 to form good contact with the pad area 222 on the front side of the second wafer 21, achieving better electrical connection.

[0144] Optionally, the process for forming the solder resist layer 27 includes one of a liquid sealant curing process, a vacuum lamination process, and a spin coating process. The solder resist layer 27 includes one of an epoxy resin layer, a polyimide layer, and a silicone layer, and completely covers the back side of the second wafer 21 and the metal wiring layer 26. After forming the solder resist layer 27, a planarization process is also included. The planarization process enables the optoelectronic packaging structure to maintain a suitable thickness, further reducing the volume of the packaging structure and improving the packaging quality.

[0145] Specifically, in this embodiment, the process of forming the solder resist layer 27 is as follows: after screen printing solder resist ink on the surface of the image sensor chip 22, it undergoes pre-curing, exposure, development, and thermal curing processes in sequence to cure the solder resist ink into the solder resist layer 27. Further, a windowing process is performed on the solder resist layer 27 to expose the pad areas 222 on the image sensor chip 22. The solder resist layer 27 provides a permanent electrical environment and a protective layer against chemical corrosion for the image sensor chip 22, while also enhancing its appearance.

[0146] In step S15, referring to Figures 9 and 15, the solder resist layer 27 is photolithographically formed to form a solder resist opening 252, which exposes the metal wiring layer 26 covering the back side of the second wafer 21.

[0147] In this embodiment, as shown in FIG15, the solder resist layer 27 is photolithographically formed to create a solder resist window 252. Specifically, a photoresist mask layer is formed on the solder resist layer 27, and the photoresist mask layer is exposed and developed to form a patterned photoresist mask layer. Based on the patterned photoresist mask layer, the solder resist layer 27 is etched to form the solder resist window 252 in the solder resist layer 27, which exposes the metal wiring layer 26 on the back side of the second wafer 21. The photoresist mask layer is then removed. The process conditions used for photolithographically forming the solder resist layer 27 are well known in the art, and those skilled in the art can adjust them according to actual needs, which will not be described in further detail here.

[0148] In step S16, referring to Figures 1, 16, and 17, a substrate 28 is provided, the optical chip 20 is bonded to the substrate 28, and the image sensor chip 22 is bonded to the optical chip 20. A first curing adhesive 291 is filled between the optical chip 20 and the substrate 28, and a second curing adhesive 292 is filled between the image sensor chip 22 and the optical chip 20, thereby achieving the connection and fixation of the image sensor chip 22, the optical chip 20, and the substrate 28.

[0149] As an example, before bonding the image sensor chip 22 to the optical chip 20, the process further includes cutting the wafer according to the preset dicing grooves on the second wafer 21, cutting the second wafer 21 into individual image sensor chips 22, and performing a debonding process on the image sensor chips 22 to remove the temporary carrier 23 and the release layer 24.

[0150] Specifically, the second wafer 21 contains a plurality of image sensor chips 22. The second wafer 21 is diced along a pre-defined dicing groove area to separate the plurality of image sensor chips 22, thereby forming a plurality of individual image sensor chips 22. This achieves both the individual separation of the image sensor chips 22 and ensures the integrity and reliability of the circuit functions of the image sensor chips 22.

[0151] Optionally, the temporary substrate 23 and the release layer 24 can be removed by UV irradiation or chemical immersion. Preferably, in this embodiment, UV irradiation is used to make the release layer 24 lose its adhesiveness, thereby removing the temporary substrate 23 and cleaning off the release layer 24. As shown in FIG16, which is a top view of the image sensor chip 22, the surface of the image sensor chip 22 has an image area 221 and a pad area 222. The image area 221 is located at the center of the image sensor chip 22, and the pad area 222 is distributed circumferentially along the edge of the image sensor chip 22. After encapsulation, the image area 221 is positioned opposite the grating coupling area 202 so that the image sensor chip 22 can receive image light received from the grating coupling area 201 and transmitted to the grating coupling area 202.

[0152] As an example, the substrate 28 may include a metal substrate 28, a glass substrate 28, a semiconductor substrate 28, a polymer substrate 28, or a ceramic substrate 28 that is thermally compatible with the optical chip 20. The present invention does not particularly limit its material, properties, or internal structure. Preferably, as shown in FIG17, in this embodiment, the substrate 28 is selected as a ceramic substrate 28 that is thermally compatible with the optical chip 20. Before the optical chip 20 is bonded to the substrate 28, a receiving space 281 needs to be formed at the corresponding contact position of the substrate 28. The height of this receiving space 281 is greater than the sum of the heights of the optical chip 20 and the image sensor chip 22. This receiving space 281 can protect the packaging structure, prevent the packaging structure from being affected by the external environment during use, prevent damage to the packaging structure, and improve the service life of the packaging structure.

[0153] Specifically, before bonding the optical chip 20 to the substrate 28, the method further includes forming a groove in the substrate 28 to accommodate the optical chip 20 and the image sensor chip 22 through the groove. The method of forming the groove includes a laser drilling process. The laser grooving process has good precision and high controllability, and can accurately form the groove without affecting other structures.

[0154] As shown in Figure 17, during the bonding process between the optical chip 20 and the substrate 28, a first gap is formed between the optical chip 20 and the substrate 28. In order to improve the strength of the packaging structure, the first gap needs to be filled with a first curing adhesive 291, and the first curing adhesive 291 is subjected to high-temperature curing heating. The technical principle of high-temperature curing heating is to use high-temperature hot air to heat the first curing adhesive 291, so that the first curing adhesive 291 in the first gap fuses under the action of high-temperature hot air, thereby forming a larger contact area to achieve the connection and fixation between the optical chip 20 and the substrate 28.

[0155] As shown in Figure 18, during the bonding process between the image sensor chip 22 and the optical chip 20, a second gap is formed between them. To improve the strength of the encapsulation structure, a second curing adhesive 292 needs to be filled into the second gap, and the second curing adhesive 292 is cured at high temperature. This allows the second curing adhesive 292 in the second gap to fuse under the action of high-temperature hot air, thereby forming a larger contact area to achieve the connection and fixation between the image sensor chip 22 and the optical chip 20. Preferably, the second curing adhesive 292 is a non-conductive epoxy resin adhesive with high light transmittance, thereby further improving the effect of the grating coupling region 202 in coupling the image light transmitted in the optical chip 20 to the image sensor chip 22.

[0156] As an example, a first lead 30 that is insensitive to thermal mismatch of materials is provided between the substrate 28 and the metal wiring layer 26 in the solder mask opening 252, so as to realize the electrical connection between the image sensor chip 22 and the substrate 28 by soldering.

[0157] Specifically, as shown in Figure 18, in order to lead the electrical signals of the image sensor chip 22 to external devices, a first lead 30 needs to be provided between the substrate 28 and the metal wiring layer 26 in the solder mask opening 252. The first lead 30 is made of a material that is not sensitive to thermal mismatch. Then, one end of the first lead 30 is soldered to the metal wiring layer 26 in the solder mask opening 252, and the other end of the first lead 30 is soldered to the substrate 28, thereby realizing the electrical connection between the image sensor chip 22 and the substrate 28. On the one hand, the wire bonding technology is mature and can save packaging costs; on the other hand, it can also avoid packaging problems caused by thermal mismatch of materials in the packaging structure.

[0158] In step S17, referring to Figures 9 and 19, a cover plate 31 is provided, which covers the substrate 28 to complete the encapsulation of the optical chip 20 and the image sensor chip 22.

[0159] Specifically, as shown in Figure 19, a light window 311 is provided on the cover plate 31, and the light window 311 is positioned directly opposite the grating coupling region 201, so that light is coupled into the grating coupling region 201 of the optical chip 20 through the light window 311. After the optical chip 20, the image sensor chip 22 and the substrate 28 are bonded together, the cover plate 31 is fixed on the substrate 28, thereby completing the optoelectronic system packaging of the optical chip 20 and the image sensor chip 22.

[0160] In the fabrication method of the optoelectronic packaging structure of this embodiment, a first through-hole 251 is formed on the back side of the image sensor chip 22, and a metal wiring layer 26 and a solder resist layer 27 are formed on the first through-hole 251 and the back side of the image sensor chip 22. This allows the electrical signal of the image sensor chip 22 to be led from the front side to the back side. This ensures that the distance between the image sensor chip 22 and the grating coupling surface of the optical chip 20 can be controlled to within 10 μm. This enables close-range reception of the optical signal of the optical chip 20, while the electrical signal of the image sensor chip 22 can also be led to the substrate 28 through the metal wiring layer 26 on the back side of the image sensor chip 22 through the formed solder resist window 252. This effectively reduces the signal transmission difficulty between the optical chip 20, the image sensor chip 22, and other devices.

[0161] Example 4

[0162] This embodiment provides a photoelectric packaging structure, as shown in Figure 19, which is a cross-sectional view of the photoelectric packaging structure. The photoelectric packaging structure includes: a substrate 28, located at the bottom layer of the photoelectric packaging structure, used to provide mechanical strength support; a cover plate 31, on which a light window 311 is provided, the cover plate 31 being connected to the substrate 28 and forming an accommodating space with the groove of the substrate 28; a photoelectric chip 20, located within the accommodating space and filled with a first curing adhesive 291 between the photoelectric chip 20 and the substrate 28, the surface of the photoelectric chip 20 having a grating coupling-in region 201 and a grating coupling-out region 202; and an image sensor chip 22, located above the photoelectric chip 20 and filled with a second curing adhesive 292 between the image sensor chip 22 and the photoelectric chip 20, the image sensor chip 22 having a centrally located... The image sensor chip 22 comprises an image region 221 and a pad region 222 distributed circumferentially along the edge of the image sensor chip 22. A first via 251 is formed in the image sensor chip 22 to expose the pad region 222. A metal wiring layer 26 is located within the first via 251 and on the back side of the image sensor chip 22 to electrically lead the pad region 222 to the back side of the image sensor chip 22. A solder resist layer 27 is located on the back side of the image sensor chip 22. The solder resist layer 27 has a solder resist opening 252 to expose the metal wiring layer 26, and a first lead 30 is provided in the solder resist opening 252. The two ends of the first lead 30 are electrically connected to the metal wiring layer 26 exposed by the solder resist opening 252 and the substrate 28, respectively.

[0163] Preferably, the light window 311 is positioned opposite the grating coupling region 201 of the optical chip 20, and the image sensor chip 22 is positioned opposite the grating coupling region 202 of the optical chip 20, so that the image sensor chip 22 can receive image light rays received from the grating coupling region 201 and transmitted to the grating coupling region 202.

[0164] As an example, in order to bring the electrical signals of the image sensor chip 22 to an external device, a first lead 30 is provided between the substrate 28 and the metal wiring layer 26 in the solder mask opening 252. The first lead 30 is made of a material that is not sensitive to thermal mismatch. Then, one end of the first lead 30 is soldered to the metal wiring layer 26 in the solder mask opening 252 and the other end of the first lead 30 is soldered to the substrate 28 to achieve electrical connection between the image sensor chip 22 and the substrate 28 and avoid thermal mismatch problems in the packaging structure.

[0165] In summary, compared with the prior art, the optoelectronic packaging structure and its fabrication method of the present invention, during the packaging process, use a fan-out process to complete the micro solder bump connection at the pad area of ​​the optical chip and the image sensor, thereby achieving large-scale, high-density optoelectronic co-packaging of the optical chip and the image sensor. The distance between the image area of ​​the image sensor and the grating coupling area of ​​the optical chip is controlled to be within 30 μm. This ensures that the image sensor and the optical chip can receive the optical signal from the optical chip in close contact, while also ensuring that the electrical signal of the image sensor is led out to the substrate through the second lead. This effectively reduces the signal transmission difficulty between the optical chip, the image sensor, and other devices. Furthermore, by using the back of the image sensor chip... A first through-hole is formed on the front side, and a metal wiring layer and a solder mask layer are formed on the back side of the first through-hole and the image sensor chip. This allows the electrical signals of the image sensor chip to be led from the front side to the back side, ensuring that the distance between the image sensor chip and the grating coupling surface of the optical chip can be controlled within 10μm. This achieves close-range reception of the optical signal from the optical chip, while the electrical signals of the image sensor chip can also be led to the substrate through the metal wiring layer on the back side of the image sensor chip via the formed solder mask opening. This effectively reduces the signal transmission difficulty between the optical chip, the image sensor chip, and other devices. In addition, this optoelectronic packaging structure is relatively simple and has low manufacturing cost, thereby improving the yield and service life of the finished optoelectronic packaging structure. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0166] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an optoelectronic packaging structure, characterized in that, The preparation method includes the following steps: An optical chip is provided, the surface of which has a grating coupling-in region and a grating coupling-out region; A first electrical pin and a second electrical pin are formed on the surface of the optical chip, and the first electrical pin and the second electrical pin are connected by a first lead. A solder resist layer is formed on the surface of the optical chip, the solder resist layer exposing the grating coupling region, the grating coupling out region, the first electrical pin and the second electrical pin; An image sensor is provided, the image sensor having an image region located at a central position and a pad region distributed circumferentially along the image region, the pad region being electrically connected to the optical chip; A substrate is provided, and a first gap is formed between the optical chip and the substrate. The first gap is filled with curing adhesive, and the curing adhesive is cured at high temperature to achieve the connection and fixation between the optical chip and the substrate. A cover plate is provided, the cover plate having a light window facing the grating coupling area, and the cover plate is fixed to the substrate to complete the encapsulation of the optical chip and the image sensor.

2. The method for preparing the optoelectronic packaging structure according to claim 1, characterized in that: A micro solder bump is formed between the pad area of ​​the image sensor and the first electrical pin to achieve electrical connection between the optical chip and the image sensor. The micro solder bump formation process includes one of laser ball-mounting technology, ultrasonic solder ball-mounting technology, solder paste printing ball-mounting technology, electroplating bump technology, or vapor deposition bump technology.

3. The method for preparing the optoelectronic packaging structure according to claim 2, characterized in that: The shape of the micro solder bumps can be one of sphere, cylinder, cone, frustum, or cuboid.

4. The method for preparing the optoelectronic packaging structure according to claim 1, characterized in that: The first electrical pin is distributed circumferentially along the edge of the grating coupling region, and the second electrical pin is distributed circumferentially along the edge of the optical chip.

5. The method for preparing the optoelectronic packaging structure according to claim 1, characterized in that: A second lead that is insensitive to thermal mismatch of materials is provided between the substrate and the second electrical pin, so as to achieve electrical connection between the optical chip and the substrate by welding.

6. The method for preparing the optoelectronic packaging structure according to claim 1, characterized in that: The substrate includes one of a glass substrate, a semiconductor substrate, a polymer substrate, or a ceramic substrate that is thermally adapted to the optical chip.

7. A photoelectric packaging structure, characterized in that, The optoelectronic packaging structure includes: The substrate, located at the bottom of the co-package structure, is used to provide mechanical strength support; A cover plate, wherein the cover plate is provided with a light window, and the cover plate is connected to the substrate and together with the substrate form an accommodating space; An optical chip is located within the accommodating space and forms a first gap with the substrate. The surface of the optical chip has a grating coupling-in region and a grating coupling-out region, and the grating coupling-in region is positioned directly opposite the optical window. A curing adhesive is used to fill the first gap so as to fix the optical chip to the substrate. A solder resist layer is located on the optical chip, and the solder resist layer exposes the grating coupling-in region and the grating coupling-out region; An image sensor is located above and electrically connected to the optical chip. The image sensor has an image area located at the center and a pad area distributed circumferentially along the image area. The image area is positioned opposite the grating coupling area.

8. The optoelectronic packaging structure according to claim 7, characterized in that: The optical chip is further provided with a first electrical pin and a second electrical pin on its surface. The first electrical pin is distributed circumferentially along the edge of the grating coupling region, and the second electrical pin is distributed circumferentially along the edge of the optical chip. The first electrical pin and the second electrical pin are connected by a first lead.

9. The optoelectronic packaging structure according to claim 8, characterized in that: The solder mask layer also exposes the first electrical pin and the second electrical pin, and a micro solder bump is provided between the first electrical pin and the pad area of ​​the image sensor to realize the electrical connection between the optical chip and the image sensor. A second lead is provided between the second electrical pin and the substrate to realize the electrical connection between the optical chip and the substrate.

10. The optoelectronic packaging structure according to claim 9, characterized in that: The micro solder bumps include one of gold balls, copper balls, tin balls, or tin-silver-copper alloy solder balls, and the diameter of the micro solder bumps ranges from 18 to 30 μm.

11. The optoelectronic packaging structure according to claim 9, characterized in that: The micro solder bumps include one of gold pillars, copper pillars, indium pillars, tin pillars, or tin-silver-copper alloy pillars, and the height of the micro solder bumps is less than 30 μm.

12. A method for fabricating an optoelectronic packaging structure, characterized in that, The preparation method includes the following steps: An optical chip is provided, the surface of which has a grating coupling-in region and a grating coupling-out region; A temporary carrier and a second wafer are provided. The second wafer includes a plurality of image sensor chips, each of which has an image area and a pad area. The second wafer and the temporary carrier are bonded together by a release layer. A first etching process is performed to etch the second wafer to form a first via, the first via exposing a portion of the pad area; A metal wiring layer and a solder mask layer are sequentially formed in the first through-hole. One end of the metal wiring layer is connected to the pad area, and the other end of the metal wiring layer covers the back side of the second wafer. The solder mask layer completely covers the second wafer and the metal wiring layer. Photolithography is used to form solder resist openings in the solder resist layer, which expose the metal wiring layer covering the back side of the second wafer. A substrate is provided, the optical chip is bonded to the substrate, and the image sensor chip is bonded to the optical chip. A first curing adhesive is filled between the optical chip and the substrate, and a second curing adhesive is filled between the image sensor chip and the optical chip, thereby realizing the connection and fixation of the image sensor chip, the optical chip and the substrate. A cover plate is provided, the cover plate having a light window, the cover plate covering the substrate to complete the packaging of the optical chip and the image sensor chip.

13. The method for preparing the optoelectronic packaging structure according to claim 12, characterized in that: The light window is positioned directly opposite the grating coupling area of ​​the optical chip, and the image sensor chip is positioned directly opposite the grating coupling area of ​​the optical chip.

14. The method for preparing the optoelectronic packaging structure according to claim 13, characterized in that: The second cured adhesive is a non-conductive epoxy resin adhesive with high light transmittance.

15. The method for preparing the optoelectronic packaging structure according to claim 12, characterized in that: The image region is located at the center of the image sensor chip, and the pad region is distributed circumferentially along the edge of the image sensor chip.

16. The method for preparing the optoelectronic packaging structure according to claim 12, characterized in that: Before bonding the optical chip to the substrate, the method further includes forming a groove in the substrate to accommodate the optical chip and the image sensor chip through the groove, wherein the method of forming the groove includes a laser drilling process.

17. The method for preparing the optoelectronic packaging structure according to claim 12, characterized in that: It also includes the steps of cutting the wafer according to the preset dicing grooves on the second wafer, cutting the second wafer into individual image sensor chips, and performing a debonding process on the image sensor chips to remove the temporary carrier and release layer.

18. The method for preparing the optoelectronic packaging structure according to claim 12, characterized in that: A first lead, which is insensitive to thermal mismatch of materials, is provided between the substrate and the metal wiring layer exposed by the solder mask opening, so as to realize the electrical connection between the image sensor chip and the substrate by soldering.

19. The method for preparing the optoelectronic packaging structure according to claim 12, characterized in that: The substrate includes one of a metal substrate, a glass substrate, a semiconductor substrate, a polymer substrate, or a ceramic substrate that is thermally adapted to the optical chip.

20. A photoelectric packaging structure, characterized in that, The optoelectronic packaging structure includes: The substrate, located at the bottom layer of the optoelectronic packaging structure, is used to provide mechanical strength support; A cover plate, wherein the cover plate is provided with a light window, the cover plate is connected to the substrate and together with the groove of the substrate to form an accommodating space; An optical chip is located within the accommodating space and is filled with a first curing adhesive between itself and the substrate. The surface of the optical chip has a grating coupling-in region and a grating coupling-out region. An image sensor chip is located above an optical chip and a second curing adhesive is filled between the two chips. The image sensor chip has an image area located at the center and a pad area distributed circumferentially along the edge of the image sensor chip. A first through-hole is formed in the image sensor chip to expose the pad area. A metal wiring layer is located within the first via and on the back side of the image sensor chip to electrically lead the pad area to the back side of the image sensor chip. A solder resist layer is located on the back side of the image sensor chip. The solder resist layer has a solder resist window to expose the metal wiring layer, and a first lead is disposed in the solder resist window. The two ends of the first lead are electrically connected to the metal wiring layer exposed by the solder resist window and the substrate, respectively.

21. The optoelectronic packaging structure according to claim 20, characterized in that: The light window is positioned directly opposite the grating coupling area of ​​the optical chip, and the image sensor chip is positioned directly opposite the grating coupling area of ​​the optical chip.

Images