Method of synchronizing an internal clock signal of a target device
The method synchronizes the internal clock of a target device with an external clock using a feedback loop, addressing inefficiencies in continuous reference signal reliance and enhancing data transmission accuracy.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- NEXPERIA BV
- Filing Date
- 2025-12-12
- Publication Date
- 2026-06-18
AI Technical Summary
Existing clock synchronization methods in communication networks require continuous reference signals, which is inefficient and may lead to synchronization errors due to signal gaps.
A method for synchronizing an internal clock signal of a target device using a closed feedback loop, where the target device receives an external clock signal, measures its frequency, calculates a relative frequency value, and adjusts its internal clock using a tuning word to align with the external clock, utilizing a tunable oscillator or fractional frequency divider.
Achieves accurate clock synchronization without continuous reference signals, ensuring precise data transmission by aligning the internal clock with the external clock, reducing synchronization errors.
Smart Images
Figure EP2025086945_18062026_PF_FP_ABST
Abstract
Description
[0001] TITLE Method of synchronizing an internal clock signal of a target device
[0002] TECHNICAL FIELD
[0003] The present disclosure relates to a method of synchronizing an internal clock signal of a target (slave) device, more precise to a method of generating an accurate internal clock signal based on an intermittent received external communication protocol signal.
[0004] BACKGROUND OF THE DISCLOSURE
[0005] Document US8762762B2 discloses a method and apparatus for controlling the phase and frequency of the local clock of a USB device, the apparatus comprising circuitry for observing USB traffic and decoding from the USB traffic a periodic data structure containing information about the frequency and phase of a distributed clock frequency, and phase and circuitry for receiving the periodic data structure and generating from at least the periodic data structure a local clock signal locked in both frequency and phase to the periodic data structure. The circuitry for receiving the periodic data structure and generating the local clock signal can generate the local clock signal with a frequency that is a non-integral multiple of a frequency of the periodic data structure.
[0006] Document US8923141 B2 discloses an apparatus for providing clock synchronization in a packet-based network, the network having as components nodes and links therebetween and having a network topology, is arranged to compute a forward clock synchronization packet path to a synchronization destination from the network topology according to a computation rule such that the return path for a clock synchronization packet from the synchronization destination is the same as the forward path.
[0007] Accordingly, it is a goal of the present disclosure to provide an improved solution of providing clock synchronization in the communication network without continuously present reference signal distributed in the network.
[0008] SUMMARY OF THE DISCLOSURE
[0009] According to a first example of the disclosure, a method of synchronizing an internal clock signal of a target device is disclosed. The target device (slave) comprises an internal clock signal source (typically an analog oscillator). The internal clock signal of a target device is synchronized with an external clock signal provided by a controller device (master) comprises an external clock signal source in a serial bus network. The serial bus network comprises the controller device communicatively connected with the least one target device. The method according to this example of the disclosure comprises the following steps: a. receiving the external clock signal by the target device provided by the controller device; b. generating a clock gating signal based on the external clock signal and measuring the internal clock signal frequency by counting the internal clock signal pulses received during duration of the clock gating signal. c. calculating a relative frequency value of the external clock signal to the internal clock signal. The relative frequency measurement is over a certain amount of clock pulses from the external communication signal. Certain means here, that the count of clock cycles must be high enough to guarantee a good accuracy of the relative frequency measurement. d. calculating a tuning word value using the relative frequency value and changing the internal clock value using the tuning word as a feedback value for a closed feedback loop synchronization or incrementally change the internal clock.
[0010] In another example of the disclosure the internal clock signal in the target device is generated by a tunable analog oscillator unit and the tunning word is a value of voltage and / or current used for modifying the analog oscillator resonate frequency. The tunable analog oscillator unit is an RC or LC oscillator.
[0011] In another example of the disclosure the internal clock signal in the target device is generated by a fractional frequency divider comprising a fixed untenable uncompensated oscillator unit and the tunning word is a divider value used for dividing the oscillator frequency to calculate the internal clock signal. The tunable analog oscillator unit is an RC or LC oscillator.
[0012] In another example of the disclosure in the step c. calculating a tuning word value further comprises a step of comparing the relative frequency value with a previously stored target frequency value.
[0013] BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The disclosure will now be discussed with reference to the drawings, which show in:
[0015] Figure 1 Schematic of the incrementally change the internal clock value using the tuning word as a feedback value for a closed feedback loop synchronization.
[0016] Figure 2 Schematic of the incrementally change the internal clock value using the tuning word as a feedback value for a closed feedback loop synchronization with digital comparator.
[0017] Figure 3 Schematic of the immediate change the internal clock value using the tuning word as a feedback value for a closed feedback loop synchronization with frequency divider.
[0018] DETAILED DESCRIPTION OF THE DISCLOSURE
[0019] For a proper understanding of the disclosure, in the detailed description below corresponding elements or parts of the disclosure will be denoted with identical reference numerals in the drawings.
[0020] According to a first example of the disclosure, a method of synchronizing an internal clock signal 6 of a target device is disclosed (Fig.1). The target device 2 (also referred as slave) comprises an inaccurate internal clock signal 6 source (typically an RC oscillator or similar simple non accurate clock signal source). The internal clock signal 6 of a target device is synchronized (must be synchronized for data transmission purposes) with an external clock signal 1 (accurate signal) provided by a controller device (also referred as master) comprising an external clock signal 1 source (precise clock source e.g. XTAL oscillator) in a serial bus network. The serial bus network (I2C, I3C, SPI, UART, eSPI, SDIO) comprises the controller device communicatively connected with the least one target device 2.
[0021] The method according to this example of the disclosure comprises following steps: a. receiving the external clock signal 1 by the target device 2 provided by the controller device. The controller device comprises a precise clock signal generating unit (element, device) according to which all data communication is executed. b. generating a clock gating signal based on the external clock signal 1 and measuring the internal clock signal 6 frequency (performed by the frequency measurement unit 4) by counting the internal clock signal 6 pulses received during duration of the clock gating signal. This is done by counting the internal clock cycles using e.g., a counter (digital counter or shift register). Whenever a rising or falling edge of a clock pulse of the internal clock generator is seen, this counter increments its binary output value by one. The counter is reset (set on zero) on a certain event e.g., whenever a communication method starts. Once an amount of n clock edges of the external communication signal is reached, the counter value is latched, e.g., using D-Flipflops and the result further processed. The actual value n is defined by the IC architect / designer to meet accuracy requirements. c. calculating a relative frequency value of the external clock signal 1 to the internal clock signal 6. The count of clock cycles must be high enough to guarantee a good accuracy of the relative frequency measurement. Furthermore, the external clock signal 1 has to be without gaps during this certain number of cycles. The longer the count clock cycles, the higher the accuracy is. The designer of an IC with this method can estimate how many consecutive clock cycles are required and define based on this a bus transfer sequence which is used as a clock gating signal for the measurement. d. calculating a tuning word value using the relative frequency value and changing the internal clock value 6 using the tuning word 5 as a feedback value for a closed feedback loop synchronization or incrementally change the internal clock.
[0022] In another example of the disclosure the internal clock signal 6 in the target device 2 is generated by a tunable analog oscillator unit and the tunning word 5 is a value of voltage and / or current used for modifying the analog oscillator resonate frequency. The tunable analog oscillator unit is an RC oscillator (Figure 2).
[0023] In another example of the disclosure the internal clock signal 6 in the target device 2 is generated by a fractional frequency divider comprising a fixed untenable uncompensated oscillator unit and the tunning word 5 is a divider value used for dividing the oscillator frequency to calculate the internal clock signal 6 (Figure 3). The tunable analog oscillator unit is an RC oscillator.
[0024] In another example of the disclosure in the step d. calculating a tuning word value further comprises (before changing the internal clock value) a step of comparing the relative frequency value with a previously stored target frequency value.
[0025] LIST OF REFERENCE NUMERALS USED
[0026] 1. External clock signal
[0027] 2. Target device
[0028] 3. Relative frequency
[0029] 4. Frequency measurement unit
[0030] 5. Tunning word
[0031] 6. Internal clock signal
Claims
CLAIMS1. A method of synchronizing an internal clock signal of a target device comprising an internal clock signal source, with an external clock signal provided by a controller device comprising an external clock signal source in a serial bus network comprising the controller device communicatively connected with the least one target device, comprising steps: a. receiving by the target device the external clock signal provided by the controller device; b. generating a clock gating signal based on the external clock signal and measuring the internal clock signal frequency by counting the internal clock signal pulses received during duration of the clock gating signal; c. calculating a relative frequency value of the external clock signal to the internal clock signal; d. calculating a tuning word value using the relative frequency value and changing the internal clock value using the tuning word as a feedback value for a closed feedback loop synchronization or incrementally change the internal clock value.
2. The method according to claim 1, wherein the internal clock signal in the target device is generated by a tunable analog oscillator unit and the tunning word is a value of voltage and / or current used for modifying the analog oscillator resonate frequency.
3. The method according to claim 2, wherein the tunable analog oscillator unit is an RC or LC oscillator.
4. The method according to claim 1, wherein the internal clock signal in the target device is generated by a fractional frequency divider comprising a fixed untenable uncompensated oscillator unit and the tunning word is a divider value used for dividing the oscillator frequency to calculate the internal clock signal.
5. The method according to claim 4, wherein the tunable analog oscillator unit is an RC or LC oscillator.
6. The method according to any of proceeding claim 1, 2, 3, 4 or 5 wherein in the step d. of calculating a tuning word value comprises a step of comparing the relative frequency value with a previously stored target frequency value.