Semiconductor device

Abstract

The present invention reduces warpage deformation of a semiconductor device.　A case (11) of a semiconductor device (1) has, on two opposing short sides, recesses that seal bent portions and undersides of a plurality of external terminals (12a-12d) and expose internal connection portions of the plurality of external terminals (12a-12d) while penetrating side surfaces of long sides. In addition, the case (11) exposes the external terminals (12a-12d) on the upper surface thereof, and has, on the upper surface, grooves (11a1, 11a2) extending in parallel to the two short sides above conductive pattern layers adjacent to the outer periphery of an insulating circuit board among a plurality of conductive pattern layers, in a plan view, and inside external connection portions of the external terminals (12a-12d).

Description

Semiconductor device 【0001】 The present invention relates to a semiconductor device. 【0002】 In a semiconductor device having a plurality of terminals exposed on the upper surface of the case, it has been proposed to provide a groove on the upper surface of the case to ensure an insulating distance between the terminals (see, for example, Patent Document 1). Further, a semiconductor device in which a groove is provided on the surface of the encapsulating resin to subdivide the warpage generation and relieve the warpage (see, for example, Patent Document 2), and a semiconductor device in which a recess is provided on the resin surface above the semiconductor chip to prevent the resin end from being lifted have been proposed (see, for example, Patent Document 3). Further, a semiconductor module having a concave shape provided in a part of the module member (see, for example, Patent Document 4), and a power module structure in which a concave groove (stress relief portion) is provided in the terminal have been proposed (see, for example, Patent Document 5). 【0003】 International Publication No. 2016 / 047455 Japanese Patent Application Laid-Open No. 2007-281380 Japanese Patent Application Laid-Open No. 2000-174170 International Publication No. 2017 / 094189 Japanese Patent Application Laid-Open No. 2007-165600 【0004】 An object of the present embodiment is to reduce the warpage deformation of the semiconductor device. 【0005】According to one aspect of the present invention, an insulating circuit board having a heat sink, an insulating layer disposed on the upper surface of the heat sink, and a plurality of conductive pattern layers disposed on the upper surface of the insulating layer, a semiconductor chip connected to some of the conductive pattern layers among the plurality of conductive pattern layers, an internal connection portion conductively connected to the semiconductor chip, a plurality of external terminals having a bent portion continuous from the internal connection portion and an external connection portion continuous from the bent portion, and a substantially rectangular shape in plan view, with the bent portion and the lower side of the plurality of external terminals sealed on two opposing short sides. A semiconductor device is provided, comprising: a case having a recess that penetrates the side of the long side and exposes the internal connection portion of the plurality of external terminals, the plurality of external terminals exposed on the upper surface, and a groove on the upper surface that is inside the external connection portion of the plurality of external terminals and, in a plan view, above the conductive pattern layer among the plurality of conductive pattern layers adjacent to the outer circumference of the insulating circuit board, which extends parallel to the two short sides; and a sealing resin that integrally seals the semiconductor chip, the recess of the case, and the internal connection portion of the plurality of external terminals. 【0006】 The grooves may be provided one on each of the two short sides of the case in a plan view. 【0007】 The groove may be provided in a plan view at a distance of 8 mm or less in the inward direction of the insulating circuit board from the short side of the insulating circuit board that is parallel to the two short sides of the case. 【0008】 The width of the groove may be 1 mm or more and 3 mm or less. 【0009】 The depth of the groove may be 0.1 mm or more and 0.5 mm or less. 【0010】 The groove may have a tapered shape, with its width narrowing in the depth direction. 【0011】The aforementioned plurality of external terminals include a positive terminal, a negative terminal, an intermediate terminal, and an output terminal. The positive terminal, the negative terminal, and the intermediate terminal may be held on one of the two short sides of the case, and the output terminal may be held on the other side. It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. 【0012】 In one aspect, warping deformation of semiconductor devices can be reduced. The above and other objects, features and advantages of the present invention will become apparent from the following description in conjunction with the accompanying drawings illustrating preferred embodiments as examples of the present invention. 【0013】 This is a top view showing an example of a semiconductor device according to an embodiment. This is a cross-sectional view along line II-II in Figure 1. This is a cross-sectional view along line III-III in Figure 1. This is a cross-sectional view along line IV-IV in Figure 1. This is a side view of a semiconductor device according to an embodiment. This is a top view showing an example of an insulating circuit board. This is a cross-sectional view showing an enlarged view of the negative terminal. This is a cross-sectional view showing an enlarged view of the positive terminal. This is a cross-sectional view showing an enlarged view of the intermediate terminal. This is a cross-sectional view showing an enlarged view of the output terminal. This is a diagram showing the circuit configuration of an example of a three-level inverter. This is a diagram explaining the warping that occurs in a semiconductor device. This is the result of a simulation analysis of the difference in the magnitude of overall warping due to the presence or absence of grooves. This is the result of a simulation analysis of the difference in the magnitude of overall warping due to the presence or absence of grooves and the difference in the position of grooves. This is the result of a simulation analysis of the difference in the magnitude of warping in the second warping region (bonding part) due to the presence or absence of grooves and the difference in the position of grooves. This is a diagram showing a modified example of a groove. 【0014】The embodiments for carrying out the invention will be described below with reference to the drawings. In the following description, "front surface" and "top surface" refer to the X-Y plane facing upwards (+Z direction) in the semiconductor device 1 shown in Figures 1 to 5. Similarly, "up" refers to the direction upwards (+Z direction) in the semiconductor device 1 shown in Figures 1 to 5. "Back surface" and "bottom surface" refer to the X-Y plane facing downwards (-Z direction) in the semiconductor device 1 shown in Figures 1 to 5. Similarly, "down" refers to the direction downwards (-Z direction) in the semiconductor device 1 shown in Figures 1 to 5. The same directionality will be used in other drawings as needed. "Front surface," "top surface," "up," "back surface," "bottom surface," and "down" are merely convenient expressions to specify relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions "up" and "down" are not limited to the direction of gravity. 【0015】 Figure 1 is a top view showing an example of a semiconductor device according to an embodiment. Figure 2 is a cross-sectional view taken along line II-II in Figure 1. Figure 2 shows not only the configuration of the cross-section along line II-II, but also components visible in the +Y direction from line II-II in Figure 1. Figure 3 is a cross-sectional view taken along line III-III in Figure 1. Figure 3 shows not only the configuration of the cross-section along line III-III, but also components visible in the +Y direction from line III-III in Figure 1. Figure 4 is a cross-sectional view taken along line IV-IV in Figure 1. Figure 4 shows not only the configuration of the cross-section along line IV-IV, but also components visible in the +Y direction from line IV-IV in Figure 1. Furthermore, Figure 5 is a side view of a semiconductor device according to an embodiment. Figure 6 is a top view showing an example of an insulating circuit board. 【0016】 The semiconductor device 1 according to this embodiment is sometimes called a three-level inverter. The semiconductor device 1 also has a modular configuration of a half-bridge circuit including, for example, an upper arm and a lower arm. 【0017】The semiconductor device 1 includes a case 11, external terminals 12a to 12d, terminals 13a to 13l, positioning pins 14a and 14b, an insulating circuit board 20, a semiconductor chip 21, conductive pins 22, a printed circuit board 23, and a sealing resin 24. 【0018】 (Regarding the insulating circuit board 20) First, the insulating circuit board 20 will be described. As shown in Figure 6, the insulating circuit board 20 is rectangular in plan view. The insulating circuit board 20 has a heat sink 20a, an insulating layer 20b placed on the upper surface of the heat sink 20a, and a plurality of conductive pattern layers 20c1 to 20c6 placed on the upper surface of the insulating layer 20b. 【0019】 The heat sink 20a has a rectangular shape when viewed from above. The corners of the heat sink 20a may also be rounded (R-chamfered) or chamfered (C-chamfered). The heat sink 20a is mainly composed of a metal with excellent thermal conductivity. The metal may be, for example, copper, aluminum, or an alloy containing at least one of these. 【0020】 The insulating layer 20b has a rectangular shape in plan view. The corners of the insulating layer 20b may be rounded (R-chamfered) or chamfered (C-chamfered). The insulating layer 20b is made of, for example, an insulating resin. The insulating resin may be a material with low thermal resistance and high insulating properties. Examples of such resins include, among thermosetting resins, at least one of epoxy resin, cyanate resin, polyimide resin, benzoxazine resin, unsaturated polyester resin, phenolic resin, melamine resin, silicone resin, and maleimide resin. Examples of thermoplastic resins include at least one of acrylic resin and polyamide resin. These resins may also contain a filler. The filler is made of at least one of oxides and nitrides. Examples of oxides include silicon oxide and aluminum oxide. Examples of nitrides include silicon nitride, aluminum nitride, and boron nitride. Furthermore, hexagonal boron nitride may also be used as the filler. 【0021】The insulating layer 20b may be an insulating board mainly composed of ceramics. Such ceramics are made of materials mainly composed of, for example, aluminum oxide, aluminum nitride, or silicon nitride. In this case, such an insulating circuit board 20 can be, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate. 【0022】 The conductive pattern layers 20c1 to 20c6 are composed of a metal with excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy containing at least one of these. 【0023】 (Regarding the semiconductor chip 21) The semiconductor chip 21 is mounted on the main surface of the insulating circuit board 20, as shown in Figure 2. The main surface of the insulating circuit board 20 is the front surface (top surface) of the conductive pattern layers 20c1 to 20c6. If the semiconductor device 1 is a 4-in-1 type semiconductor device, four semiconductor chips are mounted on the conductive pattern layers 20c2 and 20c6, and eight semiconductor chips are mounted on the conductive pattern layer 20c3. Each semiconductor chip, including the semiconductor chip 21, is joined to the front surface of one of the conductive pattern layers 20c2, 20c3, or 20c6 by solder. 【0024】 Each semiconductor chip includes a switching element made of silicon, silicon carbide, or gallium nitride. The switching element is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Furthermore, each semiconductor chip may be an RC (Reverse-Conducting) IGBT. An RC-IBGT combines the functions of both an IGBT and a FWD (Free Wheeling Diode). Alternatively, the switching element may be a power MOSFET made of silicon carbide. In this case, the body diode of the power MOSFET may perform a function similar to that of the FWD in an RC-IGBT. 【0025】Although not shown in the diagram, each semiconductor chip has a main electrode and a control electrode on its front surface. When the switching element of each semiconductor chip is an IGBT, the main electrode is the emitter electrode, and when the switching element is a power MOSFET, the main electrode is the source electrode. The main electrode on the front surface is electrically connected to external terminal 12a, external terminal 12c, or external terminal 12d via a connecting member. The control electrode is the gate electrode of the switching element contained in each semiconductor chip. The control electrode is electrically connected to one of terminals 13a to 13l via a connecting member. 【0026】 Although not shown in the diagram, each semiconductor chip also has a main electrode on its back surface. When the switching element of each semiconductor chip is an IGBT, the main electrode on the back surface is the collector electrode, and when the switching element is a power MOSFET, the main electrode on the back surface is the drain electrode. The main electrode on the back surface of each semiconductor chip is electrically connected to external terminal 12b, external terminal 12d, or the main electrode on the back surface of another semiconductor chip. 【0027】 Furthermore, conductive pins 22 as shown in Figure 2, or a printed circuit board 23 described later, can be used as connecting members. 【0028】 Furthermore, the number of semiconductor chips is not limited to the configuration described above. The number of semiconductor chips may be provided according to the specifications of the semiconductor device 1. In addition, other semiconductor chips, such as diode elements, may be mounted on the insulating circuit board 20. 【0029】 (Regarding external terminals 12a to 12d) External terminals 12a to 12d are integrally molded with case 11. External terminals 12a and 12b are external connection terminals for the main current to which different potentials are applied. In the following description, external terminal 12a is assumed to be connected to the negative side of the DC power supply, and external terminal 12b is assumed to be connected to the positive side of the DC power supply. For this reason, external terminal 12a can also be called the negative terminal and external terminal 12b can be called the positive terminal. 【0030】External terminal 12c is a terminal sometimes called the intermediate terminal (or neutral terminal) of a three-level inverter. External terminal 12d is an output terminal. External terminals 12a to 12d are made of a material with excellent conductivity. This material is, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these materials. 【0031】 Figure 7 is a cross-sectional view showing an enlarged view of the negative terminal. The negative terminal, external terminal 12a, has an internal connection portion 12a1 conductively connected to one of the aforementioned semiconductor chips (for example, semiconductor chip 21), a bent portion 12a2 continuous with the internal connection portion 12a1, and an external connection portion 12a3 continuous with the bent portion 12a2. The boundaries of the internal connection portion 12a1, the bent portion 12a2, and the external connection portion 12a3 shown in Figure 7 are shown for convenience only and are not limited to the configuration shown in Figure 7. The same applies to the other external terminals 12b to 12d described later. 【0032】 The internal connection portion 12a1 is joined to the conductive pattern layer 20c1 by a bonding member such as solder or a metal sintered material, thereby electrically connecting to any semiconductor chip via the conductive pattern layer 20c1 or the printed circuit board 23. The bonding member is not shown in the illustration. Alternatively, bonding may be performed by ultrasonic bonding instead of such a bonding member (the same applies hereafter). 【0033】 The bent portion 12a2 is the part that connects the internal connection portion 12a1 and the external connection portion 12a3. The bent portion 12a2 extends diagonally upward along the long side direction (+X direction) of the case 11 from the end of the internal connection portion 12a1 closest to the inner surface of the case 11, and is connected to the external connection portion 12a3 which is bent and extends in the +X direction. The angle of rise of the bent portion 12a2 with respect to the upper surface of the internal connection portion 12a1 may be, for example, 35° or more and 70° or less, and may be about 45°. 【0034】 At least a portion of the external connection part 12a3 is exposed from the case 11. 【0035】Figure 8 is a cross-sectional view showing an enlarged view of the positive terminal. The positive terminal, the external terminal 12b, has an internal connection portion 12b1 conductively connected to one of the aforementioned semiconductor chips, a bent portion 12b2 continuous with the internal connection portion 12b1, and an external connection portion 12b3 continuous with the bent portion 12b2. 【0036】 The internal connection portion 12b1 is joined to the conductive pattern layer 20c6 by a bonding member such as solder or a metal sintered material, thereby electrically connecting to any semiconductor chip via the conductive pattern layer 20c6. 【0037】 The shape of the bent portion 12b2 and the external connection portion 12b3 is the same as that of the bent portion 12a2 and the external connection portion 12a3 of the external terminal 12a. 【0038】 Figure 9 is a cross-sectional view showing an enlarged view of the intermediate terminal. The intermediate terminal, the external terminal 12c, has an internal connection portion 12c1 conductively connected to one of the aforementioned semiconductor chips, a bent portion 12c2 continuous with the internal connection portion 12c1, and an external connection portion 12c3 continuous with the bent portion 12c2. 【0039】 The internal connection portion 12c1 is joined to the conductive pattern layer 20c5 by a bonding member such as solder or a metal sintered material, thereby electrically connecting to any semiconductor chip via the conductive pattern layer 20c5 or the printed circuit board 23. 【0040】 The shape of the bent portion 12c2 and the external connection portion 12c3 is almost the same as that of the bent portions 12a2 and 12b2 and external connection portions 12a3 and 12b3 of the external terminals 12a and 12b. However, since the external connection portion 12c3 is positioned higher than the external connection portions 12a3 and 12b3, the bent portion 12c2 rises to a higher position than the bent portions 12a2 and 12b2. 【0041】 Figure 10 is a cross-sectional view showing an enlarged view of the output terminal. The external terminal 12d, which is the output terminal, has an internal connection portion 12d1 that is electrically connected to one of the aforementioned semiconductor chips, a bent portion 12d2 that is continuous with the internal connection portion 12d1, and an external connection portion 12d3 that is continuous with the bent portion 12d2. 【0042】The internal connection part 12d1 is joined to the conductive pattern layer 20c4 by a joining member such as solder or a metal sintering material, and is conductively connected to any semiconductor chip via the conductive pattern layer 20c4, the printed circuit board 23, etc. 【0043】 The bent part 12d2 is a part that connects the internal connection part 12d1 and the external connection part 12d3. The bent part 12d2 extends obliquely upward along the long side direction (-X direction) of the case 11 from the end of the internal connection part 12d1 closest to the inner surface of the case 11, bends, and is connected to the external connection part 12d3 provided to extend in the -X direction. The rising angle of the bent part 12d2 with respect to the upper surface of the internal connection part 12d1 may be, for example, 35° or more and 70° or less, and may be about 45°. 【0044】 At least a part of the external connection part 12d3 is exposed from the case 11. 【0045】 (Regarding terminals 13a to 13l) The terminals 13a to 13l function as control terminals or auxiliary source terminals to be described later. As shown in FIG. 1, the terminals 13a to 13l are provided along the long side of the case 11. One end of the terminals 13a to 13l is exposed upward from the upper surface of the case 11 as shown in FIGS. 2 to 5, and the other end penetrates the upper surface of the case 11, which is not shown, and protrudes downward. Note that the terminals 13a to 13l may also be integrally formed with the case 11 together with the external terminals 12a to 12d. As such terminals 13a to 13l, for example, press-fit pins can be used. 【0046】 (Regarding the case 11) The case 11 is substantially rectangular in plan view, seals the bent parts 12a2 to 12d2 and the lower surface side of a plurality of external terminals 12a to 12d on two opposing short sides, respectively, and exposes the external terminals 12a to 12d on the upper surface. The two opposing short sides of the case 11 function as holding regions for holding the external terminals 12a to 12d. Among the two short sides, the external terminals 12a to 12c are held on one side, and the external terminal 12d is held on the other side. 【0047】In the examples of FIGS. 7 and 8 described above, a part of the bent portions 12a2 and 12b2 of the external terminals 12a and 12b and most of the lower surface sides of the external connection portions 12a3 and 12b3 are sealed by the short sides (the holding regions) of the case 11. Also, a part of the external connection portions 12a3 and 12b3 is exposed on the upper surface of the case 11. 【0048】 In the example of FIG. 9 described above, a part of the bent portion 12c2 of the external terminal 12c and the lower surface side of the external connection portion 12c3 are sealed by the short side (the holding region) of the case 11. Also, the upper surface of the external connection portion 12c3 is exposed on the upper surface of the case 11. 【0049】 In the example of FIG. 10 described above, a part of the bent portion 12d2 of the external terminal 12d and the lower surface side of the external connection portion 12d3 are sealed by the short side (the holding region) of the case 11. Also, the upper surface of the external connection portion 12d3 is exposed on the upper surface of the case 11. 【0050】 Note that the bent portions 12a2 to 12d2 of the external terminals 12a to 12d may be entirely sealed by the case 11. Also, a part of the internal connection portions 12a1 to 12d1 may be sealed by the case 11. 【0051】 Furthermore, as shown in FIG. 5, the case 11 has recesses 11d that expose the internal connection portions 12a1 to 12d1 of the external terminals 12a to 12d while penetrating the side surfaces of the long sides. In the example of FIG. 5, the configuration after the recesses 11d are sealed by the sealing resin 24 is shown, but in the state before sealing by the sealing resin 24, the internal connection portions 12a1 to 12d1 are exposed by these recesses 11d. Although not shown, the opposite side surfaces of the long sides of the case 11 shown in FIG. 5 have the same configuration. 【0052】Furthermore, as shown in Figures 1 to 4, the case 11 has grooves 11a1 and 11a2 on its upper surface. Groove 11a1 extends parallel to the short side of the case 11, in a position inside the external connection portions 12a3 to 12c3 of the external terminals 12a to 12c and above the conductive pattern layers 20c1, 20c5, and 20c6 (see Figure 6) adjacent to the outer periphery of the insulating circuit board 20 in a plan view. Groove 11a2 extends parallel to the short side of the case 11, in a position inside the external connection portion 12d3 of the external terminal 12d and above the conductive pattern layer 20c4 (see Figure 6) adjacent to the outer periphery of the insulating circuit board 20 in a plan view. 【0053】 The width (length in the X direction) of the grooves 11a1 and 11a2 is preferably, for example, 1 mm or more and 3 mm or less, from the viewpoint of ease of molding. The deeper the grooves 11a1 and 11a2, the greater the effect of reducing the overall warping deformation of the semiconductor device 1, which will be described later. However, in order to maintain the strength of the case 11, it is preferably, for example, 0.1 mm or more and 0.5 mm or less. The thickness of the top surface of the case 11 is, for example, 1.2 mm or more and 3.6 mm or less. 【0054】 Furthermore, the longer the grooves 11a1 and 11a2 are, the greater the effect in reducing the overall warping deformation of the semiconductor device 1, which will be described later. In the example shown in Figure 1, due to molding considerations, there is a gap of a predetermined width between both ends of the grooves 11a1 and 11a2 and the long sides of the case 11, but both ends may extend from one long side to the other long side of the case 11. 【0055】 Based on the analysis results described later, the position in the X direction where grooves 11a1 and 11a2 are formed is preferably, in a plan view, at a distance of 8 mm or less inward from the short side of the insulating circuit board 20 that is parallel to the two short sides of the case 11. 【0056】 It is preferable that grooves 11a1 and 11a2 be provided one on each of the two short sides of the case 11 in a plan view, as shown in Figure 1. However, even if only one of the grooves 11a1 or 11a2 is provided, the effect of reducing warping deformation can still be obtained. 【0057】The top surface of the case 11 may also be provided with openings 11b1 to 11b5, as shown in Figure 1, to prevent the sealing resin 24, described later, from peeling off the case 11. The sealing resin 24 is exposed through the openings 11b1 to 11b5. The top surface of the case 11 may also be provided with mounting holes 11c1 to 11c4 (through holes) for passing mounting screws to attach a cooler to the back surface of the semiconductor device 1. In this case, the insulating circuit board 20 and the printed circuit board 23 are also provided with mounting holes (through holes) in the same positions as the mounting holes 11c1 to 11c4 when viewed from above. 【0058】 Furthermore, the upper surface of the case 11 may be provided with holes for positioning pins 14a and 14b to pass through for positioning between the case 11, the insulating circuit board 20, and the printed circuit board 23. In this case, the printed circuit board 23 will also have holes in the same position as the holes in the case 11 for passing the positioning pins 14a and 14b when viewed from above. In addition, the insulating circuit board 20 may have, for example, a recess at the same position as the holes in the case 11 when viewed from above (the position where the ends of the positioning pins 14a and 14b abut). 【0059】 Such cases 11 are molded, for example, by injection molding using a thermoplastic resin. Examples of thermoplastic resins include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, acrylonitrile butadiene styrene resin, or liquid crystal polymer. 【0060】 (Regarding the printed circuit board 23) Although not shown in Figures 2 to 4, the printed circuit board 23 is, for example, a multilayer PCB (Printed Circuit Board). In the printed circuit board 23, for example, a wiring layer may be formed on at least one of the upper and lower surfaces of the insulating layer, and one or more wiring layers may also be formed inside the insulating layer. 【0061】The insulating layer is formed of, for example, an insulating resin. Examples of resin layers using insulating resin include paper phenolic substrates, paper epoxy substrates, glass composite substrates, and glass epoxy substrates. The wiring layer is formed of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or alloys mainly composed of at least one of these. 【0062】 The printed circuit board 23 is positioned above the insulating circuit board 20 in the region where the sealing resin 24 is filled. The printed circuit board 23 has a plurality of wiring holes, although these are not shown in the illustration. The main electrodes and control electrodes (not shown) on the upper surface of each semiconductor chip (such as the semiconductor chip 21 in Figure 2), and conductive pins (such as the conductive pin 22 in Figure 2) joined to the insulating circuit board 20 are inserted into the plurality of wiring holes. The ends of terminals 13a to 13l on the -Z direction are also inserted into the plurality of wiring holes. Each wiring hole is connected to one of the wiring layers formed on the printed circuit board 23. 【0063】 Using such a printed circuit board 23, each of the external terminals 12a to 12d can be electrically connected to one of the semiconductor chips via conductive pins and the wiring layer of the printed circuit board 23. Furthermore, each of the terminals 13a to 13l can be electrically connected to one of the semiconductor chips via conductive pins and the wiring layer of the printed circuit board 23. 【0064】 If lead frames or bonding wires are used as connecting members to each semiconductor chip, the number of conductive pattern layers required for wiring on the insulating circuit board 20 tends to increase, leading to an increase in the size and cost of the semiconductor device 1. In contrast, by using the printed circuit board 23 described above, the wiring that was previously wired for each semiconductor chip is consolidated onto the printed circuit board 23 and wired three-dimensionally on the semiconductor chip, thereby reducing the number of conductive pattern layers required for wiring, making the module smaller and enabling high-density mounting. 【0065】 Furthermore, by integrating terminals 13a to 13l, external terminals 12a to 12d, and the printed circuit board 23 with the case 11 and mounting them on the insulated circuit board 20, the manufacturing process can be simplified. 【0066】 (Regarding the sealing resin 24) The sealing resin 24 integrally seals the semiconductor chip 21, the recess 11d of the case 11, and the internal connection portions 12a1 to 12d1 of the external terminals 12a to 12d. When sealing is performed by transfer molding, the sealing resin 24 is made of a hard resin. As the hard resin, for example, a thermosetting resin such as epoxy resin is used. 【0067】 (Circuit example of semiconductor device 1) Figure 11 shows the circuit configuration of an example of a three-level inverter. The three-level inverter shown in Figure 11 is a T-type NPC (Neutral Point Clamped) inverter circuit and includes four transistors Q1 to Q4. Transistors Q1 to Q4 are realized using multiple semiconductor chips, for example, semiconductor chip 21. 【0068】 The drain electrode of transistor Q1 is connected to the P terminal, which is the positive input terminal. The P terminal corresponds to the external terminal 12b shown in Figure 1, etc. The source electrode of transistor Q2 is connected to the N terminal, which is the negative input terminal. The N terminal corresponds to the external terminal 12a shown in Figure 1, etc. 【0069】 The drain electrode of transistor Q3 and the drain electrode of transistor Q4 are connected, and the source electrode of transistor Q3 is connected to the M terminal (intermediate terminal), which is an input terminal at an intermediate potential. The M terminal corresponds to the external terminal 12c shown in Figure 1, etc. 【0070】 The source electrode of transistor Q1, the drain electrode of transistor Q2, and the source electrode of transistor Q4 are connected to the output terminal U. Terminal U corresponds to the external terminal 12d shown in Figure 1, etc. 【0071】The gate electrodes of transistors Q1 to Q4 are connected to gate terminals G1 to G4, which are input terminals for the control signal of the switching operation. Each of the gate terminals G1 to G4 corresponds to one of the terminals 13a to 13l shown in Figure 1, etc. The source electrodes of transistors Q1 to Q4 are connected to auxiliary source terminals S1 to S4, which are output terminals. Each of the auxiliary source terminals S1 to S4 corresponds to one of the terminals 13a to 13l shown in Figure 1, etc. 【0072】 In this three-level inverter, when the control signals to gate terminals G1 and G2 are ON and the control signals to gate terminals G3 and G4 are OFF, the output voltage from terminal U is E / 2. When the terminals to gate terminals G2 and G3 are ON and the terminals to gate terminals G1 and G4 are OFF, the output voltage from terminal U is 0. When the control signals to gate terminals G3 and G4 are ON and the control signals to gate terminals G1 and G2 are OFF, the output voltage from terminal U is -E / 2. 【0073】 (Effects of providing grooves 11a1 and 11a2) Next, we will explain the effects of providing grooves 11a1 and 11a2. Figure 12 is a diagram illustrating the warping that occurs in a semiconductor device. A first warping region 30 and a second warping region 31 are shown as areas where warping occurs. First, we will explain the warping that occurs in the first warping region 30 (hereinafter referred to as overall warping). Note that the distance d in Figure 12 is the distance from the short side of the insulating circuit board 20, which is parallel to the two short sides of the case 11, to grooves 11a1 and 11a2. 【0074】 On the back surface of the insulating circuit board 20 of the semiconductor device 1 (the back surface of the heat sink 20a), a cooler for dissipating heat generated by each semiconductor chip (for example, semiconductor chip 21) may be bonded using a bonding material. 【0075】If a case 11 with a larger coefficient of thermal expansion (sometimes called the coefficient of linear expansion) than the sealing resin 24 is used, the opposing short sides of the case 11 (the holding area for the external terminals 12a to 12d) may deform in the direction of the arrow (-Z direction) due to heating during bonding. If grooves 11a1 and 11a2 as described above are not provided, the degree of overall warping due to this deformation will be large, and an unbonded area may occur between the cooler and the semiconductor device 1. Furthermore, from a reliability standpoint, the load on the bonding material between the semiconductor device 1 and the cooler will increase, raising concerns about a decrease in reliability. In addition, the above-mentioned overall warping may cause the external terminals 12a to 12d to bend or lift upward. 【0076】 In contrast, when grooves 11a1 and 11a2 are provided, local thermal deformation of the opposing short side portions of the case 11 (the holding area for the external terminals 12a to 12d) is mitigated. This reduces the overall warping of the semiconductor device 1. 【0077】 Figure 13 shows the results of a simulation analysis of the difference in the magnitude of overall warpage depending on the presence or absence of grooves. In Figure 13, the horizontal axis represents temperature (°C), and the vertical axis represents warpage (mm) (magnitude of overall warpage). Figure 13 shows the results of a simulation of the occurrence of warpage after resin sealing at 175°C during the molding process and then returning to room temperature. 【0078】 The grooves 11a1 and 11a2 used in the simulation have a width of 1 mm and a depth of 0.5 mm. The position in the X direction where grooves 11a1 and 11a2 are formed is at d = 5.05 mm in Figure 12. 【0079】 As shown in Figure 13, the overall curvature when returned to room temperature (25°C) is reduced by approximately 10% when grooves 11a1 and 11a2 are present compared to when grooves 11a1 and 11a2 are not present. 【0080】 Figure 14 shows the results of a simulation analysis of the difference in the magnitude of overall warpage due to the presence or absence of grooves and the position of the grooves. In Figure 14, the horizontal axis represents the presence or absence of grooves and the position of the grooves, and the vertical axis represents warpage (mm) (magnitude of overall warpage). Figure 14 also shows the results of a simulation of the occurrence of warpage when the material is returned to room temperature (25°C) after resin sealing at 175°C during the molding process. 【0081】 The grooves 11a1 and 11a2 used in the simulation have a width of 1 mm and a depth of 0.5 mm. Furthermore, there are four possible positions in the X-direction where grooves 11a1 and 11a2 are formed: d = 5.05 mm (= Ref), d = Ref + 1 mm, d = Ref + 3 mm, and d = Ref + 7 mm. 【0082】 As shown in Figure 14, the overall curvature when returned to room temperature (25°C) is reduced by 12% when grooves 11a1 and 11a2 are at the position d = Ref, compared to when grooves 11a1 and 11a2 are not present. When grooves 11a1 and 11a2 are at the positions d = Ref + 1 mm, d = Ref + 3 mm, and d = Ref + 7 mm, the curvature is reduced by 13% compared to when grooves 11a1 and 11a2 are not present. 【0083】 Thus, the difference in the effect of reducing warpage due to the difference in the position in the X direction where grooves 11a1 and 11a2 are formed is small. 【0084】 Next, we will explain the warping that occurs in the second warp region 31 in Figure 12. The second warp region 31 is the attachment area in the semiconductor device 1 where the cooler is attached (joined). 【0085】 Figure 15 shows the results of a simulation analysis of the difference in the magnitude of warping in the second warp region (bonded area) due to the presence or absence of grooves and the position of the grooves. In Figure 15, the horizontal axis represents the presence or absence of grooves and the position of the grooves, and the vertical axis represents the warping (mm) (magnitude of warping in the second warp region 31). Figure 15 also shows the results of a simulation of the occurrence of warping after resin sealing at 175°C in the molding process and then returning to room temperature (25°C). 【0086】 The grooves 11a1 and 11a2 used in the simulation have a width of 1 mm and a depth of 0.5 mm. Furthermore, there are four possible positions in the X-direction where grooves 11a1 and 11a2 are formed: d = 5.05 mm (= Ref), d = Ref + 1 mm, d = Ref + 3 mm, and d = Ref + 7 mm. 【0087】As shown in Figure 15, when the material is returned to room temperature (25°C), the curvature of the second curvature region 31 increases by 2% when grooves 11a1 and 11a2 are at the position d = Ref, compared to when grooves 11a1 and 11a2 are absent. Furthermore, when grooves 11a1 and 11a2 are at the position d = Ref + 1 mm, the curvature of the second curvature region 31 increases by 8% compared to when grooves 11a1 and 11a2 are absent. Furthermore, when grooves 11a1 and 11a2 are at the position d = Ref + 3 mm, the curvature of the second curvature region 31 increases by 18% compared to when grooves 11a1 and 11a2 are absent. In addition, when grooves 11a1 and 11a2 are at the position d = Ref + 7 mm, the curvature of the second curvature region 31 increases by 39% compared to when grooves 11a1 and 11a2 are absent. 【0088】 Thus, if the curvature of the second curvature region 31 becomes large, it becomes difficult to join the semiconductor device 1 and the cooler. For this reason, it is preferable that the position in the X direction where grooves 11a1 and 11a2 are formed be kept to about 18% or less, and that the distance d from the short side of the insulating circuit board 20 parallel to the short side of the case 11 in the inward direction of the insulating circuit board 20 is within 8 mm. 【0089】 As described above, according to the semiconductor device 1 of this embodiment, the warping deformation of the semiconductor device 1 can be reduced by providing grooves 11a1 and 11a2. This suppresses warping deformation during heating and improves the manufacturability of the joint between the cooler and the semiconductor device 1, as well as the reliability of the joint. 【0090】 (Modified Groove) Figure 16 shows a modified groove. Unlike groove 11a1 shown in Figure 1, groove 40 has a tapered shape in which the width narrows in the depth direction (-Z direction). Other components (position, size, shape, etc.) are the same as groove 11a1. 【0091】 By giving groove 40 this tapered shape, the release properties of the case 11 from the mold during manufacturing are improved. Groove 11a2 can also be given a tapered shape similar to groove 40. 【0092】 Note that the grooves 11a1, 11a2, and 40 are not limited to the above configuration, and may be formed by dividing them into multiple parts in the Y direction in Figure 1, for example. 【0093】 The above describes one aspect of the semiconductor device of the present invention based on embodiments, but these are merely examples and the invention is not limited to those described above. The above merely illustrates the principle of the present invention. Furthermore, numerous modifications and changes are possible for those skilled in the art, and the present invention is not limited to the exact configurations and applications shown and described above, and all corresponding modifications and equivalents are considered to be within the scope of the present invention as defined by the appended claims and equivalents. 【0094】 1 Semiconductor device 11 Case 11a1, 11a2, 40 Grooves 11b1 to 11b5 Openings 11c1 to 11c4 Mounting holes 11d Recesses 12a to 12d External terminals 12a1 to 12d1 Internal connection parts 12a2 to 12d2 Bent parts 12a3 to 12d3 External connection parts 13a to 13l Terminals 14a, 14b Positioning pins 20 Insulated circuit board 20a Heat sink 20b Insulating layer 20c1 to 20c6 Conductive pattern layer 21 Semiconductor chip 22 Conductive pins 23 Printed circuit board 24 Sealing resin 30 First warped region 31 Second warped region

Claims

1. An insulating circuit board having a heat sink, an insulating layer disposed on the upper surface of the heat sink, and a plurality of conductive pattern layers disposed on the upper surface of the insulating layer; a semiconductor chip connected to some of the conductive pattern layers among the plurality of conductive pattern layers; a plurality of external terminals having an internal connection portion conductively connected to the semiconductor chip, a bent portion continuous from the internal connection portion, and an external connection portion continuous from the bent portion; a case having a substantially rectangular shape in plan view, with two opposing short sides that seal the bent portions and lower sides of the plurality of external terminals, respectively, and recesses that penetrate the side of the long side and expose the internal connection portions of the plurality of external terminals, with the plurality of external terminals exposed on the upper surface, and having grooves on the upper surface that are inside the external connection portions of the plurality of external terminals and, in plan view, above the conductive pattern layers among the plurality of conductive pattern layers adjacent to the outer circumference of the insulating circuit board, parallel to the two short sides; and a sealing resin that integrally seals the semiconductor chip, the recesses of the case, and the internal connection portions of the plurality of external terminals. A semiconductor device equipped with a semiconductor device.

2. The semiconductor device according to claim 1, wherein, in a plan view, one groove is provided on each of the two short sides of the case.

3. The semiconductor device according to claim 1, wherein the groove is provided in a plan view at a distance of 8 mm or less in the inward direction of the insulating circuit board from the short side of the insulating circuit board parallel to the two short sides of the case.

4. The semiconductor device according to claim 1, wherein the width of the groove is 1 mm or more and 3 mm or less.

5. The semiconductor device according to claim 1, wherein the depth of the groove is 0.1 mm or more and 0.5 mm or less.

6. The semiconductor device according to claim 1, wherein the groove has a tapered shape that narrows in width in the depth direction.

7. The semiconductor device according to claim 1, wherein the plurality of external terminals include a positive terminal, a negative terminal, an intermediate terminal, and an output terminal, and the positive terminal, the negative terminal, and the intermediate terminal are held on one of the two short sides of the case, and the output terminal is held on the other.

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