Wafer level package, wafer level-chip size package, and method for manufacturing same

Abstract

A wafer level package (1) comprises: a lower substrate (22); an upper substrate (23) facing the lower substrate (22); a plurality of elements (20) arranged in an array, the plurality of elements (20) being formed on at least one of the lower substrate (22) and the upper substrate (23), or being mounted between the lower substrate (22) and the upper substrate (23); a first eutectic material f formed on the surface of the lower substrate (22) facing the upper substrate (23); a second eutectic material f' formed on the surface of the upper substrate (23) facing the lower substrate (22); a plurality of frame bodies (24) surrounding the plurality of elements (20) respectively; and connection parts (26) that connect parts of the frame bodies (24) respectively surrounding adjacent elements (20) from among the plurality of elements (20). The frame bodies (24) and the connection parts (26) are formed by eutectically bonding the first eutectic material f and the second eutectic material f'. The eutectic material ratio between the first eutectic material f and the second eutectic material f' is different between at least the frame bodies (24) and a part of the connection parts (26).

Claims

1. A wafer-level package comprising: a first wafer; a second wafer facing the first wafer; a plurality of elements arranged in an array, formed on at least one of the first wafer and the second wafer, or mounted between the first wafer and the second wafer; a plurality of frames surrounding each of the plurality of elements; and connecting portions connecting parts of the frames that surround adjacent elements, wherein the frames and the connecting portions are formed by eutectic bonding of a first eutectic material and a second eutectic material, and the eutectic material ratio of the first eutectic material and the second eutectic material is different between at least a part of the connecting portions and the frames.

2. The wafer-level package according to claim 1, wherein the first eutectic material is Al and the second eutectic material is Ge.

3. With respect to the frame, the eutectic material ratio of the first eutectic material to the second eutectic material is Al:Ge=αat%:(100-α)at%, and with respect to the connecting portion, the eutectic material ratio of the first eutectic material to the second eutectic material is Al:Ge=βat%:(100-β)at%, wherein 25 < α < 35 and 5 < β-α or β-α > 5, the wafer-level package according to claim 2.

4. The wafer-level package according to any one of claims 1 to 3, wherein the frame is rectangular in shape, and the connecting portion is connected to the corner of the frame.

5. The wafer-level package according to any one of claims 1 to 4, wherein the connecting portion is connected only to the frame surrounding the elements arranged on the outermost periphery of the first wafer and the second wafer among the plurality of elements.

6. A wafer-level chip-size package in which the connecting portion of the wafer-level package described in any one of claims 1 to 5 is cut and fragmented.

7. A wafer-level chip-size package according to claim 6, having a portion of the connecting portion connected to the frame, wherein there is a portion between the portion of the connecting portion and the frame in which the eutectic material ratio of the first eutectic material and the second eutectic material is different.

8. A wafer-level package comprising: a first wafer; a second wafer facing the first wafer; a plurality of elements arranged in an array, each element formed on at least one of the first wafer and the second wafer, or mounted between the first wafer and the second wafer; a first eutectic material formed on the surface of the first wafer facing the second wafer; and a second eutectic material formed on the surface of the second wafer facing the first wafer, wherein, when the first eutectic material and the second eutectic material are eutectic-jointed, they constitute a plurality of frames surrounding each of the plurality of elements, and connecting portions connecting parts of the frames that surround adjacent elements, wherein at least one of the first eutectic material or the second eutectic material is missing such that a fluid path is formed in the region between the frames.

9. A method for manufacturing a wafer-level chip-size package, comprising: a step of preparing a first wafer and a second wafer; a step of arranging a plurality of elements in an array on at least one of the first wafer and the second wafer, or between the first wafer and the second wafer; a step of forming a first eutectic material on the surface of the first wafer facing the second wafer; a step of forming a second eutectic material on the surface of the second wafer facing the first wafer; an alignment step of aligning the first wafer and the second wafer so that the first eutectic material and the second eutectic material are in contact with each other; a eutectic bonding step of eutectic bonding the first eutectic material and the second eutectic material to form a plurality of frames that surround and seal each of the plurality of elements, and connecting portions that connect parts of the frames that surround adjacent elements among the plurality of elements; and a step of cutting the connecting portions to form individual pieces. A method for manufacturing a wafer-level chip-size package, wherein in the alignment step, at least one of the first eutectic material or the second eutectic material is missing so that a fluid path is formed in the region between the frames, and in the eutectic bonding step, the path is filled by eutectic bonding between the first eutectic material and the second eutectic material.

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