Display panel and driving method therefor, and display device

Abstract

A display panel, a driving method, and a display device. Each pixel (02) in the display panel comprises an anti-peeping light-emitting device and a shared light-emitting device, and a gate driving circuit (03) and a first light-emitting driving circuit (04) each comprise driving units (001) and control units (002). Each control unit (002) can select, on the basis of a received enable signal, to output a driving signal provided by the corresponding driving unit (001) or output a turn-off signal to the connected pixel (02), such that the corresponding shared light-emitting device is flexibly controlled to emit light in an anti-peeping mode and a sharing mode, the display panel is controlled to refresh and display at a higher refresh rate in a high-refresh scenario, and the display panel is controlled to refresh and display at a lower refresh rate in a low-refresh scenario. The display panel has a plurality of display modes.

Description

Display panel and its driving method, display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and its driving method and display device. Background Technology

[0002] Display panels are electronic device components used to display images and videos, and are widely used in various display devices such as mobile phones, computers, and automotive displays. Summary of the Invention

[0003] A display panel and its driving method, as well as a display device, are provided.

[0004] On one hand, a display panel is provided, the display panel comprising:

[0005] Substrate;

[0006] Multiple pixels located on the substrate, each pixel including a driving transistor, a privacy light-emitting device, and a shared light-emitting device;

[0007] A gate driving circuit located on the substrate is used to control the driving transistor in the pixel to receive data signals;

[0008] A first light-emitting driving circuit located on the substrate is used to control the light-emitting state of the shared light-emitting device in the pixel;

[0009] Each of the gate driving circuit and the first light-emitting driving circuit includes: a plurality of cascaded driving units and a plurality of control units, wherein the output terminals of the plurality of driving units are connected to the plurality of control units, the output terminals of the plurality of control units are connected to the plurality of pixels, and each driving unit is also connected to an enable terminal.

[0010] Furthermore, each of the driving units is used to output a driving signal, and each of the control units is used to output the driving signal or a shutdown signal to the connected pixel in response to the enable signal provided by the enable terminal; the driving signal output by the control unit in the gate driving circuit is used to indicate that the plurality of pixels are lit up at a first refresh rate, and the shutdown signal output by the control unit in the gate driving circuit is used to indicate that the plurality of pixels are lit up at a second refresh rate, wherein the first refresh rate is greater than the second refresh rate; the driving signal output by the control unit in the first light-emitting driving circuit is used to control the shared light-emitting device to emit light, and the shutdown signal output by the control unit in the first light-emitting driving circuit is used to control the shared light-emitting device not to emit light.

[0011] Optionally, the gate driving circuit includes a P-type gate driving circuit and an N-type gate driving circuit. The P-type gate driving circuit is connected to the P-type transistors in the plurality of pixels, and the N-type gate driving circuit is connected to the N-type transistors in the plurality of pixels. Both the P-type gate driving circuit and the N-type gate driving circuit include the cascaded plurality of driving units and the plurality of control units.

[0012] Optionally, the P-type transistor is used to control the first terminal of the driving transistor in the pixel to receive the data signal; the N-type transistor is used to control the gate of the driving transistor in the pixel to receive the data signal; the plurality of pixels are arranged in an array.

[0013] In the P-type gate driving circuit, multiple driving units are connected to multiple rows of pixels one-to-one through multiple control units;

[0014] In other driving circuits besides the P-type gate driving circuit, multiple driving units are connected to multiple rows of pixels one-to-one through multiple control units, or each driving unit is connected to at least two rows of pixels through a corresponding control unit.

[0015] Optionally, in other driving circuits besides the P-type gate driving circuit, each driving unit is connected to two adjacent rows of pixels through a corresponding control unit.

[0016] Optionally, the display panel further includes:

[0017] A first reset driving circuit located on the substrate is used to control the driving transistor in the pixel to receive a reset signal;

[0018] A second reset driving circuit located on the substrate is used to control the shared light-emitting device in the pixel to receive a reset signal;

[0019] A second light-emitting driving circuit located on the substrate is used to control the light-emitting state of the privacy light-emitting device in the pixel;

[0020] Wherein, at least one of the first reset driving circuit, the second reset driving circuit, and the second light-emitting driving circuit includes: the cascaded plurality of driving units, and the plurality of control units;

[0021] Furthermore, the drive signals output by the control units in the first reset drive circuit and the second reset drive circuit are used to instruct the plurality of pixels to be lit up according to the first refresh rate, the shutdown signals output by the control units in the first reset drive circuit and the second reset drive circuit are used to instruct the plurality of pixels to be lit up according to the second refresh rate, the drive signals output by the control units in the second light-emitting drive circuit are used to control the privacy light-emitting device to emit light, and the shutdown signals output by the control units in the second light-emitting drive circuit are used to control the privacy light-emitting device not to emit light.

[0022] Optionally, the plurality of pixel arrays are arranged in a row direction, and the display panel includes: one of the gate driving circuits located on each side of the substrate in the row direction;

[0023] The at least one driving circuit is the first reset driving circuit; the first light-emitting driving circuit and the second reset driving circuit are located on one side of the substrate, and the second light-emitting driving circuit and the first reset driving circuit are located on the other side of the substrate.

[0024] Optionally, on one of the two sides, along the direction close to the pixel, the second reset driving circuit, the first light-emitting driving circuit, the N-type gate driving circuit in the gate driving circuit, and the P-type gate driving circuit in the gate driving circuit are arranged in sequence.

[0025] On the other side of the two sides, along the direction close to the pixel, the second light-emitting driving circuit, the first reset driving circuit, the N-type gate driving circuit in the gate driving circuit, and the P-type gate driving circuit in the gate driving circuit are arranged in sequence.

[0026] Optionally, each of the driving units is also connected to a switch terminal and is used to output the driving signal or a shutdown signal to the connected pixel in response to the enable signal, the switch signal provided by the switch terminal, and the driving signal; the control unit includes:

[0027] A switch subunit is connected to the enable terminal, the switch terminal, and the first node respectively, and is used to control the connection and disconnection between the enable terminal and the first node in response to the switch signal;

[0028] The control subunit is connected to the first power supply terminal, the second power supply terminal, the first node, the output terminal of the drive unit, and the output terminal of the control unit, respectively. It is used to control the connection and disconnection between each of the first power supply terminals and the second power supply terminal and the output terminal of the control unit in response to the potential of the first node and the drive signal, so as to output the drive signal, and to control the connection and disconnection between one of the first power supply terminals and the second power supply terminal and the output terminal of the control unit, so as to output the shutdown signal.

[0029] Optionally, the switching terminal includes one or more switching terminals; the switching subunit includes one or more first transistors;

[0030] The one or more switching transistors are connected in series between the enable terminal and the first node, and the gates of the one or more switching transistors are connected to the one or more switching terminals in a one-to-one correspondence.

[0031] Optionally, the output terminal of the drive unit includes a first output terminal and a second output terminal, wherein the first drive signal output by the drive unit through the first output terminal and the second drive signal output through the second output terminal are inverse signals to each other; the control subunit responds to the first drive signal by controlling the connection and disconnection between the first power supply terminal and the output terminal of the control unit, or responds to the second drive signal by controlling the connection and disconnection between the second power supply terminal and the output terminal of the control unit.

[0032] The switching terminal includes two sets of switching terminals, each set of switching terminals includes two switching terminals. The two switching terminals in one set of switching terminals are respectively connected to the first output terminal and the second output terminal of the current stage drive unit, and the two switching terminals in the other set of switching terminals are respectively connected to the first output terminal and the second output terminal of the cascaded previous stage drive unit.

[0033] The switching subunit includes: two sets of first transistors, each set of first transistors including two first transistors of different types; the gates of the two first transistors in one set of first transistors are respectively connected to the first output terminal and the second output terminal of the current stage driving unit; the gates of the two first transistors in the other set of first transistors are respectively connected to the first output terminal and the second output terminal of the previous stage driving unit; the first electrode of the two first transistors in the set of first transistors is connected to the enable terminal; the second electrode of the two first transistors in the set of first transistors is connected to the first electrode of the two first transistors in the other set of first transistors; and the second electrode of the two first transistors in the other set of first transistors is connected to the first node.

[0034] Optionally, the control subunit includes:

[0035] The first control unit is connected to the first node, the first power supply terminal, the second power supply terminal, and the second node respectively, and is used to control the connection and disconnection between the first power supply terminal and the second node in response to the potential of the first node.

[0036] The second control unit is connected to the second node, the first power supply terminal, the second power supply terminal and the first node respectively, and is used to control the connection and disconnection between the first power supply terminal and the first node in response to the potential of the second node, and to control the connection and disconnection between the second power supply terminal and the first node.

[0037] The third control unit is connected to the output terminal of the drive unit, the second node, the first power supply terminal, another power supply terminal of the second power supply terminal, and the third node, respectively, and is used to control the on / off state of the second node and the third node in response to the drive signal, and to control the on / off state of the other power supply terminal and the third node.

[0038] The fourth control unit is connected to the third node, the first power supply terminal, the second power supply terminal, and the output terminal of the control unit, respectively, and is used to control the connection and disconnection between each of the first power supply terminal and the second power supply terminal and the output terminal of the control unit in response to the potential of the third node, and to control the connection and disconnection between one of the first power supply terminal and the second power supply terminal and the output terminal of the control unit.

[0039] Optionally, the first control unit includes: a second transistor and a third transistor of different types; the second control unit includes: a fourth transistor and a fifth transistor of different types; the third control unit includes: a sixth transistor and a seventh transistor of different types; and the fourth control unit includes: an eighth transistor and a ninth transistor of different types.

[0040] The gates of the second transistor and the third transistor are both connected to the first node; the first terminals of the second transistor and the third transistor are respectively connected to the first power supply terminal and the second power supply terminal; and the second terminals of the second transistor and the third transistor are both connected to the second node.

[0041] The gates of the fourth transistor and the fifth transistor are both connected to the second node. The first terminals of the fourth transistor and the fifth transistor are respectively connected to the first power supply terminal and the second power supply terminal. The second terminals of the fourth transistor and the fifth transistor are both connected to the first node.

[0042] The gates of the sixth transistor and the seventh transistor are both connected to the output terminal of the driving unit. The first terminals of the sixth transistor and the seventh transistor are respectively connected to the second node and the other power terminal of the first power terminal and the second power terminal. The second terminals of the sixth transistor and the seventh transistor are both connected to the third node.

[0043] The gates of the eighth transistor and the ninth transistor are both connected to the third node. The first terminals of the eighth transistor and the ninth transistor are respectively connected to the first power supply terminal and the second power supply terminal. The second terminals of the eighth transistor and the ninth transistor are both connected to the output terminal of the control unit.

[0044] Optionally, the control subunit further includes: a first storage capacitor connected between the first node and the second power supply terminal; and / or, a second storage capacitor connected between the third node and the second power supply terminal.

[0045] On the other hand, a driving method for a display panel is provided, applied to a display panel as described in the above aspect; the method includes:

[0046] In the shared mode or under the control of the first scan instruction, the enable terminal provides an enable signal at the first potential, causing multiple control units in the gate drive circuit to respond to the received enable signal and output drive signals to the connected multiple pixels to indicate that the multiple pixels are lit according to the first refresh rate, and causing multiple control units in the first light-emitting drive circuit to respond to the received enable signal and output drive signals to the connected multiple pixels to indicate that the shared light-emitting device in the multiple pixels emits light.

[0047] In privacy mode or under the control of the second scan command, the enable terminal provides an enable signal at the second potential, causing multiple control units in the gate drive circuit to respond to the received enable signal and output a shutdown signal to the connected multiple pixels to indicate that the multiple pixels are lit according to the second refresh rate, and causing multiple control units in the first light-emitting drive circuit to respond to the received enable signal and output a shutdown signal to the connected multiple pixels to indicate that the shared light-emitting device in the multiple pixels does not emit light.

[0048] Wherein, the first refresh rate controlled by the first scan command is greater than the second refresh rate controlled by the second scan command.

[0049] In another aspect, a display device is provided, the display device comprising: a power supply component, and a display panel as described in the other aspect above;

[0050] The power supply component is connected to the display panel and is used to supply power to the display panel. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0053] Figure 2 is a schematic diagram of a pixel circuit structure in a display panel provided in an embodiment of this application;

[0054] Figure 3 is a schematic diagram of the pixel working timing in a display panel provided in an embodiment of this application;

[0055] Figure 4 is a schematic diagram of the film structure of a privacy OLED and a shared OLED provided in an embodiment of this application;

[0056] Figure 5 is a schematic diagram of the structure of a driving circuit in a display panel provided in an embodiment of this application;

[0057] Figure 6 is a schematic diagram of the circuit and pixel arrangement in a display panel provided in an embodiment of this application;

[0058] Figure 7 is a schematic diagram of the structure of a control unit provided in an embodiment of this application;

[0059] Figure 8 is a schematic diagram of another control unit provided in an embodiment of this application;

[0060] Figure 9 is a schematic diagram of the circuit structure of a driving unit provided in an embodiment of this application;

[0061] Figure 10 is a schematic diagram of the circuit structure of a control unit based on Figure 8;

[0062] Figure 11 is a schematic diagram of the operating timing of a circuit based on Figure 10;

[0063] Figure 12 is a schematic diagram of the signal timing of a display panel in different modes according to an embodiment of this application;

[0064] Figure 13 is a schematic diagram of the signal timing of another display panel provided in an embodiment of this application under different modes;

[0065] Figure 14 is a flowchart illustrating a driving method for a display panel according to an embodiment of this application;

[0066] Figure 15 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0068] It is understood that the transistors used in all embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this application are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this application, the source is referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the control electrode, also known as the gate; the signal input terminal is the source; and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this application can include either P-type or N-type switching transistors. A P-type switching transistor conducts when the gate is low and is cut off when the gate is high; an N-type switching transistor conducts when the gate is high and is cut off when the gate is low. In addition, multiple signals in various embodiments of this application correspond to a first level and a second level. The first level and the second level only represent that the potential of the signal has two states; they do not represent that the first level or the second level has a specific value throughout the text.

[0069] A display panel typically includes multiple pixels located on a substrate and a display driving circuit that drives the pixels to emit light. The display driving circuit can be, for example, a gate driving circuit or a light-emitting driving circuit. The display driving circuit transmits driving signals to the pixel circuits within the pixels, causing the pixel circuits to drive the light-emitting elements within the pixels to emit light based on the driving signals. However, current display panels can only refresh at a single frequency and cannot achieve privacy protection, resulting in a relatively limited display method. Based on this, embodiments of this application provide a novel display panel that can achieve privacy protection and shared display in any area under circuit control, and can also achieve high-frequency and low-frequency display in any area, offering a richer display method and better display flexibility.

[0070] It is understood that privacy display refers to a display panel with pixels emitting light from a narrow viewing angle, making the displayed information visible only to the user of the display panel and invisible to others, thus preventing information leakage. Shared display refers to a display panel with pixels emitting light from a wide viewing angle, making the displayed information visible to the user and others, ensuring information sharing. High-frequency display refers to a display panel refreshing the image at a higher frequency, resulting in a higher refresh rate. Low-frequency display refers to a display panel refreshing the image at a lower frequency, resulting in a lower refresh rate. Refresh rate refers to the number of times the display panel refreshes the image per second, usually measured in Hertz (Hz). In the embodiments of this application, "large" and "small," "high" and "low" are all relative.

[0071] Figure 1 is a schematic diagram of a display panel provided in an embodiment of this application. As shown in Figure 1, the display panel includes:

[0072] Substrate 01.

[0073] Multiple pixels 02 are located on substrate 01. Based on Figure 1 and referring to Figure 2, each pixel 02 includes a driving transistor T01, a privacy light-emitting device, and a shared light-emitting device. That is, each pixel 02 may include one privacy light-emitting device and one shared light-emitting device, and these two devices can share a single pixel circuit, which may include the driving transistor T01. The privacy light-emitting device is a small-viewing-angle light-emitting device to achieve privacy display; the shared light-emitting device is a large-viewing-angle light-emitting device to achieve shared display.

[0074] Optionally, Figure 2 illustrates a pixel using an organic light-emitting diode (OLED) as the light-emitting device. Referring to Figure 2, it can also be seen that the pixel circuit structure in pixel 02 is a 9T1C structure (i.e., nine transistors T01 to T09 and one capacitor Cst). The privacy-protecting light-emitting device in pixel 02 is a privacy-protecting OLED, and the shared light-emitting device is a shared OLED. The 9T1C pixel circuit is connected to both the privacy-protecting OLED and the shared OLED to drive them to emit light. Of course, this pixel circuit structure is only illustrative.

[0075] Optionally, based on Figure 2, Figure 3 also schematically illustrates a pixel's operating timing diagram. Referring to Figure 3, it can be seen that the stages for driving the pixel to emit light can include refresh frames and hold frames. The difference between refresh frames and hold frames lies in the reset drive signal provided by the reset signal terminal P_Reset, and the gate drive signals provided by the gate signal terminals N_Gate and P_Gate are different.

[0076] Furthermore, it is understood that, referring to Figures 2 and 3, for the P-type transistor in the pixel circuit, the P-type transistor can be turned on when the potential of the driving signal received at the gate is low; conversely, the P-type transistor can be turned off when the potential of the driving signal received at the gate is high. For the N-type transistor in the pixel circuit, the N-type transistor can be turned on when the potential of the driving signal received at the gate is high; conversely, the N-type transistor can be turned off when the potential of the driving signal received at the gate is low. Thus, the working principle of the pixel circuit can be determined by referring to the timing shown in Figure 3. For example, for the structure shown in Figure 2, when the potential of the light-emitting driving signal provided by the light-emitting control terminal EM is low, the light-emitting driving current generated by the driving transistor T01 can be transmitted to the privacy OLED, causing the privacy OLED to emit light. Only when the potential of the light-emitting driving signal provided by the light-emitting control terminal EM2 is also low can the light-emitting driving current transmitted to the privacy OLED be further transmitted to the shared OLED, causing the shared OLED to emit light. That is, the light-emitting control terminal EM can be regarded as the common control terminal for the privacy OLED and the shared OLED, while the light-emitting control terminal EM2 can be regarded as the separate control terminal for the shared OLED. When the shared OLED emits light, the privacy OLED also emits light; and when the shared OLED does not emit light, the privacy OLED can still emit light. Based on this, in the embodiments of this application, in the privacy mode, only the privacy OLED can be controlled to emit light, and the shared OLED can be controlled not to emit light; in the shared mode, both the privacy OLED and the shared OLED can be controlled to emit light.

[0077] Of course, for more precise control of privacy and sharing, if it is desired to control only the sharing OLED to emit light in sharing mode, while controlling the privacy OLED to not emit light, then, similar to the configuration of transistor T08, a transistor T10 can be added between the privacy OLED and transistor T07, and the gate of this transistor T10 can be connected to another light emission control terminal EM3. In this way, the light emission control signal provided by the light emission control terminal EM3 can be flexibly configured to control whether the privacy OLED emits light or not.

[0078] Optionally, based on Figure 2, Figure 4 also schematically illustrates a film structure diagram of a privacy OLED and a shared OLED. Referring to Figure 4, a privacy OLED can refer to a structure with a shielding layer above the OLED. Under the shielding layer, the privacy OLED can emit light from a narrow viewing angle. Furthermore, in some embodiments, in addition to the shielding layer, a lens structure is also provided above the privacy OLED to concentrate and block the light emitted from the privacy OLED from a wide viewing angle, allowing only a narrow viewing angle. A shared OLED can refer to a structure without a shielding layer above the OLED or with the shielding layer far from the OLED opening. The shared OLED can emit light from a wide viewing angle. The shielding layer can be, for example, the BM shielding layer shown in Figure 4, or a metal layer with poor light transmittance. This application does not limit the choice of shielding layer. Of course, the OLED device structure shown in Figure 4 is only schematic illustration.

[0079] Optionally, the pixels including the privacy OLED and the shared OLED can be applied to display panels in various scenarios, such as mobile phones, laptops (notebooks, NBs), tablets, and automotive displays. Based on the above examples, and continuing to refer to Figure 5, it can be seen that the display panel described in this embodiment further includes:

[0080] A gate driving circuit 03 located on substrate 01 is used to control the driving transistor T01 in pixel 02 to receive data signals.

[0081] For example, referring to Figure 2, the gate drive circuit 03 can be connected to the gate signal terminal N_Gate of transistor T02 and transmit a gate drive signal to the gate signal terminal N_Gate to control the switching of transistor T02, thereby indirectly controlling the data signal provided by the data terminal Vdata to be written to the gate of the driving transistor T01. Furthermore, the gate drive circuit 03 can be integrated onto the substrate using gate driver on array (GOA) technology, and is also called a GOA circuit.

[0082] A first light-emitting driving circuit 04 is located on the substrate 01. The first light-emitting driving circuit 04 is used to control the light-emitting state of the shared light-emitting device in the pixel 02.

[0083] For example, referring to Figure 2, the first light-emitting driving circuit 04 can be connected to the light-emitting control terminal EM2 connected to the gate of transistor T08, and transmit a light-emitting driving signal to the light-emitting control terminal EM2 to control the switching of transistor T08, thereby controlling the light-emitting driving current output by driving transistor T01 to be written to the shared light-emitting device, so that the shared light-emitting device emits light. Furthermore, the first light-emitting driving circuit 04 can also be integrated onto the substrate using GOA technology, also known as a GOA circuit.

[0084] Referring to Figure 5, each driving circuit in the gate driving circuit 03 and the first light-emitting driving circuit 04 can include: multiple cascaded driving units 001 and multiple control units 002. The output terminal OUT of the multiple driving units 001 is connected to the multiple control units, the output terminal EOUT of the multiple control units 002 is connected to the multiple pixels 02, and each control unit 002 is also connected to the enable terminal EN.

[0085] For example, multiple driving units 001 and multiple control units 002 can correspond one-to-one, multiple pixels 02 can be arranged in an array, and each control unit 002 can be connected to at least one row of pixels 02. Furthermore, as described above, the output terminal EOUT of the control unit 002 in the gate driving circuit 03 can be connected to the gate signal terminal N_Gate in the pixel 02; the output terminal EOUT of the control unit 002 in the first light-emitting driving circuit 04 can be connected to the light-emitting control terminal EM2 in the pixel 02. In addition, cascading multiple driving units 001 can refer to cascading two adjacent driving units 001; however, this is only an illustrative example.

[0086] Each drive unit 001 is used to output a drive signal, and each control unit 002 is used to output a drive signal or a shutdown signal to the connected pixel 02 in response to the enable signal provided by the enable terminal EN. The drive unit 001 is also called the GOA unit. The control unit 002 is also called the EN control circuit.

[0087] That is, the driving unit 001 can be the part that generates and outputs the driving signal, while the control unit 002 can be the part that controls whether the driving signal is output to pixel 02. For example, the control unit 002 can control the driving signal output by the driving unit 001 through the output terminal OUT to be further transmitted to pixel 02, that is, to output a normal driving signal to pixel 02; or, the control unit 002 can also control the driving signal output by the driving unit 001 through the output terminal OUT to be unable to be transmitted to pixel 02, but instead output a shutdown signal to pixel 02. Here, the driving signal can refer to a pulse signal with a high potential and a low potential, and the shutdown signal can be a DC signal with a continuous high potential or a low potential. The driving signal can be used to control the normal switching of the transistor, and the shutdown signal can be used to control the transistor to remain in the off state.

[0088] As described above, the driving signal generated by the driving unit 001 in the gate driving circuit 03 is also the gate driving signal. Since this gate driving signal is used to control the writing of data signals, it can be known that the display refresh rate can be controlled by controlling the writing frequency of the data signals. The driving signal generated by the driving unit 001 in the first light-emitting driving circuit 04 is also the light-emitting control signal. Since this light-emitting control signal is used to control the writing of light-emitting driving current to the shared light-emitting device, it can be known that the shared light-emitting device can be controlled to emit light or not emit light by controlling whether light-emitting driving current is written to it.

[0089] In other words, the drive signal output by the control unit 002 in the gate drive circuit 03 can be used to instruct multiple pixels to be lit at a first refresh rate, and the off signal output by the control unit 002 in the gate drive circuit 03 can be used to instruct multiple pixels to be lit at a second refresh rate, where the first refresh rate is greater than the second refresh rate. In other words, the drive signal output by the control unit 002 in the gate drive circuit 03 can control the display panel to display at a high frequency; the off signal output by the control unit 002 in the gate drive circuit 03 can control the display panel to display at a low frequency. The drive signal output by the control unit 002 in the first light-emitting drive circuit 04 can be used to control the shared light-emitting device to emit light, and the off signal output by the control unit 002 in the first light-emitting drive circuit 04 can be used to control the shared light-emitting device to not emit light. Based on controlling the shared light-emitting device to emit light, shared display can be achieved; based on controlling the shared light-emitting device to not emit light, privacy display can be achieved by controlling only the privacy light-emitting device to emit light. Therefore, by flexibly setting the enable signal, the display panel can be flexibly controlled to display at a low or high frequency, or to display at a privacy or shared frequency.

[0090] For example, for the gate drive circuit 03, when the enable signal provided by the enable terminal EN is at the first potential, the control unit 002 can control the drive signal output by the drive unit 001 to be further transmitted to the pixel 02, such as to the gate signal terminal N_Gate in the pixel 02 as shown in Figure 2, so that the transistor T02 can be switched on and off normally, thereby allowing the data signal provided by the data terminal Vdata to be written normally to the gate of the drive transistor T01, thus controlling the high-frequency display of the display panel. When the enable signal provided by the enable terminal EN is at the second potential, the control unit 002 can directly transmit a shutdown signal to the pixel, such as transmitting a shutdown signal to the gate signal terminal N_Gate in the pixel 02 as shown in Figure 2, so that the transistor T02 remains off, thereby preventing the data signal provided by the data terminal Vdata from being written normally to the gate of the drive transistor T01, thus controlling the low-frequency display of the display panel.

[0091] For example, for the first light-emitting driving circuit 04, when the enable signal provided by the enable terminal EN is at the first potential, the control unit 002 can control the driving signal output by the driving unit 001 to be further transmitted to the pixel 02, such as to the light-emitting control terminal EM2 in the pixel 02 as shown in Figure 2, so that the transistor T08 can be turned on, and thus the light-emitting driving current transmitted by the driving transistor T01 to the privacy light-emitting device can also be further transmitted to the shared light-emitting device, thereby controlling both the shared light-emitting device and the privacy light-emitting device to emit light. When the enable signal provided by the enable terminal EN is at the second potential, the control unit 002 can directly transmit a shutdown signal to the pixel, such as transmitting a shutdown signal to the light-emitting control terminal EM2 in the pixel 02 as shown in Figure 2, so that the transistor T08 remains off, and thus the light-emitting driving current transmitted by the driving transistor T01 to the privacy light-emitting device cannot be further transmitted to the shared light-emitting device, thereby controlling the shared light-emitting device not to emit light and only the privacy light-emitting device to emit light.

[0092] Based on this, it can also be understood that the enable terminals EN connected to the gate driving circuit 03 and the first light-emitting driving circuit 04 should be different enable terminals. Optionally, in the embodiments of this application, the first potential can be a low potential relative to the second potential. Of course, in some other embodiments, the first potential can also be a high potential relative to the second potential.

[0093] Based on the above description, the embodiments of this application can drive the pixels to work through the GOA circuit in conjunction with the EN control circuit, so that the display panel can display at low frequency or high frequency, display privacy or share display, and be compatible with different display modes.

[0094] In summary, this application provides a display panel. The pixels in this display panel include privacy-protected light-emitting devices and shared light-emitting devices, and both the gate driving circuit and the light-emitting driving circuit include a driving unit and a control unit. Since the control unit can selectively output a driving signal provided by the driving unit or an off signal to the connected pixels based on a received enable signal, the enable signal can be flexibly set to allow flexible control of the shared light-emitting device in privacy mode, flexible control of the shared light-emitting device in shared mode, and control of the display panel to refresh at a higher refresh rate in high refresh rate scenarios and at a lower refresh rate in low refresh rate scenarios. That is, it can balance privacy protection and shared display, as well as low refresh rate and high refresh rate display. This display panel offers a variety of display modes.

[0095] Optionally, based on Figure 5 and further referring to Figure 6, the gate driving circuit 03 may include a P-type gate driving circuit 031 and an N-type gate driving circuit 032. The P-type gate driving circuit 031 may be connected to P-type transistors in multiple pixels, and the N-type gate driving circuit 032 may be connected to N-type transistors in multiple pixels. Both the P-type gate driving circuit 031 and the N-type gate driving circuit 032 may include multiple cascaded driving units 001 and multiple control units 002.

[0096] That is, in the embodiments of this application, the structures of the P-type gate driving circuit 031 and the N-type gate driving circuit 032 can both be as shown in FIG. 5, and the control unit 002 is connected to different enable terminals EN. FIG. 6 only schematically shows the two driving units 001 and two control units 002 that correspond one-to-one in the P-type gate driving circuit 031, and schematically shows the one driving unit 001 and one control unit 002 that correspond one-to-one in the N-type gate driving circuit 032.

[0097] For example, referring to Figure 2, the P-type gate drive circuit 031 can be connected to the gate signal terminal P_Gate connected to the P-type transistor T05, and is used to transmit the P-type gate drive signal to the gate signal terminal P_Gate. The N-type gate drive circuit 032 can be connected to the gate signal terminal N_Gate connected to the N-type transistor T02, and is used to transmit the N-type gate drive signal to the gate signal terminal N_Gate. It can be understood that the P-type gate drive signal is a drive signal with an effective potential of low potential and an invalid potential of high potential; the N-type gate drive signal is a drive signal with an effective potential of high potential and an invalid potential of low potential. Based on this, in Figure 6, the drive unit 001 included in the P-type gate drive circuit 031 is directly labeled as P_Gate, and the drive unit 001 included in the N-type gate drive circuit 032 is directly labeled as N_Gate.

[0098] Optionally, in conjunction with the foregoing description and Figure 2, a P-type transistor (e.g., T05) can be used to control the first terminal of the driving transistor T01 in pixel 02 to receive data signals. An N-type transistor (e.g., T02) can be used to control the gate of the driving transistor T01 in pixel 02 to receive data signals. That is, the P-type transistor T05 connected to the gate signal terminal P_Gate can control the data signal provided by the data terminal Vdata to be directly written to the first terminal of the driving transistor T01, while the N-type transistor T02 connected to the gate signal terminal N_Gate can control the data signal written to the first terminal of the driving transistor T01 to be indirectly written to the gate of the driving transistor T01, so that the driving transistor T01 generates a light-emitting driving current based on the data signal.

[0099] Thus, combining Figures 1 and 6, multiple pixels 02 can be arranged in an array. That is, the display panel can include multiple rows and columns of pixels 02. Figure 6 schematically shows two rows of pixels Pixel1 and Pixel2. Furthermore, in the P-type gate driving circuit 031, multiple driving units 001 can be connected one-to-one with multiple rows of pixels 02 through multiple control units 002. That is, as shown in Figure 6, the P-type gate driving circuit 031 can include two driving units 001 and two control units 002, to be connected one-to-one with two rows of pixels Pixel1 and Pixel2, so that the two rows of pixels Pixel1 and Pixel2 can emit light row by row.

[0100] In driving circuits other than the P-type gate driving circuit 031 (e.g., the N-type gate driving circuit 032), multiple driving units 001 can be connected one-to-one with multiple rows of pixels 02 through multiple control units 002, or each driving unit 001 can be connected to at least two rows of pixels through a corresponding control unit 002. That is, like the P-type gate driving circuit 031, the N-type gate driving circuit 032 can also include multiple driving units 001 and multiple control units 002 that are connected one-to-one with multiple rows of pixels. Alternatively, at least two rows of pixels 02 can share one driving unit 001 and one control unit 002.

[0101] For example, referring to Figure 6, in the N-type gate driving circuit 032 shown therein, each driving unit 001 can be connected to two adjacent rows of pixels 02 through a corresponding control unit 002. This not only does not affect the independent driving of the two rows of pixels 02, but also simplifies the structure and wiring, thus facilitating narrow bezel designs and saving costs.

[0102] Of course, in the P-type gate driving circuit 031, each driving unit 001 can also be connected to at least two rows of pixels 02 through a corresponding control unit 002. This allows the same data signal to be written to at least two rows of pixels 02 simultaneously, so that at least two rows of pixels 02 can emit light simultaneously. It is understood that the circuit and pixel connections are not shown in Figure 6.

[0103] Optionally, referring further to Figure 6, the display panel described in the embodiments of this application may further include:

[0104] A first reset drive circuit 05 is located on the substrate. This first reset drive circuit 05 can be used to control the drive transistor in the pixel to receive a reset signal. For example, referring to Figure 2, the first reset drive circuit 05 can be connected to the reset signal terminal P_Reset connected to the gate of the P-type transistor T03, and is used to provide a reset drive signal to the reset signal terminal P_Reset to control the switching of the P-type transistor T03, so that the power signal provided by the initial power supply terminal Vinit1 can be transmitted to the second terminal of the drive transistor T01, thereby resetting the second terminal of the drive transistor T01.

[0105] A second reset driving circuit 06 is located on the substrate. This second reset driving circuit 06 can be used to control the shared light-emitting device in the pixel to receive a reset signal. For example, referring to Figure 2, the second reset driving circuit 06 can be connected to the reset signal terminal P_ResetH connected to the gate of the P-type transistor T09, and is used to provide a reset driving signal to the reset signal terminal P_ResetH to control the switching of the P-type transistor T09, so that the power signal provided by the initial power supply terminal Vinit2 can be transmitted to the shared OLED, thereby resetting the shared OLED.

[0106] A second light-emitting driving circuit 07 is located on the substrate. This second light-emitting driving circuit 07 can be used to control the light-emitting state of the privacy-protecting light-emitting device in the pixel. For example, referring to Figure 2, the second light-emitting driving circuit 07 can be connected to the light-emitting control terminal EM connected to the gate of P-type transistors T06 and T07, and is used to provide a light-emitting driving signal to the light-emitting control terminal EM to control the switching of P-type transistors T06 and T07, so that a loop can be formed between the power supply terminal VDD and the cathode of the privacy-protecting OLED, so that the driving transistor T01 can output a light-emitting driving signal to the privacy-protecting OLED to drive the privacy-protecting OLED to emit light.

[0107] Furthermore, at least one of the first reset drive circuit 05, the second reset drive circuit 06, and the second light-emitting drive circuit 07 can each include: a plurality of cascaded drive units 001 and a plurality of control units 002. That is, the structure of at least one of the first reset drive circuit 05, the second reset drive circuit 06, and the second light-emitting drive circuit 07 can be any of the circuit structures shown in FIG. 5, wherein the control units 002 are connected to different enable terminals EN.

[0108] Furthermore, the drive signals output by the control units 002 in the first reset drive circuit 05 and the second reset drive circuit 06 can be used to instruct multiple pixels 02 to be lit according to the first refresh rate, and the off signals output by the control units 002 in the first reset drive circuit 05 and the second reset drive circuit 06 can be used to instruct multiple pixels to be lit according to the second refresh rate. The drive signals output by the control units 002 in the second light-emitting drive circuit 07 are used to control the privacy light-emitting device to emit light, and the off signals output by the control units 002 in the second light-emitting drive circuit 07 are used to control the privacy light-emitting device to not emit light. That is, similar to the gate drive circuit 03, the reset drive signals output by each reset drive circuit can also control the display panel to display at a high frequency, while the output off signals can control the display panel to display at a low frequency. Similar to the first light-emitting drive circuit 04, the light-emitting drive signals output by the second light-emitting drive circuit 07 can control the privacy light-emitting device to emit light, and the output off signals of the second light-emitting drive circuit 07 can control the privacy light-emitting device to not emit light. Thus, the enable signals provided by the enable terminal EN connected to the above-mentioned drive circuits can also be flexibly set to control low-frequency display or high-frequency display, and to control privacy display or shared display.

[0109] For example, in the circuits shown in Figure 6, only the first reset drive circuit 05 includes a drive unit 001 and a control unit 002; the other drive circuits do not include the control unit 002. This is mainly because the second reset drive circuit 06 resets the shared light-emitting device and does not affect the refresh rate, and the second light-emitting drive circuit 07 outputs a light-emitting drive signal to the light-emitting control terminal EM shared by the privacy light-emitting device and the shared light-emitting device, which does not directly affect the light-emitting state of the shared light-emitting device. Therefore, it is possible to select only the first reset drive circuit 05 to include a drive unit 001 and a control unit 002. Since the first reset drive circuit 05 resets the drive transistor T1, its output reset drive signal can also affect the writing of data signals, thereby affecting the refresh rate. Based on the setting of the first reset drive circuit 05 to include a drive unit 001 and a control unit 002, the reset drive signal can be flexibly set to output a reset drive signal to the pixel, making the display panel display at a high refresh rate, or output a shutdown signal, making the display panel display at a low refresh rate. Based on this, in Figure 6, the driving unit 001 included in the first reset driving circuit 05 is directly labeled as P_Reset, the second reset driving circuit 06 is directly labeled as P_ResetH, and the second light-emitting driving circuit 07 is directly labeled as EM.

[0110] As mentioned above, multiple pixels 02 can be arranged in an array. Based on this, referring to Figure 6, it can be seen that the display panel can include: one gate driving circuit 03 on each side of the substrate 01 in the row direction X1, including a P-type gate driving circuit 031 and an N-type gate driving circuit 032.

[0111] In addition to the gate driving circuit 03 and the first light-emitting driving circuit 04, at least one driving circuit including the driving unit 001 and the control unit 002 can be a first reset driving circuit 05. The first light-emitting driving circuit 04 and the second reset driving circuit 06 can be located on one side of the substrate 01, and the second light-emitting driving circuit 07 and the first reset driving circuit 05 can be located on the other side of the substrate 01. In this way, space can be better utilized for circuit layout, which is beneficial for narrow bezel design.

[0112] Optionally, referring to Figure 6, on one side of the circuit, along the direction closer to pixel 02, the second reset driving circuit 06, the first light-emitting driving circuit 04, the N-type gate driving circuit 032 in the gate driving circuit 03, and the P-type gate driving circuit 031 in the gate driving circuit 03 can be arranged sequentially. On the other side of the circuit, along the direction closer to pixel 02, the second light-emitting driving circuit 07, the first reset driving circuit 05, the N-type gate driving circuit 032 in the gate driving circuit 03, and the P-type gate driving circuit 031 in the gate driving circuit 03 can be arranged sequentially. This not only facilitates layout and narrow bezel design but also reduces the impact of the load on the signal on the circuit and pixel connection lines. This ensures that each pixel on both sides of the substrate 01 in each row can receive a signal with essentially the same potential, resulting in better display uniformity for the pixels on both sides of the substrate 01 and ensuring a better display effect.

[0113] That is, in this embodiment, the system mainly relies on the configuration of a P-type gate driving circuit 031, an N-type gate driving circuit 032, a first reset driving circuit 05, and a first light-emitting driving circuit 04, including a GOA circuit and an EN control circuit. The system determines whether to output a normal waveform driving signal or a shutdown signal to the pixel by setting an enable signal provided by the enable terminal EN. For example, when the enable signal is at a low potential, the EN control circuit can control the driving signal generated by the GOA circuit to be further output to the pixel; when the enable signal is at a high potential, the EN control circuit can output a shutdown signal to the pixel. For the P-type transistor in the pixel, this shutdown signal is a high-potential signal; for the N-type transistor in the pixel, this shutdown signal is a low-potential signal. Furthermore, the first light-emitting driving circuit 04 can control shared display or privacy display, and the P-type gate driving circuit 031, the N-type gate driving circuit 032, and the first reset driving circuit 05 can control high-frequency display or low-frequency display.

[0114] Optionally, in this embodiment of the application, as shown in FIG7, each control unit 002 can also be connected to the switch terminal K and can be used to output a drive signal or a turn-off signal to the connected pixel in response to an enable signal, a switch signal provided by the switch terminal K, and a drive signal. Based on this, as shown in FIG7, the control unit 002 can include: a switch subunit 0021 and a control subunit 0022. FIG7 shows a circuit structure using the first light-emitting drive circuit 04 as an example.

[0115] The switch subunit 0021 can be connected to the enable terminal EN, the switch terminal K, and the first node N1, respectively. Furthermore, the switch subunit 0021 can be used to control the on / off state of the enable terminal EN and the first node N1 in response to a switch signal.

[0116] For example, the switch subunit 0021 can control the enable terminal EN to be connected to the first node N1 when the switch signal potential is a first potential, so that the enable signal provided by the enable terminal EN can be transmitted to the first node N1. The switch subunit 0021 can also control the enable terminal EN to be disconnected from the first node N1 when the switch signal potential is a second potential. That is, the potential of the first node N1 can be the potential of the enable signal.

[0117] Optionally, as mentioned above, for a P-type transistor, the first potential can be a low potential relative to the second potential; for an N-type transistor, the first potential can be a high potential relative to the second potential.

[0118] The control subunit 0022 can be connected to the first power supply terminal V1, the second power supply terminal V2, the first node N1, the output terminal OUT of the drive unit 001, and the output terminal EOUT of the control unit 002, respectively. Furthermore, the control subunit 0022 can be used, in response to the potential of the first node N1 and the drive signal, to control the on / off state of each power supply terminal in the first power supply terminal V1 and the second power supply terminal V2 with the output terminal EOUT of the control unit 002 to output a drive signal, and to control the on / off state of one of the power supply terminals in the first power supply terminal V1 and the second power supply terminal V2 with the output terminal EOUT of the control unit 002 to output a shutdown signal.

[0119] Optionally, the potential of the first power signal provided by the first power supply terminal V1 can be high, and the potential of the second power signal provided by the second power supply terminal V2 can be low. Here, high and low potentials can be relative. Correspondingly, the first power supply terminal V1 can also be called the pull-up power supply terminal VGH, and the second power supply terminal V2 can also be called the pull-down power supply terminal VGL.

[0120] For example, as described above, when the potential of the first node N1 (i.e., the potential of the enable signal) is at the first potential, the control subunit 0022, in response to the potential of the first node N1 and the drive signal, controls the first power supply terminal V1 and the second power supply terminal V2 to alternately conduct with the output terminal EOUT, so as to output a drive signal including high and low potential signals to the connected pixel via the output terminal EOUT. When the potential of the first node N1 (i.e., the potential of the enable signal) is at the second potential, the control subunit 0022 controls the first power supply terminal V1 or the second power supply terminal V2 to continuously conduct with the output terminal EOUT, so as to output a high or low potential off signal to the connected pixel via the output terminal EOUT.

[0121] It is understandable that if the transistor connected to the light-emitting control terminal EM2 in the pixel circuit is a P-type transistor T08 as shown in Figure 2, then the shutdown signal output through the output terminal EOUT should be a high-potential signal (e.g., a high-potential first power supply signal provided by the first power supply terminal V1) to reliably turn off the P-type transistor. Correspondingly, it can be known that the control subunit 0022 can control the first power supply terminal V1 and the output terminal EOUT to remain continuously connected when the potential of the first node N1 is the second potential. If the transistor connected to the light-emitting control terminal EM2 in the pixel circuit is an N-type transistor, then the shutdown signal output through the output terminal EOUT should be a low-potential signal (e.g., a low-potential second power supply signal provided by the second power supply terminal V2) to reliably turn off the N-type transistor. Correspondingly, it can be known that the control subunit 0022 can control the second power supply terminal V2 and the output terminal EOUT to remain continuously connected when the potential of the first node N1 is the second potential.

[0122] Optionally, based on Figure 7, and continuing to refer to Figure 8, it can be seen that the control subunit 0022 in the control unit 002 may include: a first control unit 00221, a second control unit 00222, a third control unit 00223, and a fourth control unit 00224.

[0123] The first control unit 00221 can be connected to the first node N1, the first power supply terminal V1, the second power supply terminal V2, and the second node N2, respectively. Furthermore, the first control unit 00221 can control the switching on and off of the first power supply terminal V1 and the second node N2 in response to the potential of the first node N1, and also control the switching on and off of the second power supply terminal V2 and the second node N2.

[0124] For example, when the potential of the first node N1 is a first potential, the first control unit 00221 can control the first power supply terminal V1 to be connected to the second node N2, and control the second power supply terminal V2 to be disconnected from the second node N2, so that the high-potential first power signal provided by the first power supply terminal V1 is transmitted to the second node N2, that is, control the potential of the second node N2 to be high. The first control unit 00221 can also control the first power supply terminal V1 to be disconnected from the second node N2, and control the second power supply terminal V2 to be connected to the second node N2 when the potential of the first node N1 is a second potential, so that the low-potential second power signal provided by the second power supply terminal V2 is transmitted to the second node N2, that is, control the potential of the second node N2 to be low.

[0125] The second control unit 00222 can be connected to the second node N2, the first power supply terminal V1, the second power supply terminal V2, and the first node N1, respectively. Furthermore, the second control unit 00222 can control the switching between the first power supply terminal V1 and the first node N1 in response to the potential of the second node N2, and also control the switching between the second power supply terminal V2 and the first node N1.

[0126] For example, when the potential of the second node N2 is a first potential (e.g., a low potential), the second control unit 00222 can control the first power supply terminal V1 to be connected to the first node N1 and control the second power supply terminal V2 to be disconnected from the first node N1, so that the high-potential first power signal provided by the first power supply terminal V1 is transmitted to the first node N1, that is, control the potential of the first node N1 to be high. The second control unit 00222 can also control the first power supply terminal V1 to be disconnected from the first node N1 and control the second power supply terminal V2 to be connected to the first node N1 when the potential of the second node N2 is a second potential (e.g., a high potential), so that the low-potential second power signal provided by the second power supply terminal V2 is transmitted to the first node N1, that is, control the potential of the first node N1 to be low.

[0127] That is, in accordance with the above description, when the enable signal provided by the enable terminal EN is at a low potential, the first control unit 00221 and the second control unit 00222 can cooperate with each other to control the potential of the first node N1 to be stable at a low potential and control the potential of the second node N2 to be at a high potential; when the enable signal provided by the enable terminal EN is at a high potential, the first control unit 00221 and the second control unit 00222 can cooperate with each other to control the potential of the first node N1 to be stable at a high potential and control the potential of the second node N2 to be at a low potential.

[0128] The third control unit 00223 can be connected to the output terminal OUT of the drive unit 001, the second node N2, the other power supply terminal of the first power supply terminal V1 and the second power supply terminal V2, and the third node N3. Furthermore, the third control unit 00223 can be used to control the switching on and off of the second node N2 and the third node N3 in response to a drive signal, and also control the switching on and off of the other power supply terminal and the third node N3.

[0129] For example, the third control unit 00223 can control the second node N2 and the third node N3 to conduct when the potential of the drive signal is the first potential, and control the other power supply terminal to disconnect from the third node N3, so that the signal transmitted to the second node N2 is further transmitted to the third node N3, that is, control the potential of the third node N3 to be the same as the potential of the second node N2. The third control unit 00223 can also control the second node N2 and the third node N3 to disconnect when the potential of the drive signal is the second potential, and control the other power supply terminal to conduct to the third node N3, so that the power signal provided by the other power supply terminal is transmitted to the third node N3.

[0130] The fourth control unit 00224 can be connected to the third node N3, the first power supply terminal V1, the second power supply terminal V2, and the output terminal of the control unit, respectively. Furthermore, the fourth control unit 00224 can control the connection and disconnection of each of the first power supply terminals V1 and V2 with the output terminal EOUT of the control unit 002 in response to the potential of the third node N3, and can also control the connection and disconnection of one of the first power supply terminals V1 and V2 with the output terminal EOUT of the control unit 002.

[0131] For example, the fourth control unit 00224 can control the first power supply terminal V1 to be connected to the output terminal EOUT and control the second power supply terminal V2 to be disconnected from the output terminal EOUT when the potential of the third node N3 is the first potential, so that the high-potential first power signal provided by the first power supply terminal V1 can be output through the output terminal EOUT. The fourth control unit 00224 can also control the first power supply terminal V1 to be disconnected from the output terminal EOUT and control the second power supply terminal V2 to be connected to the output terminal EOUT when the potential of the third node N3 is the second potential, so that the low-potential second power signal provided by the second power supply terminal V2 can be output through the output terminal EOUT.

[0132] Therefore, to control the first power supply terminal V1 and the second power supply terminal V2 to alternately conduct with the output terminal EOUT, the potential of the third node N3 needs to be controlled to alternately be the first potential and the second potential. Conversely, to control the first power supply terminal V1 or the second power supply terminal V2 to continuously conduct with the output terminal EOUT, the potential of the third node N3 needs to be controlled to continuously be the first potential or the second potential. For example, to control the first power supply terminal V1 to continuously conduct with the output terminal EOUT, the potential of the third node N3 needs to be controlled to continuously be the first potential; to control the second power supply terminal V2 to continuously conduct with the output terminal EOUT, the potential of the third node N3 needs to be controlled to continuously be the second potential.

[0133] Based on this, since the potential of the second node N2 is flexible and variable, assuming that the potential of the third node N3 needs to be continuously controlled to the first potential (e.g., low potential), that is, regardless of whether the potential of the driving signal is high or low, the potential of the third node N3 needs to be controlled to be low, as shown in Figure 8, the other power supply terminal connected to the third control unit 00223 can be the second power supply terminal V2 that can provide a low potential power signal. Conversely, assuming that the potential of the third node N3 needs to be continuously controlled to the second potential (e.g., high potential), that is, regardless of whether the potential of the driving signal is high or low, the potential of the third node N3 needs to be controlled to be high, the other power supply terminal connected to the third control unit 00223 can be the first power supply terminal V1 that can provide a high potential power signal.

[0134] Understandably, since the third control unit 00223 responds to the drive signal of the second potential to control the other power supply terminal to conduct with the third node N3, in the scenario where the other power supply terminal connected to the third control unit 00223 is the second power supply terminal V2, and the low-potential power signal provided by the second power supply terminal V2 is transmitted to the third node N3, and then the fourth control unit 00224 controls the high-potential power signal provided by the first power supply terminal V1 to be transmitted to the output terminal EOUT, the drive signal of the second potential should be high. Conversely, in the scenario where the other power supply terminal connected to the third control unit 00223 is the first power supply terminal V1, and the high-potential power signal provided by the first power supply terminal V1 is transmitted to the third node N3, and then the fourth control unit 00224 controls the low-potential power signal provided by the second power supply terminal V2 to be transmitted to the output terminal EOUT, the drive signal of the second potential should be low. That is, the drive signal should be different and inversely related depending on the other power supply terminal selected.

[0135] Accordingly, referring to the circuit structure diagram of a driving unit shown in Figure 9, the output terminal OUT of the driving unit 001 can include a first output terminal OUT1 and a second output terminal FOUT1. The first driving signal output by the driving unit 001 through the first output terminal OUT1 and the second driving signal output through the second output terminal FOUT1 are inverted signals. The second driving signal can be considered as the signal obtained by inverting the first driving signal. The control subunit 0022 can control the connection and disconnection between the second power supply terminal V2 and the output terminal of the control unit in response to the first driving signal, or control the connection and disconnection between the first power supply terminal V1 and the output terminal of the control unit in response to the second driving signal. That is, referring to Figure 9, when the other power supply terminal is the second power supply terminal V2, the third control unit 00223 can be connected to the first output terminal OUT1 to receive the first driving signal; while when the other power supply terminal is the first power supply terminal V1, the third control unit 00223 can be connected to the second output terminal FOUT1 to receive the second driving signal.

[0136] Optionally, referring to Figure 9, it can also be seen that the circuit structure of the driving unit 001 can be 18T2C (i.e., including 18 transistors T1 to T18, and 2 capacitors C1 and C2). Among them, T9 and T0 can be connected to the first output terminal OUT1, and T13 and T14 can form an inverter and be connected to the second output terminal FOUT1. The first driving signal output from the first output terminal OUT1 is inverted and then output through the second output terminal FOUT1.

[0137] Optionally, in some embodiments, the switch terminal K may include one or more switch terminals K. Correspondingly, the switch sub-unit may include one or more first transistors CT1. That is, it is not limited to the single switch terminal K shown in the figure above.

[0138] One or more first transistors CT1 can be connected in series between the enable terminal EN and the first node N1, and the gates of one or more first transistors can be connected one-to-one with one or more switch terminals K.

[0139] For example, the output terminal OUT of the drive unit 001 may include a first output terminal OUT1 and a second output terminal FOUT1, and based on the cascaded control unit 002, as shown in Figure 10, the switch terminal K may include two sets of switch terminals K-1 and K-2. Each set of switch terminals K includes two switch terminals K11 and K12. The two switch terminals K11 and K12 in one set of switch terminals K-1 can be connected to the first output terminal OUT1 and the second output terminal FOUT1 of the current stage drive unit 001, respectively. The two switch terminals K11 and K12 in the other set of switch terminals K-2 can be connected to the first output terminal OUT0 and the second output terminal FOUT0 of the cascaded previous stage drive unit, respectively.

[0140] Based on this, referring to Figure 10, the switching subunit 0021 can include two sets of first transistors CT1-1 and CT1-2. Each set of first transistors can include two first transistors CT11 and CT12 of different types. The gates of the two first transistors CT11 and CT12 in the first set of first transistors CT1-1 are connected to the first output terminal OUT1 and the second output terminal FOUT1 of the current stage driving unit 001, respectively. The gates of the two first transistors CT11 and CT12 in the other set of first transistors CT1-2 can be connected to the first output terminal OUT0 and the second output terminal FOUT0 of the previous stage driving unit 001, respectively. The first terminals of the two first transistors CT11 and CT12 in the first set of first transistors CT1-1 can be connected to the enable terminal EN. The second terminals of the two first transistors CT11 and CT12 in the first set of first transistors CT1-1 can be connected to the first terminals of the two first transistors CT11 and CT12 in the other set of first transistors CT1-2. The second terminals of the two first transistors CT11 and CT12 in the other set of first transistors CT1-2 can be connected to the first node N1.

[0141] It is understandable that different types can refer to N-type and P-type. For example, referring to Figure 10, in a set of first transistors CT1-1, the first transistor CT11 can be a P-type transistor, and the first transistor CT12 can be an N-type transistor. The gate of the first transistor CT11 can be connected to the first output terminal OUT1, and the gate of the first transistor CT12 can be connected to the second output terminal FOUT1. In another set of first transistors CT1-2, the first transistor CT11 can be an N-type transistor, and the first transistor CT12 can be a P-type transistor. The gate of the first transistor CT11 can be connected to the first output terminal OUT0, and the gate of the first transistor CT12 can be connected to the second output terminal FOUT0.

[0142] Thus, when the potential of the first drive signal provided by the first output terminal OUT1 and the potential of the second drive signal provided by the second output terminal FOUT0 are both low, and the potential of the second drive signal provided by the second output terminal FOUT1 and the potential of the first drive signal provided by the first output terminal OUT0 are both high, all first transistors CT1 can be turned on, making the enable terminal EN connected to the first node N1. Each group of first transistors CT1 can be regarded as a transmission gate.

[0143] Optionally, referring to Figure 10, the first control unit 00221 may include a second transistor CT2 and a third transistor CT3 of different types. For example, the second transistor CT2 may be a P-type transistor; and the third transistor CT3 may be an N-type transistor.

[0144] The gates of the second transistor CT2 and the third transistor CT3 can both be connected to the first node N1. The first terminals of the second transistor CT2 and the third transistor CT3 can be connected to the first power supply terminal V1 and the second power supply terminal V2, respectively. The second terminals of the second transistor CT2 and the third transistor CT3 can both be connected to the second node N2.

[0145] The second control unit 00222 may include a fourth transistor CT4 and a fifth transistor CT5 of different types. For example, the fourth transistor CT4 may be a P-type transistor; and the fifth transistor CT5 may be an N-type transistor.

[0146] The gates of the fourth transistor CT4 and the fifth transistor CT5 can both be connected to the second node N2. The first terminal of the fourth transistor CT4 and the first terminal of the fifth transistor CT5 can be connected to the first power supply terminal V1 and the second power supply terminal V2, respectively. The second terminals of the fourth transistor CT4 and the fifth transistor CT5 can both be connected to the first node N1.

[0147] The third control unit 00223 may include a sixth transistor CT6 and a seventh transistor CT7 of different types. For example, the sixth transistor CT6 may be a P-type transistor; the seventh transistor CT7 may be an N-type transistor.

[0148] The gates of the sixth transistor CT6 and the seventh transistor CT7 can both be connected to the output terminal OUT of the driving unit 001. The first terminal of the sixth transistor CT6 and the first terminal of the seventh transistor CT7 can be connected to the second node N2 and the other power supply terminal of the first power supply terminal V1 and the second power supply terminal V2, respectively. The second terminals of the sixth transistor CT6 and the seventh transistor CT7 can both be connected to the third node N3.

[0149] The fourth control unit 00224 may include an eighth transistor CT8 and a ninth transistor CT9 of different types. For example, the eighth transistor CT8 may be a P-type transistor; the ninth transistor CT9 may be an N-type transistor.

[0150] The gates of the eighth transistor CT8 and the ninth transistor CT9 can both be connected to the third node N3. The first terminals of the eighth transistor CT8 and the ninth transistor CT9 can be connected to the first power supply terminal V1 and the second power supply terminal V2, respectively. The second terminals of the eighth transistor CT8 and the ninth transistor CT9 can both be connected to the output terminal EOUT of the control unit 002. That is, each control unit can actually be regarded as an inverter.

[0151] In Figure 10, with the third control unit 00223 connected to the first output terminal OUT1, it can be seen from Figure 10 that the sixth transistor CT6 is a P-type transistor; the seventh transistor CT7 is an N-type transistor. The first terminal of the sixth transistor CT6 is connected to the second node N2, and the first terminal of the seventh transistor CT7 is connected to the second power supply terminal V2. Furthermore, the gates of both the sixth and seventh transistors are connected to the first output terminal OUT1. Alternatively, with the third control unit 00223 connected to the second output terminal FOUT1, the sixth transistor CT6 is an N-type transistor; the seventh transistor CT7 is a P-type transistor. The first terminal of the sixth transistor CT6 is connected to the second node N2, and the first terminal of the seventh transistor CT7 is connected to the first power supply terminal V1. Furthermore, the gates of both the sixth and seventh transistors are connected to the second output terminal FOUT1.

[0152] Optionally, referring further to Figure 10, the control subunit 0022 may further include: a first storage capacitor CC1 connected between the first node N1 and the second power supply terminal V2; and / or a second storage capacitor CC2 connected between the third node N3 and the second power supply terminal V2. The first storage capacitor CC1 can be used to stabilize the potential of the first node N1; the second storage capacitor CC2 can be used to stabilize the potential of the third node N3, ensuring good potential stability of the above nodes.

[0153] Of course, the circuit structure shown in Figure 10 is a schematic illustration, and any circuit capable of achieving the above functions is applicable to this application. Optionally, taking the structure shown in Figure 10, and taking the first light-emitting driving circuit 04 as an example, Figure 11 schematically shows a timing diagram of the operation of a control subunit 0022.

[0154] Referring to Figure 11, it can be seen that during the same time period, the potentials of the first drive signal output by the current stage control unit 002 via the first output terminal OUT1 and the second drive signal output via the second output terminal FOUT1 are exactly opposite; the potentials of the first drive signal output by the previous stage control unit 002 via the first output terminal OUT0 and the second drive signal output via the second output terminal FOUT0 are also exactly opposite. Furthermore, during the same time period, the potentials of the first drive signal output via the first output terminal OUT1 and the second drive signal output via the second output terminal FOUT0 are both low, and simultaneously, the potentials of the second drive signal output via the second output terminal FOUT1 and the first drive signal output via the first output terminal OUT0 are both high. At this time, each first transistor CT1 can be turned on, making the enable terminal EN connected to the first node N1, thus enabling the enable signal provided by the enable terminal EN to be transmitted to the first node N1.

[0155] Furthermore, for the structure shown in Figure 10, when the enable signal provided by the enable terminal EN is at a high potential, causing the potential of the first node N1 to be high, the P-type second transistor CT2 can be turned off, and the N-type third transistor CT3 can be turned on. Correspondingly, the second power supply terminal V2 (i.e., the pull-down power supply terminal VGL) can be turned on to the second node N2, and the first power supply terminal V1 (i.e., the pull-up power supply terminal VGH) can be disconnected from the second node N2. Furthermore, the second power supply terminal V2 can transmit a low-potential second power signal to the second node N2, controlling the potential of the second node N2 to be low. Based on the low potential of the second node N2, the P-type fourth transistor CT4 can be turned on, and the N-type fifth transistor CT5 can be turned off. Correspondingly, the first power supply terminal V1 can be turned on to the first node N1, and the second power supply terminal V2 can be disconnected from the first node N1. Furthermore, the first power supply terminal V1 can transmit a high-potential first power signal to the first node N1. In other words, the potential of the first node N1 can be reliably controlled to remain high. That is, when the potential of the enable signal is high (vgh), the potential of the first node N1 can be controlled to be high, and the potential of the second node N2 can be controlled to be low.

[0156] When the enable signal provided by the enable terminal EN is at a low potential, causing the potential of the first node N1 to be low, the P-type second transistor CT2 can be turned on, and the N-type third transistor CT3 can be turned off. Correspondingly, the first power supply terminal V1 can be connected to the second node N2, and the second power supply terminal V2 can be disconnected from the second node N2. Furthermore, the first power supply terminal V1 can transmit a high-potential second power signal to the second node N2, controlling the potential of the second node N2 to be high. With the potential of the second node N2 high, the P-type fourth transistor CT4 can be turned off, and the N-type fifth transistor CT5 can be turned on. Correspondingly, the second power supply terminal V2 can be connected to the first node N1, and the first power supply terminal V1 can be disconnected from the first node N1. Furthermore, the second power supply terminal V2 can transmit a low-potential second power signal to the first node N1. That is, the potential of the first node N1 can be reliably controlled to remain low. That is, when the enable signal is at a low potential vgl, the potential of the first node N1 can be controlled to be low, and the potential of the second node N2 can be controlled to be high.

[0157] Furthermore, when the potential of the first drive signal output through the first output terminal OUT1 is high, the P-type sixth transistor CT6 can be turned off, and the N-type seventh transistor CT7 can be turned on. Correspondingly, this allows the second power supply terminal V2 to conduct with the third node N3, and disconnects the second node N2 from the third node N3. This allows the second power supply terminal V2 to transmit a low-potential second power signal to the third node N3. When the potential of the first drive signal output through the first output terminal OUT1 is low, the P-type sixth transistor CT6 can be turned on, and the N-type seventh transistor CT7 can be turned off. Correspondingly, this allows the second node N2 to conduct with the third node N3, and disconnects the second power supply terminal V2 from the third node N3. Since the potential of the second node N2 is low when the potential of the enable signal is high (vgh), it can be known that the potential of the third node N3 can also be controlled to be low at this time. Since the second node N2 has a high potential when the enable signal is at a low potential (vgl), it can be concluded that the third node N3 can be controlled to have a high potential at this time. That is, when the enable signal is at a high potential (vgh), the third node N3 can be controlled to remain at a low potential regardless of whether the first drive signal is high or low; when the enable signal is at a low potential (vgl), the third node N3 can be controlled to remain at a low potential when the first drive signal is high, and vice versa.

[0158] Finally, when the potential of the third node N3 is high, the P-type eighth transistor CT8 can be turned off, and the N-type ninth transistor CT9 can be turned on. Correspondingly, the second power supply terminal V2 can be connected to the output terminal EOUT, and the first power supply terminal V1 can be disconnected from the output terminal EOUT. Furthermore, the second power supply terminal V2 can transmit a low-potential second power supply signal to the output terminal EOUT. That is, a low-potential signal can be output through the output terminal EOUT at this time. When the potential of the third node N3 is low, the P-type eighth transistor CT8 can be turned on, and the N-type ninth transistor CT9 can be turned off. Correspondingly, the first power supply terminal V1 can be connected to the output terminal EOUT, and the second power supply terminal V2 can be disconnected from the output terminal EOUT. Furthermore, the first power supply terminal V1 can transmit a high-potential first power supply signal to the output terminal EOUT. That is, a high-potential signal can be output through the output terminal EOUT at this time.

[0159] Based on the preceding description and referring to Figure 2, when the enable signal is at a high potential (vgh), regardless of whether the first driving signal is at a high or low potential, the potential of the third node N3 can be controlled to remain at a low potential. Therefore, it can be seen that a high-potential signal can be continuously output through the output terminal EOUT to control the P-type transistor T08 connected to the light-emitting control terminal EM2 in the pixel circuit to remain in the off state, thereby controlling the shared light-emitting device not to emit light. When the enable signal is at a low potential (vgl), when the first driving signal is at a high potential, the potential of the third node N3 can be controlled to be at a low potential. Therefore, it can be seen that a high-potential signal with the same as the first driving signal can be output through the output terminal EOUT. When the first driving signal is at a low potential, the potential of the third node N3 can be controlled to be at a high potential. Therefore, it can be seen that a low-potential signal with the same as the first driving signal can be output through the output terminal EOUT. That is, at this time, the same signal as the first driving signal can be output through the output terminal EOUT. This can be understood as the first driving signal being further output to the pixel through the output terminal EOUT to control the normal switching of the P-type transistor T08 connected to the light-emitting control terminal EM2 in the pixel circuit, thereby controlling the shared light-emitting device to emit light normally.

[0160] That is, as can be seen from Figure 11, the structure shown in Figure 10 can be used to drive the P-type transistor T08 connected to the light-emitting control terminal EM2 in the pixel circuit to work. When the enable signal potential is high, it can continuously output a high-potential signal to the light-emitting control terminal EM2, so that the P-type transistor T08 connected to the light-emitting control terminal EM2 remains off, thereby controlling the shared light-emitting device not to emit light. When the enable signal potential is low, it can alternately output low-potential and high-potential signals to the light-emitting control terminal EM, so that the P-type transistor T08 connected to the light-emitting control terminal EM2 switches normally, thereby controlling the shared light-emitting device to emit light.

[0161] Similarly, when transistor T08 is replaced with an N-type transistor, the circuit connecting the third control unit 00223 to the second output terminal FOUT1 works as follows: when the enable signal is at a high potential (vgh), the potential of the first node N1 can be controlled to be high, and the potential of the second node N2 can be controlled to be low. When the enable signal is at a low potential (vgl), the potential of the first node N1 can be controlled to be low, and the potential of the second node N2 can be controlled to be high.

[0162] The difference from Figure 10 is that when the potential of the second drive signal output through the second output terminal FOUT1 is low, the N-type sixth transistor CT6 can be turned off, and the P-type seventh transistor CT7 can be turned on. Correspondingly, the first power supply terminal V1 can be connected to the third node N3, and the second node N2 can be disconnected from the third node N3. Furthermore, the first power supply terminal V1 can transmit a high-potential first power signal to the third node N3. When the potential of the second drive signal output through the second output terminal FOUT1 is high, the N-type sixth transistor CT6 can be turned on, and the P-type seventh transistor CT7 can be turned off. Correspondingly, the second node N2 can be connected to the third node N3, and the second power supply terminal V2 can be disconnected from the third node N3. Since the potential of the second node N2 is high when the potential of the enable signal is low (vgl), it can be known that the potential of the third node N3 can also be controlled to be high at this time. Since the second node N2 has a low potential when the enable signal is at a high potential (vgh), it can be concluded that the third node N3 can be controlled to have a low potential at this time. That is, when the enable signal is at a low potential (vgl), the third node N3 can be controlled to remain at a high potential regardless of whether the second drive signal is high or low; when the enable signal is at a high potential (vgh), the third node N3 can be controlled to be high when the second drive signal is low, and vice versa.

[0163] Finally, similarly, when the potential of the third node N3 is high, the P-type eighth transistor CT8 can be turned off, and the N-type ninth transistor CT9 can be turned on. Correspondingly, the second power supply terminal V2 can be connected to the output terminal EOUT, and the first power supply terminal V1 can be disconnected from the output terminal EOUT. Furthermore, the second power supply terminal V2 can transmit a low-potential second power supply signal to the output terminal EOUT. That is, a low-potential signal can be output through the output terminal EOUT at this time. When the potential of the third node N3 is low, the P-type eighth transistor CT8 can be turned on, and the N-type ninth transistor CT9 can be turned off. Correspondingly, the first power supply terminal V1 can be connected to the output terminal EOUT, and the second power supply terminal V2 can be disconnected from the output terminal EOUT. Furthermore, the first power supply terminal V1 can transmit a high-potential first power supply signal to the output terminal EOUT. That is, a high-potential signal can be output through the output terminal EOUT at this time.

[0164] Based on the preceding description, when the enable signal is at a low potential (vgl), regardless of whether the first driving signal is at a high or low potential, the potential of the third node N3 can be controlled to remain at a high potential. Therefore, it can be known that a low potential signal can be continuously output through the output terminal EOUT to control the N-type transistor T08 connected to the light-emitting control terminal EM2 in the pixel circuit to remain in the off state, thereby controlling the shared light-emitting device not to emit light. When the enable signal is at a high potential (vgh), when the second driving signal is at a low potential, the potential of the third node N3 can be controlled to be at a high potential. Therefore, it can be known that a low potential signal identical to the second driving signal can be output through the output terminal EOUT. When the second driving signal is at a high potential, the potential of the third node N3 can be controlled to be at a low potential. Therefore, it can be known that a high potential signal identical to the first driving signal can be output through the output terminal EOUT. That is, at this time, the same signal as the second driving signal can be output through the output terminal EOUT. This can be understood as the second driving signal being further output to the pixel through the output terminal EOUT to control the normal switching of the N-type transistor T08 connected to the light emission control terminal EM2 in the pixel circuit, thereby controlling the shared light emission device to emit light normally.

[0165] Optionally, based on the foregoing description and taking the pixel shown in Figure 2 as an example, the different operating modes of the display panel are explained as follows:

[0166] Referring to Figures 12 and 13, it can be seen that substrate 01 can have a display area AA and a peripheral area BB. Pixel 02 can be located in the display area AA, while all the aforementioned driving circuits can be located in the peripheral area BB, which is uniformly labeled GOA in Figures 12 and 13. The display area AA can be divided into a shared area and a privacy area, and can also be divided into a low-frequency area and a high-frequency area. For example, in Figure 12, the shared area and the low-frequency area are the same region, and the privacy area and the high-frequency area are the same region; in Figure 13, the shared area and the high-frequency area are the same region, and the privacy area and the low-frequency area are the same region.

[0167] Optionally, the regions shown in Figures 12 and 13 can be divided using the i-th row of pixels out of n rows as the boundary line. Of course, the boundary line between the shared area and the privacy area can be the same as the boundary line between the low-frequency area and the high-frequency area, as shown in the figures; or, the boundary line between the shared area and the privacy area can be different from the boundary line between the low-frequency area and the high-frequency area. Here, n is the total number of pixel rows in the display panel, and n is an integer greater than 0; i is an integer greater than 0 and less than n.

[0168] For the shared area, the enable signal provided by the enable terminal EN-EM2 connected to the control unit 002 in the first light-emitting driving circuit 04 can be set to a low potential vgl. This allows the light-emitting driving signal output by the driving unit 001 to be further transmitted to the light-emitting control terminal EM2, thereby enabling the P-type transistor T08 connected to the light-emitting control terminal EM2 to switch normally. When the P-type transistor T08 is turned on, the light-emitting driving current output by the driving transistor T01 can be written into the shared light-emitting device, thereby controlling the shared light-emitting device to emit light. At this time, the light-emitting driving current can also be written into the privacy light-emitting device, and the privacy light-emitting device and the shared light-emitting device emit light simultaneously, allowing the display panel to share the display.

[0169] For the privacy zone, the enable signal provided by the enable terminal EN-EM2 connected to the control unit 002 in the first light-emitting driving circuit 04 can be set to a high potential vgh. This prevents the light-emitting driving signal output by the driving unit 001 from being further transmitted to the light-emitting control terminal EM2. At this time, the control unit 002 can transmit a high potential shutdown signal to the light-emitting control terminal EM2, so that the P-type transistor T08 connected to the light-emitting control terminal EM2 remains off. Consequently, the light-emitting driving current output by the driving transistor T01 cannot be written to the shared light-emitting device, thereby controlling the shared light-emitting device not to emit light. In this case, the light-emitting driving current can only be written to the privacy light-emitting device, and only the privacy light-emitting device emits light, allowing the display panel to display in a privacy-protected manner.

[0170] For the high-frequency region, taking the N-type gate drive circuit 032 as an example, the enable signal provided by the enable terminal EN-N_Gate connected to the control unit 002 in the N-type gate drive circuit 03 can be set to a low potential vgl. This allows the gate drive signal output by the drive unit 001 to be further transmitted to the gate signal terminal N_Gate, thereby enabling the N-type transistor T02 connected to the gate signal terminal N_Gate to switch normally. When the N-type transistor T02 is turned on, the data signal provided by the data terminal Vdata can be written to the gate of the drive transistor T01, thereby causing the drive transistor T01 to generate a light-emitting drive current and light up the light-emitting device for refresh display. Thus, high-frequency display can be achieved.

[0171] For the low-frequency region, taking the N-type gate drive circuit 03 as an example, the enable signal provided by the enable terminal EN-N_Gate connected to the control unit 002 in the N-type gate drive circuit 03 can be set to a high potential vgh. This prevents the gate drive signal output by the drive unit 001 from being further transmitted to the gate signal terminal N_Gate. At this time, the control unit 002 can transmit a low potential turn-off signal to the gate signal terminal N_Gate, so that the N-type transistor T02 connected to the gate signal terminal N_Gate remains off. Consequently, the data signal provided by the data terminal Vdata can no longer be written to the gate of the drive transistor T01, thus stopping the refresh display. In this way, low-frequency display can be achieved.

[0172] It is understandable that the control methods of other P-type gate drive circuits 031 and the first reset drive circuit 05 are similar, and will not be described in detail here. In Figures 12 and 13, the enable terminal EN-P_Gate is the enable terminal EN connected to the control unit 002 in the P-type gate drive circuit 031; the enable terminal EN-P_Reset is the enable terminal EN connected to the control unit 002 in the first reset drive circuit 05.

[0173] When applying the above control method to in-vehicle displays, the enable signal provided by the enable terminal EN can be flexibly configured. This allows the screen closest to the driver to operate in a shared display mode while simultaneously operating in a low-frequency display mode, such as displaying simple content like navigation, achieving information sharing while saving power. Conversely, the screen closest to the passenger can operate in a privacy display mode while simultaneously operating in a high-frequency display mode, such as displaying entertainment videos. This provides a rich entertainment experience for the passenger without interfering with the driver's driving, ensuring driving safety. Of course, the above operating modes are only illustrative.

[0174] In summary, this application provides a display panel. The pixels in this display panel include privacy-protected light-emitting devices and shared light-emitting devices, and both the gate driving circuit and the light-emitting driving circuit include a driving unit and a control unit. Since the control unit can selectively output a driving signal provided by the driving unit or an off signal to the connected pixels based on a received enable signal, the enable signal can be flexibly set to allow flexible control of the shared light-emitting device in privacy mode, flexible control of the shared light-emitting device in shared mode, and control of the display panel to refresh at a higher refresh rate in high refresh rate scenarios and at a lower refresh rate in low refresh rate scenarios. That is, it can balance privacy protection and shared display, as well as low refresh rate and high refresh rate display. This display panel offers a variety of display modes.

[0175] This application also provides a driving method for a display panel, which can be applied to the display panel described in the above embodiments. As shown in FIG14, the method includes:

[0176] Step 1401: In the shared mode or under the control of the first scan instruction, the enable terminal provides an enable signal of the first potential, so that multiple control units in the gate drive circuit respond to the received enable signal and output drive signals to the connected multiple pixels to indicate that the multiple pixels are lit according to the first refresh rate, and multiple control units in the first light-emitting drive circuit respond to the received enable signal and output drive signals to the connected multiple pixels to indicate that the shared light-emitting device in the multiple pixels emits light.

[0177] Step 1402: In privacy mode or under the control of the second scan command, the enable terminal provides an enable signal at the second potential, causing multiple control units in the gate drive circuit to respond to the received enable signal and output a shutdown signal to the connected multiple pixels to indicate that the multiple pixels are lit according to the second refresh rate, and causing multiple control units in the first light-emitting drive circuit to respond to the received enable signal and output a shutdown signal to the connected multiple pixels to indicate that the shared light-emitting device in the multiple pixels does not emit light.

[0178] The first refresh rate controlled by the first scan command is greater than the second refresh rate controlled by the second scan command.

[0179] It is understandable that Figure 14 only schematically illustrates two operating modes. As can be seen from the previous description of the display panel, the display panel can also operate in other modes, and the working principle will not be repeated here.

[0180] It is also understandable that, since the driving method of the display panel has essentially the same technical effect as the display panel described above, for the sake of brevity, the technical effect of the driving method of the display panel will not be described again here.

[0181] This application also provides a display device. As shown in FIG15, the display device includes: a power supply component 10, and a display panel 00 as described in the above embodiments.

[0182] The power supply component 10 is connected to the display panel 00 and is used to supply power to the display panel 00.

[0183] Optionally, the display device described in this application embodiment can be an OLED display device. Furthermore, the display device can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-books, and any other products or components with display functions.

[0184] It is understandable that, since the display device has essentially the same technical effect as the aforementioned display panel, for the sake of brevity, the technical effect of the display device will not be described again here.

[0185] It should be noted that the terminology used in the embodiments section of this application is only for explaining the embodiments of this application and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0186] For example, the terms "first," "second," "third," and similar words used in the patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising" or "including," and similar words mean that the element or object preceding "comprising" or "including" encompasses the element or object listed after "comprising" or "including," and does not exclude other elements or objects. The terms "connected" or "linked," and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "And / or" indicates that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0187] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, the display panel comprising: Substrate; Multiple pixels located on the substrate, each pixel including a driving transistor, a privacy light-emitting device, and a shared light-emitting device; A gate driving circuit located on the substrate is used to control the driving transistor in the pixel to receive data signals; A first light-emitting driving circuit located on the substrate is used to control the light-emitting state of the shared light-emitting device in the pixel; Each of the gate driving circuit and the first light-emitting driving circuit includes: a plurality of cascaded driving units and a plurality of control units, wherein the output terminals of the plurality of driving units are connected to the plurality of control units, the output terminals of the plurality of control units are connected to the plurality of pixels, and each driving unit is also connected to an enable terminal. Furthermore, each of the driving units is used to output a driving signal, and each of the control units is used to output the driving signal or a shutdown signal to the connected pixel in response to the enable signal provided by the enable terminal; the driving signal output by the control unit in the gate driving circuit is used to indicate that the plurality of pixels are lit up at a first refresh rate, and the shutdown signal output by the control unit in the gate driving circuit is used to indicate that the plurality of pixels are lit up at a second refresh rate, wherein the first refresh rate is greater than the second refresh rate; the driving signal output by the control unit in the first light-emitting driving circuit is used to control the shared light-emitting device to emit light, and the shutdown signal output by the control unit in the first light-emitting driving circuit is used to control the shared light-emitting device not to emit light.

2. The display panel according to claim 1, wherein, The gate driving circuit includes a P-type gate driving circuit and an N-type gate driving circuit. The P-type gate driving circuit is connected to the P-type transistors in the plurality of pixels, and the N-type gate driving circuit is connected to the N-type transistors in the plurality of pixels. Both the P-type gate drive circuit and the N-type gate drive circuit include: the cascaded multiple drive units and the multiple control units.

3. The display panel according to claim 2, wherein, The P-type transistor is used to control the first terminal of the driving transistor in the pixel to receive the data signal; the N-type transistor is used to control the gate of the driving transistor in the pixel to receive the data signal. The multiple pixel arrays are arranged; In the P-type gate driving circuit, multiple driving units are connected to multiple rows of pixels one-to-one through multiple control units; In other driving circuits besides the P-type gate driving circuit, multiple driving units are connected to multiple rows of pixels one-to-one through multiple control units, or each driving unit is connected to at least two rows of pixels through a corresponding control unit.

4. The display panel according to claim 3, wherein, In the driving circuits other than the P-type gate driving circuit, each driving unit is connected to two adjacent rows of pixels through a corresponding control unit.

5. The display panel according to any one of claims 1 to 4, wherein, The display panel also includes: A first reset driving circuit located on the substrate is used to control the driving transistor in the pixel to receive a reset signal; A second reset driving circuit located on the substrate is used to control the shared light-emitting device in the pixel to receive a reset signal; A second light-emitting driving circuit located on the substrate is used to control the light-emitting state of the privacy light-emitting device in the pixel; Wherein, at least one of the first reset driving circuit, the second reset driving circuit, and the second light-emitting driving circuit includes: the cascaded plurality of driving units, and the plurality of control units; Furthermore, the drive signals output by the control units in the first reset drive circuit and the second reset drive circuit are used to instruct the plurality of pixels to be lit up according to the first refresh rate, the shutdown signals output by the control units in the first reset drive circuit and the second reset drive circuit are used to instruct the plurality of pixels to be lit up according to the second refresh rate, the drive signals output by the control units in the second light-emitting drive circuit are used to control the privacy light-emitting device to emit light, and the shutdown signals output by the control units in the second light-emitting drive circuit are used to control the privacy light-emitting device not to emit light.

6. The display panel according to claim 5, wherein, The plurality of pixel arrays are arranged in a row, and the display panel includes: one of the gate driving circuits located on each side of the substrate in the row direction; The at least one driving circuit is the first reset driving circuit; the first light-emitting driving circuit and the second reset driving circuit are located on one side of the substrate, and the second light-emitting driving circuit and the first reset driving circuit are located on the other side of the substrate.

7. The display panel according to claim 5 or 6, wherein, On one of the two sides, along the direction close to the pixel, the second reset driving circuit, the first light-emitting driving circuit, the N-type gate driving circuit in the gate driving circuit, and the P-type gate driving circuit in the gate driving circuit are arranged in sequence. On the other side of the two sides, along the direction close to the pixel, the second light-emitting driving circuit, the first reset driving circuit, the N-type gate driving circuit in the gate driving circuit, and the P-type gate driving circuit in the gate driving circuit are arranged in sequence.

8. The display panel according to any one of claims 1 to 7, wherein, Each of the drive units is also connected to a switch terminal and is used to output the drive signal or a turn-off signal to the connected pixel in response to the enable signal, the switch signal provided by the switch terminal, and the drive signal; the control unit includes: A switch subunit is connected to the enable terminal, the switch terminal, and the first node respectively, and is used to control the connection and disconnection between the enable terminal and the first node in response to the switch signal; The control subunit is connected to the first power supply terminal, the second power supply terminal, the first node, the output terminal of the drive unit, and the output terminal of the control unit, respectively. It is used to control the connection and disconnection between each of the first power supply terminals and the second power supply terminal and the output terminal of the control unit in response to the potential of the first node and the drive signal, so as to output the drive signal, and to control the connection and disconnection between one of the first power supply terminals and the second power supply terminal and the output terminal of the control unit, so as to output the shutdown signal.

9. The display panel according to claim 8, wherein, The switching terminal includes one or more switching terminals; the switching subunit includes one or more first transistors; The one or more switching transistors are connected in series between the enable terminal and the first node, and the gates of the one or more switching transistors are connected to the one or more switching terminals in a one-to-one correspondence.

10. The display panel according to claim 9, wherein, The output terminal of the driving unit includes a first output terminal and a second output terminal. The first driving signal output by the driving unit through the first output terminal and the second driving signal output through the second output terminal are inverse signals to each other. The control subunit responds to the first drive signal by controlling the connection and disconnection between the first power supply terminal and the output terminal of the control unit, or responds to the second drive signal by controlling the connection and disconnection between the second power supply terminal and the output terminal of the control unit. The switching terminal includes two sets of switching terminals, each set of switching terminals includes two switching terminals. The two switching terminals in one set of switching terminals are respectively connected to the first output terminal and the second output terminal of the current stage drive unit, and the two switching terminals in the other set of switching terminals are respectively connected to the first output terminal and the second output terminal of the cascaded previous stage drive unit. The switching subunit includes: two sets of first transistors, each set of first transistors including two first transistors of different types; the gates of the two first transistors in one set of first transistors are respectively connected to the first output terminal and the second output terminal of the current stage driving unit; the gates of the two first transistors in the other set of first transistors are respectively connected to the first output terminal and the second output terminal of the previous stage driving unit; the first electrode of the two first transistors in the set of first transistors is connected to the enable terminal; the second electrode of the two first transistors in the set of first transistors is connected to the first electrode of the two first transistors in the other set of first transistors; and the second electrode of the two first transistors in the other set of first transistors is connected to the first node.

11. The display panel according to any one of claims 8 to 10, wherein, The control subunit includes: The first control unit is connected to the first node, the first power supply terminal, the second power supply terminal, and the second node respectively, and is used to control the connection and disconnection between the first power supply terminal and the second node in response to the potential of the first node. The second control unit is connected to the second node, the first power supply terminal, the second power supply terminal and the first node respectively, and is used to control the connection and disconnection between the first power supply terminal and the first node in response to the potential of the second node, and to control the connection and disconnection between the second power supply terminal and the first node. The third control unit is connected to the output terminal of the drive unit, the second node, the first power supply terminal, another power supply terminal of the second power supply terminal, and the third node, respectively, and is used to control the on / off state of the second node and the third node in response to the drive signal, and to control the on / off state of the other power supply terminal and the third node. The fourth control unit is connected to the third node, the first power supply terminal, the second power supply terminal, and the output terminal of the control unit, respectively, and is used to control the connection and disconnection between each of the first power supply terminal and the second power supply terminal and the output terminal of the control unit in response to the potential of the third node, and to control the connection and disconnection between one of the first power supply terminal and the second power supply terminal and the output terminal of the control unit.

12. The display panel according to claim 11, wherein, The first control unit includes: a second transistor and a third transistor of different types; the second control unit includes: a fourth transistor and a fifth transistor of different types; the third control unit includes: a sixth transistor and a seventh transistor of different types; the fourth control unit includes: an eighth transistor and a ninth transistor of different types; The gates of the second transistor and the third transistor are both connected to the first node; the first terminals of the second transistor and the third transistor are respectively connected to the first power supply terminal and the second power supply terminal; and the second terminals of the second transistor and the third transistor are both connected to the second node. The gates of the fourth transistor and the fifth transistor are both connected to the second node. The first terminals of the fourth transistor and the fifth transistor are respectively connected to the first power supply terminal and the second power supply terminal. The second terminals of the fourth transistor and the fifth transistor are both connected to the first node. The gates of the sixth transistor and the seventh transistor are both connected to the output terminal of the driving unit. The first terminals of the sixth transistor and the seventh transistor are respectively connected to the second node and the other power terminal of the first power terminal and the second power terminal. The second terminals of the sixth transistor and the seventh transistor are both connected to the third node. The gates of the eighth transistor and the ninth transistor are both connected to the third node. The first terminals of the eighth transistor and the ninth transistor are respectively connected to the first power supply terminal and the second power supply terminal. The second terminals of the eighth transistor and the ninth transistor are both connected to the output terminal of the control unit.

13. The display panel according to any one of claims 8 to 12, wherein, The control subunit further includes: a first storage capacitor connected between the first node and the second power supply terminal; and / or, a second storage capacitor connected between the third node and the second power supply terminal.

14. A driving method for a display panel, applied to a display panel as described in any one of claims 1 to 13; the method comprising: In the shared mode or under the control of the first scan instruction, the enable terminal provides an enable signal at the first potential, causing multiple control units in the gate drive circuit to respond to the received enable signal and output drive signals to the connected multiple pixels to indicate that the multiple pixels are lit according to the first refresh rate, and causing multiple control units in the first light-emitting drive circuit to respond to the received enable signal and output drive signals to the connected multiple pixels to indicate that the shared light-emitting device in the multiple pixels emits light. In privacy mode or under the control of the second scan command, the enable terminal provides an enable signal at the second potential, causing multiple control units in the gate drive circuit to respond to the received enable signal and output a shutdown signal to the connected multiple pixels to indicate that the multiple pixels are lit according to the second refresh rate, and causing multiple control units in the first light-emitting drive circuit to respond to the received enable signal and output a shutdown signal to the connected multiple pixels to indicate that the shared light-emitting device in the multiple pixels does not emit light. Wherein, the first refresh rate controlled by the first scan command is greater than the second refresh rate controlled by the second scan command.

15. A display device, the display device comprising: A power supply component, and a display panel as described in any one of claims 1 to 13; The power supply component is connected to the display panel and is used to supply power to the display panel.

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