Display substrate, display panel and display device

Abstract

Provided are a display substrate, a display panel and a display device. The display substrate comprises: a base substrate, and a drive circuit layer and a first electrode layer that are arranged sequentially away from the base substrate. The first electrode layer comprises a plurality of first electrodes. The orthographic projections of at least some first electrodes on the base substrate have a first projection shape. The first projection shape comprises a straight edge portion and a curved edge portion. The straight edge portion and the curved edge portion comprise a shared second vertex and sixth vertex, and a first common line segment. The straight edge portion further comprises a fourth vertex that is the farthest away from the curved edge portion. The curved edge portion comprises: a first vertex that is the farthest away from the straight edge portion, a first side edge located between the first vertex and the second vertex, and a second side edge located between the first vertex and the sixth vertex. The lines connecting the first vertex, the second vertex, the fourth vertex and the sixth vertex form a virtual quadrilateral, and at least one of the first side edge and the second side edge has at least three intersection points with the virtual quadrilateral.

Description

Display substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically to a display substrate, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are microdisplays that have emerged in recent years. Using mature silicon-based semiconductor processes, high-PPI (pixel density) and high-refresh-rate OLED displays can be fabricated for applications in VR (Virtual Reality) and AR (Augmented Reality). The display panels in these technologies consist of multiple pixel units to achieve high-resolution display effects. However, limitations in high resolution and wiring spacing requirements result in a relatively low pixel aperture ratio. How to maximize the pixel aperture ratio while meeting high resolution and wiring spacing requirements, and ensuring the display substrate's display performance and lifespan, is one of the important research topics for researchers.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In one aspect of this disclosure, a display substrate is provided, comprising:

[0005] Substrate;

[0006] A driving circuit layer is located on one side of the substrate.

[0007] A first electrode layer is located on the side of the driving circuit layer away from the substrate, and the first electrode layer includes a plurality of first electrodes.

[0008] At least a portion of the first electrode has a first projection shape when projected onto the substrate. The first projection shape includes a straight edge and a curved edge, wherein the straight edge and the curved edge include a common second vertex and a sixth vertex, and a first common line segment connecting the second vertex and the sixth vertex.

[0009] The straight edge portion further includes: the fourth vertex furthest from the curved edge portion and a plurality of straight edge sidewalls that sequentially connect the second vertex, the fourth vertex and the sixth vertex, the plurality of straight edge sidewalls and the first common line segment enclose and form a first region, and the straight edge portion is located in the first region;

[0010] The curved edge portion includes: a first vertex furthest from the straight edge portion; a first side edge located between the first vertex and the second vertex; and a second side edge located between the first vertex and the sixth vertex. The first side edge, the second side edge, and the first shared line segment enclose and form a second region, and the curved edge portion is located within the second region.

[0011] The line connecting the first vertex, the second vertex, the fourth vertex, and the sixth vertex forms a virtual quadrilateral, and at least one of the first side and the second side has at least three intersection points with the virtual quadrilateral.

[0012] According to some exemplary embodiments, the straight edge further includes a third vertex and a fifth vertex;

[0013] The plurality of straight-edge sidewalls include: a first straight-edge sidewall connecting the second vertex and the fourth vertex, with the third vertex located on the first straight-edge sidewall; and a second straight-edge sidewall connecting the sixth vertex and the fourth vertex, with the fifth vertex located on the second straight-edge sidewall; and

[0014] The lines connecting the first vertex, the second vertex, the third vertex, the fourth vertex, the fifth vertex, and the sixth vertex form a virtual hexagon, and at least one of the first side and the second side has at least three intersection points with the virtual hexagon.

[0015] According to some exemplary embodiments, the display substrate further includes an insulating layer located between the driving circuit layer and the first electrode layer, the insulating layer including a plurality of first vias configured to connect the first electrode and the driving circuit layer, wherein the orthographic projection of the first vias on the substrate falls within the orthographic projection of the curved portion on the substrate.

[0016] According to some exemplary embodiments, the plurality of first electrodes are arranged in an array in a first direction and a second direction, wherein the first direction and the second direction intersect.

[0017] The first electrode layer includes a plurality of electrode rows extending along the first direction, and the electrode rows include a plurality of first electrodes arranged at intervals.

[0018] The plurality of electrode rows include an i-th electrode row and an (i+1)-th electrode row that are adjacent in the second direction, wherein the i-th electrode row and the (i+1)-th electrode row are at least partially aligned in the second direction, and i is a positive integer greater than or equal to 1.

[0019] Wherein, the curved edges of the plurality of first electrodes located in the i-th electrode row face the i+1-th electrode row; and the curved edges of the plurality of first electrodes located in the i+1-th electrode row face the i-th electrode row.

[0020] According to some exemplary embodiments, the plurality of electrode rows further includes an i+2 electrode row adjacent to the i+1 electrode row in a second direction, wherein the straight edges of the plurality of first electrodes located in the i+1 electrode row and the straight edges of the plurality of first electrodes located in the i+2 electrode row are disposed opposite to each other.

[0021] According to some exemplary embodiments, in the same first electrode, the area of ​​the straight edge portion is greater than the area of ​​the curved edge portion.

[0022] According to some exemplary embodiments, the first side includes a first curved edge connected to the first vertex, at least a portion of the first curved edge being located outside the virtual hexagon; and / or,

[0023] The second side includes a second curved edge connected to the first vertex, and at least a portion of the second curved edge lies outside the virtual hexagon.

[0024] According to some exemplary embodiments, the first side further includes: a third curved edge connected to the second vertex; and a connecting line connecting the first curved edge and the third curved edge, wherein the third curved edge is located inside the virtual hexagon, and at least a portion of the connecting line is located outside the virtual hexagon; and

[0025] The curved edge portion includes a first protrusion and a second protrusion, the first protrusion being located between the first curved edge and the second curved edge; the second protrusion being located between the connecting line and at least one side of the virtual hexagon, and the second protrusion being located outside the virtual hexagon.

[0026] According to some exemplary embodiments, the first protrusion of the first electrode faces the gap between two first electrodes adjacent to the first electrode; and

[0027] The display substrate further includes a first gap region between the curved edges of two adjacent first electrodes in an adjacent electrode row, and the second protrusions of the two adjacent first electrodes in the adjacent electrode row are disposed opposite each other in the same first gap region.

[0028] According to some exemplary embodiments, the first protrusion has a discontinuous curvature at the first vertex position; and / or,

[0029] The second protrusion includes a seventh vertex furthest from the virtual hexagon, and the second protrusion has a continuous curvature at the seventh vertex position.

[0030] According to some exemplary embodiments, in the same first electrode, the area of ​​the first protrusion is larger than the area of ​​the second protrusion.

[0031] According to some exemplary embodiments, the orthographic projection of the first via on the substrate is located on the side of the curved portion that is close to the first protrusion and away from the straight portion.

[0032] According to some exemplary embodiments, the curved edge portion includes at least two recesses located on one side of the curved edge portion near the straight edge portion.

[0033] According to some exemplary embodiments, the first protrusion of the first electrode is located between two recesses of two adjacent first electrodes.

[0034] According to some exemplary embodiments, in a first planar direction, the first via is spaced from the first vertex by a first spacing distance, the first spacing distance being greater than or equal to 0.15 micrometers, and the first planar direction is perpendicular to the light emission direction of the display substrate; and

[0035] The ratio of the first interval distance to the interval distance between the first vertex and the fourth vertex is less than or equal to 1 / 4.

[0036] According to some exemplary embodiments, the display substrate further includes a pixel defining layer located on the side of the first electrode layer away from the substrate, the pixel defining layer defining a plurality of pixel openings.

[0037] The pixel defining layer includes: a first pixel defining sub-layer located on the side of the first electrode layer away from the substrate; a second pixel defining sub-layer located on the side of the first pixel defining sub-layer away from the substrate; and a third pixel defining sub-layer located on the side of the second pixel defining sub-layer away from the substrate, wherein the second pixel defining sub-layer is recessed relative to the first pixel defining sub-layer and the third pixel defining sub-layer in a direction away from the pixel opening; and

[0038] In the same sub-pixel, in the first planar direction, the first via and the pixel define a second spacing distance between the side of the second sub-layer near the pixel opening, the second spacing distance being greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer.

[0039] According to some exemplary embodiments, in the same sub-pixel, in the second planar direction, the pixel opening is separated from the side of the first electrode by a third spacing distance, the third spacing distance being greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer, and the second planar direction is perpendicular to the light emission direction of the display substrate.

[0040] According to some exemplary embodiments, in the third plane direction, two adjacent first electrodes are spaced by a fourth spacing distance, the fourth spacing distance being greater than or equal to 0.25 micrometers and less than or equal to 1 micrometer, and the third plane direction is perpendicular to the light emission direction of the display substrate.

[0041] According to some exemplary embodiments, the shape of the first protrusion includes at least one of a rectangle, at least a portion of a circle, and at least a portion of an ellipse.

[0042] According to some exemplary embodiments, the pixel opening includes a pixel opening center, and the pixel opening is symmetrical about the pixel opening center;

[0043] The fourth vertex and the first vertex are located on opposite sides of the center of the pixel opening. The first vertex is separated from the center of the pixel opening by a fifth interval distance, and the fourth vertex is separated from the center of the pixel opening by a sixth interval distance. The difference between the fifth interval distance and the sixth interval distance is greater than the radius of the first via.

[0044] In another aspect of this disclosure, a display substrate is provided, comprising:

[0045] Substrate;

[0046] A driving circuit layer is located on one side of the substrate.

[0047] An insulating layer is located on the side of the driving circuit layer away from the substrate, and the insulating layer includes a plurality of first vias;

[0048] A first electrode layer is located on the side of the insulating layer away from the substrate. The first electrode layer includes a plurality of first electrodes. The first electrodes are electrically connected to the driving circuit layer through the first via. At least a portion of the first electrodes have a first projection shape on the substrate. The first projection shape includes a first vertex, a second vertex, a third vertex, a fourth vertex, a fifth vertex, and a sixth vertex connected in sequence.

[0049] The display substrate further includes a pixel defining layer located on the side of the first electrode layer away from the substrate. The pixel defining layer defines a plurality of pixel openings, each pixel opening including a pixel opening center, and the pixel openings are symmetrical about the pixel opening center.

[0050] Wherein, the first vertex and the fourth vertex are located on opposite sides of the center of the pixel opening; and

[0051] The first vertex is spaced a fifth interval distance from the center of the pixel opening, and the fourth vertex is spaced a sixth interval distance from the center of the pixel opening. The difference between the fifth interval distance and the sixth interval distance is greater than the radius of the first via.

[0052] In another aspect of this disclosure, a display panel is provided, including a display substrate as described in any of the preceding claims.

[0053] In another aspect of this disclosure, a display device is provided, comprising a display substrate as described in any of the preceding claims or a display panel as described above. Attached Figure Description

[0054] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0055] Figure 1 is a plan view of a display substrate according to an embodiment of the present disclosure;

[0056] Figure 2 is a schematic diagram of the cross section taken along line AA' in Figure 1;

[0057] Figure 3 is a schematic diagram of the structure of a light-emitting device according to an embodiment of the present disclosure;

[0058] Figure 4 is a partial plan view of a display substrate according to an embodiment of the present disclosure;

[0059] Figure 5 is a schematic diagram of the cross section taken along line BB' in Figure 4;

[0060] Figure 6 is a partial cross-sectional schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0061] Figure 7 is a partial plan view of a display substrate according to an embodiment of the present disclosure, showing a first electrode, a first via, and a pixel opening;

[0062] Figure 8A is an enlarged schematic diagram of a first electrode and a first via according to some embodiments of the present disclosure; Figure 8B is an enlarged schematic diagram of a first electrode and a first via according to other embodiments of the present disclosure;

[0063] Figures 9A and 9B are schematic diagrams comparing pixel aperture sizes of display substrates with different first electrode shapes according to embodiments of the present disclosure.

[0064] Figure 10 is a partial planar schematic diagram of a display substrate according to an embodiment of the present disclosure, showing a first electrode, a first via, and a pixel opening;

[0065] Figures 11A and 11B are schematic diagrams comparing pixel aperture sizes of display substrates with different first electrode shapes according to embodiments of the present disclosure.

[0066] Figure 12 is a partial plan view of the first electrode of a display substrate according to an embodiment of the present disclosure;

[0067] Figure 13 is a partially enlarged schematic diagram of region N3 in Figure 12;

[0068] Figure 14A is a plan view of a first electrode according to some embodiments of the present disclosure, and Figure 14B is an enlarged view of a single first electrode in Figure 14A.

[0069] Figure 15A is a plan view of a first electrode according to some other embodiments of the present disclosure, and Figure 15B is an enlarged view of a single first electrode in Figure 15A.

[0070] Figure 16A is a plan view of a first electrode according to some embodiments of the present disclosure, and Figure 16B is an enlarged view of a single first electrode in Figure 16A.

[0071] Figure 17 is a schematic structural diagram of a display panel provided according to some embodiments of the present disclosure; and

[0072] Figure 18 is a schematic diagram of the structure of a display device provided according to some embodiments of the present disclosure.

[0073] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of the present invention may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0075] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0076] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0077] In this document, unless otherwise specified, directional terms such as "up," "down," "left," "right," "inner," and "outer" are used to indicate orientation or positional relationships based on the accompanying drawings, and are used only for the convenience of describing this disclosure, and are not intended to indicate or imply that the device, element, or component referred to must have a specific orientation, or be constructed or operated in a specific orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationships they represent may also change accordingly. Therefore, these directional terms should not be construed as limitations on this disclosure.

[0078] In this document, the directional terms "first direction" and "second direction" are used to describe different orientations of the display substrate or display panel, such as the row and column directions of pixel units. It should be understood that such representations are merely exemplary descriptions and not limitations of this disclosure.

[0079] In this document, unless otherwise stated, the term "electrical connection" can mean that two components or elements are directly electrically connected, for example, component or element A is in direct contact with component or element B, and an electrical signal can be transmitted between them; it can also mean that two components or elements are electrically connected through a conductive medium, such as a conductive wire, for example, component or element A is electrically connected to component or element B through a conductive wire to transmit an electrical signal between the two components or elements; it can also mean that two components or elements are electrically connected through at least one electronic component, for example, component or element A is electrically connected to component or element B through at least one thin-film transistor to transmit an electrical signal between the two components or elements.

[0080] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0081] The technical terms used in this disclosure are briefly described below to help those interested in the subject matter better understand this solution.

[0082] Gamma adjustment: Gamma adjustment involves modifying parameters such as brightness and color of the display panel to achieve optimal display performance. Gamma value is a parameter that measures the relationship between a monitor's brightness and its input voltage; it significantly impacts color reproduction and contrast. Due to variations in the manufacturing process, environmental factors, and monitor aging, the display panel's gamma value may deviate from the ideal value, leading to issues such as color distortion and insufficient contrast. Therefore, performing gamma adjustment is a crucial step in optimizing the display panel's performance.

[0083] Distortion: Due to the significant height difference at the partition structure, the vapor-deposited material film in the OLED device may experience rapid changes in film morphology at the partition structure, resulting in distortion. It should be understood that the probability of leakage current is higher at distorted locations.

[0084] OLED display panels are widely used in various display products due to their advantages such as self-emissiveness, low power consumption, high color gamut, wide viewing angle, and short response time. In particular, silicon-based organic light-emitting microdisplay panels (Micro-OLED display panels), which have the characteristics of small pixel size and high pixel density, have wide applications in military applications, display products for augmented reality (AR) and virtual reality (VR) technologies, and autonomous driving.

[0085] Compared to conventional displays, silicon-based microdisplays boast ultra-high resolutions, typically between 3000 and 5000 PPI (pixels per inch). This dictates the precision of their critical dimension (CD), with the smallest controllable CD around 0.1 micrometers. Traditional fine metal masks (FMMs) can achieve a maximum PPI of around 800, meaning it's difficult to use the side-by-side (SBS) method for OLED deposition in silicon-based OLEDs. Consequently, silicon-based OLED microdisplays generally employ white light-emitting devices. Current silicon-based Micro-OLED displays mostly utilize a structure of white light-emitting devices plus a color film (CF) to achieve full-color display.

[0086] Some silicon-based OLED microdisplays use a single light-emitting layer to achieve white light emission. Their light-emitting layer architecture uses a combination of different light-emitting materials to achieve white light. Their module brightness is generally between 80-600 nits, which is considered a medium-low brightness display. If this single-layer structure is used to achieve high brightness (greater than 1000 nits), power consumption and lifespan will be sacrificed.

[0087] To improve the performance, brightness, and lifespan of silicon-based OLED microdisplays, some silicon-based OLED microdisplays employ stacked OLED devices comprising two or more light-emitting layers. Stacked OLED devices utilize a charge-generating layer to connect two upper and lower light-emitting units in series, achieving a superimposed light emission effect on the device, which can improve current efficiency, output brightness, and display product lifespan. However, in addition to connecting two upper and lower light-emitting units in series, the charge-generating layer in stacked OLEDs also has strong lateral transmission capabilities, easily causing color crosstalk between pixels. Therefore, other methods are needed to separate the charge-generating layer and OLED pixels. For example, separation methods may include, but are not limited to, high separator pillars, inter-pixel vias, and undercut structures. However, these separations can cause punctures in the cathode morphology, forming leakage paths, resulting in a decrease in the luminous efficiency of light-emitting devices (e.g., blue light-emitting devices), and a loss in the overall device luminous efficiency.

[0088] In some embodiments, full-color display is achieved by using three-color color filter layers in conjunction with a white OLED light-emitting device. However, the transmittance of the current color filter layers is only about 20%, especially the blue filter layer, which often has a transmittance of less than 20%. Therefore, when fabricating OLED devices, it is necessary to prioritize improving the efficiency of blue light. Furthermore, during the subsequent electrical tuning after module fabrication, it is necessary to perform Gamma tuning on the RGB pixels, giving the RGB pixels different current densities to ensure that the final synthesized white light color point is around (0.31, 0.33).

[0089] Silicon-based display substrates are limited by the ultra-high resolution of products, resulting in very small pixel sizes, with individual pixel sizes ranging from approximately 2.0µm to 8µm. Therefore, it is difficult to use the FMM (Front-Mounted Mirror) side-by-side monochrome device deposition method for silicon-based OLEDs. Furthermore, the structure of a white light-emitting device with a color filter layer (CF) deposited across the entire surface suffers from significant brightness loss due to the CF adhesive's transmittance of only about 20%, creating a bottleneck in the product's brightness limit. This disclosure provides a display substrate. The display substrate includes: a substrate; a driving circuit layer located on one side of the substrate; and a first electrode layer located on the side of the driving circuit layer away from the substrate. The first electrode layer includes a plurality of first electrodes, at least some of which have a first projection shape on the substrate. The first projection shape includes a straight edge and a curved edge, the straight edge and the curved edge including a shared second vertex and a sixth vertex, and a first common line segment connecting the second vertex and the sixth vertex. The straight edge also includes a fourth vertex furthest from the curved edge and a plurality of straight lines sequentially connecting the second vertex, the fourth vertex, and the sixth vertex. A first region is formed by a plurality of straight side edges and a first shared line segment, and the straight side edges are located in the first region; the curved side edge includes: a first vertex furthest from the straight side edge; a first side edge located between the first vertex and the second vertex; and a second side edge located between the first vertex and the sixth vertex. The first side edge, the second side edge, and the first shared line segment form a second region, and the curved side edge is located in the second region. The line connecting the first vertex, the second vertex, the fourth vertex, and the sixth vertex forms a virtual quadrilateral, and at least one of the first side edge and the second side edge has at least three intersection points with the virtual quadrilateral.

[0090] By designing the first electrode in an irregular shape, a good electrical connection between the first electrode and the underlying driving circuit layer can be ensured while increasing the pixel aperture ratio. This design has two advantages: firstly, it improves the brightness of the display panel, allowing for greater adjustment range in the gamma tuning of the display substrate; secondly, it allows for driving with a lower voltage at the same brightness, thus extending the lifespan of the display substrate.

[0091] Figure 1 is a plan view of a display substrate according to an embodiment of the present disclosure.

[0092] Exemplary examples, in some embodiments of this disclosure, referring to FIG1, show substrate 100 includes substrate 1. Substrate 1 includes a display area AA and a non-display area NA. Show substrate 100 includes a plurality of sub-pixels SP located in display area AA, the plurality of sub-pixels SP being arranged in an array along a first direction X and a second direction Y.

[0093] For example, the display substrate 100 further includes a plurality of first electrodes 20, such as the first electrodes 20 being the anodes of light-emitting devices in the sub-pixels SP. The plurality of first electrodes 20 are arranged in an array along a first direction X and a second direction Y. The display substrate 100 also includes a pixel defining layer PDL located on the side of the first electrodes 20 away from the substrate 1, the pixel defining layer PDL having a plurality of pixel openings VH. The plurality of pixel openings VH define the light-emitting regions of the plurality of sub-pixels SP.

[0094] For example, the orthographic projection of the pixel defining layer PDL on the substrate at least partially overlaps with the orthographic projection of the plurality of first electrodes 20 on the substrate, such that the first electrodes 20 of adjacent sub-pixels SP are disconnected from each other. The orthographic projections of the plurality of pixel openings VH on the substrate fall within the orthographic projections of the plurality of first electrodes 20 on the substrate, defining the light-emitting area of ​​the sub-pixel SP.

[0095] For example, a plurality of first electrodes 20 correspond one-to-one with a plurality of sub-pixel SP positions, and the area of ​​the first electrode 20 is larger than the light-emitting area of ​​the sub-pixel.

[0096] Figure 2 is a schematic diagram of the cross section taken along line AA' in Figure 1.

[0097] Exemplary examples, in some embodiments of this disclosure, referring to Figures 1 and 2, show that the substrate 100 includes a substrate 1 and a first electrode layer 2 disposed on the substrate 1. The first electrode layer 2 may include a plurality of first electrodes 20 disposed at intervals.

[0098] The display substrate 100 may further include: a pixel defining layer PDL located on the side of the first electrode layer 2 away from the substrate, the pixel defining layer defining a plurality of pixel openings VH; a light-emitting functional layer 3 located on the side of the pixel defining layer PDL away from the substrate 1; a second electrode layer 4 located on the side of the light-emitting functional layer 3 away from the substrate 1; and an encapsulation layer 5 located on the side of the second electrode layer 4 away from the substrate 1. For example, the second electrode layer 4 may be the cathode of a light-emitting device.

[0099] In some embodiments, the encapsulation layer 5 may include a plurality of sub-encapsulation layers stacked sequentially away from the substrate 1. For example, the encapsulation layer 5 may include a first sub-encapsulation layer 51, a second sub-encapsulation layer 52, and a third sub-encapsulation layer 53. For example, the material of the first sub-encapsulation layer 51 may include an inorganic material, the material of the second sub-encapsulation layer 52 may include an organic material, and the material of the third sub-encapsulation layer 53 may include an inorganic material. By alternating between inorganic and organic materials, the ability of the encapsulation layer 5 to isolate water and oxygen can be improved, thereby increasing the lifespan of the display substrate.

[0100] In some embodiments, the substrate 1 may be a silicon substrate. The light-emitting device in the display substrate 100 may be an OLED light-emitting device. To improve the efficiency, brightness, and lifespan of the light-emitting device, the OLED light-emitting device may include an OLED device employing a stacked design.

[0101] For example, a stacked OLED device structure includes two or more light-emitting layers, which are connected in series by charge-generating layers (CGLs) to improve the luminous efficiency of the device. For instance, in a silicon-based OLED device, a yellow light-emitting layer and a blue light-emitting layer can be connected in series, or a red-green light-emitting layer and a blue light-emitting layer can be connected in series to form white light.

[0102] For example, continuing to refer to FIG2, the display substrate may further include: a planarization layer 6 located on the side of the encapsulation layer 5 away from the substrate; and a color filter layer 7 located on the side of the planarization layer 6 away from the substrate.

[0103] For example, the color filter layer 7 may include multiple color filter structures of different colors. For instance, the color filter layer 7 may include a first color filter structure 71, a second color filter structure 72, and a third color filter structure 73. For example, the first color filter structure 71 may include a red filter film, the second color filter structure 72 may include a green filter film, and the third color filter structure 73 may include a blue filter film. By combining a white OLED light-emitting device with the color filter layer 7, three colors of light can be formed, thereby achieving color display.

[0104] However, in some cases, the low transmittance of the color filter layer 7 results in a significant loss of light output brightness in the display substrate.

[0105] In some embodiments, continuing to refer to FIG2, the display substrate further includes: an optical adhesive layer 8 located on the side of the color filter layer 7 away from the substrate; and a lens layer 9 located on the side of the optical adhesive layer 8 away from the substrate. Exemplarily, the lens layer 9 includes a plurality of lens structures 91, for example, the shape of the lens structures 91 includes a hemispherical shape. By providing the lens layer, light emitted by the light-emitting device can be extracted (e.g., reducing total internal reflection at the film interface), which is beneficial to improving the luminous efficiency and brightness of the display substrate.

[0106] Figure 3 is a schematic diagram of the structure of a light-emitting device according to an embodiment of the present disclosure.

[0107] In some embodiments, to improve the brightness of the light-emitting device, the display substrate may employ a stacked structure design. Referring to FIG3, the light-emitting functional layer 3 may include a plurality of film layers stacked sequentially away from the substrate. For example, the light-emitting functional layer 3 may include: a first light-emitting functional layer 31, for example, the first light-emitting functional layer 31 is a hole injection layer; a second light-emitting functional layer 32, for example, the second light-emitting functional layer 32 is a hole transport layer; a third light-emitting functional layer 33, for example, the third light-emitting functional layer 33 is a red organic light-emitting layer; a fourth light-emitting functional layer 34, for example, the fourth light-emitting functional layer 34 is a green organic light-emitting layer; a fifth light-emitting functional layer 35, for example, the fifth light-emitting functional layer 35 is a CGL electron transport layer; a sixth light-emitting functional layer 36, for example, the sixth light-emitting functional layer 36 is a charge generation layer CGL; a seventh light-emitting functional layer 37, for example, the seventh light-emitting functional layer 37 is a hole injection layer; an eighth light-emitting functional layer 38, for example, the eighth light-emitting functional layer 38 is a hole transport layer; a ninth light-emitting functional layer 39, for example, the ninth light-emitting functional layer 39 is a blue organic light-emitting layer; a tenth light-emitting functional layer 310, for example, the tenth light-emitting functional layer 310 is an electron transport layer; and an eleventh light-emitting functional layer 311, for example, the eleventh light-emitting functional layer 311 is an electron injection layer.

[0108] In some embodiments, the charge generation layer CGL may include an N-type charge generation layer and a P-type charge generation layer.

[0109] It should be noted that although some embodiments of this disclosure schematically show that the light-emitting functional layer 3 in the stacked OLED device includes the first light-emitting functional layer 31 to the eleventh light-emitting functional layer 311, in other embodiments of this disclosure, the light-emitting functional layer may have some layers reduced or some layers increased.

[0110] It should also be noted that although some embodiments of this disclosure schematically illustrate a dual-layer OLED light-emitting device including a charge-generating layer and two light-emitting layers located on both sides of the charge-generating layer, in other embodiments of this disclosure, the light-emitting functional layer may also include a greater number of charge-generating layers and a greater number of light-emitting layers located between the charge-generating layers or between the charge-generating layers and the upper and lower electrodes (e.g., anode and cathode), thereby forming a multi-layer stacked OLED light-emitting device. For example, the stacked OLED light-emitting device may include a triple-layer, quadruple-layer, or more stacked OLED light-emitting device.

[0111] In stacked OLED devices, due to the high conductivity of the charge generation layer CGL, when the charge generation layers between adjacent pixels are not separated, lateral crosstalk between pixels is likely to occur, which may also cause leakage loss and affect the brightness of the light-emitting device.

[0112] In some embodiments, in order to reduce or eliminate lateral crosstalk in the charge generation layer CGL, the pixel confinement layer adopts an undercut structure design, thereby improving the isolation effect of the pixel confinement layer.

[0113] Figure 4 is a partial plan view of a display substrate according to an embodiment of the present disclosure, and Figure 5 is a cross-sectional view taken along line BB' in Figure 4.

[0114] For example, referring to Figures 4 and 5, the display substrate may further include a driving circuit layer 10 located between the substrate 1 and the first electrode layer 2, the driving circuit layer 10 including a plurality of pixel driving circuits 101.

[0115] Exemplarily, the display substrate may further include an insulating layer 11 located between the driving circuit layer 10 and the first electrode layer 2. The pixel driving circuit 101 can be connected to the first electrode 20 through a conductive connection portion 102 penetrating the insulating layer 11, thereby enabling driving control of the light-emitting device. Exemplarily, the conductive connection portion 102 may include tungsten metal.

[0116] For example, the insulating layer 11 includes a plurality of first vias VO1, and at least a portion of the conductive connection portion 102 is located in the first vias VO1.

[0117] In some embodiments, referring to FIG5, the side 201 of the first electrode 20 away from the pixel opening VH protrudes a first spacing distance D1 relative to the first via VO1 in a direction away from the pixel opening VH. For example, the first spacing distance D1 is greater than or equal to 0.15 micrometers. With this design, it can be ensured that the conductive connection portion 102 and the first electrode 20 have sufficient contact area, which is beneficial to improving the electrical connection effect between the conductive connection portion 102 and the first electrode 20.

[0118] In some embodiments, the side PDL11 of the pixel definition layer PDL near the pixel opening protrudes a certain distance relative to the side 201 of the first electrode 20 away from the pixel opening in the direction of approaching the pixel opening VH, thereby ensuring that the edge region of the first electrode is covered by the pixel definition layer PDL, so that the pixel definition layer PDL can define multiple pixel openings VH.

[0119] In some embodiments, continuing to refer to FIG5, the pixel defining layer PDL may include multiple film layers. For example, the pixel defining layer PDL may include: a pixel defining first sub-layer PDL1 located on the side of the first electrode layer 2 away from the substrate; a pixel defining second sub-layer PDL2 located on the side of the pixel defining first sub-layer PDL1 away from the substrate; and a pixel defining third sub-layer PDL3 located on the side of the pixel defining second sub-layer PDL2 away from the substrate. The multiple film layers in the pixel defining layer PDL can be used to form an undercut structure UDC. For example, the pixel defining second sub-layer PDL2 is recessed by a fifth recess distance D5 relative to the pixel defining first sub-layer PDL1 and the pixel defining third sub-layer PDL3 in a direction away from the pixel opening VH. For example, the fifth recess distance D5 is in the range of 0.05 micrometers to 0.06 micrometers.

[0120] By designing an undercut structure UDC in the pixel limiting layer (PDL), the charge generation layer (CGL) between adjacent pixels can be disconnected at the undercut structure UDC, thereby reducing lateral crosstalk between pixels and improving the display effect of the display substrate.

[0121] In some embodiments, multiple undercut structures can be provided in the region near the pixel opening VH in the pixel limiting layer PDL to further improve the isolation effect of the pixel limiting layer, which is beneficial to reduce the leakage probability of the display substrate and improve the display effect of the display substrate.

[0122] The inventors discovered through research that during the process of forming the first via VO1 (e.g., a tungsten via), the tungsten via is uneven relative to the horizontal plane. When the first via VO1 is too close to the undercut structure UDC, the unevenness of the film layer near the first via VO1 may cause instability or even collapse of the nearby undercut structure, which can easily lead to lateral leakage and cause poor display.

[0123] Figure 6 is a partial cross-sectional schematic diagram of a display substrate according to an embodiment of the present disclosure.

[0124] For example, in some embodiments, referring to FIG6, when the film layer step difference near the pixel opening VH region is large, the upper part of the film layer may be distorted, for example, the second electrode layer 4 may have a puncture 41. For example, the distance d5 between the puncture 41 in the second electrode layer 4 and the lower first electrode layer 20 is smaller than the distance d2 between the main body portion 42 in the second electrode layer and the lower first electrode layer 20, for example, d5 / d2 is about 0.7. This may cause the lateral resistance to be less than the forward resistance, and the current to flow more easily from the side to the second electrode layer.

[0125] For example, d2 is in the range of 1000 nm to 3000 nm, the vertical distance d3 between the puncture 41 and the first electrode layer 20 is about 400 nm, the horizontal spacing distance d4 between the puncture 41 and the side of the second electrode 20 away from the pixel opening is about 550 nm, and d5 is about 680 nm.

[0126] In some embodiments, since the distance between the first via and the pixel opening is too close, the unevenness of the first via may further increase the step difference of the film layer in the region where the undercut structure adjacent to the pixel opening is located, causing distortion of part of the film layer (e.g., cathode) in that region, thereby resulting in lateral leakage and reduced luminous efficiency of the light-emitting device.

[0127] In some display substrates employing a dual-layer OLED structure, referring to Figures 3 and 6, the blue light-emitting layer is located above the red and green light-emitting layers. For example, the third light-emitting functional layer 33 is a red organic light-emitting layer, the fourth light-emitting functional layer 34 is a green organic light-emitting layer, and the ninth light-emitting functional layer 39 is a blue organic light-emitting layer. This makes the blue light-emitting layer more susceptible to the puncture effect in the second electrode layer than the red light-emitting layer, forming a leakage path. This reduces the blue light-emitting efficiency, further widening the light emission difference between the red, green, and blue pixels, and further narrowing the maximum brightness range that can be adjusted by Gamma.

[0128] For example, in a high-resolution display substrate, due to the limitation of wiring space, the distance between the undercut structure UDC and the first via VO1 is relatively close. The conductive connection portion 102 located at the first via VO1 is prone to causing the upper film layer to be uneven in the nearby area, which may lead to the damage or even collapse of the upper undercut structure, resulting in the inability to achieve the pixel isolation effect.

[0129] In order to balance the electrical connection effect between the conductive connection portion 102 and the first electrode layer 2 and the isolation effect of the undercut structure UDC, and at the same time improve the flatness of the film layer in the area near the pixel opening and avoid puncture of the upper film layer (e.g., the second electrode layer), it is necessary to optimize the spacing between the conductive connection portion 102 and the undercut structure UDC to reduce the influence of the conductive connection portion 102 on the film layer in the area near the pixel opening VH, especially the influence of the undercut structure UDC and the second electrode layer. Some embodiments of this disclosure have optimized the spacing between the first via VO1 and the undercut structure UDC.

[0130] For example, referring to FIG5, in order to avoid the conductive connection portion 102 in the area where the first via VO1 is located from adversely affecting the adjacent undercut structure, the first via VO1 and the undercut structure UDC are set at a certain distance apart. For example, the first via VO1 and the side PDL21 near the pixel opening in the second sub-layer PDL2 defined by the pixel are separated by a second spacing distance D2, for example, the second spacing distance D2 is greater than or equal to 0.2 micrometers.

[0131] This design reduces the impact of the conductive connection portion 102 located in the first via VO1 on the undercut structure UDC, thereby improving the pixel separation effect of the display substrate.

[0132] The inventors discovered through research that when the first electrode adopts a regular shape design, such as a square, rectangle, triangle, rhombus, polygon, etc., in order to avoid poor contact, UDC collapse, or cathode puncture, it is necessary to ensure a safe distance between multiple components such as the first via, pixel opening, and the side of the first electrode. For example, the first distance D1 is greater than or equal to 0.15 micrometers, and the second distance D2 is greater than or equal to 0.2 micrometers. This may result in the pixel opening size being set too small, causing a low aperture ratio of the display substrate, which in turn leads to a lower maximum brightness of the display substrate and a reduced range of Gamma adjustment.

[0133] In order to balance the yield of the display substrate, ensure a safe distance between multiple components such as the first via, pixel opening, and the side of the first electrode, and maximize the aperture ratio of the display substrate, the first electrode in some embodiments of this disclosure adopts an irregular shape design. At least a portion of the first electrode near the first via is designed to protrude, and then the first via is offset to the protruding position. This can increase the size of the pixel opening while ensuring a safe distance between multiple components such as the first via, pixel opening, and the side of the first electrode, which is beneficial to increasing the pixel aperture ratio and the maximum adjustable brightness of the display substrate.

[0134] Figure 7 is a partial planar schematic diagram of a display substrate according to an embodiment of the present disclosure, showing a first electrode, a first via, and a pixel opening; Figure 8A is an enlarged schematic diagram of the first electrode and the first via according to some embodiments of the present disclosure; Figure 8B is an enlarged schematic diagram of the first electrode and the first via according to some other embodiments of the present disclosure; Figures 9A and 9B are schematic diagrams comparing pixel opening sizes of display substrates with different first electrode shapes according to embodiments of the present disclosure.

[0135] Exemplary examples, in some embodiments of this disclosure, referring to Figures 7 and 8A, show a plurality of first electrodes arranged in an array. At least a portion of the first electrodes 20 may employ an irregular design. For example, at least a portion of the first electrodes 20, when projected onto the substrate, has a first projection shape, which includes a straight edge 210 and a curved edge 220. The straight edge 210 and the curved edge 220 include a shared second vertex P2 and a sixth vertex P6, and a first shared line segment L26 connecting the second vertex P2 and the sixth vertex P6. It should be noted that the first shared line segment L26 refers to a virtual connecting line shared by the straight edge 210 and the curved edge 220, rather than a real side edge.

[0136] For example, referring to FIG8A, the straight edge portion 210 may further include a fourth vertex P4 furthest from the curved edge portion 220 and a plurality of straight edge side edges L210 sequentially connecting the second vertex P2, the fourth vertex P4, and the sixth vertex P6. For example, the plurality of straight edge side edges L210 include: a first straight edge side edge L2101 connecting the second vertex P2 and the fourth vertex P4; and a second straight edge side edge L2102 connecting the sixth vertex P6 and the fourth vertex P4. For example, the shape of the first straight edge side edge L2101 may include a pattern of multiple line segments connected together. The shape of the second straight edge side edge L2102 may include a pattern of multiple line segments connected together. The plurality of straight edge side edges L210 and the first common line segment L26 surround and form a first region N1, in which the straight edge portion 210 is located.

[0137] For example, the curved edge portion 220 may include: a first vertex P1 furthest from the straight edge portion 210; a first side L12 located between the first vertex P1 and the second vertex P2; and a second side L16 located between the first vertex P1 and the sixth vertex P6. The first side L12, the second side L16, and the first common line segment L26 surround and form a second region N2, in which the curved edge portion 220 is located.

[0138] For example, the lines connecting the first vertex P1, the second vertex P2, the fourth vertex P4, and the sixth vertex P6 form a virtual quadrilateral M1.

[0139] For example, at least one of the first side L12 and the second side L16 intersects with the virtual quadrilateral M1 at least three points. For instance, the first side L12 and the virtual quadrilateral M1 include a first intersection point m1, a second intersection point m2, and a third intersection point m3. These three points are all located between the first vertex P1 and the second vertex P2, and are spaced apart from both vertices P1 and P2. As another example, the second side L16 and the virtual quadrilateral M1 include a fourth intersection point m4, a fifth intersection point m5, and a sixth intersection point m6. These three points are all located between the first vertex P1 and the sixth vertex P6, and are spaced apart from both vertices P1 and P6.

[0140] For example, referring to FIG8B, the straight edge may further include a third vertex P3 and a fifth vertex P5. For example, the third vertex P3 is located on the side L2101 of the first straight edge. For example, the side L2101 of the first straight edge may include: a side L23 connecting the second vertex P2 and the third vertex P3; and a side L34 connecting the third vertex P3 and the fourth vertex P4.

[0141] For example, the fifth vertex P5 is located on the side of the second straight edge L2102. The side of the second straight edge L2102 may include a side L45 connecting the fourth vertex P4 and the fifth vertex P5; and a side L56 connecting the fifth vertex P5 and the sixth vertex P6.

[0142] For example, the lines connecting the first vertex P1, the second vertex P2, the third vertex P3, the fourth vertex P4, the fifth vertex P5, and the sixth vertex P6 form a virtual hexagon M0. At least one of the first side L12 and the second side L16 intersects the virtual hexagon M0 at least three points. For instance, the intersection between the first side L12 and the virtual hexagon M0 may include a first intersection point m1, a second intersection point m2, and a third intersection point m3. As another example, the intersection between the second side L16 and the virtual hexagon M0 may include a fourth intersection point m4, a fifth intersection point m5, and a sixth intersection point m6.

[0143] For example, the display substrate also includes a plurality of first vias VO1. The orthographic projection of the first vias VO1 on the substrate falls within the orthographic projection of the curved edge portion 220 on the substrate.

[0144] For example, referring to Figures 5 and 7, in the first planar direction X1, the first via VO1 is separated from the first vertex P1 by a first spacing distance D1, which is greater than or equal to 0.15 micrometers. The first planar direction X1 is perpendicular to the light emission direction of the display substrate. This design improves the electrical connection performance between the conductive connecting post located in the first via VO1 and the first electrode. The first planar direction X1 can be parallel to the shortest connection line between the first vertex P1 and the first via VO1.

[0145] For example, referring to Figure 8A, the distance between the first vertex P1 and the fourth vertex P4 is D10. The ratio of the first distance D1 to the distance D10 between the first vertex P1 and the fourth vertex P4 is less than or equal to 1 / 4, that is, D1 / D10≤1 / 4.

[0146] For example, referring to Figures 5 and 7, within the same sub-pixel, in the first planar direction X1, the first via VO1 is separated from the side edge PDL21 of the second sub-layer PDL2 near the pixel opening by a second spacing distance D2, the second spacing distance D2 being greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer. The first planar direction X1 may be parallel to the shortest connecting line between the first via VO1 and the pixel opening VH. For example, the second spacing distance D2 may be approximately 0.2 micrometers, 0.4 micrometers, 0.6 micrometers, 0.8 micrometers, or 1 micrometer.

[0147] This design reduces the impact of uneven film layers in the area where the first via is located on the undercut structure (UDC) in the pixel limiting layer, preventing damage or even collapse of the undercut structure. It also helps reduce the probability of cathode puncture in the vicinity of the undercut structure and improves the yield of the display substrate.

[0148] In some embodiments, referring to Figures 5 and 7, the shape of the pixel opening VH can be defined by the pixel-defined first sub-layer PDL1. Since the pixel-defined second sub-layer PDL2 is recessed relative to the pixel-defined first sub-layer PDL1 in a direction away from the pixel opening, the spacing distance D6 between the pixel opening VH and the first via VO1 is greater than the second spacing distance D2, that is, D6 is greater than 0.2 micrometers. For example, the spacing distance D6 between the pixel opening VH and the first via VO1 is approximately 0.26 micrometers, 0.5 micrometers, or 0.8 micrometers.

[0149] In some embodiments of this disclosure, referring to FIG7, within the same sub-pixel, in the second planar direction X2, the pixel opening VH is spaced from the side of the first electrode 20 by a third spacing distance D3. The second planar direction X2 is perpendicular to the light-emitting direction of the display substrate and intersects with the first planar direction X1. For example, the third spacing distance D3 is greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer. For example, the third spacing distance D3 can be approximately 0.2 micrometers, 0.4 micrometers, 0.6 micrometers, 0.8 micrometers, or 1 micrometer. This design ensures that the pixel defining layer can better enclose the side of the first electrode, avoiding defects such as short circuits.

[0150] In some embodiments of this disclosure, two adjacent first electrodes 20 are spaced apart by a fourth spacing distance D4 along the third planar direction X3. The third planar direction X3 is perpendicular to the light-emitting direction of the display substrate and intersects both the first planar direction X1 and the second planar direction X2. For example, the fourth spacing distance D4 is greater than or equal to 0.25 micrometers and less than or equal to 1 micrometer. For example, the fourth spacing distance D4 can be approximately 0.25 micrometers, 0.45 micrometers, 0.65 micrometers, 0.8 micrometers, or 1 micrometer. This design facilitates the alignment and fabrication of subsequent process steps, avoiding defects such as short circuits and crosstalk caused by process deviations.

[0151] It should be noted that the "first plane direction," "second plane direction," and "third plane aspect" are all parallel to the plane formed by the first and second directions. For different sub-pixels, the "first plane direction," "second plane direction," and "third plane aspect" can be the same or different.

[0152] In some embodiments, the shape of the pixel opening VH can be substantially similar to the shape of the first electrode 20. For example, the first electrode 20 adopts a hexagonal-based irregular design, and the shape of the pixel opening includes a hexagon.

[0153] For example, the shape of the pixel aperture VH includes a centrally symmetrical shape. For instance, the pixel aperture VH includes a pixel aperture center Z1, and the pixel aperture VH is symmetrical about the pixel aperture center Z1. For instance, the shape of the orthographic projection of the pixel aperture VH onto the substrate includes a hexagon, and the hexagon of the orthographic projection of the pixel aperture VH onto the substrate is a centrally symmetrical figure about the pixel aperture center Z1.

[0154] In some embodiments, referring to FIG14B, the intersection of the line connecting the second vertex P2 and the fifth vertex P5 with the line connecting the third vertex P3 and the sixth vertex P6 substantially coincides with the pixel opening center Z1. This design allows the light-emitting area of ​​the pixel to be located substantially in the central region of the first electrode, thereby improving the uniformity of the light-emitting device's brightness at various angles.

[0155] For example, referring to FIG8B, in the same first electrode 20, the area of ​​the straight edge portion 210 is larger than the area of ​​the curved edge portion 220. This design makes it easier to design and manufacture irregular shapes for the first electrode, which helps to reduce the difficulty of the process and improve the yield.

[0156] For example, the edge profile of the curved portion 220 includes a smooth curve. For instance, referring to FIG13, the shape of the first side L12 includes a smooth curve. As another example, the shape of the second side L16 includes a smooth curve.

[0157] For example, the first side L12 includes a first curved edge L121 connected to the first vertex P1. At least a portion of the first curved edge L121 lies outside the virtual hexagon M0.

[0158] For example, the second side L16 includes a second curved edge L161 connected to the first vertex P1. At least a portion of the second curved edge L161 lies outside the virtual hexagon M0.

[0159] For example, the curved edge portion 220 may include a first protrusion 2201. The first protrusion 2201 is located between the first curved edge L121 and the second curved edge L161.

[0160] For example, the orthographic projection of the first via VO1 on the substrate is located on the side of the curved edge 220 that is close to the first protrusion 2201 and away from the straight edge 210.

[0161] For example, the orthographic projection of the first via VO1 on the substrate overlaps at least partially with the orthographic projection of the first protrusion 2201 on the substrate.

[0162] By placing the first via in the region close to the first protrusion, the orthographic projections of the first via and the first protrusion on the substrate at least partially overlap. This can increase the size of the pixel opening and improve the aperture ratio of the display substrate while ensuring that the spacing between the first via, the pixel opening, and the first electrode meets the safe spacing distance.

[0163] It should be noted that the "safety gap distance" in the embodiments of this disclosure refers to a gap distance between the first via VO1 and the side of the first electrode 20 that is greater than or equal to 0.15 micrometers, and a gap distance between the first via VO1 and the pixel opening VH that is greater than or equal to 0.2 micrometers.

[0164] By way of example, continuing to refer to FIG7 and FIG8B, the curved edge portion 220 includes at least two recesses 2203, which are located on the side of the curved edge portion 220 near the straight edge portion 210.

[0165] For example, in the same first electrode 20, the first protrusion 2201 of the first electrode is located between the two recesses 2203 of two adjacent first electrodes.

[0166] This design improves the uniformity of the spacing between adjacent first electrodes, facilitating the alignment design of subsequent processes and reducing the probability of short circuits caused by alignment deviations.

[0167] For example, referring to FIG9A, the first electrode adopts a regular shape design (e.g., a regular hexagon), wherein when the spacing between the pixel opening VH, the first via VO1, and the side 201 of the first electrode 20 meets the safety spacing distance, the pixel opening VH includes the first pixel opening VH1. Referring to FIG9B, the first electrode adopts a design combining curved and straight edges to form a structure protruding to one side, wherein when the spacing between the pixel opening VH, the first via VO1, and the side 201 of the first electrode 20 meets the safety spacing distance, the pixel opening VH includes the second pixel opening VH2.

[0168] By comparing Figures 9A and 9B, it can be seen that, with other parameters (such as pixel density, size of a single pixel, and spacing between multiple components) being the same, the size of the second pixel opening VH2 is larger than the size of the first pixel opening VH1, and the area of ​​the orthographic projection of the second pixel opening VH2 onto the substrate is larger than the area of ​​the orthographic projection of the first pixel opening VH1 onto the substrate. In other words, with other parameters remaining constant, using an irregularly shaped design for the first electrode (such as the irregularly shaped first electrode in Figure 9B) and offsetting the first via towards the side closer to the first protrusion of the first electrode helps to increase the pixel opening size, thereby increasing the aperture ratio of the display substrate and improving its brightness.

[0169] This design allows for two main advantages: firstly, it increases the aperture ratio of the display substrate, enabling greater display brightness and providing more room for Gamma adjustment; secondly, it requires a lower driving voltage to achieve the same brightness, which helps improve the lifespan of the display substrate.

[0170] In some embodiments, the shape of the pixel opening may be different from the shape of the first electrode.

[0171] Figure 10 is a partial planar schematic diagram of a display substrate according to an embodiment of the present disclosure, showing a first electrode, a first via, and a pixel opening; Figures 11A and 11B are schematic diagrams comparing pixel opening sizes of display substrates with different first electrode shapes according to embodiments of the present disclosure.

[0172] For example, referring to Figures 10-11B, the pixel opening VH and the first electrode 20 have different shapes. For instance, the first electrode 20 adopts a hexagonal irregular design, and its structure can be the same as that of the first electrode in the embodiment shown in Figure 7. Unlike the embodiment shown in Figure 7, the pixel opening in Figures 10-11B adopts a circular design.

[0173] Referring to Figure 11A, the first electrode 20 is a regular hexagon, and the pixel opening VH is circular. When the spacing between the pixel opening VH, the first via VO1, and the first electrode 20 meets the safety spacing distance, the pixel opening VH may include the first pixel opening VH1.

[0174] Referring to Figure 11B, the first electrode 20 has a hexagonal irregular shape, and the pixel opening VH is circular. The first electrode 20 employs a combination of curved and straight edges to form a structure that protrudes to one side. When the spacing between the pixel opening VH, the first via VO1, and the side edge 201 of the first electrode 20 meets the safety spacing requirement, the pixel opening VH may include a second pixel opening VH2.

[0175] By comparing Figures 11A and 11B, it can be seen that, with other parameters (such as pixel density, size of a single pixel, and spacing between multiple components) being the same, the size of the second pixel opening VH2 is larger than the size of the first pixel opening VH1, and the area of ​​the orthographic projection of the second pixel opening VH2 onto the substrate is larger than the area of ​​the orthographic projection of the first pixel opening VH1 onto the substrate. In other words, when all other parameters remain constant, if the first electrode adopts the irregular shape design in the embodiments of this disclosure, and the pixel opening adopts a circular design, offsetting the first via towards the first protrusion of the irregularly shaped first electrode helps to increase the pixel opening size, thereby increasing the aperture ratio of the display substrate and improving the brightness of the display substrate.

[0176] According to some exemplary embodiments, referring back to Figures 8B and 9B, the first side L12 may include: a third curved edge L123 connected to the second vertex P2; and a connecting line L122 connecting the first curved edge L121 and the third curved edge L123, wherein the third curved edge L123 is located inside the virtual hexagon M0, and at least a portion of the connecting line L122 is located outside the virtual hexagon M0.

[0177] For example, the connecting line L122 may include at least one of a straight line and a curve; or, the connecting line L122 may include a combination of a straight line and a curve.

[0178] In some embodiments, the first curved edge L121, the connecting line L122, and the third curved edge L123 can form a smooth curve.

[0179] For example, the curved portion 220 includes a second protrusion 2202. The second protrusion 2202 is located between the connecting line L122 and at least one side of the virtual hexagon M0, and the second protrusion 2202 is located outside the virtual hexagon M0.

[0180] This design can reduce the wiring space occupied by the first electrodes while ensuring the consistency of the spacing between multiple first electrodes, which is beneficial to improving the aperture ratio of the display substrate.

[0181] Figure 12 is a partial planar schematic diagram of the first electrode of the display substrate according to an embodiment of the present disclosure, and Figure 13 is a partial enlarged schematic diagram of the N3 region in Figure 12.

[0182] In some embodiments of this disclosure, referring to FIG12, the first protrusion 2201 of the first electrode 20 faces the gap M1 between the two first electrodes adjacent to the first electrode 20.

[0183] Referring again to Figure 12, the first electrode layer 2 includes a plurality of electrode rows extending along the first direction X, and each electrode row includes a plurality of first electrodes 20 arranged at intervals. For example, the plurality of electrode rows include adjacent i-th electrode rows K in the second direction Y. i and the (i+1)th electrode row K i+1 , where i is a positive integer greater than or equal to 1.

[0184] For example, the i-th electrode row K i and the (i+1)th electrode row K i+1 At least partially aligned in the second direction Y.

[0185] For example, located in the i-th electrode row K i The curved edges 220 of the multiple first electrodes are directed toward the (i+1)th electrode. i+1 ; and the K located in the (i+1)th electrode row i+1The curved edges 220 of the multiple first electrodes are oriented towards the i-th electrode. i .

[0186] This design allows for staggered design of curved edges, which helps save wiring space, improves the uniformity of the spacing between adjacent first electrodes, and reduces the probability of short circuits due to process deviations.

[0187] For example, the plurality of electrode rows also includes the (i+1)th electrode row K along the second direction Y. i+1 Adjacent (i+2)th electrode row K i+2 Located in the (i+1)th electrode row K i+1 The straight edge portion 210 of the multiple first electrodes and the K located in the (i+2)th electrode row i+2 The straight edges 210 of the multiple first electrodes are arranged opposite each other. This design improves the uniformity of the spacing between adjacent first electrodes and reduces the probability of short circuits due to process deviations.

[0188] For example, referring to FIG13, the display substrate may include a first gap region M2 located between the curved edges of two adjacent first electrodes in an adjacent electrode row. The second protrusions 2202 of the two adjacent first electrodes in the adjacent electrode row are disposed opposite each other within the same first gap region M2.

[0189] For example, the connecting line L122 may include a curve. This design reduces the number of tips (or sharp corners) in the first electrode, thereby reducing the probability of tip discharge and improving the yield of the display substrate.

[0190] For example, the first protrusion 2201 has a discontinuous curvature at the first vertex P1 position.

[0191] For example, the second protrusion 2202 includes a seventh vertex P7 furthest from the virtual hexagon M0. For instance, the seventh vertex P7 is located in the connecting line L122. The second protrusion 2202 has a continuous curvature at the location of the seventh vertex P7.

[0192] For example, in the same first electrode 20, the area of ​​the first protrusion 2201 is larger than the area of ​​the second protrusion 2202.

[0193] For example, the shape of the first protrusion 2201 may include at least one of a rectangle, at least a portion of a circle, or at least a portion of an ellipse.

[0194] For example, the first protrusion 2201 is symmetrical about the line connecting the first vertex P1 and the fourth vertex P4.

[0195] Preferably, referring to FIG8B, the shape of the first protrusion 2201 includes a portion of a circle. This design facilitates the design of the spacing between adjacent first electrodes and reduces the number of sharp points in the first electrodes, which helps to reduce the probability of sharp discharge and thus improves the yield of the display substrate.

[0196] Figure 14A is a plan view of a first electrode according to some embodiments of the present disclosure, and Figure 14B is an enlarged view of a single first electrode in Figure 14A; Figure 15A is a plan view of a first electrode according to other embodiments of the present disclosure, and Figure 15B is an enlarged view of a single first electrode in Figure 15A.

[0197] By way of example, in an embodiment of this disclosure, referring to FIG14A, the shape of the first protrusion 2201 may also include a rectangle. The shape of the recess 2203 adjacent to the first protrusion 2201 may include a curved recess shape.

[0198] For example, the spacing between adjacent first electrodes 20 may be the same or different.

[0199] For example, referring to FIG14B, the fourth vertex P4 and the first vertex P1 are located on opposite sides of the pixel aperture center Z1. The first vertex P1 is separated from the pixel aperture center Z1 by a fifth interval distance D5, and the fourth vertex P4 is separated from the pixel aperture center Z1 by a sixth interval distance D6. The difference between the fifth interval distance D5 and the sixth interval distance D6 is greater than the radius of the first via VO1.

[0200] By way of example, in an embodiment of this disclosure, referring to FIG15A, the shape of the first protrusion 2201 may further include at least a portion of an ellipse. The shape of the recess 2203 adjacent to the first protrusion 2201 may include a curved recess shape.

[0201] For example, referring to FIG15B, the fourth vertex P4 and the first vertex P1 are located on opposite sides of the pixel aperture center Z1. The first vertex P1 is separated from the pixel aperture center Z1 by a fifth interval distance D5, and the fourth vertex P4 is separated from the pixel aperture center Z1 by a sixth interval distance D6. The difference between the fifth interval distance D5 and the sixth interval distance D6 is greater than the radius of the first via VO1.

[0202] For example, the radius of the first via VO1 is greater than or equal to 0.1 micrometers, such as the radius of the first via VO1 being about 0.15 micrometers, 0.25 micrometers or 0.35 micrometers.

[0203] This design allows for increased aperture ratio of the display substrate while ensuring that the spacing between the first via, the first electrode, and the pixel opening meets the safety requirements. This facilitates greater display brightness, provides more adjustment space for Gamma tuning, and requires lower driving voltage to achieve the same brightness, thus improving the lifespan of the display substrate.

[0204] In some embodiments, the first electrode may also have a regular shape design, for example, the shape of the first electrode's orthographic projection on the substrate is hexagonal. One end of the hexagon may be stretched (protruded) and the first via may be located near the stretched end of the first electrode.

[0205] Figure 16A is a plan view of a first electrode according to some embodiments of the present disclosure, and Figure 16B is an enlarged view of a single first electrode in Figure 16A.

[0206] Exemplary embodiments of this disclosure also provide a display substrate. Referring to Figures 5, 16A, and 16B, the display substrate includes: a substrate 1; a driving circuit layer 10 located on one side of the substrate; an insulating layer 11 located on the side of the driving circuit layer 10 away from the substrate, the insulating layer 11 including a plurality of first vias VO1; and a first electrode layer 2 located on the side of the insulating layer 11 away from the substrate, the first electrode layer 2 including a plurality of first electrodes 20, the first electrodes 20 being electrically connected to the driving circuit layer 10 through the first vias VO1.

[0207] The display substrate also includes a pixel defining layer PDL located on the side of the first electrode layer 2 away from the substrate. The pixel defining layer PDL defines a plurality of pixel openings VH, and the pixel openings VH include a pixel opening center Z1. The pixel openings VH are symmetrical about the pixel opening center Z1.

[0208] For example, at least a portion of the first electrode 20 has a first projection shape on the substrate, the first projection shape including a first vertex P1, a second vertex P2, a third vertex P3, a fourth vertex P4, a fifth vertex P5 and a sixth vertex P6 connected in sequence.

[0209] For example, the first projection shape includes a hexagon. The first vertex P1 and the fourth vertex P4 are located on opposite sides of the pixel opening center Z1.

[0210] In some embodiments of this disclosure, the hexagonal first electrode 20 is designed with a stretching feature at the end near the first vertex P1, and the first through hole VO1 is disposed at the stretching end near the first electrode.

[0211] The first vertex P1 is separated from the pixel opening center Z1 by a fifth interval distance D5, and the fourth vertex P4 is separated from the pixel opening center Z1 by a sixth interval distance D6. The difference between the fifth interval distance D5 and the sixth interval distance D6 is greater than the radius of the first via VO1.

[0212] For example, the radius of the first via VO1 is greater than or equal to 0.1 micrometers, such as the radius of the first via VO1 being about 0.15 micrometers, 0.25 micrometers or 0.35 micrometers.

[0213] This design allows for increased aperture ratio of the display substrate while ensuring that the spacing between the first via, the first electrode, and the pixel opening meets the safety requirements. This facilitates greater display brightness, provides more adjustment space for Gamma tuning, and requires lower driving voltage to achieve the same brightness, thus improving the lifespan of the display substrate.

[0214] Figure 17 is a schematic diagram of the structure of a display panel provided according to some embodiments of the present disclosure.

[0215] Optionally, embodiments of this disclosure provide a display panel. Referring to FIG17, the display panel 200 may include the display substrate 100 described above.

[0216] Figure 18 is a schematic diagram of the structure of a display device provided according to some embodiments of the present disclosure.

[0217] Optionally, embodiments of this disclosure also provide a display device 300. Referring to FIG18, the display device 300 may include the aforementioned display substrate 100 or the aforementioned display panel 200. The display device may include, but is not limited to, any product or component with display function such as electronic paper, mobile phone, tablet computer, monitor, laptop computer, digital photo frame, and navigator. It should be understood that this display device has the same beneficial effects as the display substrate provided in the foregoing embodiments.

[0218] While some embodiments of the general concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized by, The display substrate comprises: a substrate substrate; a driving circuit layer located on one side of the substrate substrate; a first electrode layer located on a side of the driving circuit layer away from the substrate substrate, the first electrode layer comprising a plurality of first electrodes, a first projection shape of at least part of the first electrode on the substrate substrate, the first projection shape comprising a straight edge part and a curved edge part, the straight edge part and the curved edge part comprising a second common vertex and a sixth vertex, and a first common line segment connecting the second vertex and the sixth vertex; the straight edge part further comprises: a fourth vertex farthest from the curved edge part, and a plurality of straight edge part side edges sequentially connecting the second vertex, the fourth vertex and the sixth vertex, the plurality of straight edge part side edges and the first common line segment forming a first region, and the straight edge part is located in the first region; the curved edge part comprises: a first vertex farthest from the straight edge part; a first side edge between the first vertex and the second vertex; and a second side edge between the first vertex and the sixth vertex, the first side edge, the second side edge and the first common line segment forming a second region, and the curved edge part is located in the second region, wherein the line connecting the first vertex, the second vertex, the fourth vertex and the sixth vertex forms a virtual quadrilateral, and at least one of the first side edge and the second side edge and the virtual quadrilateral comprises at least three intersection points. 2.The display substrate of claim 1, wherein, The straight edge part further comprises a third vertex and a fifth vertex; the plurality of straight edge part side edges comprises: a first straight edge part side edge connecting the second vertex and the fourth vertex, the third vertex being located on the first straight edge part side edge; and a second straight edge part side edge connecting the sixth vertex and the fourth vertex, the fifth vertex being located on the second straight edge part side edge; and the line connecting the first vertex, the second vertex, the third vertex, the fourth vertex, the fifth vertex and the sixth vertex forms a virtual hexagon, and at least one of the first side edge and the second side edge and the virtual hexagon comprises at least three intersection points. 3.The display substrate according to claim 1 or 2, wherein, The display substrate further comprises: an insulating layer between the driving circuit layer and the first electrode layer, the insulating layer comprising a plurality of first vias configured to connect the first electrodes and the driving circuit layer, wherein the first via on the substrate substrate falls within the projection of the curved edge part on the substrate substrate. 4.The display substrate of claim 3, wherein, The plurality of first electrodes are arranged in an array in a first direction and a second direction, the first direction and the second direction intersecting; the first electrode layer comprises a plurality of electrode rows extending in the first direction, the electrode rows comprising a plurality of first electrodes arranged at intervals, wherein a plurality of the electrode rows comprise an i-th electrode row and an i+1-th electrode row adjacent in the second direction, the i-th electrode row and the i+1-th electrode row being at least partially aligned in the second direction, i being a positive integer greater than or equal to 1, The curved edge portion of the first electrode in the i-th electrode row faces the i+1-th electrode row; and the curved edge portion of the first electrode in the i+1-th electrode row faces the i-th electrode row. 5.The display substrate of claim 4, wherein, The plurality of electrode rows further comprises an i+2-th electrode row adjacent to the i+1-th electrode row in the second direction, the straight edge portion of the first electrode in the i+1-th electrode row and the straight edge portion of the first electrode in the i+2-th electrode row are oppositely arranged. 6.The display substrate according to any one of claims 2-5, wherein, In the same first electrode, the area of the straight edge portion is greater than the area of the curved edge portion. 7.The display substrate according to any one of claims 2-6, wherein, The first side edge comprises a first curved edge connected to the first vertex, at least a part of the first curved edge is located outside the virtual hexagon; And / or, The second side edge comprises a second curved edge connected to the first vertex, at least a part of the second curved edge is located outside the virtual hexagon. 8.The display substrate of claim 7, wherein, The first side edge further comprises a third curved edge connected to the second vertex, and a connecting line connecting the first curved edge and the third curved edge, the third curved edge is located inside the virtual hexagon, and at least a part of the connecting line is located outside the virtual hexagon; and The curved edge portion comprises a first protruding portion and a second protruding portion, the first protruding portion is located between the first curved edge and the second curved edge; the second protruding portion is located between the connecting line and at least one side of the virtual hexagon, and the second protruding portion is located outside the virtual hexagon. 9.The display substrate of claim 8, wherein, The first protruding portion of the first electrode faces the gap between two first electrodes adjacent to the first electrode; and The display substrate further comprises a first gap region between the curved edge portions of two adjacent first electrodes in adjacent electrode rows, the second protruding portions of the two adjacent first electrodes in adjacent electrode rows are oppositely arranged in the same first gap region. 10.The display substrate according to claim 8 or 9, wherein The first protruding portion has discontinuous curvature at the position of the first vertex; and / or, The second protruding portion comprises a seventh vertex farthest from the virtual hexagon, and the second protruding portion has continuous curvature at the position of the seventh vertex. 11.The display substrate according to claim 8 or 9, wherein In the same first electrode, the area of the first protruding portion is greater than the area of the second protruding portion. 12.The display substrate according to any one of claims 8-11, wherein, The first via has a projection on the substrate, and the projection is located on one side of the curved edge portion close to the first protruding portion and away from the straight edge portion. 13.The display substrate of claim 12, wherein, The curved edge portion comprises at least two recessed portions, and the recessed portions are located on one side of the curved edge portion close to the straight edge portion. 14.The display substrate of claim 13, wherein, The first protruding portion of the first electrode is located between two recessed portions of two adjacent first electrodes. 15.The display substrate according to any one of claims 3-14, wherein, In a first plane direction, the first via is spaced apart from the first vertex by a first spacing distance, the first spacing distance is greater than or equal to 0.15 microns, and the first plane direction is perpendicular to the light output direction of the display substrate; And The ratio of the first spacing distance to the spacing distance between the first vertex and the fourth vertex is less than or equal to 1 / 4. 16.The display substrate according to any one of claims 3-15, wherein, The display substrate further comprises a pixel definition layer on the side of the first electrode layer away from the substrate, and the pixel definition layer defines a plurality of pixel openings, The pixel defining layer comprises: a pixel defining first sub-layer located on a side of the first electrode layer away from the substrate; a pixel defining second sub-layer located on a side of the pixel defining first sub-layer away from the substrate; and a pixel defining third sub-layer located on a side of the pixel defining second sub-layer away from the substrate, the pixel defining second sub-layer is recessed relative to the pixel defining first sub-layer and the pixel defining third sub-layer in a direction away from the pixel opening; and In the same sub-pixel, in the first planar direction, the first via is spaced from a side of the pixel defining second sub-layer close to the pixel opening by a second spacing distance, the second spacing distance is greater than or equal to 0.2 microns and less than or equal to 1 micron. 17.The display substrate of claim 16, wherein, In the same sub-pixel, in a second planar direction, the pixel opening is spaced from a side of the first electrode by a third spacing distance, the third spacing distance is greater than or equal to 0.2 microns and less than or equal to 1 micron, the second planar direction is perpendicular to the light-out direction of the display substrate. 18.The display substrate of claim 17, wherein, In a third planar direction, two adjacent first electrodes are spaced by a fourth spacing distance, the fourth spacing distance is greater than or equal to 0.25 microns and less than or equal to 1 micron, the third planar direction is perpendicular to the light-out direction of the display substrate.

19. The display substrate of claim 8, wherein, The shape of the first protruding part includes at least one of a rectangle, at least a part of a circle, and at least a part of an ellipse. 20.The display substrate according to any one of claims 16-19, wherein, The pixel opening includes a pixel opening center, the pixel opening is symmetrical about the pixel opening center; The fourth vertex and the first vertex are located on opposite sides of the pixel opening center, the first vertex is spaced from the pixel opening center by a fifth spacing distance, the fourth vertex is spaced from the pixel opening center by a sixth spacing distance, the difference between the fifth spacing distance and the sixth spacing distance is greater than the radius of the first via.

21. A display substrate, comprising: Comprising: a substrate; a drive circuit layer located on a side of the substrate; an insulating layer located on a side of the drive circuit layer away from the substrate, the insulating layer comprising a plurality of first vias; a first electrode layer located on a side of the insulating layer away from the substrate, the first electrode layer comprising a plurality of first electrodes, the first electrodes being electrically connected to the drive circuit layer through the first vias, at least part of the first electrodes has a first projection shape in orthographic projection on the substrate, the first projection shape comprises a first vertex, a second vertex, a third vertex, a fourth vertex, a fifth vertex and a sixth vertex connected in turn; The display substrate further comprises a pixel defining layer located on a side of the first electrode layer away from the substrate, the pixel defining layer defines a plurality of pixel openings, the pixel opening includes a pixel opening center, the pixel opening is symmetrical about the pixel opening center, wherein the first vertex and the fourth vertex are located on opposite sides of the pixel opening center; and The first vertex is spaced a fifth spacing distance from the center of the pixel opening, the fourth vertex is spaced a sixth spacing distance from the center of the pixel opening, and a difference between the fifth spacing distance and the sixth spacing distance is greater than the radius of the first via.

22. A display panel, wherein, A display substrate comprising the display substrate of any of claims 1-21.

23. A display device, wherein, A display panel comprising the display substrate of any of claims 1-21 or the display panel of claim 22.

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