Display substrate and display device

Abstract

A display substrate and a display device. In the display substrate, a sub-pixel further comprises a first via, a second via, an anode via, an anode connection pad, and a first connection pad; a first reset signal line extends in a first direction; a pixel circuit further comprises a first reset transistor, wherein a first electrode of the first reset transistor is electrically connected to the first reset signal line, and a second electrode of the first reset transistor is connected to a first electrode of a light-emitting component; a first reset signal connection line extends in a second direction intersecting the first direction, is configured to transmit a first reset signal, and is electrically connected to the first reset signal line through the first via; the first electrode of the light-emitting component is electrically connected to the anode connection pad through the anode via, the anode connection pad is electrically connected to the first connection pad through the second via, and the first connection pad is electrically connected to an active layer of the first reset transistor; the distance between the first via and the second via in the second direction is greater than the distance between the first via and the anode via in the second direction.

Description

Display substrate and display device Technical Field

[0001] At least one embodiment of this disclosure relates to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays have advantages over traditional liquid crystal displays (LCDs), such as self-illumination, wide color gamut, high contrast, and thinness, making them widely used in mobile phones, tablets, and other fields.

[0003] As people's requirements for display quality increase, display panels with high resolution and pixel circuits for better driving effects can achieve better display effects and have greater advantages. However, such display panels have high pixel density and more transistors in the pixel circuits, and require more interconnecting vias between different film layers, which increases the design difficulty. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display substrate, which includes: a substrate, sub-pixels, a first reset signal line, and a first reset signal connection line. A sub-pixel is disposed on the surface of the substrate and includes a pixel circuit. The pixel circuit includes a light-emitting device and a driving transistor. The driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device. The light-emitting device is configured to receive the driving current and be driven by the driving current to emit light. The sub-pixel also includes a first via, a second via, an anode via, an anode connection pad, and a first connection pad. A first reset signal line extends along a first direction. The pixel circuit also includes a first reset transistor. The first electrode of the first reset transistor is electrically connected to the first reset signal line, and the second electrode of the first reset transistor is connected to the first electrode of the light-emitting device. A first reset signal connection line extends along a second direction intersecting the first direction, is configured to transmit a first reset signal, and is electrically connected to the first reset signal line via the first via. The first electrode of the light-emitting device is electrically connected to the anode connection pad through the anode via. The anode connection pad is electrically connected to the first connection pad through the second via. The first connection pad is electrically connected to the active layer of the first reset transistor. The distance between the first via and the second via in the second direction is greater than the distance between the first via and the anode via in the second direction.

[0005] For example, at least one embodiment of this disclosure provides a display substrate, the display substrate including a pixel array, the pixel array including a plurality of sub-pixels arranged in an array, the plurality of sub-pixels including a first sub-pixel and a second sub-pixel adjacent to each other in a second direction, the first sub-pixel and the second sub-pixel sharing a first via, the first via being located in the boundary region between the first sub-pixel and the second sub-pixel in the second direction; the distance between the first via and the second via of the first sub-pixel in the second direction is greater than the distance between the first via and the anode via of the first sub-pixel in the second direction; and the distance between the first via and the second via of the second sub-pixel in the second direction is greater than the distance between the first via and the anode via of the second sub-pixel in the second direction.

[0006] For example, in at least one embodiment of this disclosure, a display substrate is provided in which, in the second direction, at least a portion of the anode via of the first sub-pixel is located between the first via and the second via, and the anode via of the second sub-pixel is located on the side of the first via away from the second via.

[0007] For example, in at least one embodiment of this disclosure, a display substrate is provided in which the distance between the first via and the second via of the second sub-pixel in the first direction is 3 to 5 times the distance between the first via and the anode via of the second sub-pixel in the first direction.

[0008] For example, in at least one embodiment of this disclosure, a display substrate is provided in which, in the second direction, the entire anode via of the first sub-pixel is located between the first via and the second via, and the distance between the first via and the second via of the first sub-pixel in the second direction is 5 to 8 times the distance between the first via and the anode via of the first sub-pixel in the second direction.

[0009] For example, in at least one embodiment of this disclosure, a display substrate is provided in which, in the second direction, a portion of the anode via of the first sub-pixel is located between the first via and the second via, and the distance between the first via and the second via of the first sub-pixel in the second direction is 2 to 10 times the distance between the first via and the anode via of the first sub-pixel in the second direction.

[0010] For example, at least one embodiment of this disclosure provides a display substrate in which the anode via of the first sub-pixel overlaps with the first via in the first direction.

[0011] For example, at least one embodiment of this disclosure provides a display substrate in which the orthographic projection of the first via on the surface of the substrate at least partially overlaps with the orthographic projection of the first reset signal connection line on the surface of the substrate. The first reset signal connection line is located between the first sub-pixel and the second sub-pixel in the first direction. The first sub-pixel and the second sub-pixel share the first reset signal connection line and the first via. The second via of the first sub-pixel and the second via of the second sub-pixel are substantially symmetrical with respect to the first reset signal connection line.

[0012] For example, at least one embodiment of this disclosure provides a display substrate in which the sub-pixel further includes a third sub-pixel adjacent to the second sub-pixel in the first direction; at least a portion of the orthographic projection of at least one of the second via of the second sub-pixel and the second via of the third sub-pixel on the surface of the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device of the third sub-pixel on the surface of the substrate.

[0013] For example, at least one embodiment of this disclosure provides a display substrate in which the entire orthographic projection of at least one of the second via of the second sub-pixel and the second via of the third sub-pixel on the surface of the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device of the third sub-pixel on the surface of the substrate.

[0014] For example, at least one embodiment of this disclosure provides a display substrate in which the area of ​​the first electrode of the light-emitting device of the third sub-pixel is larger than the area of ​​the first electrode of the light-emitting device of the first sub-pixel, and larger than the area of ​​the first electrode of the light-emitting device of the second sub-pixel.

[0015] For example, in at least one embodiment of this disclosure, a display substrate is provided in which the length of the first via in the first direction is greater than the width of the first via in the second direction; and the length of the second via in the first direction is greater than the width of the first via in the second direction.

[0016] For example, in at least one embodiment of this disclosure, a display substrate is provided in which the distance between the first via and the second via in the second direction is greater than the distance between the second via of the first sub-pixel and the second via of the second sub-pixel in the first direction.

[0017] For example, at least one embodiment of this disclosure provides a display substrate, the display substrate further comprising: a second power supply voltage line, the second power supply voltage line including a first trace extending along the first direction, wherein the first trace includes a first bend, the first bend being located between the first via and the second via in the second direction.

[0018] For example, at least one embodiment of this disclosure provides a display substrate in which the first trace of the second power supply voltage line further includes a second bend connected to the first bend, the second bend being located between the first and second electrodes of the first reset transistor in the second direction.

[0019] For example, at least one embodiment of this disclosure provides a display substrate in which the sub-pixel further includes a first connection structure, wherein the first reset signal connection line and the first electrode of the first reset transistor are electrically connected to the first connection structure; the first connection structure includes a connection body extending along a first direction, a second connection pad connected to the connection body and protruding from the connection body toward a second via in a second direction, and a third connection pad and a fourth connection pad located at both ends of the connection body in the first direction; the orthographic projection of the first via on the surface of the substrate at least partially overlaps with the orthographic projection of the second connection pad on the surface of the substrate, and the first reset signal connection line is connected to the second connection pad via the first via; for the first sub-pixel, the third connection pad is electrically connected to the first reset signal connection line via the second connection pad via the first reset transistor. The signal line and the source region of the active layer of the first reset transistor are connected; for the second sub-pixel, the fourth connection pad is connected to the first reset signal line and the source region of the active layer of the first reset transistor respectively; the sub-pixel also includes a fourth via and a fifth via; the first reset signal connection line is connected to the second connection pad of the first connection structure through the first via; the third connection pad is electrically connected to the first reset signal line through the fourth via of the first sub-pixel, and the third connection pad is electrically connected to the first electrode of the first reset transistor of the first sub-pixel through the fifth via of the first sub-pixel; the fourth connection pad is electrically connected to the first reset signal line through the fourth via of the second sub-pixel, and the fourth connection pad is electrically connected to the first electrode of the first reset transistor of the second sub-pixel through the fifth via of the second sub-pixel.

[0020] For example, at least one embodiment of this disclosure provides a display substrate in which the pixel circuit further includes a second reset transistor, the first terminal of the second reset transistor being connected to a second reset signal line, the second terminal of the second reset transistor being connected to the gate of the driving transistor, and configured to reset the gate of the driving transistor using a second reset signal from the second reset signal line; the display substrate further includes a second reset signal connection line extending along a second direction and spaced apart from the first reset signal connection line in the first direction; the display substrate further includes a second connection structure, the second reset signal connection line and the first terminal of the second reset transistor being electrically connected to the second connection structure respectively; the plurality of sub-pixels further include a fourth sub-pixel and a fifth sub-pixel adjacent in the first direction, the fourth sub-pixel and the fifth sub-pixel including and sharing the second connection structure, the second connection structure including a first strip extending along the first direction and a first strip extending along the first direction, and a second reset signal connection line and a second reset signal connection line. The system comprises a second stripe extending toward the first via along the second direction, a sixth connecting pad located at the end of the second stripe away from the first stripe in the second direction, and a seventh and eighth connecting pads located at both ends of the first stripe in the first direction, respectively; a portion of the sub-pixels includes a first sub-via, a sixth via, a seventh via, and an eighth via; the fourth and fifth sub-pixels share a first sub-via and a sixth via; the fourth sub-pixel includes the seventh via, and the fifth sub-pixel includes the eighth via; a second reset signal connection line is connected to the sixth connecting pad via the first sub-via; the first stripe is connected to the second reset signal line via the sixth via; the seventh connecting pad is connected to the source region of the active layer of the second reset transistor of the fourth sub-pixel via the seventh via; and the eighth connecting pad is connected to the source region of the active layer of the second reset transistor of the fifth sub-pixel via the eighth via.

[0021] For example, at least one embodiment of this disclosure provides a display substrate in which the pixel circuit further includes a third reset transistor, the first terminal of which is connected to a third reset signal line, the second terminal of which is connected to the first terminal of the driving transistor, and is configured to reset the first terminal of the driving transistor using a third reset signal from the third reset signal line; the display substrate further includes a third reset signal connection line, which extends along the second direction and is spaced apart from the first reset signal connection line and the second reset signal connection line in the first direction; the display substrate further includes a third connection structure and a fourth connection structure, the first terminal of the third reset transistor and the third reset signal line are electrically connected to the third connection structure respectively, and the reset signal connection line and the third reset signal line are electrically connected to the fourth connection structure respectively; the sub-pixel further includes a third sub-pixel adjacent to the second sub-pixel in the first direction and a third sub-pixel adjacent to the second sub-pixel in the first direction. A sixth sub-pixel adjacent to three sub-pixels; a portion of the sub-pixels includes a second sub-via, and the third and sixth sub-pixels include and share a second sub-via; the second and third sub-pixels include and share the third connection structure, and the third and sixth sub-pixels include and share the fourth connection structure; the display substrate includes a ninth, a tenth, and an eleventh via, the second and third sub-pixels share a ninth via and a tenth via, and the third and sixth sub-pixels share an eleventh via; the third connection structure is connected to the third reset signal line through the ninth via, and the third connection structure is connected to the source region of the active layer of the third reset transistor of the second sub-pixel and the source region of the active layer of the third reset transistor of the third sub-pixel through the tenth via; the fourth connection structure is connected to the third reset signal line through the eleventh via, and the fourth connection structure is connected to the third reset signal connection line through the second sub-via.

[0022] For example, at least one embodiment of this disclosure provides a display substrate in which a third reset signal line includes a main reset line, a first reset connection pad, and a second reset connection pad. The first reset connection pad and the second reset connection pad protrude from different positions of the main reset line along a second direction. A third connection structure is connected to the first reset connection pad of the third reset signal line through the ninth via, and a fourth connection structure is connected to the second reset connection pad of the third reset signal line through the eleventh via.

[0023] For example, at least one embodiment of this disclosure provides a display substrate, the display substrate including a display area and a bonding area located on one side of the display area; the display area includes a first sub-display area that at least partially overlaps with the bonding area and a second sub-display area located on at least one side of the first sub-display area and not overlapping with the bonding area; both the first sub-display area and the second sub-display area include the sub-pixel; the first sub-display area includes a first data line extending along a first direction and configured to provide a data signal, the driving transistor being configured to control the magnitude of the driving current flowing through the light-emitting device according to the data signal; the second sub-display area includes a second data line and a data transmission line, the data transmission line including a first transmission line and a second transmission line disposed on different layers from each other, the first transmission line extending along the second direction and the second transmission line extending along the first direction; a first end of the first transmission line is connected to the second transmission line through a data via.

[0024] For example, at least one embodiment of this disclosure provides a display substrate in which the first transmission line and the first trace of the second power supply voltage line are disposed on the same layer, and in the second sub-display area, there is a break between the end of the first transmission line in the first direction and the end of the first trace of the second power supply voltage line in the first direction; the first data line, the second transmission line and the first reset signal connection line are disposed on the same layer.

[0025] At least one embodiment of this disclosure provides a display device, which includes any of the display substrates provided in the embodiments of this disclosure. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0027] Figure 1 is a schematic diagram of the pixel array arrangement of a display substrate provided in an embodiment of the present disclosure;

[0028] Figure 2 is a schematic plan view of a display substrate provided in an embodiment of the present disclosure;

[0029] Figure 3 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0030] Figure 4 is a driving timing diagram of the pixel driving circuit shown in Figure 3;

[0031] Figure 5 is another driving timing diagram of the pixel driving circuit shown in Figure 3;

[0032] Figure 6 is a schematic diagram of the structure of a sub-pixel of a display substrate provided in an embodiment of the present disclosure;

[0033] Figure 7 is a schematic cross-section diagram along line AA in Figure 6;

[0034] Figures 8-21 are schematic diagrams of a single layer of the display substrate shown in Figure 6, including the bottom light-shielding layer, the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer, the first insulating layer, the fourth conductive layer, the third insulating layer, the first planarization layer, the fifth conductive layer, the second planarization layer, and the first electrode layer.

[0035] Figures 22-33 are schematic diagrams of the structure after the films shown in Figures 8-21 are stacked sequentially;

[0036] Figure 34 is a schematic diagram of the structure of a sub-pixel of another display substrate provided in an embodiment of the present disclosure;

[0037] Figure 35 is a schematic diagram of a single layer of the first flattening layer in Figure 34;

[0038] Figure 36 is an equivalent circuit diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0039] Figure 37 is a schematic block diagram of a display device provided according to an embodiment of the present disclosure. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. The embodiments described below are some, but not all, embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0041] Unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0042] It should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure all use thin-film transistors as an example for illustration. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one of the terminals is directly described as the first terminal, and the other as the second terminal.

[0043] To achieve better driving performance, pixel circuit designs vary widely. Some pixel circuits have a large number of transistors, such as 7T1C, 8T1C, 8T2C, and 9T1C circuits. A larger number of transistors in a pixel circuit means more film layers in each sub-pixel, requiring more interconnecting vias between these layers. Furthermore, high-resolution display panels have high pixel density, limiting the design space for each sub-pixel. This makes the sub-pixel structure layout design more challenging, making it difficult to ensure that the vias avoid the sub-pixel anode while achieving a reasonable arrangement of sub-pixel structures. Overlapping vias with the anode reduces the anode's flatness, causing defects such as color shift.

[0044] At least one embodiment of this disclosure provides a display substrate, which includes: a substrate, sub-pixels, a first reset signal line, and a first reset signal connection line. A sub-pixel is disposed on the surface of the substrate and includes a pixel circuit. The pixel circuit includes a light-emitting device and a driving transistor. The driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device. The light-emitting device is configured to receive the driving current and be driven by the driving current to emit light. The sub-pixel also includes a first via, a second via, an anode via, an anode connection pad, and a first connection pad. A first reset signal line extends along a first direction. The pixel circuit also includes a first reset transistor. The first electrode of the first reset transistor is electrically connected to the first reset signal line, and the second electrode of the first reset transistor is connected to the first electrode of the light-emitting device. A first reset signal connection line extends along a second direction intersecting the first direction, is configured to transmit a first reset signal, and is electrically connected to the first reset signal line via the first via. The first electrode of the light-emitting device is electrically connected to the anode connection pad through the anode via. The anode connection pad is electrically connected to the first connection pad through the second via. The first connection pad is electrically connected to the active layer of the first reset transistor. The distance between the first via and the second via in the second direction is greater than the distance between the first via and the anode via in the second direction.

[0045] According to the display substrate provided in the embodiments of this disclosure, the first electrode is electrically connected to the anode connection pad via an anode via, thereby placing the position of the first electrode close to the anode via. For a sub-pixel, this increases the space between the first via and the second via in the second direction. This not only increases the design space of the first electrode, which helps to reduce the overlap between the first electrode and the second via in the direction perpendicular to the surface of the substrate, but also provides space for the design of other traces. It allows other traces to be set in the space between the first via and the second via as needed, so as to realize a reasonable layout of the sub-pixel structure using the limited space of each sub-pixel. This is especially true for high-resolution (Pixels Per Inch, PPI) display substrates and cases where there are many transistors, various signal lines, adapter vias, and adapter connection lines that need to be arranged in the space of each sub-pixel.

[0046] At least one embodiment of this disclosure provides a display device, which includes any of the display substrates provided in the embodiments of this disclosure.

[0047] Figure 1 is a schematic diagram of the pixel array arrangement of a display substrate according to an embodiment of the present disclosure. As shown in Figure 1, for example, the display substrate 10 includes a plurality of sub-pixels P arranged in an array, and at least some of the sub-pixels P include light-emitting devices and pixel circuits for driving the light-emitting devices to emit light. For example, the pixel circuit may include a 2T1C (i.e., two transistors and one capacitor) pixel circuit, a 4T2C, a 5T1C, a 7T1C, an 8T1C, an 8T2C, a 9T1C, or an nTmC (n and m are positive integers) pixel circuit. For example, in different embodiments, the pixel circuit may also include a compensation sub-circuit, which may include an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit may include transistors, capacitors, etc. For example, as needed, the pixel circuit may further include a reset circuit, a light-emitting control sub-circuit, a detection circuit, etc.

[0048] For example, as shown in Figure 1, multiple sub-pixels P are located in the display area. For example, in the display substrate 10 provided in some embodiments. For example, a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 constitute a sub-pixel unit, i.e., a repeating unit, and the pixel array includes multiple repeating units arranged in an array. For example, the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 are respectively a red sub-pixel (R) emitting red light, a green sub-pixel (G) emitting green light, a blue sub-pixel (B) emitting blue light, and a green sub-pixel (G) emitting green light. For example, for two adjacent rows of sub-pixels, in the first row, the arrangement order of the sub-pixels in a repeating unit is RGBG, and in the second row, the arrangement order of the sub-pixels in a repeating unit is BGRG. Of course, this is only an example. In other embodiments of this disclosure, it is not limited to a sub-pixel unit including 6 sub-pixels, and the emission colors of multiple sub-pixels are not limited to the situations listed above. Those skilled in the art can adjust the emission colors of each sub-pixel according to actual needs.

[0049] For example, the display substrate 10 is an organic light-emitting diode (OLED) display substrate, and the light-emitting device is an OLED. The display substrate 10 may also include multiple scan lines and multiple data lines to provide scan signals (control signals) and data signals to the multiple sub-pixels, thereby driving the multiple sub-pixels. As needed, the display substrate 10 may further include power lines, detection lines, etc.

[0050] Figure 2 is a schematic plan view of a display substrate provided in an embodiment of this disclosure. Referring to Figure 2, a display substrate 10 provided in at least one embodiment of this disclosure includes a display area AA and a bonding area BB located on one side of the display area AA. The display area AA includes a first sub-display area 01 that at least partially overlaps with the bonding area BB and a second sub-display area 02 located on at least one side of the first sub-display area 01 and not overlapping with the bonding area BB. For example, the dimension L1 of the display area AA along the first direction D1 is greater than the dimension L2 of the bonding area BB along the first direction D1.

[0051] For example, in Figure 2, the second sub-display area 02 is located on both sides of the first sub-display area 01 in the first direction D1. For example, in other embodiments, the second sub-display area may be located only on one side of the first sub-display area in the first direction D1.

[0052] For example, in Figure 2, a portion of the first sub-display area 01 overlaps with the binding area BB in the second direction D2, while another portion of the first sub-display area 01 does not overlap with the binding area BB in the second direction D2. For example, in other embodiments, the entire first sub-display area 01 overlaps with the binding area BB in the second direction D2.

[0053] Referring to Figure 2, for example, both the first sub-display area 01 and the second sub-display area 02 include sub-pixels P. The display substrate includes multiple data signal lines DL, which are configured to provide data signals. The driving transistors of the pixel circuit (described below) are configured to control the magnitude of the driving current flowing through the light-emitting devices of the pixel circuit according to the data signals. The multiple data signal lines DL are at least partially located within the display area AA, extending along the second direction D2 and arranged along the first direction D1. The multiple data signal lines DL include a first data signal line DL1 located in the first sub-display area 01 and a second data signal line DL2 located in the second sub-display area 02. That is, the first sub-display area 01 includes a first data line DL1, which extends along the second direction D2. For example, the first data signal line DL1 can extend along the second direction D2 from the first sub-display area 01 to the bonding area BB to connect with the driving circuit board in the bonding area BB, thereby obtaining data signals from the driving circuit board.

[0054] For example, the display substrate also includes data transmission lines, which include a first transmission line 110 and a second transmission line 120 disposed on different layers. The first transmission line 110 extends along a first direction D1, and the second transmission line 120 extends along a second direction D2; an insulating layer exists between the conductive layer where the first transmission line 110 is located and the conductive layer where the second transmission line 120 is located. Referring to FIG2, for example, the data transmission line is generally zigzag-shaped. The first end of the first transmission line 110 is connected to the second data signal line DL2 through a first data via penetrating the insulating layer to form a first connection point P1, and the second end of the first transmission line 110 is connected to one end of the second transmission line 120 through a second data via penetrating the insulating layer to form a second connection point P2. Both the first connection point P1 and the second connection point P2 are located within the display area AA, thereby, the data signal is transmitted to the second data signal line DL2 via the second transmission line 120 and the first transmission line 110.

[0055] For example, referring to Figure 2, the display area AA may further include a third sub-display area 03 and a fourth sub-display area 04 arranged in the second direction D2. The fourth sub-display area 04 is located on the side of the third sub-display area 03 closest to the binding area BB. For example, the binding area BB is located along the lower edge of the display area AA, and the fourth sub-display area 04 is adjacent to the lower edge of the display area AA. The length of the fourth sub-display area 04 in the second direction D2 is less than the length of the third sub-display area 03 in the second direction D2. For example, the aforementioned data transmission line is located in the fourth sub-display area 04.

[0056] For example, the data transmission line is connected to the second data signal line DL2 and extends to the bonding area BB. The second transmission line 120 extends to the bonding area BB to connect with the drive circuit board in the bonding area BB, thereby obtaining data signals from the drive circuit board and providing the data signals to the second data signal line DL2. For example, the second data signal line DL2 located in the second sub-display area 02 can be led out to the bonding area BB through the data transmission line (through the first transmission line 110 and the second transmission line 120). For example, the above-mentioned fan-out method of adding a data transmission line in the display area can be called display area fan-out (Fanout In AA, FIAA) or pixel fan-out (Fanout In Pixel, FIP).

[0057] The display substrate provided in this embodiment can be a FIP-type display substrate. In this case, the specific structures of the sub-pixels P described below exist in the first sub-display area 01 and the second sub-display area 02, as well as in the third sub-display area 03 and the fourth sub-display area 04. That is to say, for all sub-pixels P in the entire display area AA, the pixel circuit and structural layout of the sub-pixels described below can be adopted.

[0058] Of course, the display substrate provided in this embodiment may not be an FIP type display substrate. In the entire display area, the data lines extend along the second direction D2 and are arranged along the first direction D1. The data lines are arranged in the same way in each sub-pixel P of the display area.

[0059] Figure 3 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of this disclosure. As shown in Figure 3, the pixel circuit has a 9T1C structure and may include nine transistors (first transistor T1 to ninth transistor T9) and one storage capacitor Cst. Each pixel circuit is connected to the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, the fifth scan signal line S5, the first light emission signal line EM1, the second light emission signal line EM2, the first reset signal line Vinit1, the second reset signal line Vinit2, the third reset signal line Vinit3, the data signal line DATA, and the first power supply voltage line VDD.

[0060] It should be noted that in the embodiments disclosed herein, S1 represents both the first scan signal line and the first scan signal, S2 represents both the second scan signal line and the second scan signal, S3 represents both the third scan signal line and the third scan signal, S4 represents both the fourth scan signal line and the fourth scan signal, S5 represents both the fifth scan signal line and the fifth scan signal, EM1 represents both the first light emission signal line and the first light emission control signal, EM2 represents both the second light emission signal line and the second light emission control signal, Vinit1 represents both the first reset signal line and the first reset signal, Vinit2 represents both the second reset signal line and the second reset signal, Vinit3 represents both the third reset signal line and the third reset signal, DATA represents both the data signal line and the data signal, VDD represents both the first power supply voltage line and the first power supply voltage, and VSS represents both the second power supply voltage line and the second power supply voltage.

[0061] For example, referring to Figure 3, each pixel circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. Specifically, the first node N1 is connected to the gate electrode of the third transistor T3, the second electrode of the ninth transistor T9, and the first terminal of the storage capacitor Cst. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The fifth node N5 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the ninth transistor T9. The fourth node N4 is also connected to the first electrode of the light-emitting device EL.

[0062] For example, referring to Figure 3, the first end of the storage capacitor Cst in the pixel circuit is connected to the first node N1, and the second end of the storage capacitor Cst is connected to the first power supply voltage line VDD.

[0063] For example, referring to Figure 3, the first transistor T1 can be called the first reset transistor. The gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first electrode of the first transistor T1 is connected to the second reset signal line Vinit2, and the second electrode of the first transistor T1 is connected to the fifth node N5.

[0064] For example, referring to Figure 3, the second transistor T2 can be called a compensation transistor. The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the fifth node N5, and the second electrode of the second transistor T2 is connected to the third node N3.

[0065] For example, referring to Figure 3, the third transistor T3 serves as a driving transistor, configured to control the magnitude of the driving current flowing through the light-emitting device EL. The light-emitting device EL is configured to receive the driving current and be driven by the driving current to emit light. The gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0066] For example, referring to Figure 3, the fourth transistor T4 is used as a data writing transistor. The gate electrode of the fourth transistor T4 is connected to the second scan signal line S2, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0067] For example, referring to Figure 3, the fifth transistor T5 serves as the first light-emitting control transistor. The gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply voltage line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0068] For example, referring to Figure 3, the sixth transistor T6 serves as the second light-emitting control transistor. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0069] For example, referring to Figure 3, the seventh transistor T7 serves as the second reset transistor. The gate electrode of the seventh transistor T7 is connected to the fourth scan signal line S4, the first electrode of the seventh transistor T7 is connected to the first reset signal line Vinit1, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0070] For example, referring to Figure 3, the eighth transistor T8 serves as the third reset transistor. The gate electrode of the eighth transistor T8 is connected to the fifth scan signal line S5, the first electrode of the eighth transistor T8 is connected to the third reset signal line Vinit3, and the second electrode of the eighth transistor T8 is connected to the second node N2.

[0071] For example, referring to Figure 3, the gate electrode of the ninth transistor T9 is connected to the second scan signal line S2, the first electrode of the ninth transistor T9 is connected to the fifth node N5, and the second electrode of the ninth transistor T9 is connected to the first node N1.

[0072] For example, referring to Figure 3, the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power supply voltage line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode.

[0073] For example, referring to Figure 3, the signal of the first power supply voltage line VDD is a continuously supplied high-level signal, and the signal of the second power supply voltage line VSS is a continuously supplied low-level signal.

[0074] In some possible exemplary embodiments, the first transistor T1 to the ninth transistor T9 in the pixel circuit can be a P-type transistor or an N-type transistor. In other possible exemplary embodiments, the first transistor T1 to the ninth transistor T9 in the pixel circuit can include both P-type and N-type transistors.

[0075] The active layer of the low-temperature polycrystalline silicon (LTPS) transistor is made of LTPS, while the active layer of the oxide transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and oxide transistors on a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate allows for the utilization of the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality. In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 in the pixel circuit can be either LTPS transistors or oxide transistors. Alternatively, the transistor connected to the gate of the driving transistor T3 can be an oxide transistor, while the other transistors can be LTPS transistors, to improve the stability of the gate signal of the driving transistor T3.

[0076] In the embodiment shown in Figure 3, the first transistor T1 and the second transistor T2 in the pixel circuit are oxide transistors and are N-type transistors, and the third transistor T3 to the ninth transistor T9 are low-temperature polysilicon transistors and are P-type transistors.

[0077] Figure 4 is a driving timing diagram of the pixel driving circuit shown in Figure 3. As shown in Figure 4, in an exemplary embodiment, the operation of the pixel driving circuit may include:

[0078] The first stage, A1, can be referred to as the reset stage of the second node N2 and the fourth node N4. The signals of the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4, and the fifth scan signal line S5 are low-level signals, while the signals of the second scan signal line S2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, which turns on the seventh transistor T7 and the eighth transistor T8, and turns off the other transistors.

[0079] The seventh transistor T7 is turned on, providing the signal of the first reset signal line INIT2 to the fourth node N4, initializing (resetting) the first electrode of the light-emitting device EL, clearing the original charge in the first electrode of the light-emitting device EL, and setting the potential of the fourth node N4 to Vinit2. The eighth transistor T8 is turned on, providing the signal of the third reset signal line INIT3 to the second node N2, initializing (resetting) the second node N2, and setting the potential of the second node N2 to Vinit3.

[0080] The second stage, A2, can be called the first node N1 reset stage. The signal on the first scan signal line S1 is a low-level signal. The signal on the second scan signal line S2 appears low-level twice and high-level for the rest of the time. The signals on the third scan signal line S3, the fourth scan signal line S4, the fifth scan signal line S5, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, which turns on the first transistor T1. The fourth transistor T4 and the ninth transistor T9 are turned on twice, and the other transistors are turned off.

[0081] The first transistor T1 is turned on, providing the signal of the second reset signal line INIT1 to the fifth node N5. When the fourth transistor T4 and the ninth transistor T9 are turned on, the signal of the second reset signal line INIT1 is provided to the first node N1 to initialize (reset) the first node N1, clearing the original charge in the first node N1. The potential of the first node N1 is Vinit1. Since the ninth transistor T9 is a low-temperature polysilicon transistor, before the ninth transistor T9 is turned on for the first time, it is affected by the potential of the first node N1 and the gate bias voltage. The potential of the first node N1 is related to the data voltage of the previous stage, so the characteristics of the ninth transistor T9 are affected by the previous stage. After the ninth transistor T9 is turned on for the first time, the potential of the first node N1 is reset to Vinit1. The gate voltage of the ninth transistor T9 is relatively fixed whether it is high or low level. Therefore, after the first turn-on and turn-off, the influence of the previous stage data on the characteristics of the ninth transistor T9 can be cleared. When the ninth transistor T9 is turned on for the second time, the potential of the first node N1 is reset to Vinit1 again. This disclosure, by resetting the first node N1 twice consecutively, can better eliminate the influence of the data voltage from the previous stage on the characteristics of the ninth transistor T9, thereby improving image retention and low grayscale image quality. Furthermore, because the fourth transistor T4 is turned on twice in this stage, the data signal line DATA writes the data voltage of the first few cell rows to the second node N2. This changes the potential of the second node N2, thus changing the gate-source voltage of the third transistor T3. The characteristics of the third transistor T3 are reset, which can further improve image retention.

[0082] The third stage, A3, can be called the third node N3 reset stage. The signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, the fifth scan signal line S5, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, which turns on the first transistor T1 and the second transistor T2, and turns off the other transistors.

[0083] The second transistor T2 turns on, causing the third node N3 and the fifth node N5 to turn on. The first transistor T1 turns on, causing the signal of the second reset signal line INIT1 to be provided to the third node N3, which initializes (resets) the third node N3, clears the original charge in the third node N3, and makes the potential of the third node N3 Vinit1.

[0084] The fourth stage, A4, can be called the data writing stage. The signal on the third scan signal line S3 is a low-level signal, the signal on the second scan signal line S2 is a low-level signal for a short period of time, and the signals on the first scan signal line S1, the fourth scan signal line S4, the fifth scan signal line S5, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, which turns on the second transistor T2, the fourth transistor T4, and the ninth transistor T9, while turning off the other transistors.

[0085] The conduction of the second transistor T2 turns on the third node N3 and the fifth node N5, and the conduction of the ninth transistor T9 turns on the first node N1 and the fifth node N5. Since the third transistor T3 remains on during this stage, the fourth transistor T4 turns on, allowing the data signal output from the data signal line DATA to be supplied to the first node N1 via the second node N2, the conducting third transistor T3, the third node N3, the conducting second transistor T2, the fifth node N5, and the conducting ninth transistor T9. The difference between the data voltage output from the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage at the first node N1 is Vd1 - |Vth|, where Vd is the data voltage output from the data signal line DATA, and Vth is the threshold voltage of the third transistor T3. When the ninth transistor T9 is off, the storage capacitor Cst maintains the data voltage.

[0086] The fifth stage, A5, can be referred to as the reset stage for the second node N2, the third node N3, and the fourth node N4. The signals on the first scan signal line S1 and the third scan signal line S3 are low-level signals. The signals on the fourth scan signal line S4 and the fifth scan signal line S5 are successively low-level signals for a short period. The signals on the second scan signal line S2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, turning on the seventh transistor T7 and the eighth transistor T8, while turning off the other transistors.

[0087] When the seventh transistor T7 is turned on, the signal of the first reset signal line INIT2 is provided to the fourth node N4. Since the third transistor T3 remains on during this stage, the eighth transistor T8 is turned on, providing the signal of the third reset signal line INIT3 to the second node N2 and the third node N3, resetting the second node N2, the third node N3, and the fourth node N4 respectively. The potentials of the second node N2 and the third node N3 are Vinit3, and the potential of the fourth node N4 is Vinit2. This stage of resetting the second node N2, the third node N3, and the fourth node N4 can eliminate and improve the hysteresis deviation caused by grayscale differences between adjacent pixels, reducing the hysteresis deviation. It can also periodically reset the OLED anode, improving low-frequency flicker.

[0088] The sixth stage, A6, can be referred to as the reset stage of the second node N2 and the third node N3. The signals of the first scan signal line S1, the third scan signal line S3, and the first light-emitting signal line EM1 are low-level signals, while the signals of the second scan signal line S2, the fourth scan signal line S4, the fifth scan signal line S5, and the second light-emitting signal line EM2 are high-level signals, which turns on the fifth transistor T5 and turns off the other transistors.

[0089] The fifth transistor T5 is turned on, so that the power supply voltage Vdd output from the first power supply voltage line VDD is provided to the second node N2 and the third node N3, resetting the second node N2 and the third node N3, that is, resetting the first and second terminals of the third transistor T3.

[0090] The seventh stage, A7, can be called the light-emitting stage. The signals of the first scan signal line S1, the third scan signal line S3, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, while the signals of the second scan signal line S2, the fourth scan signal line S4, and the fifth scan signal line S5 are high-level signals, which turns on the fifth transistor T5 and the sixth transistor T6, while turning off the other transistors.

[0091] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply voltage line VDD provides a driving voltage to the first electrode of the light-emitting device EL through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T6, driving the light-emitting device EL to emit light.

[0092] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage of the first node N1 is Vd - |Vth|, the driving current of the third transistor T3 is: I = K*(Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[Vdd-Vd] 2

[0093] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device EL, K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0094] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 in each pixel driving circuit is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product, and improving the display effect of the entire display product.

[0095] Figure 5 is another driving timing diagram of the pixel driving circuit shown in Figure 3. As shown in Figure 5, in the exemplary embodiment, the operation of the pixel driving circuit is basically the same as that in Figure 4, except that: in the first stage A1, the signals of the fourth scan signal line S4 and the fifth scan signal line S5 are high-level signals, the seventh transistor T7 and the eighth transistor T8 are off, and the second node N2 and the fourth node N4 are not reset in this stage. In the fifth stage A5, before the seventh transistor T7 and the eighth transistor T8 are turned on, the second scan signal line S2 is a low-level signal for a short period of time, the fourth transistor T4 and the ninth transistor T9 are turned on again, the fourth transistor T4 turns on so that the data voltage of the next unit row resets the second node N2 and the third node N3, the ninth transistor T9 turns on so that the first node N1 and the fifth node N5 are turned on, after the charge of the two nodes is neutralized, there is no longer a potential difference between the two nodes.

[0096] Figure 6 is a schematic diagram of the structure of a sub-pixel of a display substrate provided in an embodiment of the present disclosure. Figure 7 is a cross-sectional schematic diagram along line AA in Figure 6. Figures 8-21 are schematic diagrams of a single layer of the display substrate shown in Figure 6, namely, the light-shielding layer BSM, the first semiconductor layer Poly, the first conductive layer Gate1, the second conductive layer Gate2, the second semiconductor layer IGZO, the third conductive layer Gate3, the first insulating layer ILD, the fourth conductive layer SD1, the second insulating layer PVX, the first planarization layer PLN1, the fifth conductive layer SD2, the second planarization layer PLN2, and the first electrode layer AND.

[0097] To clearly illustrate the relative positions of the stacked layers, Figure 22 shows a schematic diagram of the light-shielding layer BSM stacked with the first semiconductor layer Poly; Figure 23 shows a schematic diagram of the light-shielding layer BSM stacked with the first semiconductor layer Poly and the first conductive layer Gate1; Figure 24 shows a schematic diagram of the light-shielding layer BSM stacked with the first semiconductor layer Poly, the first conductive layer Gate1, and the second conductive layer Gate2; Figure 25 shows a schematic diagram of the light-shielding layer BSM stacked with the first semiconductor layer Poly, the first conductive layer Gate1, the second conductive layer Gate2, and the second semiconductor layer IGZO; and Figure 26 shows a schematic diagram of the light-shielding layer BSM stacked with the first semiconductor layer Poly, the first conductive layer Gate1, and the second conductive layer Gate2. 2. A schematic diagram of the superposition of the second semiconductor layer IGZO and the third conductive layer Gate3. Figure 27 is a schematic diagram of the superposition of the light-shielding layer BSM with the first semiconductor layer Poly, the first conductive layer Gate1, the second conductive layer Gate2, the second semiconductor layer IGZO, the third conductive layer Gate3, and the first insulating layer ILD. Figure 28 is a schematic diagram of the superposition of the light-shielding layer BSM with the first semiconductor layer Poly, the first conductive layer Gate1, the second conductive layer Gate2, the second semiconductor layer IGZO, the third conductive layer Gate3, and the first insulating layer ILD. Figure 29 is a schematic diagram of the superposition of the light-shielding layer BSM with the first semiconductor layer Poly, the first conductive layer Gate1, the second conductive layer Gate2, and the second semiconductor layer IGZO. Figure 30 is a schematic diagram showing the superposition of the light-shielding layer BSM with the first semiconductor layer Poly, the first conductive layer Gate1, the second conductive layer Gate2, the second semiconductor layer IGZO, the third conductive layer Gate3, the first insulating layer ILD, the fourth conductive layer SD1, and the second insulating layer PVX. Figure 31 is a schematic diagram showing the superposition of the light-shielding layer BSM with the first semiconductor layer Poly, the first conductive layer Gate1, the second conductive layer Gate2, the second semiconductor layer IGZO, the third conductive layer Gate3, the first insulating layer ILD, the fourth conductive layer SD1, the second insulating layer PVX, and the first planarization layer PLN1. Figure 32 is a schematic diagram of the light-shielding layer BSM superimposed with the first semiconductor layer Poly, the first conductive layer Gate1, the second conductive layer Gate2, the second semiconductor layer IGZO, the third conductive layer Gate3, the first insulating layer ILD, the fourth conductive layer SD1, the second insulating layer PVX, the first planarization layer PLN1, and the fifth conductive layer SD2. Figure 33 is a schematic diagram of the light-shielding layer BSM superimposed with the first semiconductor layer Poly, the first conductive layer Gate1, the second conductive layer Gate2, the second semiconductor layer IGZO, the third conductive layer Gate3, the first insulating layer ILD, the fourth conductive layer SD1, the second insulating layer PVX, the first planarization layer PLN1, the fifth conductive layer SD2, and the second planarization layer PLN2.Figure 6 is a schematic diagram of the first electrode layer AND superimposed on the basis of Figure 33.

[0098] The structure of the sub-pixel P of the display substrate provided in at least one embodiment of this disclosure will be exemplarily described below, taking the pixel circuit shown in Figure 3 as an example and in conjunction with Figures 8-33.

[0099] In this embodiment, the first transistor T1 and the second transistor T2 in the pixel circuit are oxide transistors, and the third transistor T3 to the ninth transistor T9 are low-temperature polysilicon transistors.

[0100] For example, referring to Figures 6 and 7, the display substrate 10 includes: a substrate Sub, the aforementioned sub-pixel P, a first reset signal line Vinit1, and a reset signal connection line Vinit0. The sub-pixel P is disposed on the surface of the substrate Sub and includes the aforementioned pixel circuit. For example, each sub-pixel P that performs display functions further includes a first via V1, a second via V2, an anode via V0, an anode connection pad C0, and a first connection pad C1.

[0101] Referring to Figures 1 and 6, the plurality of sub-pixels P includes a first sub-pixel P1 and a second sub-pixel P2 that are adjacent to each other in the first direction D1, and a third sub-pixel P3 that is adjacent to the second sub-pixel P2 in the first direction D1 and located on the side of the second sub-pixel P2 away from the first sub-pixel P1. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are arranged sequentially and continuously in the first direction D1. The display substrate also includes a pixel defining layer PDL (refer to Figure 7), which includes a plurality of openings, each opening exposing the light-emitting area of ​​a sub-pixel. The first electrode EL1 is at least partially located within the light-emitting area.

[0102] For ease of distinction, V21 represents the second via of the first sub-pixel P1, V22 represents the second via of the second sub-pixel P2, V23 represents the second via of the third sub-pixel P3, V01 represents the anode via of the first sub-pixel P1, V02 represents the anode via of the second sub-pixel P2, and V03 represents the anode via of the third sub-pixel P3.

[0103] Referring to Figures 6, 13, and 29, the first reset signal line Vinit1 extends along the first direction D1. The pixel circuit also includes a first reset transistor T7, i.e., the aforementioned seventh transistor T7 serves as the first reset transistor. The first terminal of the first reset transistor T7 is electrically connected to the first reset signal line Vinit1, and the second terminal of the first reset transistor T7 is connected to the first electrode EL1 of the light-emitting device EL. Referring to Figure 19, the first reset signal connection line Vinit0 extends along the second direction D2 intersecting the first direction D1, is configured to provide a first reset signal, and is electrically connected to the first reset signal line Vinit1 via the first via V1, so that the first reset signal line Vinit1 receives the first reset signal Vinit1 from the first reset signal connection line Vinit0. The first reset signal line Vinit1 is configured to reset the first electrode EL1 of the light-emitting device EL using the first reset signal Vinit1.

[0104] The first reset signal connection line Vinit0 and the first reset signal line Vinit1 are configured on different layers. The first reset signal Vinit0 provides the first reset signal Vinit1 to the first reset signal line Vinit1, and the first reset signal Vinit1 is provided to the first terminal of the first reset transistor of the sub-pixel via the first reset signal line Vinit1. Similarly, the second reset signal line and the third reset signal line described below are electrically connected to the second reset signal connection line and the third reset signal connection line via vias, respectively, so as to obtain the second reset signal Vinit2 and the third reset signal Vinit3 via the second reset signal connection line and the third reset signal connection line, respectively, thereby providing the second reset signal and the third reset signal to multiple sub-pixels respectively via the second reset signal line and the third reset signal line.

[0105] For example, the first reset signal Vinit1, the second reset signal Vinit2, and the third reset signal Vinit3 are different signals from different reset signal sources. Alternatively, in other embodiments, the first reset signal Vinit1, the second reset signal Vinit2, and the third reset signal Vinit3 may also be the same signal from the same reset signal source.

[0106] Referring to Figures 6, 16, and 18-21, the first electrode EL1 of the light-emitting device EL is electrically connected to the anode connecting pad C0 through the anode via V0. The anode connecting pad C0 is electrically connected to the first connecting pad C1 through the second via V2. The first connecting pad C1 is electrically connected to the active layer T7a of the first reset transistor T7 (refer to Figure 9). The distance d3 between the first via V1 and the second via V2 (e.g., the second via V22 or the second via V21) in the second direction D2 is greater than the distance d4 between the first via V1 and the anode via V0 in the second direction D2. For example, referring to Figure 6, the distance d1 between the first via V1 and the second via V2 (e.g., the second via V22 or the second via V21) in the second direction D2 is greater than the distance d5 between the first via V1 and the anode via V0 (e.g., the anode via V01) in the second direction D2. For example, distances d1 and d3 may be equal; however, in other embodiments, d1 and d3 may not be equal.

[0107] For example, for each row of sub-pixels, various distance relationships between the first via V1, the second via V2, and the anode via V0 as described in the embodiments of this disclosure are satisfied.

[0108] Specifically, for example, referring to Figure 6, the distance between the first via V1 and the second via V21 of the first sub-pixel P1 in the second direction D2, and the distance between the first via V1 and the second via V22 of the second sub-pixel P2 in the second direction D2 are both greater than the distance between the first via V1 and the anode via V02 of the second sub-pixel P2 in the second direction D2, and both are greater than the distance between the first via V1 and the anode via V01 of the first sub-pixel P1 in the second direction D2.

[0109] It should be noted that the distance between two holes in this disclosure refers to the distance between the geometric centers of the orthographic projections of the two holes onto the surface of the substrate, or the distance between the closest edges or points of the orthographic projections of the two holes onto the surface of the substrate.

[0110] According to the display substrate 10 provided in the embodiments of this disclosure, the first electrode EL is electrically connected to the anode connection pad C0 via the anode via V0, thereby the position of the first electrode EL is close to the anode via V0. For a sub-pixel, since the distance between the first via V1 and the second via V2 in the second direction D2 is greater than the distance between the first via V1 and the anode via V0 in the second direction D2, the space between the first via V1 and the second via V2 in the second direction D2 is increased. This not only increases the design space of the first electrode EL, which is beneficial to reduce the degree of overlap between the first electrode EL and the second via V2 in the direction perpendicular to the surface of the substrate Sub (hereinafter referred to as the vertical direction), but also provides space for the design of other traces, allowing other traces to be set in the space between the first via V1 and the second via V2 as needed, so as to realize the reasonable layout of the sub-pixel structure by utilizing the limited space of each sub-pixel, especially for high-resolution (Pixels Per Inch, abbreviated as PPI) display substrates and the case where there are many transistors, various signal lines, adapter vias, and adapter connection lines that need to be arranged in the space of each sub-pixel.

[0111] As described above, the display substrate 10 includes a pixel array, which includes a plurality of sub-pixels P arranged in an array. For example, referring to Figures 1 and 6, the first sub-pixel P1 and the second sub-pixel P2 share a first via V1, that is, the first via V1 in Figure 6 belongs to both the first sub-pixel P1 and the second sub-pixel P2. The first via V1 is located in the boundary region of the first sub-pixel P1 and the second sub-pixel P2 in the second direction D2 to save space. For example, referring to Figures 6 and 18, the distance d1 between the first via V1 and the second via V21 of the first sub-pixel P1 in the second direction D2 is greater than the distance d5 between the first via V1 and the anode via V01 of the first sub-pixel P1 in the second direction D2; and the distance d2 between the first via V1 and the second via V22 of the second sub-pixel P2 in the second direction D2 is greater than the distance d4 between the first via V1 and the anode via V02 of the second sub-pixel P2 in the second direction D2.

[0112] It should be noted that, for example, both the first sub-pixel P1 and the second sub-pixel P2 include the aforementioned pixel circuit, and thus each has the aforementioned second via V2, first electrode EL1, anode via V0, and various signal lines, etc. For the connection relationships of each structure in each sub-pixel, the structural relationships of each transistor, signal line, and connection line will be described using one sub-pixel as an example, without repeating the description for each sub-pixel. Therefore, the connection relationships and functions of the same components in different sub-pixels within their respective sub-pixels, as well as their relative positions within each sub-pixel, are the same. For example, the connection relationship of the second via V21 in the first sub-pixel P1 is the same as the connection relationship of the second via V22 in the second sub-pixel P2. For example, in the embodiment shown in Figure 6, adjacent sub-pixel substrates are mirror-symmetrical, so that adjacent sub-pixels can share some structures, thereby saving space. The pixel array includes multiple pixel columns and multiple pixel rows. Each pixel column extends along a second direction D2, and each pixel row extends along a first direction D1. Within the same pixel column, the structure of each sub-pixel constitutes a repeating unit, and the same pixel column includes multiple repeating units. Of course, in other embodiments, each sub-pixel can also serve as a repeating unit in both each sub-pixel column and each sub-pixel row.

[0113] For example, in the second direction D2, at least a portion of the anode via of the first sub-pixel is located between the first via and the second via of the first sub-pixel. In the embodiments shown in Figures 6, 18, and 20, in the second direction D2, the entire anode via V01 of the first sub-pixel P1 is located between the first via V1 and the second via V21 of the first sub-pixel P1. Furthermore, the anode via V02 of the second sub-pixel P2 is located on the side of the first via V1 away from the second via V22 of the second sub-pixel P2. This allows for the anode vias of adjacent first sub-pixels and second sub-pixels to be staggered in the second direction D2 and for the distance between them to be increased. This provides more space for the design of the first electrode EL1 of consecutively adjacent first sub-pixels P1, second sub-pixels P2, and third sub-pixels P3, ensuring that the first electrodes of these three sub-pixels avoid overlapping with the second vias V21 of the first sub-pixel P1, V22 of the second sub-pixel P2, and V23 of the third sub-pixel P3 below the first electrode. This improves the flatness of the first electrode of each sub-pixel, thereby reducing defects such as color shift in the display substrate.

[0114] For example, the area of ​​the first electrode EL13 of the third sub-pixel P3 is larger than the area of ​​the first electrode EL11 of the first sub-pixel P1 and larger than the area of ​​the first electrode EL12 of the second sub-pixel P2. That is, the area of ​​the first electrode EL13 of the third sub-pixel P3 is the largest, and the area of ​​the first electrode EL11 of the first sub-pixel P1 is the second largest. Therefore, the design of increasing the distance between the first via V1 and the second via V2 in the second direction D2 for a sub-pixel, thereby increasing the space between the first via V1 and the second via V2 in the second direction D2, and the design of staggering the anode vias of adjacent first sub-pixels and second sub-pixels in the second direction D2 can especially reduce the overlap area of ​​the first electrode EL13 of the largest sub-pixel P3 with the second via V22 of the second sub-pixel P2 and the second via V23 of the third sub-pixel P3 located below it. In practical applications, it is difficult to solve the technical problem of the overlap between the first electrode EL13 of the largest sub-pixel P3 and the second via V22 of the second sub-pixel P2 and the second via V23 of the third sub-pixel P3 located below it.

[0115] In the display substrate 10 provided in this embodiment, at least a portion of the orthogonal projection of at least one of the second via V22 of the second sub-pixel P2 and the second via V23 of the third sub-pixel P3 onto the surface of the substrate Sub does not overlap with the orthogonal projection of the first electrode EL13 of the light-emitting device EL of the third sub-pixel P3 onto the surface of the substrate Sub. Referring to Figures 6 and 7, the first electrode EL13 of the third sub-pixel P3 overlaps with a portion of the second via V22 of the second sub-pixel P2 in a direction perpendicular to the surface of the substrate Sub, but does not overlap with a portion of the second via V22 of the second sub-pixel P2 in a direction perpendicular to the surface of the substrate Sub, thereby improving the flatness of the first electrode of the third sub-pixel and reducing defects such as color shift in the display substrate. Furthermore, the fact that the first electrode EL13 of the third sub-pixel P3 overlaps with a portion of the second via V23 of the third sub-pixel P3 in a direction perpendicular to the surface of the substrate Sub, but does not overlap with a portion of the second via V23 of the third sub-pixel P3 in a direction perpendicular to the surface of the substrate Sub, further improves the flatness of the first electrode of the third sub-pixel. In some other embodiments, it is even possible to ensure that the first electrode EL13 of the third sub-pixel P3 and the entire second via V22 of the second sub-pixel P2 do not overlap in a direction perpendicular to the surface of the substrate Sub (described below).

[0116] For example, the overlapping portion of the second via V22 of the second sub-pixel P2 and the orthographic projection of the first electrode EL13 of the light-emitting device EL of the third sub-pixel P3 onto the surface of the substrate Sub, and the overlapping portion of the second via V23 of the third sub-pixel P3 and the orthographic projection of the first electrode EL13 of the light-emitting device EL of the third sub-pixel P3 onto the surface of the substrate Sub are symmetrical with respect to the axis of symmetry extending along the second direction D2, so as to facilitate the uniformity of light emission at the boundary position of the light-emitting area of ​​the third sub-pixel P3.

[0117] For example, the first sub-pixel P1 is a red sub-pixel (R) that emits red light, the second sub-pixel P2 is a green sub-pixel (G) that emits green light, the third sub-pixel P3 is a blue sub-pixel (B) that emits blue light, and the fourth sub-pixel is a green sub-pixel (G) that emits green light. Corresponding to the schematic block diagram in Figure 1, this application uses an RGBG pixel arrangement in a pixel row as an example. Of course, the emission color of each sub-pixel is not limited to this case.

[0118] For example, the light-emitting device EL is an electroluminescent device, such as an organic light-emitting diode (OLED) device; for example, the first electrode is an anode. Of course, in other embodiments, the light-emitting device EL can also be other types of light-emitting devices, such as inorganic light-emitting diodes, etc.

[0119] For example, referring to Figures 6 and 18, the distance d3 between the first via V1 and the second via V22 of the second sub-pixel P2 in the second direction D2 is 3 to 5 times the distance d4 between the first via V1 and the anode via V02 of the second sub-pixel P2 in the second direction D2. Based on experimental design, this numerical range achieves good space utilization, utilizing limited space for arrangement, and ensuring that part or all of the second vias V22 and V23 do not overlap with the first electrode EL13 of the third sub-pixel P3.

[0120] For example, in the embodiment shown in Figure 6, as shown in Figures 6 and 18, in the second direction D2, the entire anode via V01 of the first sub-pixel P1 is located between the first via V1 and the second via V21. In this case, the distance d1 between the first via V1 and the second via V21 of the first sub-pixel P1 in the second direction D2 is 5 to 8 times the distance d5 between the first via V1 and the anode via V01 of the first sub-pixel P1 in the second direction D2. According to experimental design exploration, a better space utilization effect can be achieved within this numerical range, utilizing limited space arrangement, and ensuring that part or all of the second vias V22 and V23 do not overlap with the first electrode EL13 of the third sub-pixel P3.

[0121] For example, referring to Figures 6, 18, and 19, the orthographic projection of the first via V1 on the surface of the substrate Sub at least partially overlaps with the orthographic projection of the first reset signal connection line Vinit0 on the surface of the substrate Sub. The first reset signal connection line Vinit0 is located between the first sub-pixel P1 and the second sub-pixel P2 in the second direction D2. The first sub-pixel P1 and the second sub-pixel P2 share the first reset signal connection line Vinit0 and the first via V1. The second via V21 of the first sub-pixel P1 and the second via V22 of the second sub-pixel P2 are substantially symmetrical with respect to the first reset signal connection line Vinit0 to save space.

[0122] For example, referring to Figures 6 and 16, the sub-pixel also includes a first connection structure CS1, and the reset signal connection line Vinit0 and the first electrode of the first reset transistor T7 are electrically connected to the first connection structure CS1, thereby realizing the electrical connection of the first electrode of the first reset transistor T7 to the reset signal connection line Vinit0 through the first connection structure CS1.

[0123] In a direction perpendicular to the surface of the substrate Sub, the first connection structure CS1 is located between the first reset signal line Vinit1 and the first reset signal connection line Vinit0. For example, the first reset signal connection line Vinit0 is located on the side of the first reset signal line Vinit1 away from the substrate Sub. For example, the first reset signal line Vinit1 is located in the third conductive layer Gate3, the first connection structure CS1 is located in the fourth conductive layer SD1, and the first reset signal connection line Vinit0 is located in the fifth conductive layer SD2.

[0124] Specifically, referring to Figures 6 and 16, the first connection structure CS1 extends generally along the first direction D1, including a connection body CB extending along the first direction D1, a second connection pad C2 connected to the connection body and protruding from the connection body CB along the second direction D2 toward the second via V21 / V22, and a third connection pad C3 and a fourth connection pad C4 located at opposite ends of the connection body CB in the first direction D1. Referring to Figures 19 and 32, the orthographic projection of the first via V1 onto the surface of the substrate Sub at least partially overlaps with the orthographic projection of the second connection pad C2 onto the surface of the substrate Sub. The first reset signal connection line Vinit0 is connected to the second connection pad C2 via the first via V1. The first reset signal connection line Vinit0 includes a fifth connection pad C5, which is connected to the second connection pad C2 via the first via V1. For the first sub-pixel P1, the third connecting pad C3 is connected to both the first reset signal line Vinit1 and the source region of the active layer T7a of the first reset transistor T7 (meaning connected to the source region of the active layer of the first reset transistor T7 in the first semiconductor layer Poly), thereby electrically connecting the first reset signal line Vinit1 and the first electrode of the first reset transistor T7 through the third connecting pad C3. This achieves the electrical connection of the first electrode of the first reset transistor T7 to the first reset signal connection line Vinit0, so as to receive the first reset signal Vinit1 from the first reset signal connection line Vinit0. For the second sub-pixel P2, the fourth connecting pad C4 of the first connecting structure CS1 is connected to both the first reset signal line Vinit1 and the source region of the active layer T7a of the first reset transistor T7. In other words, the fourth connecting pad C4 of the first connecting structure CS1 performs the same function as the third connecting pad C3 in the first sub-pixel P1, and in the same way, electrically connects the first electrode of the first reset transistor T7 of the second sub-pixel P2 to the reset signal connection line through the fourth connecting pad C4 of the first connecting structure CS1. Therefore, the first sub-pixel P1 and the second sub-pixel P2 share a first connection structure CS1.

[0125] For example, referring to Figures 16 and 27-29, two drilling processes are used to form ILD vias and EBB vias penetrating the first insulating layer (ILD) at different locations. The depths of the ILD vias and EBB vias are different, resulting in different exposed film structures. The film exposed by the ILD vias is closer to the substrate (Sub) than the film exposed by the EBB vias; for example, the depth of the ILD vias is greater than the depth of the EBB vias.

[0126] For example, each sub-pixel includes a fourth via V41 / V42 penetrating the first insulating layer ILD and a fifth via V51 / V52 penetrating the first insulating layer ILD. The first reset signal connection line Vinit0 is connected to the second connection pad C2 of the first connection structure CS via the first via V1; the third connection pad C3 of the first connection structure CS1 is electrically connected to the first reset signal line Vinit1 via the fourth via V41 of the first sub-pixel P1, and the third connection pad C3 of the first connection structure CS1 is electrically connected to the first electrode of the first reset transistor T7 of the first sub-pixel P1 via the fifth via V51 of the first sub-pixel P1; the fourth connection pad C4 of the first connection structure CS1 is electrically connected to the first reset signal line Vinit1 via the fourth via V42 of the second sub-pixel P2, and the fourth connection pad C4 of the first connection structure CS1 is electrically connected to the first electrode of the first reset transistor T7 of the second sub-pixel P2 via the fifth via V52 of the second sub-pixel P2. The fourth via V42 is the aforementioned EBB via, exposing a portion of the first reset signal line Vinit1 located in the third conductive layer Gate3; the fifth via V51 / V52 is the aforementioned ILD via, exposing a portion of the first semiconductor layer Poly.

[0127] For example, the first connecting structure CS1 is axially symmetric with respect to an axis of symmetry extending along the second direction D2; for example, the third connecting pad C3 and the fourth connecting pad C4 of the first connecting structure CS1 are symmetric with respect to this axis of symmetry, for example, the axis of symmetry passes through the second connecting pad C2.

[0128] For example, referring to FIG19, the width of the fifth connection pad C5 of the first reset signal connection line Vinit0 in the first direction D1 is greater than the width of the strip portion of the first reset signal connection line Vinit0 extending along the second direction D2 in the first direction D1, excluding the fifth connection pad C5. The orthographic projection of the first via V1 on the surface of the substrate Sub at least partially overlaps with the orthographic projection of the fifth connection pad C5 on the surface of the substrate Sub, so as to ensure that the fifth connection pad C5 is electrically connected to the first reset signal line Vinit1 via the first via V1.

[0129] Similarly, for example, referring to Figures 6 and 19, the display substrate 10 further includes a second reset signal connection line Vinit01. For example, the second reset signal connection line Vinit01 extends along a second direction D2 and is spaced apart from the aforementioned first reset signal connection line Vinit0 in a first direction D1. Referring to Figures 16 and 29, a portion of the multiple sub-pixels further includes a second connection structure CS2. The first terminals of the second reset signal connection line Vinit01 and the second reset transistor T1 (the first transistor T1 is used as the second reset transistor) are electrically connected to the second connection structure CS2, thereby electrically connecting the first terminal of the second reset transistor T1 to the second reset signal connection line Vinit01 through the second connection structure CS2.

[0130] For example, referring to Figure 6, the multiple sub-pixels also include a fourth sub-pixel P4 and a fifth sub-pixel P5 that are adjacent in the first direction D1. The fourth sub-pixel P4 and the fifth sub-pixel P5 are adjacent to the first sub-pixel P1 in the first direction D1 and are located on the side of the first sub-pixel P1 away from the second sub-pixel P2. The fourth sub-pixel P4 and the fifth sub-pixel P5 include a second connection structure CS2 and share a second connection structure CS2.

[0131] Specifically, referring to Figures 6 and 16, the second connection structure CS2 is disposed in the same layer as the first connection structure CS1 and is also located in the fourth conductive layer SD1. It includes a first strip portion SCP1 extending along the first direction D1, a second strip portion SCP2 connected to the first strip portion SCP1 and extending along the second direction D2 toward the first via V1, a sixth connection pad C6 located at the end of the second strip portion SCP2 away from the first strip portion SCP1 in the second direction D2, and a seventh connection pad C7 and an eighth connection pad C8 located at both ends of the first strip portion SCP1 in the first direction D1, respectively. Referring to Figures 16, 18, 19, and 31, the orthographic projection of the first via V1 (i.e., the first via V1 on the left in Figure 31) corresponding to the fourth sub-pixel P4 and the fifth sub-pixel P5 on the surface of the substrate Sub at least partially overlaps with the orthographic projection of the sixth connection pad C6 on the surface of the substrate Sub.

[0132] For example, referring to Figures 6, 18, and 31, some sub-pixels include a first sub-via V1a, and the fourth sub-pixel P4 and the fifth sub-pixel P5 share a first sub-via V1a; the fifth connecting pad C5 of the second reset signal connecting line Vinit01 is connected to the sixth connecting pad C6 via the first sub-via V1a. For example, the second reset signal connecting line Vinit01 is a connecting line that provides a reset signal and is arranged adjacent to the first reset signal connecting line Vinit0 in the first direction D1.

[0133] For example, for a sub-pixel with a first sub-via V1a (e.g., the fourth sub-pixel P4 and the fifth sub-pixel P5), the positional relationship between the first sub-via V1a and the second sub-via V2 of that sub-pixel, including their distance relationship in the first direction D1 and the second direction D2, is the same as the positional relationship between the first sub-via V1 and the second sub-pixel (e.g., the first sub-pixel and the second sub-pixel) and its second sub-via V2. For example, the film layer penetrated by the first sub-via V1a is the same as the film layer penetrated by the first sub-via V1, and the shape and size of the first sub-via V1a are the same as the shape and size of the first sub-via V1.

[0134] The first strip SCP1 of the second connection structure CS2 is connected to the second reset signal line Vinit2 and the source region of the active layer T1a of the second reset transistor T1 (meaning connected to the source region of the active layer of the second reset transistor T1 in the second semiconductor layer IGZO), thereby realizing the electrical connection of the second reset signal line Vinit2 and the first electrode of the second reset transistor T1 through the second connection structure CS2. This achieves the electrical connection of the first electrode of the second reset transistor T1 to the second reset signal connection line Vinit01 to receive the second reset signal Vinit2 from the second reset signal connection line Vinit01.

[0135] Specifically, referring to Figures 14 and 29, the display substrate 10 includes a sixth via V6, a seventh via V7, and an eighth via V8 penetrating the first insulating layer ILD. For example, the fourth sub-pixel P4 and the fifth sub-pixel P5 share a sixth via V6, the fourth sub-pixel P4 includes the seventh via V7, and the fifth sub-pixel P5 includes the eighth via V8. The first strip portion SCP1 is connected to the second reset signal line Vinit2 through the sixth via V6, the seventh connection pad C7 is connected to the first electrode (the source region of the second reset transistor T1 in the second semiconductor layer IGZO) of the fourth sub-pixel P4 through the seventh via V7, and the eighth connection pad C8 is connected to the first electrode (the source region of the second reset transistor T1 in the second semiconductor layer IGZO) of the fifth sub-pixel through the eighth via V8.

[0136] The seventh via V7 and the eighth via V8 are the aforementioned EBB vias, exposing portions of the second semiconductor layer IGZO; the sixth via V6 is the aforementioned ILD via, exposing portions of the second reset signal line Vinit2 located in the second conductive layer Gate2.

[0137] Referring to Figures 16 and 29, the display substrate 10 further includes a fifth connection structure CS5, which functions similarly to the first strip portion SCP1. The two ends of the fifth connection structure CS5 in the first direction D1 are electrically connected via vias to the first terminals of the second reset transistors T1 of two adjacent sub-pixels (e.g., the first sub-pixel P1 and the second sub-pixel P2). The middle portion of the fifth connection structure CS5 is electrically connected via a via to the second reset signal line Vinit2 to receive the second reset signal Vinit2. The first sub-pixel P1 and the second sub-pixel P2 share one fifth connection structure CS5 to simplify the pixel array structure and save space. For example, the shape of the pattern of the fifth connection structure CS5 is substantially the same as the shape of the pattern of the first strip portion SCP1, that is, the shape of the orthographic projection of the fifth connection structure CS5 onto the surface of the substrate Sub is substantially the same as the shape of the orthographic projection of the first strip portion SCP1 onto the surface of the substrate Sub.

[0138] Referring to Figures 16 and 29, the display substrate 10 further includes a sixth connection structure CS6, similar to the fifth connection structure CS5. The two ends of the sixth connection structure CS6 in the first direction D1 are electrically connected via vias to the first terminals of the second reset transistors T1 of two adjacent sub-pixels (e.g., the third sub-pixel P3 and the sixth sub-pixel P6). The middle portion of the sixth connection structure CS6 is electrically connected via a via to the second reset signal line Vinit2 to receive the second reset signal Vinit2. The third sub-pixel P3 and the sixth sub-pixel P6 share a single fifth connection structure CS5. This enables the provision of the second reset signal Vinit2 to the first terminals of the second reset transistors T1 of each sub-pixel in the pixel array of the display substrate 10.

[0139] For example, the second connection structure CS2 is axially symmetric with respect to an axis of symmetry extending along the second direction D2; for example, the seventh connection pad C7 and the eighth connection pad C8 are symmetric with respect to this axis of symmetry, which passes through the sixth connection pad C6. For example, the sixth via V6 is located at the midpoint of the first strip SCP1, and the orthographic projections of the seventh connection pad C7 and the eighth connection pad C8 onto the surface of the substrate Sub are symmetric with respect to the orthographic projection of the sixth via V6 onto the surface of the substrate Sub. This allows adjacent fourth and fifth sub-pixels to share a single second connection structure CS2, saving space.

[0140] For example, referring to FIG3, the pixel circuit further includes a third reset transistor T8 (the eighth transistor T8 is used as the third reset transistor). The first terminal of the third reset transistor T8 is connected to the third reset signal line Vinit3, and the second terminal of the third reset transistor T8 is connected to the first terminal of the driving transistor T3. It is configured to reset the first terminal of the driving transistor T3 using the third reset signal Vinit3 from the third reset signal line Vinit3. Referring to FIG16, FIG27-FIG29, the display substrate 10 further includes a third connection structure CS3 and a fourth connection structure CS4. The first terminal of the third reset transistor T8 and the third reset signal line Vinit3 are electrically connected to the third connection structure CS3, respectively.

[0141] For example, referring to Figures 6 and 19, the display substrate 10 further includes a third reset signal connection line Vinit02. For example, the third reset signal connection line Vinit02 extends along the second direction D2 and is spaced apart from the first reset signal connection line Vinit0 and the second reset signal connection line Vinit01 in the first direction D1. The third reset signal connection line Vinit02 and the third reset signal line Vinit3 are electrically connected to the fourth connection structure CS4, respectively. For example, the third reset signal connection line Vinit02 is a reset signal connection line adjacent to the first reset signal connection line Vinit0 in the first direction D1, and is located on the side of the first reset signal connection line Vinit0 away from the second reset signal connection line Vinit01.

[0142] Referring to FIG6, the sub-pixel also includes a sixth sub-pixel P6 adjacent to the third sub-pixel P3 in the first direction. For example, referring to FIG6, FIG18 and FIG31, some sub-pixels include a second sub-via V1b, and the third sub-pixel P3 and the sixth sub-pixel P6 include and share a second sub-via V1b.

[0143] The second sub-pixel P2 and the third sub-pixel P3 include and share a third connection structure CS3, and the third sub-pixel P3 and the sixth sub-pixel P6 include and share a fourth connection structure CS4. Referring to Figures 14-15 and 27-29, the display substrate 10 includes a ninth via V9, a tenth via V10, and an eleventh via V11. The ninth via V9 penetrates the first insulating layer ILD to expose the third reset signal line Vinit3; the tenth via V10 penetrates the first insulating layer ILD and the gate insulating layer covering the active layer of the third reset transistor T8 to expose the source region of the active layer of the third reset transistor T8. The eleventh via V11 penetrates the first insulating layer ILD to expose the third reset signal line Vinit3. The ninth via V9 and the eleventh via V11 are the aforementioned EBB vias, exposing a portion of the third reset signal line Vinit3 located in the third conductive layer Gate3; the eleventh via V10 is the aforementioned ILD via, exposing a portion of the first semiconductor layer Poly. For example, the second sub-pixel P2 and the third sub-pixel P3 share a ninth via V9 and a tenth via V10, and the third sub-pixel P3 and the sixth sub-pixel P6 share an eleventh via V11; the third connection structure CS3 is connected to the third reset signal line Vinit3 through the ninth via V9, and the third connection structure CS3 is connected to the source region of the active layer of the third reset transistor T8 of the second sub-pixel P2 and the source region of the active layer of the third reset transistor T8 of the third sub-pixel P3 through the tenth via V10; for example, the source region of the active layer of the third reset transistor T8 of the second sub-pixel P2 and the source region of the active layer of the third reset transistor T8 of the third sub-pixel P3 are integrally formed.

[0144] Referring to Figures 16, 18, and 29, the orthographic projection of the second sub-via V1b shared by the third sub-pixel P3 and the sixth sub-pixel P6 onto the surface of the substrate Sub at least partially overlaps with the orthographic projection of the fourth connection structure CS4 onto the surface of the substrate Sub. Referring to Figures 19 and 29, the fourth connection structure CS4 is connected to the third reset signal line Vinit3 via the eleventh via V11. Furthermore, for example, referring to Figures 19 and 31, the fifth connection pad C5 of the third reset signal connection line Vinit02 is connected to the fourth connection structure CS4 via the second sub-via V1b, thereby electrically connecting the fourth connection structure CS4 to the third reset signal connection line Vinit02 via the second sub-via V1b. Thus, the first electrode of the third reset transistor T8 is electrically connected to the third reset signal connection line Vinit02 via the third connection structure CS3 and the fourth connection structure CS4 to receive the third reset signal Vinit3 from the third reset signal connection line Vinit02.

[0145] For example, for a sub-pixel with a second sub-via V1b (e.g., the third sub-pixel P3 and the sixth sub-pixel P6), the positional relationship between the second sub-via V1b and the second sub-via V2 of that sub-pixel, including their distance relationship in the first direction D1 and the second direction D2, is the same as the positional relationship between the first sub-via V1 and the second sub-pixel (e.g., the first sub-pixel and the second sub-pixel) and its second sub-via V2. For example, the film layer penetrated by the second sub-via V1b is the same as the film layer penetrated by the first sub-via V1, and the shape and size of the second sub-via V1b are the same as the shape and size of the first sub-via V1.

[0146] For example, referring to Figure 19, the first reset signal connection line Vinit0, the second reset signal connection line Vinit01, and the third reset signal connection line Vinit02 are disposed on the same layer and are all located in the fifth conductive layer SD2, so that these three types of reset signal connection lines can be formed in one patterning process using the same film layer, simplifying the film layer structure and manufacturing process of the display substrate 10.

[0147] For example, referring to Figure 6, the first reset signal connection line Vinit0 passes through the boundary region between the first sub-pixel P1 and the second sub-pixel P2, the second reset signal connection line Vinit01 passes through the boundary region between the fourth sub-pixel P4 and the fifth sub-pixel P5, and the third reset signal connection line Vinit02 passes through the boundary region between the third sub-pixel P3 and the sixth sub-pixel P6.

[0148] For example, referring to Figures 6, 16, and 29, the display substrate 10 further includes a second power supply voltage line VSS, which is located in the fourth conductive layer SD1. The second power supply voltage line VSS includes a first trace VSS1 extending along a first direction D1. The first trace VSS1 includes a first bend CP1, which is located in the second direction D2 between a first via V1 and a second via V2. The increased distance between the first and second vias in the second direction provides sufficient space for the first trace VSS1, preventing it from overlapping with other traces and causing signal crosstalk and static electricity accumulation. For example, the orthographic projection of the portion of the first trace VSS1 located in the sub-pixel onto the surface of the substrate Sub substantially overlaps with the orthographic projection of the portion of the third reset signal line Vinit3 located in the sub-pixel onto the surface of the substrate Sub, thereby reducing the area of ​​the opaque signal line and increasing the aperture ratio of the display substrate.

[0149] When the display substrate 10 is the aforementioned FIP type substrate, referring to Figures 2 and 16, for example, the first transmission line 110 and the first trace VSS1 of the second power supply voltage line VSS are disposed on the same layer, for example, both located on the fourth conductive layer SD1. For example, in the second sub-display area 02, there is a break between the end of the first transmission line 110 in the first direction D1 and the end of the first trace VSS1 of the second power supply voltage line VSS in the first direction D1; the first data line DL1, the second transmission line 120, and the first reset signal connection line Vinit0 are disposed on the same layer, for example, all located on the fifth conductive layer SD2.

[0150] Since Figures 6 and 16 illustrate the structure of the sub-pixels in the third sub-display area 03 of Figure 2 without data transmission lines and breaks, the first transmission line 110 is not shown in the layouts shown in Figures 6 and 16. The structures of the sub-pixels in the fourth sub-display area 04, which have data transmission lines and breaks, other than the data lines and breaks, such as the first via, the second via, and the first bend of the first trace of the second power supply voltage line, can all be configured in the same way as those in the sub-pixels shown in Figures 6 and 16.

[0151] For example, referring to Figures 13, 16, 26 and 29, the pattern of the first trace VSS1 of the second power supply voltage line VSS at least partially overlaps with the pattern of Vinit3, for example, the portions of both passing through each sub-pixel along the first direction D1 substantially overlap, in order to save space.

[0152] For example, referring to Figures 16 and 29, the first trace VSS1 of the second power supply voltage line VSS also includes a second bend CP2 connected to the first bend CP1. The second bend CP2 is located in the second direction D2 between the first electrode T7s and the second electrode T7d of the first reset transistor T7. For example, the second bend CP2 is also located in the second direction D2 between the first electrode T8s and the second electrode T8d of the eighth transistor T8. It should be noted that, in this disclosure, the first electrode of a transistor refers to the source region of the semiconductor layer of the transistor T7, and the second electrode of a transistor refers to the drain region of the semiconductor layer of the transistor.

[0153] For example, referring to Figure 19, the second power supply voltage line VSS also includes a second trace VSS2, which extends along the second direction D2 and is disposed on a different layer than the first trace VSS1. For example, the second trace VSS2 is disposed on the same layer as the data line DATA and the first reset signal connection line Vinit0, and is located between two data lines DATA extending along the second direction D2 of two adjacent sub-pixels. The second trace VSS2 and the first trace VSS1 are connected by a via (not shown) through the second insulating layer PVX and the first planarization layer PLN1, so that both the first trace VSS1 and the second trace VSS2 transmit the first power supply voltage VSS. For example, the vertical trace VDD1 of the first power supply voltage line VDD extends along the second direction D2 and is located between an adjacent reset signal connection line (e.g., the first reset signal connection line Vinit01) and the data line DATA.

[0154] For example, referring to Figures 18 and 20, the display substrate 10 further includes a first planarization layer PLN1 and a second planarization layer PLN2. The first planarization layer PLN1 is located between the first connecting pad C1 and the anode connecting pad C0, and the second planarization layer PLN2 is located between the anode connecting pad C0 and the first electrode EL of the light-emitting device EL. A first via V1 and a second via V2 are located in the first planarization layer PLN1 and penetrate the first planarization layer PLN1 in a vertical direction; an anode via V0 is located in the second planarization layer PLN2 and penetrates the second planarization layer PLN2 in a vertical direction.

[0155] The following provides a supplementary description of each film layer of the display substrate 10 provided in the embodiments of this application.

[0156] For example, referring to Figure 8, the masking layer BSM can be a bottom masking metal (BSM) layer formed on the substrate Sub. Alternatively, a barrier layer can be formed between the bottom masking metal (BSM) layer and the substrate Sub to prevent damage to the substrate Sub from subsequent film fabrication processes. For example, the pattern of the masking layer BSM for each sub-pixel may include a first masking connection line 91, a second masking connection line 92, and a masking electrode 93.

[0157] For example, the shape of the shielding electrode 93 can be rectangular, and the corners of the rectangle can be chamfered. The shape of the first shielding connecting line 91 can be a straight line or a broken line extending along the first direction D1. The first shielding connecting line 91 can be respectively disposed on both sides of the shielding electrode 93 in the first direction D1 and connected to the shielding electrode 93 respectively. The shape of the second shielding connecting line 92 can be a straight line or a broken line extending along the second direction D2. The second shielding connecting line 92 can be disposed on both sides of the shielding electrode 93 in the second direction D2 and connected to the shielding electrode 93 respectively.

[0158] For example, in a pixel row, the first occlusion connection lines 91 of two adjacent sub-pixels in the first direction D1 are connected to each other to form an interconnected integral structure. And / or, in a pixel column, the second occlusion connection lines 92 of two adjacent sub-pixels in the second direction D2 are connected to each other to form a continuous integral structure. Connecting the occlusion layers in pixel rows and pixel columns integrally ensures that the occlusion layers in the display substrate 10 have the same potential, which helps improve the uniformity of the display substrate, avoids display defects, and guarantees the display effect of the display substrate.

[0159] For example, the first blocking connection line 91 on both sides of the blocking electrode 93 can be located on a straight line extending along the first direction D1, and the second blocking connection line 92 on both sides of the blocking electrode 93 can be staggered in the first direction D1. This disclosure does not limit this aspect.

[0160] For example, referring to Figure 9, the first semiconductor layer Poly is located on the side of the shielding layer BSM away from the substrate Sub. The first semiconductor layer Poly includes the active layer of the third to ninth transistors T3 to T9, and the positions of the channel regions T3a to T9a of the third to ninth transistors T3 to T9 are marked in Figure 9. The source region and drain region of each transistor are located on both sides of the channel region and connected to the channel region. Here, the channel region of the transistor refers to the portion where the active layer of the transistor overlaps with the gate line in a direction perpendicular to the surface of the substrate Sub. For example, the material of the first semiconductor layer Poly is low-temperature polycrystalline silicon.

[0161] For example, the active layers of the third to seventh transistors T3 to T7 are connected as one unit, while the active layers of the eighth transistor T8 and the ninth transistor T9 are set separately and are separated from the integrated structure formed by the active layers of the third to seventh transistors T3 to T7.

[0162] For example, the active layers of the third to seventh transistors T3 to T7 of each of two adjacent sub-pixels (e.g., the second sub-pixel P2 and the third sub-pixel P3 mentioned above) are interconnected. This facilitates space utilization and allows adjacent sub-pixels to share some of the aforementioned structures, thereby simplifying the sub-pixel structure of the display substrate. For example, the pattern of the first semiconductor layer Poly of two adjacent sub-pixels (e.g., the second sub-pixel P2 and the third sub-pixel P3 mentioned above) is substantially axially symmetric with respect to the axis of symmetry extending along the second direction D2, which facilitates the layout design of multiple sub-pixel structures and saves space.

[0163] For example, the orthographic projection of the channel region T3a of the third transistor T3 (i.e., the driving transistor) onto the surface of the substrate Sub at least partially overlaps with the orthographic projection of the shielding electrode 93 onto the surface of the substrate Sub. The shielding electrode 93 shields the channel region T3a of the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0164] For example, in the second direction D2, the active layers of the eighth transistor T8 and the seventh transistor T7 are located on one side of the active layers of the third to sixth transistors T3 to T6. The active layers of the eighth transistor T8 and the seventh transistor T7 are both located at the end of the first semiconductor layer poly of the entire sub-pixel in the second direction D2. The aforementioned first reset signal line Vinit1 and second reset signal line Vinit2 are adjacent to this end of the first semiconductor layer poly of the entire sub-pixel in the second direction D2. This facilitates the connection of the active layers of the eighth transistor T8 and the seventh transistor T7 with the first reset signal line Vinit1 and the second reset signal line Vinit2.

[0165] For example, referring to Figures 9 and 23, the channel region T8a of the eighth transistor T8 and the channel region T7a of the seventh transistor T7 are substantially aligned in the first direction D1, so that they can overlap with the channel regions T8a of the eighth transistor T8 and T7a of the seventh transistor T7 using the same fourth scan signal line S4 (gate line) to form the gate T8g of the eighth transistor T8 and the gate T7g of the seventh transistor T7. The channel region T4a of the fourth transistor T4 and the channel region T9a of the ninth transistor T9 are substantially aligned in the first direction D1, so that they can overlap with the channel regions T4a of the fourth transistor T4 and T9a of the ninth transistor T9 using the same second scan signal line S2 (gate line) to form the gate T4g of the fourth transistor T4 and the gate T9g of the ninth transistor T9. The channel regions T5a of the fifth transistor T5 and T6a of the sixth transistor T6 are substantially aligned in the first direction D1 so that the same first light-emitting signal line EM1 (gate line, for example, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are the same signal line) overlaps with the channel regions T5a of the fifth transistor T5 and T6a of the sixth transistor T6 to form the gate T5g of the fifth transistor T5 and the gate T6g of the sixth transistor T6.

[0166] Referring to Figure 10, the first conductive layer Gate1 includes a second scan signal line S2, a fourth scan signal line S4, a first light-emitting signal line EM1, a second light-emitting signal line EM2, and a second reset signal line Vinit2, which are spaced apart from each other in the second direction D2. The portions of the second scan signal line S2, the fourth scan signal line S4, the first light-emitting signal line EM1, the second light-emitting signal line EM2, and the second reset signal line Vinit2 located in the sub-pixel extend along the first direction D1.

[0167] The first conductive layer Gate1 also includes a first electrode Cst1 of the storage capacitor Cst. The orthographic projection of the first electrode Cst1 onto the surface of the substrate Sub at least partially overlaps with the orthographic projection of the active layer of the third transistor T3 onto the surface of the substrate Sub. For example, the first electrode Cst1 can be reused as the gate T3g of the third transistor T3. For example, the orthographic projection of the first electrode Cst1 onto the surface of the substrate Sub at least partially overlaps with the orthographic projection of the shielding electrode 93 onto the surface of the substrate Sub.

[0168] Referring to Figure 11, the second conductive layer Gate2 includes a first scan signal line S1 and a third scan signal line S3 that are spaced apart from each other in the second direction D2. The portions of the first scan signal line S1 and the third scan signal line S3 located in the sub-pixels extend along the first direction D1.

[0169] Referring to Figures 12 and 25, the second semiconductor layer IGZO includes the active layer of the first transistor T1 and the active layer of the second transistor T2. For example, the material of the second semiconductor layer IGZO is an oxide semiconductor, such as indium gallium zinc oxide (IGZO). The first scan signal line S1 and the third scan signal line S3 overlap with the active layers of the first transistor T1 and the second transistor T2 in a direction perpendicular to the surface of the substrate Sub to form the first gate T1g of the first transistor T1 and the first gate T2g of the second transistor T2.

[0170] Referring to Figure 13, the second conductive layer Gate2 is located on the side of the second semiconductor layer IGZO closer to the substrate Sub, and the third conductive layer Gate3 is located on the side of the second semiconductor layer IGZO farther from the substrate Sub. The third conductive layer Gate3 includes a first reset signal line Vinit1, a third reset signal line Vinit3, a sixth scan signal line S6, and a seventh scan signal line S7, all spaced apart from each other in the second direction D2. The portions of each of the first reset signal line Vinit1, the third reset signal line Vinit3, the sixth scan signal line S6, and the seventh scan signal line S7 located in their respective sub-pixel locations extend along the first direction D1. The sixth scan signal line S6 also transmits the third scan signal S1, and the seventh scan signal line S7 also transmits the first scan signal S1. Referring to Figure 26, the sixth scan signal line S6 and the seventh scan signal line S7 overlap with the active layer of the first transistor T1 and the active layer of the second transistor T2 in a direction perpendicular to the surface of the substrate Sub to form the second gate of the first transistor T1 and the second gate of the second transistor T2. The second gate of the first transistor T1 and the second gate of the second transistor T2 are also located at the positions indicated by labels T1g and T2g, respectively, and overlap with the first gate of the first transistor T1 and the first gate of the second transistor T2 in a direction perpendicular to the surface of the substrate Sub, thereby making the first transistor T1 and the second transistor T2 dual-gate transistors.

[0171] Figure 25 shows the positions of the gates T1g to T9g of the first to ninth transistors T1 to T9 of a sub-pixel.

[0172] Referring to Figures 14 and 15, the first insulating layer ILD is located between the third conductive layer Gate3 and the fourth conductive layer SD1, and the second insulating layer EBB is located on the side of the first insulating layer ILD away from the substrate Sub. Of course, an insulating layer is provided between each conductive layer; this embodiment only specifically describes the insulating layer relevant to the technical solution of this disclosure.

[0173] Referring to Figure 16, the fourth conductive layer SD1 includes the first trace VSS1 of the second power supply voltage line VSS, the first connecting pad C1, the first connecting structure CS1, the second connecting structure CS2, the third connecting structure CS3, the fourth connecting structure CS4, and the fifth connecting structure CS5.

[0174] Referring to Figures 17-18, the second insulating layer PVX and the first planarization layer PLN1 are located between the fourth conductive layer SD1 and the fifth conductive layer SD2. The first planarization layer PLN1 is located on the side of the second insulating layer PVX away from the substrate Sub. For example, the first via V1 and the second via V2 penetrate the second insulating layer PVX and the first planarization layer PLN1. The first planarization layer PLN1 is an insulating layer and has a flat surface away from the substrate Sub to provide a flat surface for forming the fifth conductive layer SD2.

[0175] Referring to Figure 19, the fifth conductive layer SD2 includes a first reset signal connection line Vinit0, a second reset signal connection line Vinit01 and a third reset signal connection line Vinit02, as well as a data line DATA, a second trace VSS2 of the second power supply voltage line VSS, and an anode connection pad C0.

[0176] Referring to Figure 20, the second planarization layer PLN2 is located between the fifth conductive layer SD2 and the first electrode layer AND, and the anode via V0 penetrates the second planarization layer PLN1. The second planarization layer PLN1 is an insulating layer and has a flat surface away from the substrate Sub to provide a flat surface for forming the anode of the first electrode layer AND.

[0177] Referring to Figure 21, the first electrode layer AND includes the first electrode EL1 of each sub-pixel. It can be seen that in this embodiment, the area of ​​the first electrode EL11 of the third sub-pixel P3 is larger than the area of ​​the first electrode EL1 of the first sub-pixel P1, and the area of ​​the first electrode EL1 of the first sub-pixel P1 is larger than the area of ​​the first electrode EL12 of the second sub-pixel P2.

[0178] Figure 34 is a schematic diagram of the sub-pixel structure of another display substrate provided in an embodiment of this disclosure, and Figure 35 is a schematic diagram of a single layer of the first planarization layer PLN1 in Figure 34. The embodiment shown in Figure 34 differs from the embodiment shown in Figure 6 in the following ways.

[0179] Referring to Figures 34 and 35, for example, in the second direction D2, a portion of the anode via V01 of the first sub-pixel P1 is located between the first via V1 and the second via V21 / V22. The distance d1 between the first via V1 and the second via V21 of the first sub-pixel P1 in the second direction D2 is 2 to 10 times the distance between the first via V1 and the anode via V01 of the first sub-pixel P1 in the second direction D2. According to experimental design exploration, a better space utilization effect can be achieved within this numerical range. Arranging the first electrodes EL of multiple sub-pixels in a limited space helps to improve the problem of overlap between the second via V2 and the first electrode EL of the corresponding sub-pixel.

[0180] For example, referring to Figure 34, the anode via V01 of the first sub-pixel P1 overlaps with the first via V1 in the first direction D1. That is, if a straight line is drawn along the first direction D1, the line will pass through the anode via V01 and the first via V1 of the first sub-pixel P1. This ensures that the anode via V01 of the first sub-pixel P1 is as far away as possible from the second via V21 of the first sub-pixel P1 in the second direction D2. This not only helps the first electrode EL11 of the first sub-pixel P1 avoid the second via V21, but also allows sufficient space for the design of other structures (such as the first trace VSS1), enabling a reasonable arrangement of the various structures of the sub-pixel and reducing the manufacturing difficulty.

[0181] For example, referring to Figures 34 and 35, the length of the first via V1 in the first direction D1 is greater than the width of the first via V1 in the second direction D2; the length of the second via V2 in the first direction D1 is greater than the width of the first via V1 in the second direction D2, for example, the second via V21 of the first sub-pixel P1 and the second via V22 of the first sub-pixel P2 are both like this. Therefore, designing the first via V1 and each of the second via V2 as flat holes greatly reduces the width of the first via V1 and the second via V22 of the first sub-pixel P2 in the second direction D2. This not only helps to increase the space between the first via V1 and the second via V2 in the second direction D2, but more importantly, it allows the second via V22 to effectively avoid the first electrode EL13 of the nearby third sub-pixel P3. The same applies to the second via V23, which can also be designed as a flat hole as described above. In this case, if the distance between the second via V21 of the first sub-pixel P1 and the second via V22 of the first sub-pixel P2 is appropriately adjusted, the overlap problem of the first electrode EL13 with the largest area and the second vias V22 and V23 can be effectively improved. For example, referring to Figure 34, the entire orthographic projection of at least one of the second via V22 of the second sub-pixel P2 and the second via V23 of the third sub-pixel P3 onto the surface of the substrate Sub does not overlap with the orthographic projection of the first electrode EL1 of the light-emitting device EL of the third sub-pixel P3 onto the surface of the substrate Sub. This significantly improves the flatness of the first electrode EL1 of the light-emitting device EL of the third sub-pixel P3 and reduces defects such as color shift in the display substrate caused by this.

[0182] For example, referring to Figures 34 and 35, the distance d1 between the first via V1 and the second via V2 (second via V21 or second via V22) in the second direction D2 is greater than the distance d2 between the second via V21 of the first sub-pixel P1 and the second via V22 of the second sub-pixel P2 in the first direction D1, that is, d1 > d2. For example, d1 is greater than d2 and less than or equal to 1.2 times d2. Therefore, on the one hand, it is beneficial to increase the space between the first via V1 and the second via V2 in the second direction D2, which not only increases the design space of the first electrode and reduces the overlap between the first electrode and the second via, but also provides sufficient design space for other traces (such as the first trace VSS1), so as to realize the reasonable arrangement of the sub-pixel structure of the entire display substrate. On the other hand, it reduces the distance between the second via V21 of the first sub-pixel P1 and the second via V22 of the second sub-pixel P2 in the first direction D1, which further facilitates the second via V2 to move away from the first electrode it is close to, especially away from the first electrode EL13 of the third sub-pixel P3 with the largest area, so that the entire second via does not overlap with the first electrode EL13.

[0183] Figure 36 is an equivalent circuit diagram of another pixel circuit provided in an embodiment of this disclosure. For example, the sub-pixel structure layout shown in Figure 34 adopts the pixel circuit shown in Figure 36. Of course, the pixel circuit used in the sub-pixels of the display substrate provided in this disclosure is not limited to the circuits shown in Figures 2 and 36, as long as it meets the technical features of the above-mentioned first via, second via, first electrode, etc.

[0184] Figure 37 is a schematic block diagram of a display device provided according to an embodiment of the present disclosure. As shown in Figure 37, the display device 100 provided in at least one embodiment of the present disclosure includes any of the display substrates 10 provided in the embodiments of the present disclosure. The display device 100 may be, for example, an electroluminescent display device, such as an organic light-emitting diode display device, an inorganic light-emitting diode display device, or other devices with display functions or other types of devices. The embodiments of the present disclosure are not limited in this regard.

[0185] The technical effects of the display device provided in the embodiments of this disclosure can be referred to the description of the technical effects of the display substrate 10 provided in the embodiments of this disclosure above, and will not be repeated here.

[0186] For example, the display device provided in at least one embodiment of this disclosure can be any product or component with display function, such as a display panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. The embodiments of this disclosure do not limit this.

[0187] The following points also need to be explained:

[0188] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0189] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0190] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0191] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. The scope of protection of this disclosure is determined by the scope defined in the claims.

Claims

1. A display substrate, comprising: Substrate; A sub-pixel is disposed on the surface of the substrate and includes a pixel circuit, wherein the pixel circuit includes a light-emitting device and a driving transistor, the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device, and the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light; the sub-pixel also includes a first via, a second via, an anode via, an anode connection pad, and a first connection pad; A first reset signal line extends along a first direction, wherein the pixel circuit further includes a first reset transistor, the first electrode of the first reset transistor being electrically connected to the first reset signal line, and the second electrode of the first reset transistor being connected to the first electrode of the light-emitting device; and A first reset signal connection line extends along a second direction intersecting the first direction, is configured to transmit a first reset signal, and is electrically connected to the first reset signal line via the first via, wherein... The first electrode of the light-emitting device is electrically connected to the anode connection pad through the anode via, the anode connection pad is electrically connected to the first connection pad through the second via, and the first connection pad is electrically connected to the active layer of the first reset transistor. The distance between the first via and the second via in the second direction is greater than the distance between the first via and the anode via in the second direction.

2. The display substrate according to claim 1, wherein, The display substrate includes a pixel array, the pixel array includes a plurality of sub-pixels arranged in an array, the plurality of sub-pixels include a first sub-pixel and a second sub-pixel that are adjacent to each other in the second direction, the first sub-pixel and the second sub-pixel share a first via, and the first via is located in the boundary region between the first sub-pixel and the second sub-pixel in the second direction; The distance between the first via and the second via of the first sub-pixel in the second direction is greater than the distance between the first via and the anode via of the first sub-pixel in the second direction; and, The distance between the first via and the second via of the second sub-pixel in the second direction is greater than the distance between the first via and the anode via of the second sub-pixel in the second direction.

3. The display substrate according to claim 2, wherein, In the second direction, at least a portion of the anode via of the first sub-pixel is located between the first via and the second via, and the anode via of the second sub-pixel is located on the side of the first via away from the second via.

4. The display substrate according to claim 3, wherein, The distance between the first via and the second via of the second sub-pixel in the first direction is 3 to 5 times the distance between the first via and the anode via of the second sub-pixel in the first direction.

5. The display substrate according to claim 3 or 4, wherein, In the second direction, the entire anode via of the first sub-pixel is located between the first via and the second via, and the distance between the first via and the second via of the first sub-pixel in the second direction is 5 to 8 times the distance between the first via and the anode via of the first sub-pixel in the second direction.

6. The display substrate according to claim 3 or 4, wherein, In the second direction, a portion of the anode via of the first sub-pixel is located between the first via and the second via, and the distance between the first via and the second via of the first sub-pixel in the second direction is 2 to 10 times the distance between the first via and the anode via of the first sub-pixel in the second direction.

7. The display substrate according to claim 6, wherein, The anode via of the first sub-pixel overlaps with the first via in the first direction.

8. The display substrate according to any one of claims 2-7, wherein, The orthographic projection of the first via on the surface of the substrate at least partially overlaps with the orthographic projection of the first reset signal connection line on the surface of the substrate. The first reset signal connection line is located between the first sub-pixel and the second sub-pixel in the first direction. The first sub-pixel and the second sub-pixel share the first reset signal connection line and the first via. The second via of the first sub-pixel and the second via of the second sub-pixel are substantially symmetrical with respect to the first reset signal connection line.

9. The display substrate according to any one of claims 2-8, wherein, The sub-pixel also includes a third sub-pixel that is adjacent to the second sub-pixel in the first direction; At least a portion of the orthographic projection of at least one of the second via of the second sub-pixel and the second via of the third sub-pixel onto the surface of the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device of the third sub-pixel onto the surface of the substrate.

10. The display substrate according to claim 9, wherein, The entire orthographic projection of at least one of the second via of the second sub-pixel and the second via of the third sub-pixel on the surface of the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device of the third sub-pixel on the surface of the substrate.

11. The display substrate according to claim 9 or 10, wherein, The area of ​​the first electrode of the light-emitting device of the third sub-pixel is larger than the area of ​​the first electrode of the light-emitting device of the first sub-pixel, and larger than the area of ​​the first electrode of the light-emitting device of the second sub-pixel.

12. The display substrate according to any one of claims 1-11, wherein, The length of the first via in the first direction is greater than the width of the first via in the second direction; The length of the second via in the first direction is greater than the width of the first via in the second direction.

13. The display substrate according to claim 12, wherein, The distance between the first via and the second via in the second direction is greater than the distance between the second via of the first sub-pixel and the second via of the second sub-pixel in the first direction.

14. The display substrate according to any one of claims 1-13, wherein, The display substrate further includes: The second power supply voltage line includes a first trace extending along the first direction, wherein the first trace includes a first bend, and the first bend is located between the first via and the second via in the second direction.

15. The display substrate according to claim 14, wherein, The first trace of the second power supply voltage line also includes a second bend connected to the first bend, the second bend being located between the first and second terminals of the first reset transistor in the second direction.

16. The display substrate according to any one of claims 2-15, wherein, The sub-pixel further includes a first connection structure, wherein the first reset signal connection line and the first electrode of the first reset transistor are respectively electrically connected to the first connection structure; The first connection structure includes a connection body extending along the first direction, a second connection pad connected to the connection body and protruding from the connection body toward the second through hole in the second direction, and a third connection pad and a fourth connection pad located at both ends of the connection body in the first direction. The orthographic projection of the first via on the surface of the substrate at least partially overlaps with the orthographic projection of the second connection pad on the surface of the substrate, and the first reset signal connection line is connected to the second connection pad through the first via; For the first sub-pixel, the third connection pad is connected to the source region of the active layer of the first reset signal line and the first reset transistor, respectively; for the second sub-pixel, the fourth connection pad is connected to the source region of the active layer of the first reset signal line and the first reset transistor, respectively. The sub-pixel further includes a fourth via and a fifth via; the first reset signal connection line is connected to the second connection pad of the first connection structure via the first via; the third connection pad is electrically connected to the first reset signal line via the fourth via of the first sub-pixel, and the third connection pad is electrically connected to the first electrode of the first reset transistor of the first sub-pixel via the fifth via of the first sub-pixel; the fourth connection pad is electrically connected to the first reset signal line via the fourth via of the second sub-pixel, and the fourth connection pad is electrically connected to the first electrode of the first reset transistor of the second sub-pixel via the fifth via of the second sub-pixel.

17. The display substrate according to any one of claims 2-16, wherein, The pixel circuit further includes a second reset transistor, the first terminal of which is connected to a second reset signal line, the second terminal of which is connected to the gate of the driving transistor, and is configured to reset the gate of the driving transistor using a second reset signal from the second reset signal line; The display substrate further includes a second reset signal connection line, which extends along the second direction and is spaced apart from the first reset signal connection line in the first direction; The display substrate further includes a second connection structure, wherein the second reset signal connection line and the first electrode of the second reset transistor are electrically connected to the second connection structure. The plurality of sub-pixels also include a fourth sub-pixel and a fifth sub-pixel that are adjacent in the first direction. The fourth sub-pixel and the fifth sub-pixel include and share the second connection structure. The second connection structure includes a first strip extending along the first direction, a second strip connected to the first strip and extending along the second direction toward the first via, a sixth connection pad located at the end of the second strip away from the first strip in the second direction, and a seventh connection pad and an eighth connection pad located at both ends of the first strip in the first direction, respectively. Some of the sub-pixels include a first sub-via, a sixth sub-via, a seventh sub-via, and an eighth sub-via. The fourth sub-pixel and the fifth sub-pixel share a first sub-via and a sixth sub-via. The fourth sub-pixel includes the seventh sub-via, and the fifth sub-pixel includes the eighth sub-via. The second reset signal connection line is connected to the sixth connection pad via the first sub-via; The first strip portion is connected to the second reset signal line through the sixth via, the seventh connection pad is connected to the source region of the active layer of the second reset transistor of the fourth sub-pixel through the seventh via, and the eighth connection pad is connected to the source region of the active layer of the second reset transistor of the fifth sub-pixel through the eighth via.

18. The display substrate according to any one of claims 2-17, wherein, The pixel circuit further includes a third reset transistor, the first terminal of which is connected to a third reset signal line, the second terminal of which is connected to the first terminal of the driving transistor, and is configured to reset the first terminal of the driving transistor using a third reset signal from the third reset signal line; The display substrate further includes a third reset signal connection line, which extends along the second direction and is spaced apart from the first reset signal connection line and the second reset signal connection line in the first direction. The display substrate further includes a third connection structure and a fourth connection structure. The first electrode of the third reset transistor and the third reset signal line are electrically connected to the third connection structure, and the reset signal connection line and the third reset signal line are electrically connected to the fourth connection structure. The sub-pixel further includes a third sub-pixel adjacent to the second sub-pixel in the first direction and a sixth sub-pixel adjacent to the third sub-pixel in the first direction; some of the sub-pixels include a second sub-via, and the third sub-pixel and the sixth sub-pixel include and share a second sub-via; The second sub-pixel and the third sub-pixel include and share the third connection structure, and the third sub-pixel and the sixth sub-pixel include and share the fourth connection structure; The display substrate includes a ninth via, a tenth via, and an eleventh via. The second sub-pixel and the third sub-pixel share one ninth via and one tenth via, and the third sub-pixel and the sixth sub-pixel share the eleventh via. The third connection structure is connected to the third reset signal line through the ninth via, and the third connection structure is connected to the source region of the active layer of the third reset transistor of the second sub-pixel and the source region of the active layer of the third reset transistor of the third sub-pixel through the tenth via. The fourth connection structure is connected to the third reset signal line through the eleventh via, and the fourth connection structure is connected to the third reset signal connection line through the second sub-via.

19. The display substrate according to claim 18, wherein, The third reset signal line includes a main reset line, a first reset connection pad, and a second reset connection pad. The first reset connection pad and the second reset connection pad protrude from different positions of the main reset line along a second direction. The third connection structure is connected to the first reset connection pad of the third reset signal line through the ninth via, and the fourth connection structure is connected to the second reset connection pad of the third reset signal line through the eleventh via.

20. The display substrate according to claim 14 or 15, wherein, The display substrate includes a display area and a bonding area located on one side of the display area; the display area includes a first sub-display area that at least partially overlaps with the bonding area and a second sub-display area located on at least one side of the first sub-display area and not overlapping with the bonding area; Both the first sub-display area and the second sub-display area include the sub-pixel; The first sub-display area includes a first data line extending along the first direction and configured to provide a data signal. The driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to the data signal. The second sub-display area includes a second data line and a data transmission line. The data transmission line includes a first transmission line and a second transmission line disposed on different layers. The first transmission line extends along the second direction, and the second transmission line extends along the first direction. The first end of the first transmission line is connected to the second transmission line through a data via.

21. The display substrate according to claim 20, wherein, The first transmission line and the first trace of the second power supply voltage line are arranged on the same layer. In the second sub-display area, there is a break between the end of the first transmission line in the first direction and the end of the first trace of the second power supply voltage line in the first direction. The first data line, the second transmission line, and the first reset signal connection line are arranged on the same layer.

22. A display device comprising a display substrate according to any one of claims 1-21.

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