Display panel and driving method therefor, and display device

Abstract

Embodiments of the present invention relate to the technical field of display, and provide a display panel and a driving method therefor, and a display device, which can effectively mitigate the flicker phenomenon under low-frequency driving. The display panel comprises pixel circuits, each comprising a driving module and a bias adjustment module, wherein the bias adjustment module has a control end electrically connected to a first scan line, a first end electrically connected to a bias signal line, and a second end electrically connected to a first end of the driving module; the first scan line provides a first scan signal; and the bias signal line provides a bias voltage. The display panel has a first frequency, a driving cycle at the first frequency comprises a write frame and a plurality of hold frames, and the write frame and the hold frame each comprises at least one light-emitting cycle. In the light-emitting cycle, the total duration of the effective level of the first scan signal is a first duration. At the first frequency, the first duration corresponding to at least part of the hold frames is different from the first duration corresponding to the write frame, and / or a bias voltage corresponding to at least part of the hold frames is different from a bias voltage corresponding to the write frame.

Description

Display panel and its driving method, display device

[0001] This invention claims priority to Chinese Patent Application No. 202411918673.5, filed with the State Intellectual Property Office of China on December 24, 2024, entitled “Display Panel and Driving Method Thereof, Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. Background Technology

[0003] Due to factors such as transistor leakage in the pixel circuit, the brightness of the display panel cannot be sustained and uniform as expected when driven at low frequency, resulting in flickering of the displayed image.

[0004] This flickering issue limits the range of driving frequencies for the display panel, preventing it from fully utilizing the advantages of low-frequency power reduction. Summary of the Invention

[0005] This invention provides a display panel and its driving method and display device, which can effectively improve the flickering phenomenon under low-frequency driving.

[0006] In a first aspect, embodiments of the present invention provide a display panel, comprising:

[0007] The pixel circuit includes a driving module and a bias adjustment module. The control terminal of the bias adjustment module is electrically connected to a first scan line, the first terminal is electrically connected to a bias signal line, and the second terminal is electrically connected to the first terminal of the driving module. The first scan line provides a first scan signal, and the bias signal line provides a bias voltage.

[0008] The display panel has a first frequency, and the driving cycle at the first frequency includes a write frame and a plurality of hold frames, wherein the write frame and the hold frame each include at least one light emission cycle.

[0009] During the light emission cycle, the total duration of the effective level of the first scanning signal is the first duration.

[0010] At the first frequency, at least some of the hold frames have different first durations than the write frames, and / or at least some of the hold frames have different bias voltages than the write frames.

[0011] Secondly, based on the same inventive concept, the present invention also provides a driving method for a display panel, the display panel including a pixel circuit, including a driving module and a bias adjustment module, wherein the control terminal of the bias adjustment module is electrically connected to a first scan line, the first terminal is electrically connected to a bias signal line, and the second terminal is electrically connected to the first terminal of the driving module, the first scan line provides a first scan signal, and the bias signal line provides a bias voltage;

[0012] The display panel has a first frequency, and the driving cycle at the first frequency includes a write frame and a plurality of hold frames, wherein the write frame and the hold frame each include at least one light emission cycle.

[0013] During the light emission cycle, the total duration of the effective level of the first scanning signal is the first duration.

[0014] The driving method includes:

[0015] At the first frequency, control at least a portion of the hold frames to have different first durations than the write frames, and / or control at least a portion of the hold frames to have different bias voltages than the write frames.

[0016] Thirdly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the aforementioned display panel.

[0017] The technical solution provided by the embodiments of the present invention has the following beneficial effects:

[0018] In the pixel circuit, the bias adjustment transistor turns on in response to the effective level of the first scan signal, writing a bias voltage into the gate of the driving transistor, thereby adjusting the bias state of the driving transistor. The on-time of the bias adjustment transistor and the magnitude of the bias voltage affect the degree to which the bias adjustment transistor controls the bias state of the driving transistor, thus affecting the device characteristics of the driving transistor, the magnitude of the driving current, and ultimately, the pixel brightness.

[0019] Compared to the write frame, this embodiment of the invention dynamically sets the total conduction time and / or bias voltage of the bias adjustment transistor in at least part of the hold frame. This allows for further adjustment of the bias state of the driving transistor during the hold phase, adjustment of the driving current during the hold phase, suppression of the brightness change trend during the hold phase, and reduction of the brightness difference between the hold phase and the write frame, thereby effectively improving the flickering phenomenon under low-frequency driving.

[0020] On the other hand, because this technical solution can effectively improve the flicker problem of low-frequency driving, the display panel can be driven at a lower frequency, the selection range of the minimum driving frequency of the display panel can be reduced to a lower level, and the display panel can better take advantage of the power saving of low frequency. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 is a schematic diagram of brightness variation in related technologies;

[0023] Figure 2 is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0025] Figure 4 is a timing diagram provided by an embodiment of the present invention;

[0026] Figure 5 is another timing diagram provided by an embodiment of the present invention;

[0027] Figure 6 is another timing diagram provided by an embodiment of the present invention;

[0028] Figure 7 is another timing diagram provided by an embodiment of the present invention;

[0029] Figure 8 is another timing diagram provided by an embodiment of the present invention;

[0030] Figure 9 is another timing diagram provided by an embodiment of the present invention;

[0031] Figure 10 is another timing diagram provided by an embodiment of the present invention;

[0032] Figure 11 is another timing diagram provided by an embodiment of the present invention;

[0033] Figure 12 is another timing diagram provided by an embodiment of the present invention;

[0034] Figure 13 is another timing diagram provided by an embodiment of the present invention;

[0035] Figure 14 is another timing diagram provided by an embodiment of the present invention;

[0036] Figure 15 is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0037] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0039] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0040] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0041] Currently, low-frequency driving of display panels is typically achieved by reducing the frequency from the base frequency. For example, if the base frequency of the display panel is 120Hz, and one frame at the base frequency is 8.33ms, when the display panel needs to be driven at an ultra-low frequency of 1Hz, one drive cycle at 1Hz includes one write frame and 119 hold frames. The duration of both the write frame and the hold frame is 8.33ms. The data voltage is only written to the gate of the driving transistor during the write frame and not during the hold frame.

[0042] During low-frequency driving, the brightness changes during the hold phase due to factors such as leakage current in the gate reset transistor and threshold compensation transistor connected to the gate of the driving transistor in the pixel circuit. For example, during 1Hz driving, as shown in Figure 1 (a schematic diagram of brightness change in related technologies), the brightness continuously increases during the hold phase, and the difference between the brightness and the write frame becomes increasingly larger until the brightness recovers when entering the next write frame. However, this results in a very significant brightness jump when entering the next write frame, causing flickering once per second, which seriously affects the display quality.

[0043] In response, this invention proposes a technical solution that effectively improves the aforementioned flickering problem by adjusting the driving timing during the holding phase.

[0044] This invention provides a display panel, as shown in FIG2. FIG2 is a schematic diagram of a structure of the display panel provided in this invention, which includes a pixel circuit 1.

[0045] As shown in Figure 3, Figure 3 is a schematic diagram of a pixel circuit 1 provided in an embodiment of the present invention. The pixel circuit 1 includes a driving module 2 and a bias adjustment module 3. The control terminal of the bias adjustment module 3 is electrically connected to the first scan line Spx, which provides the first scan signal; the first terminal is electrically connected to the bias signal line DVH, which provides the bias voltage; and the second terminal is electrically connected to the first terminal of the driving module 2.

[0046] More specifically, the driving module 2 includes a driving transistor M0. The bias adjustment module 3 includes a bias adjustment transistor M1, the gate of which is electrically connected to the first scan line Spx, the first terminal of which is electrically connected to the bias signal line DVH, and the second terminal of which is electrically connected to the first terminal of the driving transistor M0. The bias adjustment transistor M1 turns on in response to a valid level provided by the first scan line Spx, writing a bias voltage into the first terminal of the driving transistor M0 to adjust the bias state of the driving transistor M0.

[0047] Referring to Figures 4 to 7, the display panel has a first frequency f1, which can be a low frequency, such as 1Hz, 2Hz, 5Hz, 10Hz, 20Hz, etc. The driving cycle T at the first frequency f1 includes a write frame WF and multiple hold frames HF, and the write frame WF and hold frames HF each include at least one light emission cycle T2.

[0048] Regarding Write Frame (WF) and Hold Frame (HF): The display panel has a fundamental frequency f, and one frame corresponding to the fundamental frequency f is... The drive cycle T at the first frequency f1 includes one write frame WF and The time for writing frame WF and holding frame HF is one hold frame HF.

[0049] Regarding the light emission cycle T1: Referring to Figure 3, the display panel also includes a first light emission control module 4 and a second light emission control module 5. The control terminal of the first light emission control module 4 is electrically connected to the light emission control signal line Emit, its first terminal is electrically connected to the first power supply line PVDD, and its second terminal is electrically connected to the first terminal of the driver module 2. The control terminal of the second light emission control module 5 is electrically connected to the light emission control signal line Emit, its first terminal is electrically connected to the second terminal of the driver module 2, and its second terminal is electrically connected to the light-emitting element D.

[0050] More specifically, the first light-emitting control module 4 includes a first light-emitting control transistor M2, whose gate is electrically connected to the light-emitting control signal line Emit, whose first electrode is electrically connected to the first power supply line PVDD, and whose second electrode is electrically connected to the first electrode of the driving transistor M0. The second light-emitting control module 5 includes a second light-emitting control transistor M3, whose gate is electrically connected to the light-emitting control signal line Emit, whose first electrode is electrically connected to the second electrode of the driving transistor M0, and whose second electrode is electrically connected to the light-emitting element D.

[0051] Referring to Figures 4-7, the Emit control signal line provides the light emission control signal. One light emission cycle T1 can be understood as one pulse cycle of the light emission control signal. In this embodiment of the invention, the write frame WF and the hold frame HF can each include one light emission cycle T1 as shown in Figures 5 and 7, or they can each include at least two light emission cycles T1 as shown in Figures 4 and 6. When the write frame WF and the hold frame HF each include at least two light emission cycles T1, the brightness can be more precisely controlled using the light emission control signal. The accompanying drawings of this embodiment of the invention illustrate an example where the write frame WF and the hold frame HF each include three light emission cycles T1.

[0052] As shown in Figures 4 and 5, Figure 4 is a timing diagram provided by an embodiment of the present invention, and Figure 5 is a timing diagram provided by another embodiment of the present invention. At a first frequency f1, the first duration corresponding to at least partially held frame HF and written frame WF is different, wherein the first duration is the total duration of the effective level of the first scan signal in the light emission cycle T1. That is, for a light emission cycle T1, when the first scan signal provides only one pulse, the first duration is the duration of the effective level in that pulse; when the first scan signal provides two or more pulses, the first duration is the sum of the durations of the effective level in these at least two pulses. The fact that the first duration corresponding to at least partially held frame HF and written frame WF is different means that the total conduction duration of the bias adjustment transistor M1 in at least partially held frame HF is different from the total conduction duration of the bias adjustment transistor M1 in written frame WF.

[0053] In this embodiment of the invention, the bias adjustment transistor M1 is a P-type transistor, and correspondingly, the effective level of the first scan signal is low.

[0054] And / or, as shown in Figures 6 and 7, Figure 6 is another timing diagram provided by an embodiment of the present invention, and Figure 7 is yet another timing diagram provided by an embodiment of the present invention, at least partially at the first frequency f1, the bias voltages corresponding to the hold frame HF and the write frame WF are different.

[0055] In pixel circuit 1, bias adjustment transistor M1 turns on in response to the effective level of the first scan signal, writing a bias voltage into the gate of driving transistor M0, thereby adjusting the bias state of driving transistor M0. The on-time of bias adjustment transistor M1 and the magnitude of the bias voltage affect the degree to which bias adjustment transistor M1 controls the bias state of driving transistor M0, thus affecting the device characteristics of driving transistor M0, the magnitude of the drive current, and ultimately, the pixel brightness.

[0056] Compared to the write frame (WF), this embodiment of the invention dynamically sets the total conduction time and / or bias voltage of the bias adjustment transistor M1 in at least part of the hold frame (HF). This allows for further adjustment of the bias state of the drive transistor M0 during the hold phase, adjusting the drive current during the hold phase, suppressing the trend of brightness change during the hold phase, reducing the brightness difference between the hold phase and the write frame (WF), and thus effectively improving the flickering phenomenon under low-frequency drive.

[0057] On the other hand, because this technical solution can effectively improve the flicker problem of low-frequency driving, the display panel can be driven at a lower frequency, the selection range of the minimum driving frequency of the display panel can be reduced to a lower level, and the display panel can better take advantage of the power saving of low frequency.

[0058] Referring to Figure 3, the pixel circuit 1 also includes a gate reset module 6 and a threshold compensation module 7. The control terminal of the gate reset module 6 is electrically connected to the second scan line S1N, the first terminal is electrically connected to the first reset line Ref1, and the second terminal is electrically connected to the control terminal of the drive module 2. The control terminal of the threshold compensation module 7 is electrically connected to the third scan line S2N, the first terminal is electrically connected to the second terminal of the drive module 2, and the second terminal is electrically connected to the control terminal of the drive module 2.

[0059] More specifically, the gate reset module 6 includes a gate reset transistor M4, which can be an indium gallium zinc oxide (IGZO) transistor. The gate of the gate reset transistor is electrically connected to the second scan line S1N, the first terminal is electrically connected to the first reset line Ref1, and the second terminal is electrically connected to the gate of the driving transistor M0. The threshold compensation module 7 includes a threshold compensation transistor M5, which can also be an IGZO transistor. The gate of the threshold compensation transistor is electrically connected to the third scan line S2N, the first terminal is electrically connected to the second terminal of the driving transistor M0, and the second terminal is electrically connected to the gate of the driving transistor M0.

[0060] Typically, as shown in Figure 1, due to the leakage current of the gate reset transistor M3 and the threshold compensation transistor M4, the brightness will show an upward trend during the holding phase when driven at low frequency.

[0061] To suppress this upward trend, in one feasible implementation, referring to Figures 4 and 5, the first duration corresponding to frame HF is at least partially maintained to be greater than the first duration corresponding to the written frame WF.

[0062] That is, compared to the write frame WF, the total conduction time of the bias adjustment transistor M1 is increased during at least part of the hold frame HF, and the control time of the bias adjustment transistor M1 on the drive transistor M0 is lengthened, which can control the device characteristics of the drive transistor M0 to a greater extent, suppress the upward trend of brightness during the hold phase, and reduce the brightness difference between the hold phase and the write frame WF.

[0063] In one feasible implementation, as shown in FIG8, FIG8 is another timing diagram provided by an embodiment of the present invention. The holding frame HF includes a first holding frame HF1 and a second holding frame HF2. The first holding frame HF1 is located between the write frame WF and the second holding frame HF2.

[0064] The first duration corresponding to the second hold frame HF2 is greater than the first duration corresponding to the first hold frame HF1.

[0065] In related technologies, referring to Figure 1, the farther the hold frame HF is from the write frame WF, the greater the difference in brightness between its brightness and that of the write frame WF. In the above setting method, by setting the first duration corresponding to the first hold frame HF1, which is closer to the write frame WF, to be slightly shorter, and setting the first duration corresponding to the second hold frame HF2, which is farther from the write frame WF, the timing settings of the first hold frame HF1 and the second hold frame HF2 can be adjusted more specifically, so that the brightness of the first hold frame HF1 and the second hold frame HF2 are both adjusted in a direction closer to the brightness of the write frame WF.

[0066] When the first duration corresponding to at least partially held frame HF is greater than the first duration corresponding to written frame WF, in one feasible implementation, referring to Figures 4, 5 and 8, the second duration t corresponding to at least partially held frame HF can be made greater than the second duration t corresponding to written frame WF, wherein the second duration t is the duration of a single effective level in the first scan signal, that is, the low-level duration of a single pulse in the first scan signal.

[0067] Compared to the write frame (WF), this driving method does not change the number of pulses in the first scan signal within the hold frame (HF), but only increases the duration of the effective level in the first scan signal. Increasing the duration of the effective level in the first scan signal increases the adjustment time of the bias control transistor M1 on the bias state of the driving transistor M0, thereby suppressing the upward trend of brightness during the hold phase and reducing the brightness difference between the hold phase and the write frame (WF).

[0068] To address this, embodiments of the present invention tested the brightness of the hold frame based on several different second durations. At 1 Hz, the hold frame HF brightness was 0.01640 nits when the second duration was 24 hours; 0.01609 nits when the second duration was 28 hours; 0.01580 nits when the second duration was 32 hours; and 0.01556 nits when the second duration was 36 hours. It is evident that the longer the second duration, the lower the hold frame brightness, effectively suppressing the upward trend in brightness during the hold phase.

[0069] Furthermore, as shown in Figure 9, which is another timing diagram provided by an embodiment of the present invention, the second duration corresponding to at least partially continuous hold frames HF increases.

[0070] For example, referring to Figure 9, the drive cycle T at 1Hz includes the first hold frame HF(1) to the 119th hold frame HF(119), wherein the second duration corresponding to the 12th hold frame HF(12) to the 119th hold frame HF(119) increases.

[0071] This setting method increments the second duration corresponding to multiple hold frames (HF), allowing for more precise control over the brightness within these multiple hold frames (HF). The brightness of each hold frame (HF) can be adjusted to be close to the brightness of the write frame (WF), resulting in a better improvement effect.

[0072] Alternatively, as shown in Figure 10, which is another timing diagram provided by an embodiment of the present invention, the driving period T includes a first hold period K1 and a second hold period K2. The first hold period K1 and the second hold period K2 each include at least two hold frames HF, and the first hold period K1 is located between the write frame WF and the second hold period K2.

[0073] In the first holding period K1, the second durations corresponding to different holding frames HF are equal, and in the second holding period K2, the second durations corresponding to different holding frames HF are equal. The second duration of the second holding period K2 is greater than the second duration of the first holding period K1.

[0074] For example, referring to Figure 10, the drive period T at 1Hz includes the first hold frame HF(1) to the 119th hold frame HF(119), wherein the first hold period K1 includes the 12th hold frame HF(12) to the x1th hold frame HF(x1), and the second hold period K2 includes the x1+1th hold frame HF(x1+1) to the x2th hold frame HF(x2).

[0075] The number of holding frames HF included in the first holding period K1 and the second holding period K2 can be the same or different.

[0076] In one specific driving method, the driving period T includes multiple holding periods, and each holding period includes at least two holding frames HF. The second duration corresponding to different holding frames HF in each holding period is equal, and the second duration corresponding to multiple holding periods increases sequentially. Among them, the first holding period in any two adjacent holding periods can be understood as the first holding period K1, and the second holding period can be understood as the second holding period K2.

[0077] This setting method adjusts the second duration in units of holding time periods. Setting the second duration is relatively simple and is more suitable for situations where there are many holding frames (HF).

[0078] Furthermore, the difference in the second duration corresponding to at least some of the adjacent hold frames HF is Δt, where 2H≤Δt≤8H.

[0079] Where H represents the row time. f is the fundamental frequency of the display panel, and n is the row number of pixel circuit 1 in the display panel.

[0080] Setting the minimum value of Δt to 2H ensures sufficient suppression of the brightness increase trend during the hold phase. Setting the maximum value of Δt to 8H prevents the second duration of later hold frames (HF) from becoming too long when there are many hold frames (HF). Because the high level of the emission control signal needs to cover the low level of the first scan signal, an excessively long second duration corresponding to the hold frame (HF) would require a longer duration for the high level of the emission control signal, which would compress the emission time and affect the brightness.

[0081] When the first duration corresponding to at least partially held frame HF is greater than the first duration corresponding to written frame WF, in another feasible implementation, as shown in FIG11, FIG11 is another timing diagram provided by the embodiment of the present invention, the first quantity corresponding to at least partially held frame HF is greater than the first quantity corresponding to written frame WF, wherein the first quantity is the number of effective levels of the first scan signal in the light emission period T1, that is, the number of pulses of the first scan signal in the light emission period T1.

[0082] For example, referring to Figure 11, at 1 Hz, within a write frame WF, the first scan signal has one pulse in one light emission cycle T1, and within the 12th hold frame HF(12) to the 119th hold frame HF(119), the first scan signal has two or more pulses in one light emission cycle T1.

[0083] Compared to the write frame (WF), this driving method does not change the duration of the effective level in the first scan signal within the hold frame (HF), but only increases the number of pulses in the first scan signal during the light emission period (T1). Increasing the number of pulses in the first scan signal during T1 also increases the total conduction time of the bias adjustment transistor M1, thereby increasing the degree to which the bias adjustment transistor M1 regulates the bias state of the driving transistor M0, and suppressing the upward trend of brightness during the hold phase.

[0084] Regarding the effect of bias voltage on brightness, the inventors discovered during their research that the role of bias voltage is mainly reflected in two aspects.

[0085] Firstly, the bias voltage affects the bias of the driving transistor M0, which in turn affects the device state of the driving transistor M0. The higher the bias voltage, the more negative the gate-source voltage Vgs of the driving transistor M0, and the greater the negative bias of the threshold voltage of the driving transistor M0. When the gate voltage of the driving transistor M0 remains unchanged, the more negatively biased the threshold voltage of the driving transistor M0, the lower the brightness of the pixel.

[0086] Secondly, the bias voltage affects the charging of the light-emitting element. The higher the bias voltage, the more positive charge is stored in the pixel circuit 1 for the light-emitting element to light up, resulting in an increase in the brightness of the pixel.

[0087] In low grayscale display, the charging of the light-emitting element is significantly affected by the positive charge in pixel circuit 1, so the influence of bias voltage on brightness is mainly reflected in the second aspect. In high grayscale display, however, the brightness of the light-emitting element is mainly affected by the device state of the driving transistor M0, so the influence of bias voltage on brightness is mainly reflected in the first aspect.

[0088] In one feasible implementation, as shown in Figure 12, which is another timing diagram provided by an embodiment of the present invention, at the first gray level G1 of the first frequency f1, the bias voltage corresponding to the frame HF is at least partially maintained to be less than the bias voltage corresponding to the write frame WF. Here, the first gray level G1 is less than 128 gray levels, and can be understood as a low gray level.

[0089] In the first grayscale G1, the display panel displays at a low grayscale. As mentioned earlier, the effect of the bias voltage on brightness at this time is mainly reflected in the second aspect. Therefore, compared with the write frame WF, by setting the bias voltage corresponding to the hold frame HF to a lower value, the positive charge stored in the pixel circuit 1 for the light-emitting element to light up can be reduced, thereby reducing the brightness. This can effectively suppress the upward trend of brightness during the hold phase and improve the flickering phenomenon at low grayscale.

[0090] To address this, embodiments of the present invention also tested the brightness of the maintained frame based on several different bias voltages. At 1Hz drive, the brightness was 0.02246 nits with a bias voltage of 7.2V; 0.02079 nits with a bias voltage of 7.1V; 0.01887 nits with a bias voltage of 7.05V; and 0.01733 nits with a bias voltage of 7V. It is evident that the smaller the bias voltage, the lower the brightness, and the more significant the suppression of the brightness increase trend.

[0091] Furthermore, the first gray level G1 is less than or equal to 16 gray levels.

[0092] The lower the grayscale, the more easily screen flicker becomes visible to the human eye. This invention specifically targets displays with grayscale levels of 16 and below, significantly improving low-grayscale flicker while saving power.

[0093] In one feasible implementation, as shown in Figure 13, which is another timing diagram provided by an embodiment of the present invention, at the second gray level G2 of the first frequency f1, the bias voltage corresponding to the frame HF is at least partially maintained to be greater than the bias voltage corresponding to the written frame WF. Here, the second gray level G2 is greater than or equal to 128 gray levels, which can be understood as a high gray level.

[0094] In the second grayscale G2, the display panel displays high grayscale. As mentioned earlier, the influence of the bias voltage on brightness at this time is mainly reflected in the first aspect. Therefore, compared with the write frame WF, the bias voltage corresponding to at least partially hold frame HF is set higher. By adjusting the bias state of the driving transistor M0 using the bias adjustment transistor M1, the negative bias of the threshold voltage of the driving transistor M0 can be increased, thereby reducing the brightness. This effectively suppresses the upward trend of brightness during the hold phase and improves the flickering phenomenon under high grayscale.

[0095] In one feasible implementation, the bias voltage corresponding to frame HF is maintained at least partially continuously, and further, it may be an arithmetic gradient.

[0096] For example, at 1Hz, in the first gray level G1, the bias voltages corresponding to the 12th hold frame HF(12) to the 119th hold frame HF(119) decrease sequentially, for example, to 7.15V, 7.14V, 7.13V, ... In the second gray level G2, the bias voltages corresponding to the 12th hold frame HF(12) to the 119th hold frame HF(119) increase sequentially, for example, to 7V, 7.01V, 7.02V, ...

[0097] This setting method involves gradually adjusting the bias voltage corresponding to multiple hold frames (HF), which allows for more precise control over the brightness within these multiple hold frames (HF). The brightness of each hold frame (HF) can be adjusted to be close to the brightness of the write frame (WF), resulting in a better improvement effect.

[0098] Alternatively, the drive cycle T includes a first hold period K1 and a second hold period K2, each of which includes at least two hold frames HF, and the first hold period K1 is located between the write frame WF and the second hold period K2.

[0099] In this case, the bias voltages corresponding to the first holding period K1 are equal, the bias voltages corresponding to the second holding period K2 are equal, and the bias voltages corresponding to the first holding period K1 and the second holding period K2 are different.

[0100] For example, at 1Hz, the first hold period K1 includes the 12th hold frame HF(12) to the x1th hold frame HF(x1), and the bias voltages corresponding to the 12th hold frame HF(12) to the x1th hold frame HF(x1) are equal. The second hold period K2 includes the x1+1th hold frame HF(x1+1) to the x2th hold frame HF(x2), and the bias voltages corresponding to the x1+1th hold frame HF(x1+1) to the x2th hold frame HF(x2) are equal. At the first grayscale G1, the bias voltage corresponding to the first hold period K1 is greater than the bias voltage corresponding to the second hold period K2. At the second grayscale G2, the bias voltage corresponding to the first hold period K1 is less than the bias voltage corresponding to the second hold period K2.

[0101] The number of holding frames HF included in the first holding period K1 and the second holding period K2 can be the same or different.

[0102] In one specific driving method, the driving cycle T includes multiple holding periods, each of which includes at least two holding frames HF. The bias voltages corresponding to different holding frames HF within a holding period are equal, and the bias voltages corresponding to multiple holding periods increase or decrease sequentially. In this driving method, the preceding holding period in any two adjacent holding periods can be understood as the first holding period K1, and the following holding period can be understood as the second holding period K2.

[0103] This setting method adjusts the bias voltage in units of holding time periods. The setting of the bias voltage is relatively simple and is more suitable for situations where there are many holding frames (HF).

[0104] Furthermore, the difference in bias voltage corresponding to at least some adjacent hold frames HF is ΔV, where 0.01V≤|ΔV|≤0.1V.

[0105] Setting the minimum value of |ΔV| to 0.01V ensures sufficient suppression of the upward trend in brightness during the hold phase. Setting the maximum value of |ΔV| to 0.1V avoids excessively high or low bias voltages for later hold frames (HFs) when there are many hold frames, thus reducing the design complexity of the bias voltage.

[0106] In one feasible implementation, referring to Figures 9, 12 and 13, the driving period T includes a first time period P1 and a second time period P2. The first time period P1 is located between the write frame WF and the second time period P2. The first time period P1 and the second time period P2 each include multiple hold frames HF.

[0107] In this process, the first time period P1 has the same first duration as the write frame WF, and the bias voltage corresponding to the first time period P1 is also the same as that corresponding to the write frame WF. The second time period P2 has a different first duration than the write frame WF, and / or the bias voltage corresponding to the second time period P2 is different from that corresponding to the write frame WF.

[0108] In the first time period P1, which is close to the write frame WF, the brightness change is not very obvious, and the brightness difference with the write frame WF is small. Therefore, the first duration and bias voltage corresponding to the first time period P1 can be set to be the same as the write frame WF, and only the first duration and / or bias voltage corresponding to the second time period P2 can be set to be different from the write frame WF, thereby saving power consumption.

[0109] Furthermore, the display panel also has a fundamental frequency f and a second frequency f2, where f > f2 > f1. The driving cycle T at the first frequency f1 includes... There are 1 hold frames HF, where the first time period P1 includes the 1st to the 2nd hold frames. The hold frame HF, the second time period P2 includes the first .... The ~th One hold frame HF.

[0110] In one specific driving mode, referring to Figures 9, 12, and 13, the base frequency f is 120Hz, the first frequency f1 is 1Hz, and the second frequency f2 is 10Hz. The driving cycle T at 1Hz includes one write frame WF and 119 hold frames HF, and the driving cycle T at 10Hz includes one write frame WF and 11 hold frames HF. At the first frequency f1, the first time period P1 includes the first hold frame HF(1) to the eleventh hold frame HF(11), and the second time period P2 includes the twelfth hold frame HF(12) to the eleventh hold frame HF(119).

[0111] This driving method is more suitable for situations where the first frequency f1 is an ultra-low frequency. The second frequency f2 is greater than the first frequency f1, which means that the number of hold frames (HF) in the driving period T corresponding to the second frequency f2 is less, and the increase in brightness during the hold phase will not be too large, resulting in less noticeable flickering.

[0112] To save power consumption and reduce the design complexity of the first duration and bias voltage, at the first frequency f1, the preceding frequency can be selected. The settings within each frame of HF remain unchanged. The number of hold frames HF in the drive period T corresponding to the second frequency f2, only for the first The first duration and / or bias voltage corresponding to the hold frame HF and subsequent hold frames are adjusted.

[0113] In one feasible implementation, referring to Figures 3 and 4, at least part of the first duration corresponding to the hold frame HF is different from that corresponding to the write frame WF. Specifically, at least part of the first duration corresponding to the hold frame HF is longer than the first duration corresponding to the write frame WF.

[0114] The pixel circuit 1 also includes an anode reset module 8. The control terminal of the anode reset module 8 is electrically connected to the first scan line Spx, the first terminal is electrically connected to the first reset line Ref1, and the second terminal is electrically connected to the light-emitting element D.

[0115] More specifically, the anode reset module 8 includes an anode reset transistor M6, the gate of which is electrically connected to the first scan line Spx, the first electrode of which is electrically connected to the first reset line Ref1, and the second electrode of which is electrically connected to the light-emitting element D.

[0116] When the anode reset transistor M6 responds to the effective level of the first scan signal, it turns on, writing the first reset voltage into the light-emitting element D, thus resetting the anode voltage of the light-emitting element D. The increased duration of the first hold frame HF means that the total conduction time of the anode reset transistor M6 within this hold frame HF is also longer. This increases the degree to which the anode reset transistor M6 resets the anode potential of the light-emitting element D, making the anode potential reset more thoroughly, thereby reducing the light emission brightness and suppressing the upward trend of brightness during the hold phase, further improving flicker.

[0117] In one feasible implementation, as shown in FIG14, FIG14 is another timing diagram provided by an embodiment of the present invention. The pixel circuit 1 further includes an anode reset module 8. The first end of the anode reset module 8 is electrically connected to the first reset line Ref1 for providing the first reset voltage, and the second end is electrically connected to the light-emitting element D.

[0118] At least partially, the first reset voltage corresponding to frame HF is less than the first reset voltage corresponding to the write frame WF.

[0119] Compared to the write frame WF, reducing the first reset voltage corresponding to at least part of the hold frame HF can lower the anode potential of the light-emitting element D after it is reset, thereby reducing the light emission brightness. It can also suppress the upward trend of brightness during the hold phase and further improve flicker.

[0120] In one feasible implementation, the first frequency f1 is less than 10 Hz.

[0121] The lower the frequency, the more hold frames (HF) are included in the drive cycle T, the greater the increase in brightness during the hold phase, and the more obvious the difference in brightness between the hold frame and the write frame (WF). Therefore, embodiments of the present invention can more specifically adjust the above-mentioned frequencies below 10Hz, effectively improving the flicker problem under ultra-low drive while saving some power consumption.

[0122] Regarding pixel circuit 1, see Figure 3. Pixel circuit 1 also includes data writing module 9. The control terminal of data writing module 9 is electrically connected to the fourth scan line Sp, the first terminal is electrically connected to the data line Data, and the second terminal is electrically connected to the first terminal of drive module 2.

[0123] More specifically, the data writing module 9 includes a data writing transistor M9, the gate of which is electrically connected to the fourth scan line Sp, the first terminal of which is electrically connected to the data line Data, and the second terminal of which is electrically connected to the first terminal of the driving transistor M0.

[0124] The pixel circuit 1 also includes a storage capacitor Cst, which is electrically connected between the first power line PVDD and the gate of the driving transistor M0.

[0125] The cathode of the light-emitting element D is electrically connected to the second power line PVEE.

[0126] Based on the same inventive concept, this embodiment of the invention also provides a driving method for a display panel. Referring to Figures 2 and 3, the display panel includes a pixel circuit 1, which includes a driving module 2 and a bias adjustment module 3. The control terminal of the bias adjustment module 3 is electrically connected to the first scan line Spx, the first terminal is electrically connected to the bias signal line DVH, and the second terminal is electrically connected to the first terminal of the driving module 2. The first scan line Spx provides a first scan signal, and the bias signal line DVH provides a bias voltage.

[0127] Referring to Figures 4 to 7, the display panel has a first frequency f1. The driving cycle T at the first frequency f1 includes a write frame WF and multiple hold frames HF. The write frame WF and the hold frame HF each include at least one light emission cycle T1.

[0128] The driving method includes: at a first frequency f1, controlling at least a portion of the first duration corresponding to the hold frame HF and the write frame WF to be different, the first duration being the total duration of the effective level of the first scan signal in the light emission period T1, and / or, controlling at least a portion of the bias voltage corresponding to the hold frame HF and the write frame WF to be different.

[0129] Based on the foregoing analysis, this driving method, compared to the write frame (WF), dynamically sets the total conduction time and / or bias voltage of the bias adjustment transistor M1 in at least part of the hold frame (HF). This allows for further adjustment of the bias state of the driving transistor M0 during the hold phase, adjusting the driving current during the hold phase, suppressing the trend of brightness change during the hold phase, reducing the brightness difference between the hold phase and the write frame (WF), and effectively improving flickering under low-frequency driving.

[0130] On the other hand, because this technical solution can effectively improve the flicker problem of low-frequency driving, the display panel can be driven at a lower frequency, the selection range of the minimum driving frequency of the display panel can be reduced to a lower level, and the display panel can better take advantage of the power saving of low frequency.

[0131] In one feasible implementation, referring to Figures 4 and 5, at least partially maintaining the first duration corresponding to frame HF is greater than the first duration corresponding to the written frame WF.

[0132] That is, compared to the write frame WF, the total conduction time of the bias adjustment transistor M1 is increased during at least part of the hold frame HF, and the control time of the bias adjustment transistor M1 on the drive transistor M0 is lengthened, which can control the device characteristics of the drive transistor M0 to a greater extent, suppress the upward trend of brightness during the hold phase, and reduce the brightness difference between the hold phase and the write frame WF.

[0133] In one feasible implementation, referring to Figures 4, 5 and 8, at least partially the second duration t corresponding to frame HF is maintained to be greater than the second duration t corresponding to the written frame WF, where the second duration t is the duration of the effective level in the first scan signal.

[0134] Compared to the write frame (WF), this driving method does not change the number of pulses in the first scan signal within the hold frame (HF), but only increases the duration of the effective level in the first scan signal. Increasing the duration of the effective level in the first scan signal increases the adjustment time of the bias control transistor M1 on the bias state of the driving transistor M0, thereby suppressing the upward trend of brightness during the hold phase and reducing the brightness difference between the hold phase and the write frame (WF).

[0135] And / or, referring to Figure 11, in the light emission period T1, the number of effective levels in the first scan signal is a first number, at least partially maintaining that the first number corresponding to frame HF is greater than the first number corresponding to the write frame WF.

[0136] Compared to the write frame (WF), this driving method does not change the duration of the effective level in the first scan signal within the hold frame (HF), but only increases the number of pulses in the first scan signal during the light emission period (T1). Increasing the number of pulses in the first scan signal during T1 also increases the total conduction time of the bias adjustment transistor M1, thereby increasing the degree to which the bias adjustment transistor M1 regulates the bias state of the driving transistor M0, and suppressing the upward trend of brightness during the hold phase.

[0137] In one feasible implementation, referring to Figure 12, at the first gray level G1 of the first frequency f1, the bias voltage corresponding to the frame HF is at least partially maintained to be less than the bias voltage corresponding to the written frame WF, and the first gray level G1 is less than 128 gray levels. And / or, at the second gray level G2 of the first frequency f1, the bias voltage corresponding to the frame HF is at least partially maintained to be greater than the bias voltage corresponding to the written frame WF, and the second gray level G2 is greater than or equal to 128 gray levels.

[0138] As mentioned earlier, the role of the bias voltage is mainly reflected in two aspects.

[0139] In the first grayscale G1, the display panel displays at a low grayscale. As mentioned earlier, the effect of the bias voltage on brightness at this time is mainly reflected in the second aspect. Therefore, compared with the write frame WF, by setting the bias voltage corresponding to the hold frame HF to a lower value, the positive charge stored in the pixel circuit 1 for the light-emitting element to light up can be reduced, thereby reducing the brightness. This can effectively suppress the upward trend of brightness during the hold phase and improve the flickering phenomenon at low grayscale.

[0140] In the second grayscale G2, the display panel displays high grayscale. As mentioned earlier, the influence of the bias voltage on brightness at this time is mainly reflected in the first aspect. Therefore, compared with the write frame WF, the bias voltage corresponding to at least partially hold frame HF is set higher. By adjusting the bias state of the driving transistor M0 using the bias adjustment transistor M1, the negative bias of the threshold voltage of the driving transistor M0 can be increased, thereby reducing the brightness. This effectively suppresses the upward trend of brightness during the hold phase and improves the flickering phenomenon under high grayscale.

[0141] In one feasible implementation, referring to Figures 9, 12 and 13, the driving period T includes a first time period P1 and a second time period P2. The first time period P1 is located between the write frame WF and the second time period P2. The first time period P1 and the second time period P2 each include multiple hold frames HF.

[0142] In this process, the first time period P1 has the same first duration as the write frame WF, and the bias voltage corresponding to the first time period P1 is also the same as that corresponding to the write frame WF. The second time period P2 has a different first duration than the write frame WF, and / or the bias voltage corresponding to the second time period P2 is different from that corresponding to the write frame WF.

[0143] In the first time period P1, which is close to the write frame WF, the brightness change is not very obvious, and the brightness difference with the write frame WF is small. Therefore, the first duration and bias voltage corresponding to the first time period P1 can be set to be the same as the write frame WF, and only the first duration and / or bias voltage corresponding to the second time period P2 can be set to be different from the write frame WF, thereby saving power consumption.

[0144] Furthermore, the display panel also has a base frequency f and a second frequency f2, where f > f2 > f1.

[0145] The driving cycle T includes There are 1 hold frames HF, where the first time period P1 includes the 1st to the 2nd hold frames. The hold frame HF, the second time period P2 includes the first .... The ~th One hold frame HF.

[0146] In one specific driving mode, referring to Figures 9, 12, and 13, the base frequency f is 120Hz, the first frequency f1 is 1Hz, and the second frequency f2 is 10Hz. The driving cycle T at 1Hz includes one write frame WF and 119 hold frames HF, and the driving cycle T at 10Hz includes one write frame WF and 11 hold frames HF. At the first frequency f1, the first time period P1 includes the first hold frame HF(1) to the eleventh hold frame HF(11), and the second time period P2 includes the twelfth hold frame HF(12) to the eleventh hold frame HF(119).

[0147] This driving method is more suitable for situations where the first frequency f1 is an ultra-low frequency. The second frequency f2 is greater than the first frequency f1, which means that the number of hold frames (HF) in the driving period T corresponding to the second frequency f2 is less, and the increase in brightness during the hold phase will not be too large, resulting in less noticeable flickering.

[0148] To save power consumption and reduce the design complexity of the first duration and bias voltage, at the first frequency f1, the preceding frequency can be selected. The settings within each frame of HF remain unchanged. The number of hold frames HF in the drive period T corresponding to the second frequency f2, only for the first The first duration and / or bias voltage corresponding to the hold frame HF and subsequent hold frames are adjusted.

[0149] Based on the same inventive concept, this embodiment of the invention also provides a display device, as shown in FIG15. FIG15 is a schematic diagram of a structure of the display device provided in this embodiment of the invention, which includes the aforementioned display panel 100. Of course, the display device shown in FIG15 is merely illustrative, and the display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader, or television.

[0150] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: The pixel circuit includes a driving module and a bias adjustment module. The control terminal of the bias adjustment module is electrically connected to a first scan line, the first terminal is electrically connected to a bias signal line, and the second terminal is electrically connected to the first terminal of the driving module. The first scan line provides a first scan signal, and the bias signal line provides a bias voltage. The display panel has a first frequency, and the driving cycle at the first frequency includes a write frame and a plurality of hold frames, wherein the write frame and the hold frame each include at least one light emission cycle; During the light emission cycle, the total duration of the effective level of the first scanning signal is the first duration. At the first frequency, at least some of the hold frames have different first durations than the write frames, and / or at least some of the hold frames have different bias voltages than the write frames.

2. The display panel according to claim 1, characterized in that, The duration of the first duration corresponding to at least a portion of the hold frame is greater than the duration of the first duration corresponding to the write frame.

3. The display panel according to claim 2, characterized in that, The hold frame includes a first hold frame and a second hold frame. The first hold frame is located between the write frame and the second hold frame. The first duration corresponding to the second hold frame is greater than the first duration corresponding to the first hold frame.

4. The display panel according to claim 2, characterized in that, The duration of the effective level in the first scan signal is the second duration; The second duration corresponding to at least a portion of the hold frame is greater than the second duration corresponding to the write frame.

5. The display panel according to claim 4, characterized in that, The second duration corresponding to at least partially consecutive hold frames increases; Alternatively, the drive cycle includes a first hold period and a second hold period, the first hold period being located between the write frame and the second hold period, and the first hold period and the second hold period each including at least two hold frames; Wherein, the second duration corresponding to the first holding period is equal, the second duration corresponding to the second holding period is equal, and the second duration corresponding to the second holding period is greater than the second duration corresponding to the first holding period.

6. The display panel according to claim 5, characterized in that, The difference in the second duration corresponding to at least some of the adjacent hold frames is Δt, where 2H≤Δt≤8H; Where f is the fundamental frequency of the display panel, and n is the number of rows of pixel circuits in the display panel.

7. The display panel according to claim 2, characterized in that, During the light emission cycle, the number of valid levels in the first scan signal is a first number; The first number corresponding to at least a portion of the hold frames is greater than the first number corresponding to the write frames.

8. The display panel according to claim 1, characterized in that, At the first gray level of the first frequency, at least a portion of the bias voltage corresponding to the hold frame is less than the bias voltage corresponding to the write frame, and the first gray level is less than 128 gray levels.

9. The display panel according to claim 8, characterized in that, The first gray level is less than or equal to 16 gray levels.

10. The display panel according to claim 1, characterized in that, At the second grayscale of the first frequency, at least a portion of the bias voltage corresponding to the hold frame is greater than the bias voltage corresponding to the write frame, and the second grayscale is greater than or equal to 128 grayscale levels.

11. The display panel according to claim 8 or 10, characterized in that, The bias voltage gradient corresponding to at least partially continuous holding frames; Alternatively, the drive cycle includes a first hold period and a second hold period, the first hold period being located between the write frame and the second hold period, and the first hold period and the second hold period each including at least two hold frames; Wherein, the bias voltages corresponding to the first holding period are equal, the bias voltages corresponding to the second holding period are equal, and the bias voltages corresponding to the first holding period and the second holding period are different.

12. The display panel according to claim 11, characterized in that, The difference in bias voltage corresponding to at least some of the adjacent holding frames is ΔV, where 0.01V≤|ΔV|≤0.1V.

13. The display panel according to claim 1, characterized in that, The driving cycle includes a first time period and a second time period, the first time period being located between the write frame and the second time period, and the first time period and the second time period each including a plurality of the hold frames; Wherein, the first time period is equal to the first duration corresponding to the write frame, and the bias voltage corresponding to the first time period is equal to the write frame; The second time period is different from the first duration corresponding to the write frame, and / or the second time period is different from the bias voltage corresponding to the write frame.

14. The display panel according to claim 13, characterized in that, The display panel also has a base frequency and a second frequency, wherein the base frequency is f, the first frequency is f1, and the second frequency is f2, where f > f2 > f1; The driving cycle at the first frequency includes The hold frames, wherein the first time period includes the first to the second hold frames. The second time period includes the first hold frame, wherein the second time period includes the first The ~th The aforementioned holding frames.

15. The display panel according to claim 1, characterized in that, At least some of the hold frames have a different duration than the first duration corresponding to the write frames; The pixel circuit also includes an anode reset module, wherein the control terminal of the anode reset module is electrically connected to the first scan line, the first terminal is electrically connected to the first reset line, and the second terminal is electrically connected to the light-emitting element.

16. The display panel according to claim 1, characterized in that, The pixel circuit also includes an anode reset module, the first end of which is electrically connected to a first reset line and the second end of which is electrically connected to a light-emitting element, and the first reset line provides a first reset voltage. At least a portion of the first reset voltage corresponding to the hold frame is less than the first reset voltage corresponding to the write frame.

17. The display panel according to claim 1, characterized in that, The first frequency is less than 10Hz.

18. A driving method for a display panel, characterized in that, The display panel includes a pixel circuit, including a driving module and a bias adjustment module. The control terminal of the bias adjustment module is electrically connected to a first scan line, the first terminal is electrically connected to a bias signal line, and the second terminal is electrically connected to the first terminal of the driving module. The first scan line provides a first scan signal, and the bias signal line provides a bias voltage. The display panel has a first frequency, and the driving cycle at the first frequency includes a write frame and a plurality of hold frames, wherein the write frame and the hold frame each include at least one light emission cycle; During the light emission cycle, the total duration of the effective level of the first scanning signal is the first duration. The driving method includes: At the first frequency, control at least a portion of the hold frames to have different first durations than the write frames, and / or control at least a portion of the hold frames to have different bias voltages than the write frames.

19. The driving method according to claim 18, characterized in that, The duration of the first duration corresponding to at least a portion of the hold frame is greater than the duration of the first duration corresponding to the write frame.

20. The driving method according to claim 19, characterized in that, The duration of the effective level in the first scan signal is the second duration, and at least a portion of the second duration corresponding to the hold frame is longer than the second duration corresponding to the write frame; And / or, during the light emission cycle, the number of valid levels in the first scan signal is a first number, and at least a portion of the first number corresponding to the hold frame is greater than the first number corresponding to the write frame.

21. The driving method according to claim 18, characterized in that, At the first gray level of the first frequency, at least a portion of the bias voltage corresponding to the hold frame is less than the bias voltage corresponding to the write frame, and the first gray level is less than 128 gray levels; And / or, at the second grayscale of the first frequency, at least a portion of the bias voltage corresponding to the hold frame is greater than the bias voltage corresponding to the write frame, and the second grayscale is greater than or equal to 128 grayscale levels.

22. The driving method according to claim 18, characterized in that, The driving cycle includes a first time period and a second time period, the first time period being located between the write frame and the second time period, and the first time period and the second time period each including a plurality of the hold frames; Wherein, the first time period is equal to the first duration corresponding to the write frame, and the bias voltage corresponding to the first time period is equal to the write frame; The second time period is different from the first duration corresponding to the write frame, and / or the second time period is different from the bias voltage corresponding to the write frame.

23. The driving method according to claim 22, characterized in that, The display panel also has a base frequency and a second frequency, wherein the base frequency is f, the first frequency is f1, and the second frequency is f2, where f > f2 > f1; The drive cycle comprises one of the holding frames, wherein the first time period comprises 1st~3rd one of the holding frames, the second time period comprises a first one ~ the first The aforementioned holding frames.

24. A display device comprising: Includes the display panel as described in any one of claims 1 to 17.

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