Qubit processing method

Abstract

There is provided a method for performing operations in a solid-state qubit processor. A provided (S100) logical qubit, comprising a plurality of data qubits, is extended (S102) and split (S104) to create two or more entangled portions. A first portion is shuttled (S106) in the qubit processor, separating it from a second portion, which may remain in place. During this shuttling process, faults may have occurred, which may have damaged or corrupted the first portion. Accordingly, a likelihood of fault is determined (S108), based upon a measurement operation. Based upon the likelihood of fault, the first portion or the second portion is selected (S110). In some examples, when selecting the first portion, the logical qubit is shuttled, and when selecting the second portion, the shuttling process is reversed and any potential damage or corruption to the first portion is reverted, with the logical qubit returned to its initial state. In this way, the method may provide a "logically reversible" shuttling operation.

Description

[0001] QUBIT PROCESSING METHOD

[0002] FIELD OF THE INVENTION

[0003] The invention relates to a qubit processing method, and more specifically, a qubit processing method for performing operations in a solid-state qubit processor.

[0004] BACKGROUND

[0005] Quantum computation involves the manipulation and processing of qubits. A qubit, or a quantum bit, is the quantum parallel to the “bit” used in classical (i.e. non-quantum) computers. There are a number of possible quantum computing schemes that can be used to process qubits.

[0006] Individual physical qubits are vulnerable to noise, occurring as effects from the environment or imperfections in the control processes that are applied to execute the computation. In order to overcome this issue and prevent noise from causing accumulating errors which corrupt the computation, fault tolerance can be used. In this approach a smaller number of so-called logical qubits are encoded using a larger number of physical qubits. In order to detect and correct any errors occurring due to noise, the physical qubits which make up the logical qubits are frequently checked using certain measurements called stabiliser measurements.

[0007] In the absence of any errors or faults, the outcome of these stabiliser measurements remains the same from one measurement cycle to the next. When errors occur to the physical qubits, the stabiliser cycle measurements change. The set of stabiliser measurements is referred to as the syndrome. By processing the syndrome on a classical computer it is possible to infer the nature of the error(s) that have occurred to the physical qubits. The errors can then be corrected, either by applying operations to the physical qubits or simply by recording their altered state in the classical software that controls the computation.

[0008] In order to achieve fault tolerance an error correcting code may be used. The code specifies the way in which the logical qubits are to be formed from physical qubits and specifies the check process, e.g. the stabiliser measurements that areto be made. For many codes, it may be advantageous to lay out the qubits in at least 2 dimensions. In one well-studied example called the surface code, logical qubits correspond to two-dimensional arrays of qubits and the stabiliser measurements apply to local groups of four qubits throughout this grid. It may be important that the layout or arrangement of the physical qubits is compatible with the code.

[0009] The particular way in which physical qubits can be arranged in the quantum computer depends upon the platform that is being used, i.e. the type of technology, for example ion trap, neutral atom, superconducting, or semiconducting, such as silicon. In silicon and other semiconductor solid state devices, typically small regions called quantum dots are used to trap individual electrons. A quantum dot may be on the scale of tens of nanometres in size. The spin of such an electron confined in a quantum dot can constitute a physical qubit. In these systems the layout of qubits is typically two-dimensional.

[0010] A difficulty arises in that, in the present state of technology, an extended grid of qubits in the solid-state is difficult to achieve when that grid is large, i.e. containing more than a few tens of qubits. Arrays with many hundreds of qubits along each edge may be required by a fault tolerant quantum computer. The present limitation in semiconductor devices relates to a form of wiring challenge, the difficulty of applying sufficient electrodes to define all the quantum dots that would be needed, and to make space for complementary systems such as measuring devices.

[0011] However, it is challenging to implement fault-tolerant quantum computing in different architectures, which may otherwise simplify the above. For instance, in a one-dimensional array, if a quantum dot anywhere along the length is inoperable, the device may be divided into two separate pieces and computation between these pieces would be impossible. At the present state of the technology, it is highly likely that there would be at least one such defect in a device with many thousands of quantum dots, rendering the manufacture of a qubit processor in this style infeasible. Relevant architectures have been previously discussed by the inventors in “Towards Early Fault Tolerance on a 2 *N Array of Qubits Equipped with Shuttling”, PRX Quantum 5, 040328, doi: 10.1103 / PRXQuantum.5.040328.Accordingly, there is a need for a fault-tolerant method of performing operations in a quantum computer without the complexity and spatial requirements of the above-mentioned methods.

[0012] SUMMARY OF INVENTION

[0013] According to a first aspect, there is provided a method for performing operations in a solid-state qubit processor, comprising the steps of: providing a logical qubit comprising a plurality of data qubits; extending the logical qubit by generating one or more extensions to the plurality of data qubits, wherein each extension comprises data qubits that correspond to, and are entangled with, the original plurality of data qubits; splitting the extended logical qubit into two or more portions; shuttling a first portion of the one or more portions so that the first portion and a second portion of the one or more portions are separated from one another; performing a measurement operation to determine a likelihood that faults have occurred during the shuttling step; and selecting one of the first portion or the second portion of the logical qubit based on the determined likelihood.

[0014] The method provides a means for shuttling logical qubits in a fault-tolerant manner, as is explained below, which may enable fault-tolerant quantum computing in novel architectures.

[0015] Shuttling logical qubits in qubit processors is desirable, as it allows logical qubits to be bought into close proximity with each other, such that they can interact and / or perform two-qubit gate operations. Fault-tolerant shuttling is desirable as it enables the movement of logical qubits while resisting the impact of noise and other errors, which may otherwise negatively impact computation using the logical qubits.

[0016] The logical qubit comprises a plurality of physical qubits. The physical qubits may be physical devices which behave as or otherwise host a two-state quantum system. In some examples, the physical qubit can be understood as comprising both a qubit location, that is, a device or apparatus which provides a region of space where a qubit can exist such as a quantum dot, and a quantum object,being a two-state quantum system such as an electron bound in the quantum dot. In some examples, qubits may instead have three states, four states, or N states. It should be understood that operations said to be performed on the physical qubit, such as shuttling of the qubit, may be understood as operating either on solely the quantum object, (in the example of a quantum dot, the electron bound within), or on both the qubit location (the quantum dot itself) and the quantum object (the electron).

[0017] In some examples, the physical qubits are data qubits. In some examples, the physical qubits may comprise spin qubits, and, in such examples, may comprise silicon spin qubits. The physical qubits may comprise individual electrons bound in quantum dots, where the quantum dots may be formed in silicon or other semiconducting material. Similarly, the physical qubits may comprise a plurality of electrons bound in quantum dots. Accordingly, the physical qubits may comprise silicon spin qubits comprising quantum dots formed in silicon.

[0018] Alternatively, the physical qubits may comprise atoms or ions held in a vacuum and shuttled via adjustments to electric fields or lasers.

[0019] In some examples, the logical qubit comprises data qubits located on a two-dimensional (2D) lattice. Optionally, the 2D lattice, or “latticework” may comprise a 2xN array of qubits, or, alternatively, multiple 2xN arrays of qubits, where N is an integer. Moreover, such multiple arrays of qubits need not all have the same length, that is, N may differ for each of the multiple arrays of qubits. Such arrays of qubits may be connected at junctions between multiple arrays, such as two arrays, or three arrays. Alternatively, in some examples, the logical qubit may comprise data qubits located on a 1 D lattice, or a 3D lattice.

[0020] The logical qubit may be a one-dimensional sequence of physical qubits ( / .e. a 1 xN arrangement of qubits) or may be a two-dimensional arrangement of physical qubits. Such a two-dimensional arrangement may be an MxN array or grid of qubits or may have a more complicated structure.The logical qubit is extended by providing an extension, comprising additional data qubits, where the additional data qubits are entangled with the original data qubits of the logical qubit. In some examples, there is a one-to-one correspondence between the original data qubits and the additional data qubits, i.e. the extension comprises the same number of qubits as the logical qubit. In other examples, the extension may comprise additional data qubits, or fewer data qubits, than the logical qubit. In some examples, the data qubits of the logical qubit and the extension are provided on a 2D lattice, and the extension of the logical qubit comprises lattice surgery. It should be understood that, in some examples, the logical qubit and / or the extension may comprise additional qubits, such as monitor qubits, as discussed below.

[0021] The method further comprises splitting the extended logical qubit into one or more portions. In some examples, each of these portions corresponds to either one of the one or more extensions, or the original logical qubit. In some examples, a first portion may comprise the original qubits of the logical qubit, a second portion may comprise the qubits of a first extension of the one or more extensions, etc. Alternatively, there may not be a one-to-one correspondence between the qubits of a portion and the qubits of any one of the extensions.

[0022] The method further comprises shuttling a first portion of the extended logical qubit, such that the first portion is separated from a second portion of the extended logical qubit. This shutting process comprises moving the physical qubits of the portion of the extended logical qubit in space. In some cases, for example, when the physical qubits comprise quantum dots and each data qubit therefore comprises one or more confined electrons, this comprises adjusting the shape of one or more confining electrical fields which hold electrons in place, such that each electron moves between two quantum dots (or the quantum dots themselves move with respect to the substrate).

[0023] Additionally, the method comprises performing a measurement operation to determine a likelihood that faults have occurred during the shuttling step. In some examples, the faults may comprise modification of the state of one or more qubits due to noise. The noise may comprise, for example, phase noise, charge noiseor gate noise. Such faults may cause dephasing or modified phase of the state of one or more qubits or may comprise bit flips or state transitions.

[0024] The faults may be caused by localised noise sources, which may be relatively close to the portion of the extended logical qubit during the shuttling process. For example, in the case of silicon spin qubits, a static charge defect may be present relatively close to a shuttling path and may interact with one or more data qubits as they are shuttled past. Such faults may comprise dephasing errors or logical errors, or and may cause out-of-calibration drifts or catastrophic events. The fault may comprise a correlated error, such as coherent or incoherent phase rotation of more than one of the physical qubits.

[0025] Finally, the method comprises selecting one of the first portion or the second portion of the logical qubit based on the determined likelihood. The step of selecting these portions may comprise performing a measurement operation on the non-selected portion, which may project the delocalised logical state (the logical state of the extended logical qubit, which has been separated) onto the remaining, selected portion. Accordingly, the selection step may comprise the wavefunction collapse of the state of any non-selected portions. The non-selected portions may therefore no longer contain the logical information encoded in the extended logical qubit, which, after the selection, remains only in the state of the selected portion. The selection step may be performed at least in part by a computer, such as a classical computer. With a 50% probability the act of projecting out the non-selected portion will induce a phase flip on the selected portion; whether this has indeed occurred is determined by the outcome of the measurement of the non-selected portion (“0” or “1”). If such a flip has occurred the method may involve applying a compensating operation to the selected portion, or simply suitably updating future operations on that logical qubit to subsume the compensating operation.

[0026] Of course, in other examples, there may be more than two portions, and the selection may comprise selecting one of the one or more portions.Selecting a portion based on the likelihood that faults occurred during the shuttling process allows for assessment of the risk that the first portion has become corrupt, damaged or modified by the shutting process. In some examples, if there is any substantial and / or non-zero probability of error, the first portion (the shuttled portion) will not be selected, and the second portion (the non-shuttled portion) will be selected. In other examples, the selection may be determined, at least in part, based on other factors, for instance, how critical or important this particular shuttling process is to some overall computation.

[0027] In such examples, the shuttling may be considered “logically-reversable” shuttling. This is because, when selecting the non-shuttled portion, the state of the logical qubit and / or a system in which the logical qubit is hosted, may be “reversed” to before the shuttling process was performed. Subsequently, in the case of a failure and reversal of the shuttling process by selecting the non-shuttled portion, the shuttling may be attempted again. The method may therefore be a “repeat-until-success” method, where the shuttling is attempted until a sufficiently low likelihood of fault is determined.

[0028] In some examples, the method further comprises providing and initialising a plurality of monitor qubits in the first portion, wherein the measurement operation involves measuring at least a subset of the plurality of monitor qubits in the first portion of the logical qubit. Monitor qubits may be included in the first portion of the logical qubit, prepared in a known initial quantum state, in order to provide an additional means to determine if errors or faults have occurred during the shuttling process. The monitor qubits do not store the computational information stored in the logical qubit, e.g. the logical information encoded in the logical qubit.

[0029] Optionally, in some examples, the measurement operation may comprise determining a likelihood of a fault occurring, such as phase noise having affected some or all of the data qubits, by measuring the state of at least a plurality of the monitor qubits to determine their state and / or a phase and comparing this to the initial state / initial phase. The provision of monitor qubits may enable the detection of catastrophic events such as logical errors, which may be induced by sufficientlystrong phase noise, for instance, the noise sources discussed above, or phase noise caused by a point defect along or relatively close to a shuttling path.

[0030] The number of monitor qubits provided may vary. In some examples, the number of monitor qubits may be a fixed or preset value, or it may be dependent on the size of the logical qubit (number of physical qubits in the logical qubit) or other factors, such as an estimated prevalence of phase noise or risk of fault occurring. In some examples, at least 10 monitor qubits are used, i.e. at least 10 monitor qubits are provided and initialised in the first portion. Preferably, at least 50 monitor qubits are used. More preferably, at least 100 monitor qubits are used. As the qubits host quantum states, which are by their nature probabilistic, a greater number of monitor qubits may provide a more accurate determination of a fault. Additionally, the process of measuring a monitor qubit may have some small but finite chance of reporting incorrect information, and the use of a greater number of monitor qubits reduces the significance of such errors.

[0031] In some examples, the measurement operation involves determining whether a statistical threshold of monitor qubits are in a particular state. In some examples, the measurement operation may involve determining whether a statistical threshold of the monitor qubits remain in their initial state. Optionally, the statistical threshold is preset, for example, being set at 99% of the monitor qubits being in a certain state. In some examples, all of the monitor qubits in the first portion are measured. Alternatively, it may be sufficient to measure only a subset of the monitor qubits. For instance, in some examples, once a statistical threshold has been reached (that is, a certain number of the monitor qubits have been determined to be in a particular state), it may not be necessary to measure the remaining monitor qubits.

[0032] Optionally, in some examples, the plurality of monitor qubits are interlaced with the data qubits in the first portion of the logical qubit. Interlacing the monitor qubits with the data qubits may enable the detection of short-lived sources of noise, which may appear and disappear at arbitrary times. The monitor qubits may be interlaced with the data qubits in an alternating manner or be arranged among the data qubits in any other regular or irregular pattern or sequence. Of course, themonitor qubits may also be arranged contiguously at a single location or a plurality of locations. It may be important that the monitor qubits experience the same environmental effects as the data qubits, such that the effects of noise can be accurately captured.

[0033] Optionally, in some examples, the measurement operation comprises a stabiliser operation on the data qubits and determinising a likelihood that faults have occurred based on a number of syndrome events that are determined by the stabiliser operation. This may improve the accuracy of the detection of a fault. Stabiliser operations may help to maintain a logical qubit, as well as produce measurements which may be used to detect faults and errors.

[0034] When the likelihood of fault is relatively low, or zero, the shuttling operation may be considered a success. In such an example, selecting the first portion of the extended logical qubit enables the completion of the shuttling process in such a way that the chance of error is low. Accordingly, in some examples, when the measurement operation indicates a likelihood of faults that is below a threshold, the first portion of the logical qubit is selected, and the method involves measuring the plurality of data qubits in the second portion of the logical qubit to remove that portion. As noted above, the information gained during the measurement of these data qubits determines a phase. Knowledge of this phase is necessary to maintain the integrity of the selected portion, as it implies a subsequent compensating operation on the selected portion may be required. Accordingly, in such examples, the method may further comprise the step of applying a gate operation to the first portion of the logical qubit based on the determined phase.

[0035] Optionally, in some examples, when the measurement operation indicates a likelihood of faults that is above a threshold, the second portion of the logical qubit is selected, and the method involves measuring the plurality of data qubits in the first portion of the logical qubit to remove that portion. As noted above, the information gained during the measurement of these data qubits determines a phase. Knowledge of this phase is necessary to maintain the integrity of the selected portion, as it implies a subsequent compensating operation on the selected portion may be required.When the likelihood of fault is relatively high, the shuttling operation may be considered a failure or a potential failure, in that the shuttled portion may have been modified, damaged or corrupted. In such an example, selecting the second portion of the extended logical qubit (a non-shuttled portion) enables the nonshuttled portion to be maintained, and the shuttled portion to be discarded.

[0036] In some examples, the logical qubit can be expressed as |Q>L= a |+>L+ b |->Land the step of extending the logical qubit involves generating the extension, |Q-ex> L = a |+> L |+> L + b |->L|-> L, wherein the measurement operation is performed in the Z basis. This representation of the logical qubit may be advantageous when the expected noise experienced by the logical qubit is primarily phase noise.

[0037] In some examples, the logical qubit can be expressed as |Q>L= a |0>L+ b |1>Land the step of extending the logical qubit involves generating the extension, |Q-ex> L = a |0) L |0) L + b |1) L |1) L, wherein the measurement operation is performed in the X basis. This representation of the logical qubit may be advantageous when the expected noise experienced by the logical qubit is primarily bit flip noise.

[0038] In some examples, the step of extending the logical qubit comprises performing a stabiliser sequence on the extended logical qubit. Performing a stabiliser sequence on the combination of the original logical qubit and the extension may combine the original logical qubit and the extension to create an extended logical qubit. Advantageously, as similar stabilising sequences may already be performed in order to maintain the logical qubit or as part of the measurement operation, this may simplify the extension of the logical qubit.

[0039] It may be advantageous to attempt to shuttle a logical qubit via a plurality of routes, for instance, in the case where one of the routes may be adversely affected by a noise source. This may reduce the probability of error. Accordingly, in some examples, the method may further comprise shuttling a third portion of the one or more portions, such that the first portion, second portion and third portion are separated from one another, wherein the step of performing a measurement operation comprises: measuring the first portion to determine a correspondinglikelihood that faults have occurred when shuttling the first portion; and when said likelihood is above a first threshold, measuring the third portion to determine a corresponding likelihood that faults have occurred when shuttling the third portion; wherein the step of selecting comprises selecting one of the first portion, second portion or third portion of the logical qubit based on the determined likelihoods.

[0040] In some examples, the original logical qubit is extended to produce an extended logical qubit comprising two extensions. Such an extended logical qubit may be divided into three portions. Of course, in other examples, the logical qubit may be extended and portioned any number of times. In such examples, two of these portions are shuttled (referred to as the first portion and the third portion for consistency, though it should be understood that any of these portions could be shuttled). These portions may be shuttled to the same destination, or to different destinations.

[0041] Once the shuttling processes are complete, measurement operations may be performed in order to assess the likelihood offault for each of the shuttled portions. If no or sufficiently low likelihood of fault is assessed for the first portion, this portion may be selected. Otherwise, a likelihood of fault may be determined for the third portion. If said likelihood is sufficiently low, the third portion may be selected. Otherwise, the second portion may be selected. Of course, in some examples, the likelihood of fault may be determined for all the shuttled portions (the first and third portions, in this example) before the selection step.

[0042] In some examples, this may be used to send multiple portions to the same destination via different routes. Alternatively, or in addition, multiple portions may be shuttled to multiple distinct destinations. Moreover, in some examples, multiple portions may be shuttled to the same destination via the same route.

[0043] The shuttling of qubits in a solid-state qubit processor may enable many qubit operations. For instance, it may be desirable to perform a gate operation on the shuttled qubits. According to a second aspect, there is provided a method of performing a gate operation in a solid-state qubit processor, the method comprising: providing a first logical qubit comprising a first qubit sequence and asecond logical qubit comprising a second qubit sequence; and shuttling the first and second qubit sequences through a gate region, such that, for each first qubit in the first sequence, said first qubit occupies the gate region at the same time as a respective second qubit in the second sequence; wherein: the gate region comprises at least one two-qubit gate, configured to perform a two-qubit gate operation on a qubit from each of the first and second qubit sequences; and during the step of shuttling the first and second qubit sequences, an interacting portion of each of the first and second qubit sequences occupies the gate region, and a remaining portion of each of the first and second qubit sequences is located outside of the gate region.

[0044] The provided first and second logical qubits each comprise a qubit sequence. The qubit sequence may comprise physical data qubits and / or physical monitor qubits. The discussion of logical qubits above in the first aspect should be understood as applying equally to the logical qubits in the second aspect.

[0045] In order to enable the interaction of the first and second logical qubits, the first and second qubit sequences are shuttled through a gate region. The gate region comprises at least one two-qubit gate (that is, a device configured to perform a two-qubit gate operation on two qubits).

[0046] A first interacting portion of the first qubit sequence and a second interacting portion of the second qubit sequence are located inside the gate region, with a first remaining portion of the first qubit sequence and a second remaining portion of the second qubit sequence outside of the gate region. In such examples, not all of the qubits of the first and second sequences are located in the gate region contemporaneously. In these examples, the gating is not performed on the whole of the logical qubit at the same time. This may be advantageous if the qubit sequences comprise many qubits, as the size of the gate region is not required to be the same size as the qubit sequence.

[0047] As the qubit sequences are shuttled through the gate region, they are arranged such that each first qubit in the first qubit sequence has a corresponding second qubit in the second qubit sequence. In some examples, there may be the samenumber of qubits in the first and second qubit sequences. In such examples, there may be a correspondence such that the Nth qubit of the first qubit sequence corresponds to the Nth qubit of the second qubit sequence, and the two-qubit gate operation may be performed on the corresponding pairs of qubits from each of the two sequences.

[0048] Optionally, the method may further comprise performing a stabilization operation on at least a portion ofthe first or second qubit sequence, the portion being outside of the gate region. This may allow for large qubit sequences, as the integrity of the qubit sequence may be maintained by the application of stabilization operations on the portion outside of the gate region. In some examples, stabilization operations are applied separately to the “pre-operation” portion of each qubit sequence, that is, the portion of the qubit sequence outside the gate region which is yet to pass through the gate region, and the “post-operation” portion of each qubit sequence, that is, the portion of the qubit sequence outside of the gate region which has passed through the gate region.

[0049] BRIEF DESCRIPTION OF DRAWINGS

[0050] Example methods are described herein with reference to the accompanying figures, in which:

[0051] Figure 1 depicts a schematic of physical qubit arrangements;

[0052] Figures 2a, 2b and 2c depict schematics of a shuttling process;

[0053] Figure 3 depicts a schematic of a shuttling process;

[0054] Figure 4 depicts a schematic of an example qubit processor;

[0055] Figure 5a and 5b depict schematics of example qubit processors;

[0056] Figure 6 depicts a schematic of physical qubit arrangements;

[0057] Figure 7 depicts a schematic of an example shuttling process in accordance with the present invention;

[0058] Figure 8 depicts a schematic of an example process in accordance with the present invention;

[0059] Figure 9 depicts a schematic of an example process in accordance with the present invention;Figure 10 depicts a schematic of an example process in accordance with the present invention;

[0060] Figure 11 depicts a schematic of an example process in accordance with the present invention;

[0061] Figure 12a and 12b depict a schematic of an example process in accordance with the present invention; and

[0062] Figure 13 depicts a schematic of an example process in accordance with the present invention.

[0063] DETAILED DESCRIPTION

[0064] In Figure 1, there is depicted a 1-by-N (“1xN”) array 100 of qubit locations 101. Two such 1xN arrays 100 are combined to form a 2-by-N (“2xN”) array 102. These first two arrays, the 1xN array 100 and the 2xN array 102, comprise solely qubit locations 101, where monitor qubits or data qubits may be located. In some examples, such as in the modified 2xN array 104, some or all of the qubit locations are replaced with either empty space ( / .e. there is not a qubit location present in some region of the array) or with a measuring device 106.

[0065] In this example, comprising a semiconducting qubit processor, each qubit location 101 may correspond to, for example, a single silicon quantum dot 108. This quantum dot may host a qubit 110, i.e. a qubit may be located in the qubit location, or it may be empty. Alternatively, in some examples, each qubit location may comprise a plurality of quantum dots 112, which may host a plurality of qubits.

[0066] A qubit located at a qubit location 101 may be the spin of an electron 110, or the spin of a hole (the quasiparticle which occurs when an electron is missing from an otherwise fully occupied set of states), or the spin state of a small group of electrons 112 and / or holes. An example of such a group is two electrons 112, where the qubit is stored in the so-called singlet / triplet mode. In this example, the “data state 0” is the singlet state

[0067]

[0068] >> <> ) / Sqrt(2) and the “data state 1” is the To triplet state

[0069]

[0070] >> <> ) / Sqrt(2). This two-electron example of a qubit may be advantageous as such states may be more robust against certain forms of noise(such as unwanted magnetic field variation) when compared to single-electron qubits.

[0071] The particular choice of realisation for the qubits need not be specified for the remainder of the figures, where qubit locations 101 should be understood as having the same meaning as in Figure 1.

[0072] In Figure 2a, a shuttling process 200 is depicted on a 1xN array. Before the shuttling process, the array 202 has qubit locations 101 , some of which host qubits 201. After the shuttling process, the same array 204 is depicted below, showing the movement of qubits 201 into different qubit locations 101. In some examples, this is accomplished by adjusting the shape of the confining electrical fields which hold the electrons in place. These fields may be generated by conducting electrodes in an adjacent layer of the device (not shown).

[0073] In Figure 2b, a different example shuttling process 210 is depicted on a 2xN array. In this example, the shuttling occurs in only one of the 1xN subarrays of the 2xN array, in this example being the upper subarray (though, in other examples, the lower subarray may be shuttled). Before the shuttling process, the array 212 comprises qubit locations 101, some of which host qubits 201. After the shuttling process, the same array 214 is depicted below, showing the movement of qubits 201 into different qubit locations 101.

[0074] In Figure 2c, a different example shuttling process 220 is depicted on a 2xN array 222, 224. In this example, the shuttling occurs in both of the 1xN subarrays of the 2xN array 222, 224. Before the shuttling process, the 2xN array 222 comprises qubit locations 101, some of which host qubits 201. After the shuttling process, the same array 224 is depicted below, showing the movement of qubits into different qubit locations 101. In this example, both 1xN subarrays of the 2xN array are shuttled in the same direction, that is, the qubits located in both arrays move in the same direction. In other examples, the qubits may be shuttled in different directions.When shuttling logical qubits in architectures such as those shown in Figure 2, in the naive manner shown in Figure 2, there is a considerable risk that correlated errors will occur. A correlated error occurring on the physical qubits can cause logical level errors, e.g. given a logical qubit in the surface code embodied in the typical way as a square grid of physical qubits, a logical error can be induced when errors afflict the majority of physical qubits in a given row or column.

[0075] Such errors may occur, for example, if a static charge defect in the semiconductor material is adjacent to the shuttling path and interacts with all data qubits as they are shuttled past. In a naive implementation of shuttling in a 1xN or 2xN array, or in a more complex latticework architecture, such events would be likely to prevent successful fault tolerant operation. Risk levels at least as low as 10'6, and preferably lower than 10'12, are required in order to perform the most important and valuable quantum algorithms, which is infeasible with naive shuttling algorithms.

[0076] In Figure 3, an example latticework architecture 300 is shown, comprising 2xN and 1xN lattice strips joined at junctions. Shuttling is possible at the junctions, so that physical qubits, such as the qubits 110, 201 shown in the previous figures, can move from one lattice strip to another. A first sequence of data qubits 303, a second series of data qubits 302, and a third series of data qubits 304 are shown hosted on the lattice strips in qubit locations 101. Measurement devices 406b and ancilla qubits 406a are shown periodically along the strips. In some examples, the placement of the measurement devices and ancilla qubits may be periodic, aperiodic, regular, irregular, of any amount or frequency.

[0077] To the right, the same latticework architecture 310 is shown after a shuttling operation, with all three qubit sequences 302, 303, 304 shuttling through the structure. The first 303 and second 302 qubit sequences have now entered the central 2xN region 312, with corresponding qubits from each sequence aligned in the central region 312, while the third qubit sequence 304 is exiting that region. For example, a first qubit 314 of the first qubit sequence 303 corresponds to a second qubit 316 of the second qubit sequence 302. In this way, as will be seen later, if the central region 312 corresponded to a gate region, logical qubits formedby the first and second qubit sequences 303, 302 are configured for the application of a gate operation as per an aspect of the present invention.

[0078] Figure 4 shows a different example of a section of a latticework architecture where 2-by-N and 1-by-N lattice strips, comprising qubit locations 101, are joined at junctions in order to produce an extended latticework. As above, shuttling is possible at the junctions, so that physical qubits, such as the qubits 110, 201 shown in the previous figures, can move from one lattice strip to another. Ancillary devices 406 are spaced periodically along the lattice strips, comprising measurement devices 406b and ancilla qubits 406a. The latticework comprises interaction regions 410, where individual 1xN lattice strips (arrays of qubit locations) are bought close together and run parallel, creating portions of the latticework which comprise 2xN arrays. Gate operations, such as two-qubit gate operations, such as the method of the present invention, may be carried out in such a region.

[0079] Figure 5a depicts a large-scale schematic view 500 of a section of a latticework architecture. For clarity, due to the scale, the individual qubit locations 101, etc, are omitted, which follow along the boundaries 502 as in Figure 4. Ancillary devices 506, corresponding to the ancillary devices of Figure 4, are shown in a periodic arrangement. The same is true of Figure 5b, which depicts large-scale schematic view 510 of a section of a second latticework architecture. These examples are not exhaustive and are intended to show a variety of envisaged configurations.

[0080] In one well-studied example, the so-called “surface code”, logical qubits correspond to two-dimensional arrays of qubits and stabiliser measurements apply to local groups of four qubits throughout this grid. In order to embody the surface code, it may be desirable that the layout or arrangement of the physical qubits is compatible with the code. A grid-like layout may be appropriate for the surface code. However, in Figure 6, a configuration in which a logical qubit of the surface code can be realised in the latticework architecture is depicted. Each row of the canonical representation 600 of the logical qubit becomes a section of a one-dimensional line or ‘train’ of data qubits 610. Of course, the 2D grid-like layoutmay be mapped onto a 1 D sequential layout in any way, for example, in a columnmajor order, instead of the row-major order of Figure 6. Alternatively, any order may be used to reshape the grid arrangement into a sequential arrangement.

[0081] A latticework structure 700 is generally depicted in Figure 7. A logical qubit 701 , comprising data qubits occupying qubit locations (not shown) on a portion of the latticework, is able to be shuttled to a final position 702 around inoperable regions 704 of the device. Of course, the logical qubit may also comprise monitor qubits, as above. The inoperable regions may be present due to manufacture defects in the device, or defects formed during operation, or may be inoperable regions by virtue of hosting a different logical qubit or being otherwise used for a separate function. The inoperable regions 704 result in the presence of unusable routes 706, which cannot be used to shuttle the logical qubit 701 to its destination 702.

[0082] However, the logical qubit 701 may be shuttled through the latticework structure 700 in despite of these imperfections, because it can be routed around the defects 704 by following the accessible route 708, thereby exploiting the 2D nature of the latticework. Such a routing may not be possible in a 1D device, as an inoperable region may prevent all connection between portions of said device, or in a less connected 2D device.

[0083] In Figure 8, there is depicted a logical qubit 800 comprising data qubits 801 and monitor qubits 802, wherein the monitor qubits are interlaced with the data qubits. In this example, the monitor qubits alternate with the data qubits in a one-to-one manner, though, in other examples, the monitor qubits may alternate with the data qubits in a different pattern, or may be arranged in any other regular or irregular way. For example, in some examples, the monitor qubits are arranged at the beginning and / or end of the logical qubit. In other examples, the monitor qubits are positioned between pairs of data qubits in a two-to-one, three-to-one, or N-to-one alternating manner. The monitor qubits are arranged such that they are shuttled with the data qubits.

[0084] The monitor qubits 802 are initialised in a known state prior to the shuttling process. When the logical qubit 800 is shuttled, the state 804 of the monitor qubitsmay be affected by the environment, e.g. by noise sources and / or by the shuttling process itself. The state of the monitor qubits can be measured 806 after the shuttling process, which may provide an estimate of the effect of the environment and / or the shuttling process on the monitor qubits.

[0085] For example, the monitor qubits may each be prepared in the state |+> = (|T> + |> » / Sqrt(2) prior to a shuttling process, where |T> represents a spin-up state and |sk) represents a spin-down state. In other examples, the monitor qubits may be prepared in a different state, for instance, in the state |-> = (|T> -

[0086]

[0087] <> ) / Sqrt(2), or in a more complex state, or in a state defined in a different basis. At a later time, for example once the shuttling process is complete, these qubits can be measured in the X-basis, such that the measurement outcomes are |+> and |-> where |-> = (|T>

[0088]

[0089] Of course, in other examples, the measurement operation may be performed in another appropriate basis.

[0090] If no phase error has occurred during shuttling, then all these measurements may be found to be |+>. In some examples, if there are imperfections in the measurement process, and / or some random phase noise events from the shuttling process, then some small and random portion of the shuttling qubits will be found to be in state |->. In some examples, if there has been a significant correlated phase error event during shuttling then a larger portion of the monitor qubits (or a portion that are not randomly distributed) will be found to be in state |->•

[0091] Figure 9 depicts a schematic of an example process according to an aspect of the present invention.

[0092] In step S100, a logical qubit is provided, comprising a plurality of data qubits. In this example, the logical qubit comprises a plurality of data qubits and a plurality of monitor qubits, as discussed above. In this example, the monitor qubits are interlaced with or interspersed with the data qubits as in Figure 8, though, as discussed above, in other examples, they may be in any other arrangement, for instance, interlaced with in a periodic or aperiodic manner.In this example, the logical qubit is represented in the + / - basis, that is, the logical qubit can be expressed as |Q> = a |+>L+ b |->L. This choice of basis provides protection against phase noise. However, in other examples, the logical qubit may be in a different basis, for instance, the logical qubit may be expressed as |Q>L= a |0>L+ b |1> L.

[0093] In step S102, the logical qubit is extended by generating one or more extensions to the plurality of data qubits, wherein each extension comprises data qubits that correspond to, and are entangled with, the original plurality of data qubits. As discussed above, in this example, each extension may comprise the same number of physical qubits as the logical qubit, though in some examples the number of physical qubits in the extension and the original logical qubit may differ.

[0094] In this example, the logical qubit is extended once, i.e. one extension is generated. The extended logical qubit may thus be represented in the basis |Q-ex>L= a |+>L|+> L + b |-> L |-> L, with reference to the + and - states of the original logical qubit and the extension.

[0095] In this example, the step S102 of extending the logical qubit comprises running stabilization operations on the extended logical qubit, i.e. the original logical qubit and the one or more extensions, wherein the stabilization operations are performed as if the original qubit and the one or more extensions are one single logical qubit. Performing the stabilization operation in this way may transfer the logical information contained within the state of the original physical qubits of the logical qubit to all the physical qubits of the logical qubit and the extensions. In other examples, this stabilization operation may not be performed, i.e. the performing of the stabilization routine on the extended logical qubit to transfer the logical information is optional. In other examples, the qubit may be extended using a different routine, for instance, by applying a series of gate operations. One known example that involves stabilisers can be found in “Surface code quantum computing by lattice surgery” by Horsman, Fowler, Devitt and van Meter in New J. Phys. 14 123011 (2012).In this example, monitor qubits are initialized in the extended logical qubit. The monitor qubits are located in the extension, though, alternatively or in addition, the monitor qubits may be located in the original logical qubit. In this example, the monitor qubits are interlaced with or interspersed with the data qubits, as shown in Figure 8, though, as above, may be combined with the data qubits in any arbitrary manner.

[0096] In step S104, the extended logical qubit is split into two or more portions, each portion corresponding to one of the one or more extensions. In this example, the extended logical qubit is split into two portions, the first portion corresponding to the physical qubits of the original logical qubit, and the second portion corresponding to the physical qubits of the first and only extension. In other examples, there may be more than one extension, and / or more than two portions of the extended logical qubit. In some examples, there is a one-to-one correspondence between the portions and either an extension or the original logical qubit — for instance, if two extensions are generated, the extended logical qubit is split into three portions, one for the original logical qubit, and one for each extension. In other examples, the extensions and portions do not correspond one-to-one — for instance, there may be a single extension which is split into two portions, yielding three total portions for the extended logical qubit.

[0097] In step S106, a first portion of the one or more portions is shuttled so that the first portion and a second portion of the one or more portions are separated from one another. In this example, the first portion which is shuttled is the portion comprising the physical qubits of the extension. However, in other examples, the portion comprising the physical qubits of the original logical qubit is shuttled.

[0098] In step S108, a measurement operation is performed in order to determine a likelihood that faults have occurred during the shuttling step. In this example, the monitor qubits of the shuttled portion, i.e. the first portion, comprising the physical qubits of the extension, are measured. If a statistical threshold of these monitor qubits are no longer in the known initial state, faults can be deemed to have occurred during the shuttling process. Additionally, stabilization operations are performed on the data qubits of the shuttled portion. If a statistical threshold ofsyndrome events are reported during the stabilization operations, faults can be deemed to have occurred during the shuttling process. Of course, in some examples, only one of the stabilization operations or the measurements of the monitor qubits may be performed. For instance, a likelihood of faults may be determined from the measurement of the monitor qubits alone, which may make the stabilization operation redundant as the fault is already known. The use of stabilizer operations as estimators of the likelihood of errors is well explored and discussed recently in, for example, in “Yoked Surface Codes” by Gidney, Newman, Brooks and Jones (https: / / arxiv.org / abs / 2312.04522).

[0099] In step S110, one of the first portion or the second portion of the logical qubit are selected based on the determined likelihood. In this example, either the shuttled portion or the non-shuttled portion is selected based on the determined likelihood. The non-shuttled portion may be selected if the likelihood of a fault in the shuttled portion is above a certain threshold; for example, if the process is deemed to be in the worst 10% of all shuttling events. It is possible in this method to subsequently re-attempt the shuttle. Therefore, the threshold can be set relatively high such as 10% without significantly affecting the efficiency of the overall quantum computation.. Of course, the statistical threshold may be chosen as any value.

[0100] In this example, when the likelihood of fault is above a statistical threshold, the non-shuttled portion is selected by measuring the shuttled portion. Measuring the data qubits of the shuttled portion in the Z basis reverses the extending and shuttling process by projecting or collapsing the information contained in the shuttled portion back to the non-shuttled portion. The state of the non-shuttled portion is therefore the same state as the original logical qubit up to a phase factor, which, as it has been measured from the shuttled portion, may be corrected for via the application of a phase gate operation to the non-shuttled portion. Of course, in other examples, this phase gate operation may not be performed, for instance, when the phase is not relevant or is otherwise compensated for.

[0101] Alternatively, when the likelihood of fault is below the statistical threshold, the shuttled portion is selected by measuring the non-shuttled portion. Measuring thedata qubits of the non-shuttled portion in the Z basis completes the extending and shuttling process by teleporting the information contained in the non-shuttled portion to the shuttled portion. The state of the shuttled portion is therefore the same state as the original logical qubit up to a phase factor, which, as it has been measured from the non-shuttled portion, may be corrected for via the application of a phase gate operation to the shuttled portion. Of course, in other examples, this phase gate operation may not be performed, for instance, when the phase is not relevant or is otherwise compensated for.

[0102] An aspect of the present invention may be further understood with reference to Figure 10, which describes a second shuttling operation in accordance with a method of the present invention. Initially, a provided logical qubit is extended to occupy a larger region in its starting zone 1002.

[0103] The state of the logical qubit |Q>L= a |+>L + P |-> L becomes |Q-ex> = a |+> L |+> L + |-> L |-> L , where |+>Land |->Lrepresent logical states. The portion of the extended logical qubit which is going to be shuttled, referred to here as the “head”, will typically have monitor qubits interlaced with the data qubits, as illustrated in Figure 8. The monitor qubits are prepared in a reference state. Following these steps, the head of the logical qubit is shuttled to the remote location 1004.

[0104] Depending on the nature of the physical device, e.g. the rate of shuttling versus the rate at which errors occur, it may be necessary to perform stabiliser operations on both the tail part and the head part of |Q-ex>Lduring the long-range shuttling process. On arrival at the desired location, the head part of |Q-ex> is investigated 1006: its monitor qubits are measured, and stabiliser cycle(s) are performed on its data qubits. If more than a certain defined portion of the monitor qubits show the unexpected outcome (such as |-», or if the stabiliser cycle performed on the data qubits has an unusually large number of new syndrome events, then the overall shuttling process may be deemed a failure. Otherwise, it is deemed a success.

[0105] On success 1008, the tail part of |Q-ex> (which remained at the original location) is removed by measuring it in the logical Z-basis. The outcome of this measurement should be noted as it implies potential phase gate on the remaininghead part, which is not harmful but should be known. Thus the logical qubit is again represented only in one location, and |Q>Lhas been shuttled.

[0106] On failure 1010, the head part of |Q-ex>Lis measured in the logical Z-basis, and the outcome used to update the tail part. Now |Q>Lexists only at the initial location, and remarkably any phase error that may have occurred to the travelling part has been eliminated (it maps to only a global phase of the entire quantum computer state and may therefore be considered meaningless).

[0107] Figure 11 depicts a schematic of an example process according to an aspect of the present invention.

[0108] Step S200 comprises providing a first logical qubit comprising a first qubit sequence and a second logical qubit comprising a second qubit sequence. The above discussion and examples of logical qubits and devices and / or structures which can host or contain them should be understood as applying equally to the logical qubits of this method. In this example, the logical qubits each comprise a plurality of physical qubits, arranged in a qubit sequence, located in a semiconducting qubit processor, each physical qubit corresponding to a single electron hosted in a silicon quantum dot. Of course, the following discussion applies equally to other types of physical qubit as discussed above. In this example, the first qubit sequence is located on a first 1xN array, and the second qubit sequence is located on a second 1xN array. These arrays are connected at an interface region as shown in Figure 4, wherein the interface region comprises a gate region.

[0109] Step S202 comprises shuttling the first and second qubit sequences through the gate region, such that, for each first qubit in the first sequence, said first qubit occupies the gate region at the same time as a respective second qubit in the second sequence, wherein the gate region comprises at least one two-qubit gate, configured to perform a two-qubit gate operation on a qubit from each of the first and second qubit sequences, and during the step of shuttling the first and second qubit sequences, an interacting portion of each of the first and second qubitsequences occupies the gate region, and a remaining portion of each of the first and second qubit sequences is located outside of the gate region.

[0110] In this example, during the step of shuttling the first and second qubit sequences, an interacting portion of each of the first and second qubit sequences occupies the gate region, and a remaining portion of each of the first and second qubit sequences is located outside of the gate region.

[0111] In this example, the two-qubit gate operation comprises a CNOT, or “controlled-not”, or “Feynman” gate operation. In other examples, the two-qubit gate operation may comprise any two-qubit gate operation, for example, any controlled gate operation, and / or a swap gate, or may be formed of a combination of two-qubit gate operations, such as a plurality of CNOT gates.

[0112] A gate operation in accordance with the above method may be called a “semitransversal logical gate”, in that interacting portions of the two qubit sequences are brought proximal to each-other for gating, while remaining portions are not, hence “semi-transversal”. In this example, the remaining portion comprises a preoperation portion and a post-operation portion. The pre-operation portion comprises qubits which have not get been shuttled through the gate region and been acted on by the two-qubit gate, and the post-operation portion comprises qubits which have been shuttled through the gate region and have been acted on by the two-qubit gate.

[0113] Figures 12a and 12b depict a schematic of an example method in accordance with the present invention. In Figure 12a, a canonical layout 1200 for a surface code logical qubit is depicted, as in Figure 6. The solid lines indicate groups of data qubits subject to stabiliser measurements. In Figure 12b, there is depicted an example implementation of this layout 1202 on two 1xN arrays, meeting at an intermediate region, forming a portion of a latticework architecture.

[0114] Two logical qubits A and B are depicted in the latticework architecture. Logical qubit A is shown on the left, and B is shown on the right. The logical qubits are laid out as one-dimensional sequences of data qubits, in the manner introducedin Figure 6. In the instant shown in the figure, the data qubits A11 to A15 are present in a central 2-by-N array region, and the corresponding data qubits B11 to B15 are present in that region. Moreover each data qubit is adjacent to its “opposite number”, i.e. corresponding qubit in the other logical qubit: A11 is adjacent to B11 and so on. Of course, in other examples, other mappings between the two logical qubits may be used, which need not be the same length.

[0115] In this example, a two-qubit gate, such as a control-not (CNOT) gate operation is performed. For example, the CNOT gate operation may comprise all the A-series data qubits as the control, with the corresponding B-series qubits targeted. Optionally, the data qubits outside of this region can be subjected to standard stabiliser measurements, as discussed above.

[0116] Figure 13 depicts a schematic of an example method in accordance with the present invention.

[0117] Step S300 comprises providing two logical qubits, each comprising a plurality of data qubits. This step is analogous to step S100, and the above discussion of step S100 should be understood to apply equally in this case.

[0118] Step S302 comprises extending each of the logical qubits by generating a first extension to the plurality of data qubits, wherein the first extension comprises data qubits that correspond to, and are entangled with, the original plurality of data qubits. This step is analogous to step S102, and the above discussion of step S102 should be understood to apply equally in this case.

[0119] Step S304 comprises splitting each of the extended logical qubits into two portions. This step is analogous to step S104, and the above discussion of step S104 should be understood to apply equally in this case.

[0120] Step S306 comprises shuttling a first portion of each of the extended logical qubits through a gate region, such that, for each first qubit in the first portion of the first logical qubit, said first qubit occupies the gate region at the same time as a respective second qubit in the first portion of the second logical qubit, wherein the gate region comprises at least one two-qubit gate, configured to perform a two-qubit gate operation on a qubit from each of the first and second qubit sequences. This step is analogous to step S202, and the above discussion of step S202 should be understood to apply equally in this case.

[0121] Step S308 comprises performing a measurement operation to determine a likelihood that faults have occurred during the shuttling step. This step is analogous to step S108, and the above discussion of step S108 should be understood to apply equally in this case.

[0122] Step S310 comprises selecting one of the one or more portions of each of the logical qubits based on the determined likelihood. This step is analogous to step S110, and the above discussion of step S110 should be understood to apply equally in this case.

[0123] The method shown in Figure 13 enables the ability to perform shuttling that is robust to errors, in some examples, “repeat-until-success” shuttling, and permits recovery from a fault, which is combined with the semi-transversal gate to provide a reversable gate operation.

Claims

CLAIMS1. A method for performing operations in a solid-state qubit processor, comprising the steps of:providing a logical qubit comprising a plurality of data qubits; extending the logical qubit by generating one or more extensions to the plurality of data qubits, wherein each extension comprises data qubits that correspond to, and are entangled with, the original plurality of data qubits;splitting the extended logical qubit into two or more portions; shuttling a first portion of the one or more portions so that the first portion and a second portion of the one or more portions are separated from one another;performing a first measurement operation to determine a likelihood that faults have occurred during the shuttling step; andselecting one of the first portion or the second portion of the logical qubit based on the determined likelihood, wherein said selecting comprises performing a second measurement operation on one or more non-selected portions of the logical qubit.

2. The method of claim 1, further comprising the step of providing and initialising a plurality of monitor qubits in the first portion, wherein the first measurement operation involves measuring at least a subset of the plurality of monitor qubits in the first portion of the logical qubit.

3. The method of claim 2, wherein the first measurement operation involves determining whether a statistical threshold of monitor qubits are in a particular state.

4. The method of claim 2 or claim 3, wherein the plurality of monitor qubits are interlaced with the data qubits in the first portion of the logical qubit.

5. The method of any of the preceding claims, wherein the first measurement operation comprises a stabiliser operation on the data qubits and determinising a likelihood that faults have occurred based on a number of syndrome events that are determined by the stabiliser operation.

6. The method of any of the preceding claims, wherein, when the first measurement operation indicates a likelihood of faults that is below a threshold, the first portion of the logical qubit is selected and the method involves measuring the plurality of data qubits in the second portion of the logical qubit to determine a phase.

7. The method of claim 6, further comprising the step of applying a gate operation to the first portion of the logical qubit based on the determined phase.

8. The method of any of claims 1 to 5, wherein, when the first measurement operation indicates a likelihood of faults that is above a threshold, the second portion of the logical qubit is selected and the method involves measuring the plurality of data qubits in the first portion of the logical qubit to determine a phase.

9. The method of claim 8, further comprising the step of applying a gate operation to the second portion of the logical qubit based on the determined phase.

10. The method of any of the preceding claims, wherein the logical qubit can be expressed as |Q>L= a |+>L+ b |->Land the step of extending the logical qubit involves generating the extension, |Q-ex> = a |+>L|+> L + b |->L|-> L, wherein the first measurement operation is performed in the Z basis.

11. The method of any of claims 1 to 9, wherein the logical qubit can be expressed as |Q>L= a |0>L+ b |1>Land the step of extending the logical qubit involves generating the extension, |Q-ex>L= a |0>L|0>L+ b |1>L|1 > L, wherein the first measurement operation is performed in the X basis.

12. The method of any of the preceding claims, wherein the step of extending the logical qubit comprises performing a stabiliser sequence on the extended logical qubit.

13. The method according to any of the preceding claims, further comprising:shuttling a third portion of the one or more portions, such that the first portion, second portion and third portion are separated from one another;wherein the step of performing a first measurement operation comprises: measuring the first portion to determine a corresponding likelihood that faults have occurred when shuttling the first portion; and when said likelihood is above a first threshold, measuring the third portion to determine a corresponding likelihood that faults have occurred when shuttling the third portion;wherein the step of selecting comprises selecting one of the first portion, second portion or third portion of the logical qubit based on the determined likelihoods.

14. A method of performing a gate operation in a solid-state qubit processor, the method comprising:providing a first logical qubit comprising a first qubit sequence and a second logical qubit comprising a second qubit sequence; andshuttling the first and second qubit sequences through a gate region, such that, for each first qubit in the first sequence, said first qubit occupies the gate region at the same time as a respective second qubit in the second sequence; wherein:the gate region comprises at least one two-qubit gate, configured to perform a two-qubit gate operation on a qubit from each of the first and second qubit sequences; andduring the step of shuttling the first and second qubit sequences, an interacting portion of each of the first and second qubit sequences occupies the gate region, and a remaining portion of each of the first and second qubit sequences is located outside of the gate region.

15. The method according to claim 14, further comprising performing a stabilization operation on the remaining portion of the first or second qubit sequence, while the interacting portion of each of the first and second qubit sequences occupies the gate region.

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