Physical Realisation TRIZ Cases
- J-Scheme Broadcast Network-on-Chip for Stall-Free Weight Delivery
The J-scheme routes neural-network weights across computation cores without NoC conflicts, empty slots, or pipeline stalls.
- SRAM-Based CMOS Ising Circuitry for Combinatorial Optimization
An SRAM array stores coupling-matrix values in a CMOS Ising feedback loop with noise and nonlinear processing for scalable optimization.
- Asymmetric Convolution-Attention Neural Networks for Faster Inference
Asymmetric block placement improves neural network throughput without sacrificing accuracy.
- Sparse Accelerator With Internal Sparsity Masks for Non-2-D Convolutions
Internal sparsity masks help accelerators run non-2-D convolutions with less data retrieval.
- Information-Bottleneck Neural Network Updates Against Catastrophic Forgetting
Active and inactive neurons limit representation drift while adapting neural networks to new tasks with less storage.
- Artificial Sensory Nervous Circuit with Memristor-Based Habituation
This case uses a sensor, unidirectional memristor, and charging neuron circuit to produce pulses with sensitivity and habituation.
- Computational Storage Drives With ML Coprocessors for Local Processing
Local CSD coprocessors process raw stored data in parallel, reducing bandwidth demands and dependence on high-end servers.
- Layer-Wise Neural Network Quantization for Faster Processing
Weight-difference statistics identify sensitive layers, enabling lower-bit quantization with fewer operations and controlled accuracy loss.
- Vertical Federated Learning Encoder Customization for Faster Convergence
This VFL case uses encoder selection, neuron muting, and routed gradients to reduce redundant computation and improve convergence.
- Extended LSTM Matrix Memory for Linear Long-Sequence Processing
This case addresses quadratic memory demands in long-sequence models with matrix-memory LSTM variants and linear recurrent updates.
- Dense-Connection Knowledge Distillation for Lower-Cost DNN Training
A merged teacher-student network uses dense internal and cross-network connections to reduce training stages and preserve accuracy.
- Heterogeneous 3D Optical Neural Network Accelerators for Memory Bottlenecks
This case uses VCSEL, photodetector, memory, and CMOS layers with TSVs to improve data movement and optical computing throughput.
- Neural Network Training on Low-Power Controllers Using Genetic Search
This case combines genetic search with selective backpropagation to limit training time, memory use, and power on low-power controllers.
- Programmable Lookup Tables for Adaptive DNN Activation Functions
Dynamic lookup tables adapt DNN activation functions while limiting hardware area.
- Photon AI Chip Digital Pulse-Width Modulation Without DACs
Fixed-period digital timing signals replace analog modulation, reducing quantization error and power use in photon AI chips.
- Neural Network Loss Function Balancing Incorrect Category Probabilities
This case adds differentiable terms for incorrect-category probabilities, reducing sensitivity to minor perturbations during classification.
- Adaptive Floating-Point Containers for Memory-Efficient ML Training
Dynamic mantissa and exponent sizing cuts memory footprint up to 92% while preserving training accuracy during model training.
- Multi-Dimensional Tensor Mapping Circuit for CPU Load Reduction
A tensor access circuit maps source ranks for neural engines, reducing CPU intervention and bandwidth use during convolution.
- BiMEVOX Electrolyte Transistors for Room-Temperature CMOS Integration
This case addresses humidity and CMOS integration limits using oxygen-ion-conducting BiMEVOX electrolytes for stable, low-voltage switching.
- Extended LSTM Networks with Phonological-Semantic Memory
This neural architecture combines input and semantic memory to capture complex relationships while reducing computation and energy use.