Vertical FET Design for High Voltage and Reliability
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Summary
Problems
Traditional high voltage field effect transistors (FETs) face limitations due to lattice mismatch defects in semiconductor materials, restricting their quality, reliability, and voltage capability, particularly in horizontal device approaches which are typically limited to 600 to 900 Volts.
Innovation solutions
A vertical FET device is fabricated using a gallium and nitrogen containing material like GaN or AlGaN, with a GaN substrate, n-type epitaxial layers, recessed regions, and selective area implantation with beryllium or other activated impurities to achieve low resistivity and high gate-drain breakdown voltage, along with a p-type gate region and extended drain configuration to minimize reverse leakage.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If traditional horizontal high voltage device approaches are used, then manufacturing simplicity is maintained, but voltage capability is limited to 600 to 900 Volts due to lattice mismatch defects
Why choose this principle:
The patent transitions from traditional horizontal FET architecture to a vertical FET architecture, changing the spatial dimension of current flow and electric field distribution. This dimensional change allows the device to achieve higher voltage capability (100V to 20kV range) by utilizing the vertical growth direction of GaN layers, where lattice mismatch defects are minimized, thereby resolving the voltage capability limitation while maintaining manufacturing feasibility through epitaxial growth processes
Principle concept:
If selective area implantation with beryllium is performed, then resistivity is reduced and electrical characteristics are improved, but ion implant damage is introduced
Why choose this principle:
The patent employs selective area implantation with beryllium or other activated impurities to intentionally introduce controlled ion implantation damage, which is then converted into a benefit through subsequent annealing processes. The implantation creates localized doping regions that reduce resistivity and improve electrical characteristics in specific areas (such as source and drain regions), while the damage is healed and the doping is activated through thermal annealing, thereby transforming the harmful ion implantation effect into a useful doping mechanism
Application Domain
Data Source
AI summary:
A vertical FET device is fabricated using a gallium and nitrogen containing material like GaN or AlGaN, with a GaN substrate, n-type epitaxial layers, recessed regions, and selective area implantation with beryllium or other activated impurities to achieve low resistivity and high gate-drain breakdown voltage, along with a p-type gate region and extended drain configuration to minimize reverse leakage.
Abstract
A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n− type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.