One-Time Programmable Bit Cells (OTP) and Methods for Manufacturing a One-Time Programmable Bit Cell (OTP)

Abstract

Disclosed are secure anti-fuse one-time programmable (OTP) bit cells. In an aspect, an OTP bit cell includes a P- well comprising an N+ region and a P+ region, a first contact electrically coupled to the N+ region of the P- well, a second contact electrically coupled to the P+ region of the P- well, an insulating layer disposed over a portion of the N+ region, a portion of the P- well, and a portion of the P+ region, a gate structure disposed over the insulating layer, and a third contact electrically coupled to the gate structure. In an unprogrammed mode, the insulating layer creates a high resistance between the third contact and the second contact, and in a programmed mode, a rupture in the insulating layer creates a low resistance between the third contact and the second contact.

Description

1 / 27 “ONE-TIME PROGRAMMABLE (OTP) BIT CELLS, AND METHODS OF MANUFACTURING A ONE-TIME PROGRAMMABLE (OTP) BIT CELL” BACKGROUND OF THE DISCLOSURE 1. Dissemination Field

[0001] Aspects of the disclosure generally refer to one-time programmable (OTP) memory cells. 2. Description of the Related Technique

[0002] One-time programmable (OTP) memory cells have multiple applications in the integrated circuit (IC) industry, where they are used as programmable read-only memories (ROMs) to store program or device settings in a secure manner so that the settings cannot be tampered with, storing tuning parameters for phase-locked loops and the like. Existing OTP designs that use a polysilicon (poly) electrical fuse have relatively low density and can be reprogrammed (or corrupted), causing some of their layers to reflow, reducing the security of conventional OTP designs. SUMMARY

[0003] A simplified summary relating to one or more aspects disclosed in the present invention is presented below. Thus, the following summary should not be considered an extensive overview relating to all aspects contemplated, nor should the following summary be considered to identify key or critical elements relating to all aspects contemplated, or to delineate the scope associated with any particular aspect. Petition 870250081227, dated 10 / 09 / 2025, p. 7 / 79 2 / 27 Consequently, the following summary has the sole purpose of presenting certain concepts related to one or more aspects of the mechanisms disclosed in the present invention in a simplified form to precede the detailed description presented below.

[0004] In one aspect, a once-programmable bit cell (OTP) includes a P- well comprising an N+ region and a P+ region; a first contact electrically coupled to the N+ region of the P- well; a second contact electrically coupled to the P+ region of the P- well; an insulating layer disposed over a portion of the N+ region, a portion of the P- well and a portion of the P+ region; a gate structure disposed over the insulating layer; and a third contact electrically coupled to the gate structure.

[0005] In one aspect, an OTP bit cell includes a first substrate layer; an insulating layer disposed over the first substrate layer; a gate structure disposed over the insulating layer; a first contact electrically coupled to the gate structure; and a second contact coupled to the first substrate layer and in direct contact with the insulating layer.

[0006] In one aspect, a method of manufacturing an OTP bit cell includes providing a P- well comprising an N+ region and a P+ region; providing a first contact electrically coupled to the N+ region of the P- well; providing a second contact electrically coupled to the P+ region of the P- well; providing an insulating layer disposed over a portion of the N+ region, a portion of the P- well, and a portion of the P+ region; providing a gate structure disposed over the insulating layer; and providing a third contact electrically coupled to the N+ region of the P- well. Petition 870250081227, dated 10 / 09 / 2025, page 8 / 79 3 / 27 attached to the door frame.

[0007] In one aspect, a method of manufacturing an OTP bit cell includes providing a first substrate layer; providing an insulating layer disposed over the first substrate layer; providing a gate structure disposed over the insulating layer; providing a first contact electrically coupled to the gate structure; and providing a second contact coupled to the first substrate layer and in direct contact with the insulating layer.

[0008] Other objectives and advantages associated with the aspects disclosed in the present invention will become apparent to those skilled in the art based on the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The attached drawings are presented to assist in describing various aspects of the disclosure and are provided for illustrative purposes only, and not to limit them.

[0010] Figure 1A is a cross-section of a secure anti-fuse OTP bit cell in an unprogrammed state according to disclosure aspects.

[0011] Figure 1B is a cross-section of the secure anti-fuse OTP bit cell in a programmed state.

[0012] Figure 2 illustrates an example circuit for using and programming a safe anti-fuse OTP bit cell in accordance with disclosure aspects.

[0013] Figure 3 is a simplified plan view of a layout of a three-terminal secure anti-fuse OTP bit cell according to disclosure aspects.

[0014] Figure 4 is a simplified plan view. Petition 870250081227, dated 10 / 09 / 2025, page 9 / 79 4 / 27 of a layout of another three-terminal secure anti-fuse OTP bit cell according to disclosure aspects.

[0015] Figure 5 is a simplified plan view of a two-terminal secure anti-fuse OTP bit cell layout according to disclosure aspects.

[0016] Figure 6 illustrates cross-sections of a two-terminal, fuse-safe OTP bit cell according to disclosure aspects.

[0017] Figure 7 illustrates an exemplary mobile device according to one or more aspects of disclosure.

[0018] Figure 8 illustrates various mobile devices according to one or more aspects of disclosure.

[0019] Figure 9 is a flowchart of an example process associated with the manufacture of a safe anti-fuse OTP bit cell in accordance with disclosure aspects.

[0020] Figure 10 is a flowchart of an example process associated with the manufacture of a safe anti-fuse OTP bit cell in accordance with aspects of the disclosure.

[0021] According to common practice, the attributes depicted by the drawings may not be drawn to scale. Consequently, the dimensions of the depicted attributes may be arbitrarily expanded or reduced for clarity. According to common practice, some of the drawings are simplified for clarity. Thus, the drawings may not depict all the components of a particular apparatus or method. Additionally, similar reference numbers denote similar attributes throughout the descriptive report and figures. DETAILED DESCRIPTION Petition 870250081227, dated 10 / 09 / 2025, p. 10 / 79 5 / 27

[0022] Safe once-programmable (OTP) anti-fuse bit cells are disclosed. In one aspect, an OTP bit cell includes a P-well comprising an N+ region and a P- region, a first contact electrically coupled to the N+ region of the P-well, a second contact electrically coupled to the P- region of the P-well, an insulating layer disposed over a portion of the N+ region, a portion of the P-well and a portion of the P+ region, a gate structure disposed over the insulating layer and comprising P+ polysilicon, and a third contact electrically coupled to the gate structure. In an unprogrammed mode, the insulating layer creates a high resistance between the third contact and the second contact, and in a programmed mode, a break in the insulating layer creates a low resistance between the third contact and the second contact.

[0023] In the following description, aspects of the disclosure are provided, and related drawings are directed to various examples provided for illustrative purposes. Alternative aspects may be conceived without departing from the scope of the disclosure. Additionally, well-known elements of the disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of the disclosure.

[0024] The words exemplifying and / or exemplary are used in the present invention to mean serving as an example, instance, or illustration. Any aspect described in the present invention as exemplifying and / or exemplary should not necessarily be interpreted as preferential or advantageous in relation to other aspects. Similarly, the term aspects of the disclosure does not require that all aspects of the disclosure include the attribute, Petition 870250081227, dated 10 / 09 / 2025, p. 11 / 79 6 / 27 advantage or mode of operation discussed.

[0025] Those skilled in the art will recognize that the information and signals described below can be represented using any one of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the description below can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof, depending in part on the particular application, in part on the desired design, in part on the corresponding technology, etc.

[0026] Additionally, many aspects are described in terms of sequences of actions to be performed, for example, by elements of a computing device. It will be recognized that several actions described in the present invention can be performed by specific circuits (for example, by application-specific integrated circuits (ASICs)), by program instructions that are executed by one or more processors, or by a combination of both. Furthermore, the sequence(s) of actions described in the present invention can be considered as fully incorporated in any form of non-transient computer-readable storage medium that stores a corresponding set of computer instructions which, upon execution, would cause, or instruct, an associated processor of a device to perform the functionalities described in the present invention. Thus, the various aspects of the disclosure Petition 870250081227, dated 10 / 09 / 2025, page 12 / 79 7 / 27 can be incorporated in several different forms, all of which have been contemplated as being within the scope of the claimed matter. Furthermore, for each of the aspects described in the present invention, the corresponding form of any of these aspects can be described in the present invention as, for example, logic configured to perform the described action.

[0027] One-time programmable (OTP) memory cells have multiple applications in the integrated circuit (IC) industry, where they are used as programmable read-only memories (ROMs) to securely store program or device settings so that the settings cannot be tampered with, storing tuning parameters for phase-locked loops, and the like. Existing OTP designs that use a polysilicon (poly) electrical fuse have relatively low density and can be reprogrammed (or corrupted) causing some of their layers to reflow, which can corrupt the data. This vulnerability of conventional OTP designs makes them insecure. Thus, there is a need for high-density, non-reprogrammable OTP designs.

[0028] Consequently, one-time programmable (OTP) bit cells with a P- well capacitor and programmed using an oxide fusion method are disclosed. In an unprogrammed state, the capacitor provides a very high resistance (e.g., mega-ohms) between two terminals of the OTP bit cell, and in a programmed state, a breakdown in the capacitor dielectric causes a very low resistance (e.g., kilo-ohms). Petition 870250081227, dated 10 / 09 / 2025, page 13 / 79 8 / 27 through the two terminals. The P+ gate in a P- well also provides control over the oxide fusion area and the substrate connection area. The OTP bit cells disclosed in the present invention are not susceptible to reprogramming or corruption due to temperature reflux because dielectric breakdown is destructive and cannot be repaired, making the OTP bit cells disclosed in the present invention very secure.

[0029] Figure 1A is a cross-section of a secure anti-fuse OTP bit cell 100 (which may be referred to in the present invention simply as bit cell 100) in an unprogrammed state according to aspects of the disclosure. In the example shown in Figure 1A, a substrate 102 (e.g., silicon) is covered with a buried oxide layer (BOX) 104. Shallow trench isolation (STI) 106 electrically isolates a P-well 108. Inside the P-well 108, an N+ region 110 provides an electrical contact for a programming lead (PL) 112 for the P-well 108, and a P+ region 114 provides an electrical contact for a reading lead (RL) 116 for the P-well 108. A gate dielectric (GD) layer 118 (e.g., silicon dioxide (SiO2) or other dielectric material) is disposed on top of the P-well 108.A layer of polysilicon P+ 120 and a layer of silicide 122 form a gate structure having a gate contact (GC) 124. In some aspects, the gate structure may comprise a metal gate. Figure 1A shows the OTP bit cell 100 in an unprogrammed state. In this state, the GD 118 is an insulating layer that prevents current from flowing. Petition 870250081227, dated 10 / 09 / 2025, p. 14 / 79 9 / 27 flow between GC 124 and RL 116 at operating voltages. Thus, an unprogrammed OTP bit cell 100 can be referred to as being in a high-resistance state.

[0030] Figure 1B is a cross-section of the safe anti-fuse OTP bit cell 100 after it has been programmed by applying a high bias voltage (which may also be called a programming voltage) between GC 124 and PL 112, which causes a breakdown 126 in the gate dielectric layer 118 between the N+ region 110 and the gate structure. The breakdown 126 allows a current 128 to occur between GC 124 and RL 116 at operating voltages. In this way, a programmed OTP bit cell 100 can be referred to as being in a low resistance state. Unlike conventional OTP e-fuse designs, this breakdown cannot be repaired by reflux of the silicide layer 122, which makes the bit cell 100 safer than OTP e-fuse designs.

[0031] The secure anti-fuse OTP bit cell 100 includes a unique P- well and P+ cap structure that uses oxide fusion to change the bit cell resistance from very high (e.g., mega-ohms) in the unprogrammed state to very low (e.g., kilo-ohms) in the programmed state. The layout of the bit cell 100 provides control over the oxide fusion area and the substrate connection area. The OTP bit cells described in the present invention are not susceptible to reprogramming or corruption due to temperature reflux because dielectric breakdown is destructive and cannot be repaired. The OTP bit cell 100 and other OTP bit cells described in the present invention have a P+ polysilicon in a P- well with one or more N+ regions on one side of the Petition 870250081227, dated 10 / 09 / 2025, p. 15 / 79 10 / 27 polysilicon and one or more P+ regions on the other side of the polysilicon. The N+ regions provide the electrons to burn the dielectric and, once broken, the reading leads can read the resistance between the polysilicon and the P+ region(s). In some respects, the polysilicon gate can be replaced by metal gates, making this design compatible with last-gate wafer processes. In some respects, the dielectric layer of the gate can be SiO2 or high-K gate oxides.

[0032] Figure 2 illustrates an example circuit 200 for using and programming a secure anti-fuse OTP bit cell 100 according to aspects of the disclosure. In the example shown in Figure 2, the circuit 200 includes a high-voltage (HV) programming transistor, a low-voltage (LV) reading transistor, and a detection amplifier.

[0033] During programming, Vdd is applied to a bit line (BL), which is connected to the gate contact (GC) of bit cell 100, Vss is applied to the word line read line (WL), which is connected to the gate of the read transistor LV, and a programming voltage is applied through the programming transistor HV to the programming lead wire (PL) of bit cell 100, which causes a dielectric breakdown (i.e., a short circuit) between the GC and the read lead wire (RL).

[0034] During a read, Vdd is applied to the BL and the WL read line, and VSS is applied to the PL of the 100-bit cell through the HV programming transistor. If the 100-bit cell is not programmed, there is no short circuit. Petition 870250081227, dated 10 / 09 / 2025, page 16 / 79 11 / 27 circuit between GC and RL of bit cell 100, so that the voltage on RL, which will be provided to the input for the detection amplifier through the BT readout transistor, will be very low, much lower than Vdd. If bit cell 100 is programmed, the voltage on RL and therefore at the input for the detection amplifier will be Vdd.

[0035] Figure 3 is a simplified plan view of a layout of a three-terminal 300 secure anti-fuse OTP bit cell according to aspects of the disclosure. In the example layout shown in Figure 3, a P- well contains two N+ regions on the left side and two P+ regions on the right side. The N+ regions and the P+ regions are separated by a gate structure. A PL is connected to the N+ regions, an RL is connected to the P+ regions, and a GC is connected to the gate structure via two contacts. Figure 3 also illustrates the location of the potential oxide decomposition as a result of the programming.

[0036] Figure 4 is a simplified plan view of a layout of another three-terminal 400-bit secure anti-fuse OTP bit cell according to aspects of the disclosure. In the example layout shown in Figure 4, a P- well contains two N+ regions on the left side and one N+ region on the right side and one P+ region on the right side. This variant increases the potential oxide decomposition area compared to the 300 bit cell.

[0037] Figure 5 is a simplified plan view of a layout of a two-terminal 500 secure anti-fuse OTP bit cell according to aspects of the disclosure. Figure 5 illustrates a two-terminal OTP bit cell in which a single PL / RL terminal is used for both. Petition 870250081227, dated 10 / 09 / 2025, page 17 / 79 12 / 27 programming as well as for reading. In some respects, the single PL / RL terminal is connected not only to one or more N+ regions, but also to one or more P+ regions. In the example shown in Figure 5, the single PL / RL terminal is connected to a P+ region via silicide.

[0038] Figure 6 illustrates cross-sections of another 600 fuse-resistant OTP bit cell in the unprogrammed (left) and programmed (right) states, according to aspects of the disclosure. In the example shown in Figure 6, the STI 602 is covered with a GD 604, with a P+ polysilicon layer 606 and a silicide layer 608 arranged above the STI 602. A GC 610 makes electrical contact with the silicide layer 608, and an RL 612 is arranged above the STI 602 and in contact with the GD 604. In the unprogrammed state, the GD 604 is an insulating layer that prevents current from flowing between the GC 610 and the RL 612 at operating voltages. Thus, an unprogrammed 600 OTP bit cell can be referred to as being in a high-resistance state.

[0039] The OTP 600 bit cell is programmed by applying a programming voltage between GC 610 and RL 612, which causes a decomposition 614 of GD 604 in the region between the gate structure and RL 612. The decomposition 614 allows a current 616 to occur between GC 610 and RL 612 at operating voltages. In this way, a programmed OTP 600 bit cell can be referred to as being in a low-resistance state.

[0040] Figure 7 illustrates an exemplary mobile device according to some examples from the disclosure. Now with reference to Figure 7, a block diagram of a mobile device that is configured according to aspects Petition 870250081227, dated 10 / 09 / 2025, p. 18 / 79 13 / 27 examples are generally depicted and designated as mobile device 700. In some respects, mobile device 700 can be configured as a wireless communication device. As shown, mobile device 700 includes processor 702. Processor 702 can be communicatively coupled to memory 704 via a link, which can be a chip-to-chip or chip-to-chip link. Mobile device 700 also includes display 706 and display controller 708, with display controller 708 coupled to processor 702 and display 706.

[0041] In some respects, the mobile device 700 may include the encoder / decoder (CODEC coder / decoder) 710 (for example, an audio and / or voice CODEC) coupled to the processor 702; the speaker 712 and the microphone 714 coupled to the CODEC 710; and the wireless circuits 716 coupled to the wireless antenna 718 and the processor 702.

[0042] In a particular aspect, where one or more of the blocks mentioned above are present, the processor 702, the display controller 708, the memory 704, the CODEC 710, and the wireless circuitry 716 may be included in a system-in-a-package or system-on-a-chip (SoC) device 720. The input device 722 (e.g., physical or virtual keyboard), the display 706, the speaker 712, the microphone 714, the wireless antenna 718, and the power source 724 (e.g., battery) may be external to the SoC device 720 and may be coupled to a component of the SoC device 720, such as an interface or a controller. A secure anti-fuse OTP bit cell 726 according to aspects of the disclosure may be present in the processor 702, the memory 704, or any other Petition 870250081227, dated 10 / 09 / 2025, p. 19 / 79 14 / 27 component inside the SoC 720 device, for example.

[0043] It should be mentioned that although Figure 7 depicts a mobile device 700, the processor 702 and the memory 704 may also be integrated into a set top box, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a computer, a laptop, a tablet, a communication device, a mobile phone or other similar devices.

[0044] Figure 8 illustrates various electronic devices that can be integrated into any of the aforementioned integrated devices or semiconductor devices, according to various examples in the disclosure. For example, each of a mobile phone device 800, a laptop-type computer device 802, and a fixed-location terminal device 804 can generally be considered user equipment (UE user equipment) and may include a secure anti-fuse OTP bit cell 806, as described in the present invention, for example. The mobile phone device 800, the laptop-type computer device 802, and the fixed-location terminal device 804 illustrated in Figure 8 are merely examples.Other electronic devices may also feature a secure anti-fuse OTP bit cell 806 as described in the present invention, including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, handheld personal communication system (PCS) units, etc. Petition 870250081227, dated 10 / 09 / 2025, page 20 / 79 15 / 27 portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), an Internet of Things (IoT) device, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0045] Figure 9 is a flowchart of an example 900 process associated with the fabrication of a safe anti-fuse OTP bit cell according to aspects of the disclosure. As shown in Figure 9, the 900 process may include, in block 910, providing a P- well comprising an N+ region and a P+ region. As further shown in Figure 9, the 900 process may include, in block 920, providing a first electrically coupled contact to the N+ region of the P- well. As further shown in Figure 9, the 900 process may include, in block 930, providing a second electrically coupled contact to the P+ region of the P- well. As further shown in Figure 9, the 900 process may include, in block 940, providing an insulating layer disposed over a portion of the N+ region, a portion of the P- well, and a portion of the P+ region. As further shown in Figure 9, process 900 may include, in block 950, providing a structure Petition 870250081227, dated 10 / 09 / 2025, page 21 / 79 16 / 27 of the door arranged over the insulating layer. As additionally shown in Figure 9, process 900 may include, in block 960, providing a third contact electrically coupled to the door structure.

[0046] In some respects, in an unscheduled mode, the insulating layer creates a high resistance between the third contact and the second contact, and in a programmed mode, a break in the insulating layer creates a low resistance between the third contact and the second contact.

[0047] In some respects, providing the insulating layer involves providing a layer of silicon dioxide (SiO2).

[0048] In some respects, providing the P-well involves providing a P-well above a buried oxide layer (BOX).

[0049] In some respects, providing the P-well comprises providing a P-well that is surrounded by a shallow trench isolation structure (STI).

[0050] In some respects, providing the door structure involves providing the P+ polysilicon.

[0051] In some respects, providing the gate structure further comprises providing a silicide layer disposed between the P+ polysilicon and the third contact.

[0052] Process 900 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more of the other processes described elsewhere in the present invention. Although Figure 9 shows example blocks of process 900, in some implementations, process 900 may include additional blocks, fewer blocks, different blocks, or differentially arranged blocks. Petition 870250081227, dated 10 / 09 / 2025, page 22 / 79 17 / 27 in relation to those depicted in Figure 9. Additionally or alternatively, two or more of the process blocks 900 can be performed in parallel.

[0053] Figure 10 is a flowchart of a process. Example 1000 is associated with the fabrication of a safe anti-fuse OTP bit cell according to aspects of the disclosure. As shown in Figure 10, process 1000 may include, in block 1010, providing a first substrate layer. As further shown in Figure 10, process 1000 may include, in block 1020, providing an insulating layer disposed over the first substrate layer. As further shown in Figure 10, process 1000 may include, in block 1030, providing a gate structure disposed over the insulating layer. As further shown in Figure 10, process 1000 may include, in block 1040, providing a first contact electrically coupled to the gate structure. As further shown in Figure 10, process 1000 may include, in block 1050, providing a second contact coupled to the first substrate layer and in direct contact with the insulating layer.

[0054] In some respects, in an unscheduled mode, the insulating layer creates a high resistance between the first contact and the second contact, and in a programmed mode, a break in the insulating layer creates a low resistance between the first contact and the second contact.

[0055] In some respects, providing the insulating layer involves providing a layer of silicon dioxide (SiO2).

[0056] In some respects, providing the first substrate layer comprises providing a buried oxide layer (BOX) or shallow trench isolation structure (STI). Petition 870250081227, dated 10 / 09 / 2025, page 23 / 79 18 / 27

[0057] In some respects, providing the door structure involves providing the P+ polysilicon.

[0058] In some respects, providing the gate structure further comprises providing a silicide layer disposed between the P+ polysilicon and the first contact.

[0059] Process 1000 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more of the other processes described elsewhere in the present invention. Although Figure 10 shows example blocks of process 1000, in some implementations, process 1000 may include additional blocks, fewer blocks, different blocks, or blocks differentially arranged in relation to those depicted in Figure 10. Additionally or alternatively, two or more of the blocks of process 1000 may be implemented in parallel.

[0060] The safe anti-fuse OTP bit cells disclosed in the present invention provide several technical advantages. These technical advantages include, but are not limited to, the following: small layout size / higher density than conventional OTP structures; safe and irreversible OTP design that is not susceptible to temperature reflux; good control over the oxide fusion area and substrate connection area; and easy integration into a front-end-of-line (FEOL) CMOS process flow, which can be carried out entirely within a CMOS fabrication facility.

[0061] Implementation examples are described in the following numbered clauses:

[0062] Clause 1. A programmable bit cell Petition 870250081227, dated 10 / 09 / 2025, page 24 / 79 19 / 27 once (OTP), comprising: a P- well comprising an N+ region and a P+ region; a first contact electrically coupled to the N+ region of the P- well; a second contact electrically coupled to the P+ region of the P- well; an insulating layer disposed over a portion of the N+ region, a portion of the P- well and a portion of the P+ region; a gate structure disposed over the insulating layer; and a third contact electrically coupled to the gate structure.

[0063] Clause 2. The OTP bit cell of clause 1, where the insulating layer comprises a layer of silicon dioxide (SiO2).

[0064] Clause 3. The OTP bit cell of either clause 1 to 2, where the P-well is located above a buried oxide layer (BOX).

[0065] Clause 4. The OTP bit cell of any of clauses 1 to 3, where the P-well is surrounded by a shallow trench isolation structure (STI).

[0066] Clause 5. The OTP bit cell of any of clauses 1 to 4, where the gate structure comprises polysilicon P+.

[0067] Clause 6. The OTP bit cell of clause 5, wherein the gate structure additionally comprises a silicide layer disposed between the P+ polysilicon and the third contact.

[0068] Clause 7. The OTP bit cell of any of clauses 1 to 6, where the first contact is a programming conductor, the second contact is a reading conductor, and the third contact is a port contact.

[0069] Clause 8. An one-time programmable bit cell (OTP), comprising: a first layer of Petition 870250081227, dated 10 / 09 / 2025, p. 25 / 79 20 / 27 substrate; an insulating layer placed over the first substrate layer; a door structure placed over the insulating layer; a first contact electrically coupled to the door structure; and a second contact coupled to the first substrate layer and in direct contact with the insulating layer.

[0070] Clause 9. The OTP bit cell of clause 8, in which the insulating layer comprises a layer of silicon dioxide (SiO2).

[0071] Clause 10. The OTP bit cell of any of clauses 8 to 9, wherein the first substrate layer comprises a buried oxide layer (BOX) or shallow trench insulation structure (STI).

[0072] Clause 11. The OTP bit cell of any of clauses 8 to 10, where the gate structure comprises polysilicon P+.

[0073] Clause 12. The OTP bit cell of clause 11, wherein the gate structure additionally comprises a silicide layer disposed between the P+ polysilicon and the first contact.

[0074] Clause 13. The OTP bit cell of any of clauses 8 to 12, wherein the first contact is a port contact and the second contact is a programming and reading conductor wire.

[0075] Clause 14. A method for manufacturing a one-time programmable (OTP) bit cell, the method comprising: providing a P-well comprising an N+ region and a P+ region; providing a first contact electrically coupled to the N+ region of the P-well; providing a second contact electrically coupled to the P+ region of the P-well; providing an insulating layer disposed over a portion of the N+ region, a Petition 870250081227, dated 10 / 09 / 2025, page 26 / 79 21 / 27 portion of the P- well and a portion of the P+ region; provide a gate structure disposed over the insulating layer; and provide a third contact electrically coupled to the gate structure.

[0076] Clause 15. The method of clause 14, wherein providing the insulating layer comprises providing a layer of silicon dioxide (SiO2).

[0077] Clause 16. The method of any of clauses 14 to 15, wherein providing the P- well comprises providing a P- well above a buried oxide layer (BOX).

[0078] Clause 17. The method of any of clauses 14 to 16, wherein providing well P- comprises providing a well P- that is surrounded by a shallow trench isolation structure (STI).

[0079] Clause 18. The method of any of clauses 14 to 17, wherein providing the gate structure comprises providing P+ polysilicon.

[0080] Clause 19. The method of clause 18, wherein providing the door structure further comprises providing a silicide layer disposed between the P+ polysilicon and the third contact.

[0081] Clause 20. A method for manufacturing a one-time programmable (OTP) bit cell, the method comprising: providing a first substrate layer; providing an insulating layer disposed over the first substrate layer; providing a gate structure disposed over the insulating layer; providing a first contact electrically coupled to the gate structure; and providing a second contact coupled to the first substrate layer and in direct contact with the insulating layer. Petition 870250081227, dated 10 / 09 / 2025, page 27 / 79 22 / 27

[0082] Clause 21. The method of clause 20, wherein providing the insulating layer comprises providing a layer of silicon dioxide (SiO2).

[0083] Clause 22. The method of any of clauses 20 to 21, wherein providing the first substrate layer comprises providing a buried oxide layer (BOX) or shallow trench isolation structure (STI).

[0084] Clause 23. The method of any of clauses 20 to 22, wherein providing the gate structure comprises providing P+ polysilicon.

[0085] Clause 24. The method of clause 23, wherein providing the gate structure further comprises providing a silicide layer disposed between the P+ polysilicon and the first contact.

[0086] It should be noted that the terms connected, coupled or any variant thereof mean any connection or coupling, whether direct or indirect, between elements, and may encompass the presence of an intermediate element between two elements that are connected or coupled to each other via an intermediate element, unless the connection is expressly disclosed as being directly connected.

[0087] Any reference in the present invention to an element using a designation such as first, second, and so forth does not limit the quantity and / or order of such elements. Rather, such designations are used as a convenient method of distinguishing between two or more elements or instances of an element. Furthermore, unless otherwise specified, a set of elements may comprise one or more elements. Petition 870250081227, dated 10 / 09 / 2025, page 28 / 79 23 / 27

[0088] Nothing stated or illustrated depicted in this application is intended to impart to the public any component, action, attribute, benefit, advantage, or equivalent, whether or not the component, action, attribute, benefit, advantage, or equivalent is mentioned in the claims.

[0089] Additionally, those skilled in the art will recognize that the various illustrative logic blocks, modules, circuits, and algorithm actions described in connection with the examples disclosed in the present invention can be implemented in the form of electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and actions have been described above in general terms of their functionality. The possibility of such functionality being implemented as hardware or software depends on the particular application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a deviation from the scope of the present disclosure.

[0090] Although some aspects have been described in connection with a device, it is needless to say that these aspects also constitute a description of the corresponding method and, therefore, a block or component of a device should also be understood as a corresponding method action, or as an attribute of a method action. Analogously to this, the aspects described Petition 870250081227, dated 10 / 09 / 2025, page 29 / 79 24 / 27 in connection with, or as, a method action also constitute a description of a corresponding block or detail or attribute of a corresponding device. Some or all method actions may be performed by a hardware device (or with the use of a hardware device) such as, for example, a microprocessor, a programmable computer, or an electronic circuit. In some examples, some or a plurality of the most important method actions may be performed by this type of device.

[0091] In the detailed description above, it can be noted that different attributes are grouped into examples. This disclosure method should not be understood as an intention for the example clauses to have more attributes than are explicitly mentioned in each clause. Instead, the various aspects of the disclosure may include fewer than the totality of the attributes of an individual disclosed example clause. Therefore, the example clauses should be considered incorporated into the description, where each clause by itself can serve as a separate example. Although each dependent clause may refer in the clauses to a specific combination with one of the other clauses, the aspect(s) of that dependent clause are not limited to the specific combination.It will be recognized that other example clauses may also include a combination of the aspect(s) of the dependent clause with the subject matter of any other dependent or independent clause, or a combination of any attribute with other dependent and independent clauses. The various aspects disclosed in the present invention expressly include such combinations, unless otherwise stated. Petition 870250081227, dated 10 / 09 / 2025, p. 30 / 79 25 / 27 explicitly states, or it can be easily inferred, that a specific combination is not intended (for example, contradictory aspects, such as defining an element as both an insulator and a conductor). Furthermore, it is also intended that aspects of a clause can be included in any other independent clause, even if the clause is not directly dependent on the independent clause.

[0092] The packages, devices, and functionalities previously disclosed can be designed and configured in computer files (e.g., RTL, GDSII, GERBER, etc.) stored on computer-readable media. Some or all of these files can be provided to manufacturing manipulators who fabricate devices based on such files. The resulting products may include semiconductor wafers that are then cut into semiconductor wafers and packaged into a flip-chip or other package. The packages can then be employed in devices described in the present invention.

[0093] It will be acknowledged that various aspects disclosed in the present invention can be described as functionally equivalent to structures, materials and / or devices described and / or recognized by those skilled in the art. For example, in one aspect, an apparatus may comprise a means for performing the various functionalities discussed above. It will be acknowledged that the aforementioned aspects are merely provided as examples, and that the various claimed aspects are not limited to the specific references and / or illustrations cited as examples.

[0094] One or more of the components, processes, Petition 870250081227, dated 10 / 09 / 2025, page 31 / 79 26 / 27 attributes and / or functions illustrated in Figures 1 to 8 can be rearranged and / or combined into a single component, step, attribute, or function, or incorporated into multiple components, processes, or functions. Additional elements, components, processes, and / or functions can also be added without departing from the disclosure. It should also be noted that Figures 1 to 8 and the corresponding description in this disclosure are not limited to wafers and / or ICs. In some implementations, Figures 1 to 8 and the corresponding descriptions can be used to manufacture, create, provide, and / or produce integrated devices. In some implementations, a device may include a wafer, an integrated device, a wafer package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, and / or an interposer.

[0095] Furthermore, it should be noted that methods, systems, and devices disclosed in the description or claims may be implemented by a device comprising means for performing the respective actions and / or functionalities of the disclosed methods. In addition, in some examples, an individual action may be subdivided into a plurality of sub-actions or contain a plurality of sub-actions. Such sub-actions may be contained within the disclosure of the individual action and form part of the disclosure of the individual action.

[0096] Although the aforementioned disclosure shows illustrative aspects of the disclosure, it should be noted that various changes and modifications may be made to the present invention without departing from its scope. Petition 870250081227, dated 10 / 09 / 2025, page 32 / 79 27 / 27 of the disclosure, as defined by the appended claims. The functions, steps and / or actions of the method claims according to the disclosure aspects described in the present invention need not be performed in any particular order. Furthermore, although the disclosure elements may be described or claimed in the singular, the plural is contemplated unless a limitation to the singular is explicitly stated. Petition 870250081227, dated 10 / 09 / 2025, p. 33 / 79

Claims

1 / 4 CLAIMS 1. One-time programmable bit cell (OTP) characterized by comprising: a P- well comprising an N+ region and a P+ region; a first contact electrically coupled to the N+ region of the P- well; a second contact electrically coupled to the P+ region of the P- well; an insulating layer disposed over a portion of the N+ region, a portion of the P- well and a portion of the P+ region; a gate structure disposed over the insulating layer; and a third contact electrically coupled to the gate structure.

2. OTP bit cell, according to claim 1, characterized in that the insulating layer comprises a layer of silicon dioxide (SiO2).

3. OTP bit cell, according to claim 1, characterized in that the P-well is arranged above a buried oxide layer (BOX).

4. OTP bit cell, according to claim 1, characterized in that the P-well is surrounded by a shallow trench isolation structure (STI).

5. OTP bit cell, according to claim 1, characterized in that the gate structure comprises P+ polysilicon.

6. OTP bit cell, according to claim 5, characterized in that the gate structure further comprises a silicide layer disposed between the P+ polysilicon and the third contact.

7. OTP bit cell, according to claim 1, characterized in that the first contact is a programming conductor wire, the second contact is a reading conductor wire, and the third contact is a gate contact.

8. One-time programmable bit cell (OTP) characterized by comprising: a first substrate layer; an insulating layer disposed over the first substrate layer; a gate structure disposed over the insulating layer; a first contact electrically coupled to the gate structure; and a second contact coupled to the first substrate layer and in direct contact with the insulating layer.

9. OTP bit cell, according to claim 8, characterized in that the insulating layer comprises a layer of silicon dioxide (SiO2).

10. OTP bit cell, according to claim 8, characterized in that the first substrate layer comprises a buried oxide layer (BOX) or shallow trench insulation structure (STI).

11. OTP bit cell, according to claim 8, characterized in that the gate structure comprises P+ polysilicon.

12. OTP bit cell, according to claim 11, characterized in that the gate structure additionally comprises a silicide layer disposed between the P+ polysilicon and the first contact. Petition 870250081227, dated 10 / 09 / 2025, pp. 63 / 79 3 / 4 13. OTP bit cell, according to claim 8, characterized in that the first contact is a gate contact and the second contact is a programming and reading conductor wire.

14. A method for manufacturing a one-time programmable bit cell (OTP) characterized by comprising: providing a P- well comprising an N+ region and a P+ region; providing a first contact electrically coupled to the N+ region of the P- well; providing a second contact electrically coupled to the P+ region of the P- well; providing an insulating layer disposed over a portion of the N+ region, a portion of the P- well and a portion of the P+ region; providing a gate structure disposed over the insulating layer; and providing a third contact electrically coupled to the gate structure.

15. Method according to claim 14, characterized in that the insulating layer comprises providing a layer of silicon dioxide (SiO2).

16. Method according to claim 14, characterized in that the provision of well P- comprises providing a well P- above a buried oxide layer (BOX).

17. Method according to claim 14, characterized in that the provision of well P- comprises providing a well P- that is surrounded by a shallow trench isolation structure (STI).

18. Method, according to claim 14, characterized by the provision of the door structure Petition 870250081227, dated 10 / 09 / 2025, page 64 / 79 4 / 4 comprising providing polysilicon P+.

19. Method according to claim 18, characterized in that the gate structure provision further comprises providing a silicide layer disposed between the P+ polysilicon and the third contact.

20. A method for manufacturing a one-time programmable bit cell (OTP) characterized by comprising: providing a first substrate layer; providing an insulating layer disposed over the first substrate layer; providing a gate structure disposed over the insulating layer; providing a first contact electrically coupled to the gate structure; and providing a second contact coupled to the first substrate layer and in direct contact with the insulating layer.

21. Method according to claim 20, characterized in that the insulating layer comprises providing a layer of silicon dioxide (SiO2).

22. Method according to claim 20, characterized in that the provision of the first substrate layer comprises providing a buried oxide layer (BOX) or shallow trench isolation structure (STI).

23. Method according to claim 20, characterized in that the gate structure provision comprises providing polysilicon P+.

24. Method according to claim 23, characterized in that the door structure provision further comprises providing a silicide layer disposed between the P+ polysilicon and the first contact. Petition 870250081227, dated 10 / 09 / 2025, pp. 65 / 79

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