Camera device

Abstract

A camera device comprises: a photoelectric conversion unit that performs photoelectric conversion on incident light and generates electric charges; a first transistor, a gate of which is electrically connected to the photoelectric conversion unit and outputs an electric signal corresponding to the electric charges; a second transistor, one of a source and a drain of which is electrically connected to the photoelectric conversion unit; a first capacitor connected between the source and the drain of the second transistor; and a second capacitor connected between the other of the source and the drain of the second transistor and a reference potential.

Description

[0001] This application is a divisional of an invention patent application filed on November 26, 2015, with application number 201510836849.7 and invention name “Camera Device”. Technical Field

[0002] The present application relates to an imaging device and particularly to an imaging device having a photoelectric conversion unit including a photoelectric conversion film stacked on a semiconductor substrate. Background Art

[0003] As a MOS (Metal Oxide Semiconductor) type camera device, a stacked camera device has been proposed. In a stacked camera device, a photoelectric conversion film is stacked on the outermost surface of a semiconductor substrate, and the charge generated by photoelectric conversion in the photoelectric conversion film is accumulated in a charge accumulation region (called a "floating diffusion region"). The camera device uses a CCD (Charge Coupled Device) circuit or a CMOS (Complementary MOS) circuit in the semiconductor substrate to read out the accumulated charge. For example, Patent Document 1 discloses such a camera device.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2009-164604

[0005] Patent Document 2: Japanese Patent Application Publication No. 2011-228621 Summary of the invention

[0006] In the field of imaging devices, there is a demand for noise reduction, and in particular, there is a demand for reducing kTC noise (also referred to as "reset noise") generated during resetting.

[0007] According to a non-limiting exemplary embodiment of the present application, the following technical solution is provided.

[0008] A camera device comprises: a photoelectric conversion unit that performs photoelectric conversion on incident light and generates electric charges; a first transistor, a gate of which is electrically connected to the photoelectric conversion unit and outputs an electric signal corresponding to the electric charges; a second transistor, one of a source and a drain of which is electrically connected to the photoelectric conversion unit; a first capacitor connected between the source and the drain of the second transistor; and a second capacitor connected between the other of the source and the drain of the second transistor and a reference potential.

[0009] Another imaging device comprises: a unit pixel unit, including a photoelectric conversion part that performs photoelectric conversion on incident light and generates an electric signal, a signal detection circuit that detects the electric signal, and a capacitor circuit formed by connecting a first capacitor and a second capacitor having a capacitance value larger than that of the first capacitor in series; and a feedback circuit that forms a feedback path for negatively feeding back the electric signal; the photoelectric conversion part comprises a photoelectric conversion film, a first electrode formed on the light-receiving side of the photoelectric conversion film, and a second electrode formed on the surface of the photoelectric conversion film opposite to the first electrode; the signal detection circuit comprises a first transistor and a second transistor, the first transistor amplifies and outputs a signal voltage corresponding to the potential of the second electrode, one of the source and the drain of the second transistor is connected to the second electrode; the first capacitor is connected between the source and the drain of the second transistor; the feedback circuit feeds back the electric signal negatively to the other of the source and the drain of the second transistor; and the capacitor circuit is arranged between the second electrode and a reference potential.

[0010] In addition, the inclusive or specific forms may also be realized by components, devices, systems, integrated circuits and methods. In addition, the inclusive or specific forms may also be realized by any combination of components, devices, systems, integrated circuits and methods.

[0011] Additional effects and advantages of the disclosed embodiments will become apparent from the specification and drawings. The effects and / or advantages are provided by the various embodiments or features disclosed in the specification and drawings, respectively, and it is not necessary to obtain all of them in order to obtain one or more of them.

[0012] Effects of the Invention

[0013] According to one technical solution of the present invention, there is provided an imaging device capable of further reducing noise such as kTC noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic diagram showing an exemplary circuit configuration of the imaging device according to the first embodiment.

[0015] Figure 2 Yes means Figure 1 FIG. 1 is a schematic diagram of an exemplary circuit structure of a unit pixel unit 11 shown in FIG.

[0016] Figure 3 This is a timing chart for explaining an example of the operation of the transistor in the first mode of the imaging device according to the first embodiment.

[0017] Figure 4 This is a timing chart for explaining an example of the operation of the transistor in the second mode of the imaging device according to the first embodiment.

[0018] Figure 5 1 is a plan view schematically showing an example of the layout of each element in the unit pixel unit 11 .

[0019] Figure 6 It indicates schematically Figure 5 A cross-sectional view of the AA' line section is shown.

[0020] Figure 7 1 is a plan view schematically showing another example of the layout of each element in the unit pixel unit 11 .

[0021] Figure 8 It indicates schematically Figure 7 A cross-sectional view of the cross section along the BB' line is shown.

[0022] Fig. 9 It is a schematic cross-sectional view for explaining an exemplary method of manufacturing the imaging device 101 .

[0023] Fig.10 It is a schematic cross-sectional view for explaining an exemplary method of manufacturing the imaging device 101 .

[0024] Fig.11 It is a schematic cross-sectional view for explaining an exemplary method of manufacturing the imaging device 101 .

[0025] Fig.12 It is a schematic cross-sectional view for explaining an exemplary method of manufacturing the imaging device 101 .

[0026] Fig.13 FIG. 1 is a schematic diagram showing another exemplary circuit configuration of the unit pixel unit of the imaging device according to the first embodiment.

[0027] Fig.14 It is a schematic diagram showing an exemplary circuit configuration of a unit pixel unit of the imaging device according to the second embodiment.

[0028] Fig.15 This is a schematic diagram showing an exemplary circuit configuration of a unit pixel unit of an image pickup device according to a third embodiment.

[0029] Fig.16 This is a timing chart for explaining an example of the operation of the transistor in the first mode of the imaging device according to the third embodiment.

[0030] Fig.17 This is a timing chart for explaining an example of the operation of the transistor in the second mode of the imaging device according to the third embodiment.

[0031] Fig.18It is a schematic diagram showing an exemplary circuit configuration of a unit pixel unit 14 a of an image pickup device according to a modified example of the third embodiment.

[0032] Fig.19 This is a schematic diagram showing an exemplary circuit configuration of a unit pixel unit 14b according to another modified example of the imaging device according to the third embodiment.

[0033] Fig. 20 It is a schematic cross-sectional view showing an example of a device structure of a unit pixel unit of an imaging device according to a fourth embodiment.

[0034] Fig.21 Yes means Fig. 20 FIG. 2 is a schematic plan view of an example of the arrangement of an upper electrode 62 u , a dielectric layer 62 d , and a lower electrode 62 b of a unit pixel cell 60A.

[0035] Fig. 22 It is a schematic cross-sectional view showing still another example of the device structure of the unit pixel unit of the imaging device according to the fourth embodiment.

[0036] Fig.23 Yes means Fig. 22 FIG. 2 is a schematic plan view of an example of the arrangement of an upper electrode 62 u , a dielectric layer 62 d , and a lower electrode 62 b of a unit pixel cell 60B.

[0037] Fig.24 It is a schematic cross-sectional view showing still another example of the device structure of the unit pixel unit of the imaging device according to the fourth embodiment.

[0038] Fig.25 Yes means Fig.24 FIG. 2 is a schematic plan view of an example of the arrangement of an upper electrode 62 u , a dielectric layer 62 d , and a lower electrode 62 b of a unit pixel cell 60C.

[0039] Fig.26 This is a schematic diagram showing a configuration example of a camera system according to the fifth embodiment. DETAILED DESCRIPTION

[0040] Before describing the embodiments of the present invention in detail, the findings of the present inventors will be described.

[0041] As a readout circuit for the charge accumulated in the charge accumulation region, a structure in which three transistors are arranged in a pixel is known. Figure 4In the patent document 2, a signal readout circuit having an output transistor, a row selection transistor, and a reset transistor for resetting a floating diffusion region is described. In addition, a readout circuit is also known in which a transfer transistor for transferring charges generated by photoelectric conversion to a floating diffusion region is also provided in the pixel. For example, Figure 7 The signal readout circuit in has four transistors, namely a reset transistor, an output transistor, a row selection transistor and a transistor for charge transfer. Among these four transistors, the fourth transistor is connected between the pixel electrode and the floating diffusion area. The fourth transistor is a transfer transistor that transfers the charge generated by photoelectric conversion and collected in the pixel electrode to the floating diffusion area. Hereinafter, there is a case where the readout circuit having a transfer transistor in the pixel is referred to as a "4Tr readout circuit". In addition, there is a case where the readout circuit not having a transfer transistor in the pixel is referred to as a "3Tr readout circuit". For reference, the entire disclosure of Patent Gazette No. 2011-228621 is cited in this specification.

[0042] In a so-called CCD image sensor or CMOS image sensor in which a photodiode is formed on a semiconductor substrate, it is known that the influence of reset kTC noise can be removed by applying correlated double sampling (CDS) in a 4Tr readout circuit. However, according to the research of the present inventors, it is difficult to remove the influence of reset kTC noise by the above method in a stacked type imaging device.

[0043] For stacked camera devices, typically, a metal wiring or a metal layer is sandwiched between the photoelectric conversion unit and the semiconductor substrate for electrical connection between the photoelectric conversion unit and the semiconductor substrate. Therefore, it is difficult to completely transfer the charge collected by the pixel electrode to the floating diffusion region. Therefore, in stacked camera devices, simply providing a transfer transistor in a pixel and applying correlated double sampling is not effective. It is desirable to reduce kTC noise in stacked camera devices.

[0044] An outline of one aspect of the present invention is as follows.

[0045] [Project 1]

[0046] A camera device comprises: a unit pixel unit, including a photoelectric conversion part that performs photoelectric conversion on incident light and generates an electric signal, a signal detection circuit that detects the electric signal, and a capacitor circuit formed by connecting a first capacitor and a second capacitor having a larger capacitance value than the first capacitor in series; and a feedback circuit that forms a feedback path for negatively feeding back the electric signal; the photoelectric conversion part has a photoelectric conversion film, a first electrode formed on the light-receiving surface side of the photoelectric conversion film, and a second electrode formed on the surface of the photoelectric conversion film opposite to the first electrode; the signal detection circuit includes a first transistor and a second transistor, the gate of the first transistor is connected to the second electrode, the first transistor amplifies and outputs a signal voltage corresponding to the potential of the second electrode, and one of the source and drain of the second transistor is connected to the second electrode; the electric signal is negatively fed back to the other of the source and drain of the second transistor; the capacitor circuit is arranged between the second electrode and a reference potential. According to this structure, the reset kTC noise generated in the reset action of the pixel can be effectively reduced by the capacitor circuit connected in series with the photoelectric conversion part.

[0047] [Project 2]

[0048] A camera device comprises: a unit pixel unit, including a photoelectric conversion part that performs photoelectric conversion on incident light and generates an electric signal, a signal detection circuit that detects the electric signal, and a capacitor circuit formed by connecting a first capacitor and a second capacitor having a larger capacitance value than the first capacitor in series; and a feedback circuit that forms a feedback path for negatively feeding back the electric signal; the photoelectric conversion part has a photoelectric conversion film, a first electrode formed on the light-receiving surface side of the photoelectric conversion film, and a second electrode formed on the surface of the photoelectric conversion film opposite to the first electrode; the signal detection circuit includes a first transistor and a first transistor, the gate of the first transistor is connected to the second electrode, the first transistor amplifies and outputs a signal voltage corresponding to the potential of the second electrode, and one of the source and drain of the second transistor is connected to the second electrode; the feedback circuit negatively feeds back the output of the signal detection circuit to the other of the source and drain of the second transistor; and the capacitor circuit is arranged between the second electrode and a reference potential. According to this structure, the reset kTC noise generated in the reset action of the pixel can be effectively reduced by the capacitor circuit connected in series with the photoelectric conversion part.

[0049] [Item 3]

[0050] In the imaging device described in item 1 or 2, the feedback circuit includes a first transistor and an inverting amplifier in a part of a feedback path, and negatively feeds back the electrical signal to the other of the source and the drain of the second transistor via the first transistor and the inverting amplifier.

[0051] [Item 4]

[0052] In the imaging device according to any one of items 1 to 3, the first capacitor is connected between the source and the drain of the second transistor. According to this structure, the second transistor can be used as a reset transistor and a gain switching transistor. Therefore, the unit can be miniaturized. In addition, the transistor junction leakage to the charge storage node can be reduced, and the dark current can be reduced.

[0053] [Item 5]

[0054] In the imaging device according to Item 4, the first capacitor and the second transistor are connected in parallel.

[0055] [Item 6]

[0056] In the imaging device according to any one of items 1 to 5, the second capacitor is connected to at least one of the source or the drain of the second transistor.

[0057] [Item 7]

[0058] In the imaging device according to item 4 or 5, the amount of change in the potential of the second electrode is switched by turning the second transistor on and off. With this configuration, the sensitivity of the imaging device can be switched.

[0059] [Item 8]

[0060] The imaging device according to any one of items 1 to 7, wherein the signal detection circuit further includes a third transistor that selectively outputs the output of the first transistor to the feedback circuit.

[0061] [Item 9]

[0062] The imaging device as described in any one of items 1 to 8, wherein the signal detection circuit further includes a fourth transistor that selectively transmits the electrical signal fed back to the first capacitor by the feedback circuit to the other of the source and the drain of the second transistor. According to this configuration, the feedback circuit can be selectively formed by the second transistor.

[0063] [Item 10]

[0064] In the imaging device according to any one of items 1 to 8, the signal detection circuit further includes a fourth transistor connected between a source and a drain of the second transistor and configured to selectively transfer the electrical signal fed back from the feedback circuit to the first capacitor.

[0065] [Item 11]

[0066] A camera device is realized, which has a unit pixel unit, the unit pixel unit includes a photoelectric conversion part that performs photoelectric conversion on incident light, a signal detection circuit that detects a signal of the photoelectric conversion part, and a capacitor circuit formed by connecting a first capacitor and a second capacitor whose capacitance value is larger than the first capacitor in series; the photoelectric conversion part has a photoelectric conversion film, a first electrode formed on the light-receiving side of the photoelectric conversion film, and a second electrode formed on the surface of the photoelectric conversion film opposite to the first electrode; the signal detection circuit includes a first transistor that amplifies and outputs a signal voltage corresponding to the potential of the second electrode, and a second transistor whose source and drain are connected to the second electrode; the capacitor circuit is arranged between the second electrode and a reference potential, and the first capacitor is connected between the source and drain of the second transistor; the change amount of the potential of the second electrode is switched by turning the second transistor on and off. According to this structure, a camera device capable of switching photographic sensitivity is realized.

[0067] [Item 12]

[0068] In the imaging device according to Item 11, the second transistor is turned on and off according to the imaging mode.

[0069] [Item 13]

[0070] In the imaging device as recited in Item 12, the photographing mode includes a mode for photographing when the subject is bright and a mode for photographing when the subject is dark.

[0071] [Item 14]

[0072] A camera device includes a unit pixel unit, the unit pixel unit includes a photoelectric conversion part that performs photoelectric conversion on incident light, and a signal detection circuit that detects a signal generated by the photoelectric conversion part; the photoelectric conversion part includes a photoelectric conversion film, a first electrode formed on the light-receiving surface side of the photoelectric conversion film, and a second electrode that is opposite to the first electrode via the photoelectric conversion film; the signal detection circuit includes an amplifier transistor whose gate is connected to the second electrode, a reset transistor whose source and drain are connected to the second electrode, a first capacitor element, and a second capacitor element having a capacitance value larger than that of the first capacitor element; the amplifier transistor and the reset transistor are formed on the same semiconductor substrate; the second capacitor element includes a first insulating film provided on a portion of the semiconductor substrate, and a third electrode that is opposite to a portion of the semiconductor substrate via the first insulating film; the first capacitor element includes a second insulating film formed on the third electrode, and a fourth electrode that is connected to the second electrode and at least a portion of which overlaps with the third electrode via the second insulating film when viewed from the normal direction of the semiconductor substrate.

[0073] According to the configuration of item 14, it is possible to reduce kTC noise generated in association with resetting while suppressing an increase in the capacitance value of the entire signal charge storage region.

[0074] [Item 15]

[0075] The imaging device according to item 14 further comprises a feedback circuit for performing negative feedback on the output of the signal detection circuit; and an output line of the feedback circuit is connected to the other of the source and the drain of the reset transistor.

[0076] According to the structure of item 15, the generated kTC noise can be eliminated in a short time.

[0077] [Item 16]

[0078] In the imaging device according to item 14 or 15, a part of the semiconductor substrate is connected to a voltage source that supplies a sensitivity adjustment voltage.

[0079] According to the configuration of item 16, the potential of the charge storage node for storing signal charges can be controlled, and the sensitivity of the imaging device can be adjusted.

[0080] [Item 17]

[0081] In the imaging device according to any one of items 14 to 16, the third electrode is connected to the other of the source and the drain of the reset transistor.

[0082] According to the configuration of item 17, by switching the reset transistor on and off, it is possible to select whether to connect the second capacitor to the charge storage node via the first capacitor or to connect the second capacitor to the charge storage node via the reset transistor.

[0083] [Item 18]

[0084] In the imaging device as described in any one of items 14 to 17, the signal detection circuit includes an address transistor formed on a semiconductor substrate and supplying the output of the amplifier transistor as an input to the feedback circuit in accordance with an input signal.

[0085] According to the structure of item 18, one of the plurality of unit pixel cells sharing the feedback line can be selected to perform resetting and / or noise elimination.

[0086] [Item 19]

[0087] In the imaging device according to any one of items 14 to 18, the fourth electrode is a part of a wiring layer that connects the gate of the amplifier transistor to one of the source and the drain of the reset transistor.

[0088] According to the structure of item 19, the first capacitor element can be formed in the unit pixel unit without increasing the number of steps.

[0089] [Item 20]

[0090] In the imaging device according to any one of items 14 to 19, the third electrode and the fourth electrode are formed of polysilicon.

[0091] According to the configuration of item 20, a highly accurate first capacitor element having a flat CV characteristic can be realized.

[0092] [Item 21]

[0093] The imaging device according to any one of items 14 to 20 includes a fifth electrode overlapping the third electrode via a second insulating film, wherein the fifth electrode has a third capacitive element electrically connected to a portion of the semiconductor substrate.

[0094] According to the structure of item 21, a capacitor element electrically connected to the second capacitor element can be further formed without adding a dedicated process. As a result, a larger combined capacitance can be obtained, so kTC noise can be reduced more effectively.

[0095] [Item 22]

[0096] A camera device includes a unit pixel unit, the unit pixel unit includes a photoelectric conversion part that performs photoelectric conversion on incident light, and a signal detection circuit that detects a signal generated by the photoelectric conversion part; the photoelectric conversion part has a photoelectric conversion film, a first electrode formed on the light-receiving surface side of the photoelectric conversion film, and a second electrode opposite to the first electrode across the photoelectric conversion film; the signal detection circuit includes an amplifier transistor whose gate is connected to the second electrode, a reset transistor whose source and drain are connected to the second electrode, a first capacitor element, and a second capacitor element having a capacitance value larger than that of the first capacitor element; the amplifier transistor and the reset transistor are formed on the same semiconductor substrate; the second capacitor element includes a third electrode arranged between the semiconductor substrate and the second electrode, a fourth electrode that is farther from the second electrode than the third electrode, and a first dielectric layer arranged between the third electrode and the fourth electrode.

[0097] According to the configuration of item 22, it is possible to reduce kTC noise generated in association with resetting while suppressing an increase in the capacitance value of the entire signal charge storage region.

[0098] [Item 23]

[0099] In the imaging device as described in Item 22, the fourth electrode of the second capacitor element is formed in an impurity region of a semiconductor substrate; the first capacitor element includes a second dielectric layer; at least a portion of the electrode on one side of the first capacitor element overlaps with the third electrode when viewed from the normal direction of the semiconductor substrate; and the second dielectric layer of the first capacitor element is arranged between the electrode on one side and the third electrode.

[0100] According to the structure of item 23, it is possible to form a second capacitor element having a relatively high capacitance while suppressing an increase in the number of manufacturing steps.

[0101] [Item 24]

[0102] In the imaging device according to Item 23, one of the electrodes is a part of a wiring layer connecting the gate of the amplifier transistor to one of the source and the drain of the reset transistor.

[0103] According to the structure of item 24, the first capacitor element can be formed in the unit pixel unit without increasing the number of steps.

[0104] [Item 25]

[0105] The imaging device according to item 23 or 24 includes a third capacitance element including a fifth electrode overlapping the third electrode via the second dielectric layer, and the fifth electrode is electrically connected to the fourth electrode.

[0106] According to the structure of item 25, a capacitor element electrically connected to the second capacitor element can be further formed without adding a dedicated process. As a result, a larger combined capacitance can be obtained, so kTC noise can be reduced more effectively.

[0107] [Item 26]

[0108] In the imaging device according to any one of items 22 to 25, the third electrode is connected to the other of the source and the drain of the reset transistor.

[0109] According to the configuration of item 26, by switching the reset transistor on and off, it is possible to select whether to connect the second capacitor to the charge storage node via the first capacitor or to connect the second capacitor to the charge storage node via the reset transistor.

[0110] [Item 27]

[0111] The imaging device according to any one of items 22 to 26 further comprises a feedback circuit for negatively feeding back an output of the signal detection circuit; an output line of the feedback circuit is connected to the other of the source and the drain of the reset transistor.

[0112] According to the structure of item 27, the generated kTC noise can be eliminated in a short time.

[0113] [Item 28]

[0114] In the imaging device described in Item 27, the signal detection circuit has an address transistor formed on a semiconductor substrate and supplies the output of the amplification transistor as an input to the feedback circuit in accordance with an input signal.

[0115] According to the structure of item 28, it is possible to select one of the plurality of unit pixel cells sharing the feedback line and perform resetting and / or noise elimination.

[0116] [Item 29]

[0117] In the imaging device according to any one of items 22 to 28, the fourth electrode is connected to a voltage source that supplies a sensitivity adjustment voltage.

[0118] According to the configuration of item 29, the potential of the charge storage node that stores signal charges can be controlled, and the sensitivity of the imaging device can be adjusted.

[0119] [Item 30]

[0120] The imaging device as described in any one of items 1 to 29, wherein the feedback circuit includes a first transistor and an inverting amplifier in a part of a feedback path, and negatively feeds back the electrical signal to the other of the source and the drain of the second transistor via the first transistor and the inverting amplifier.

[0121] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, the embodiments described below all represent inclusive or specific examples. The numerical values, shapes, materials, constituent elements, configurations of constituent elements and connection forms, steps, the order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present invention. The various forms described in this specification can be combined with each other as long as no contradiction occurs. In addition, among the constituent elements of the following embodiments, constituent elements that are not recorded in the independent claims representing the highest concept are described as arbitrary constituent elements. In the following description, constituent elements having substantially the same function are represented by common reference numerals and the description is sometimes omitted.

[0122] (First embodiment)

[0123] Figure 1 An exemplary circuit configuration of the imaging device according to the first embodiment is schematically shown. Figure 1 The imaging device 101 shown has a plurality of unit pixel units 11 and peripheral circuits. The plurality of unit pixel units 11 are arranged two-dimensionally on a semiconductor substrate to form a photosensitive region (pixel region). The semiconductor substrate is not limited to a substrate whose entirety is a semiconductor. The semiconductor substrate may also be an insulating substrate having a semiconductor layer on the surface of one side where the photosensitive region is formed.

[0124] In the figure 1In the example shown, the plurality of unit pixel units 11 are arranged in the row direction and the column direction. In this specification, the row direction and the column direction refer to the directions in which the rows and columns extend respectively. That is, in the figure, the vertical direction in the paper is the column direction, and the horizontal direction is the row direction. The plurality of unit pixel units 11 can also be arranged in one dimension. In other words, the imaging device 101 can be a line sensor.

[0125] The unit pixel cells 11 are connected to the power supply wiring 22. A predetermined power supply voltage is supplied to each unit pixel cell 11 via the power supply wiring 22. As described in detail later, each unit pixel cell 11 includes a photoelectric conversion unit having a photoelectric conversion film stacked on a semiconductor substrate. Figure 1 As shown in FIG. 1 , the imaging device 101 includes a storage control line 17 for applying the same constant voltage to all the photoelectric conversion parts.

[0126] The peripheral circuit of the imaging device 101 includes a vertical scanning circuit (also called a "row scanning circuit") 16, a load circuit 19, a column signal processing circuit (also called a "row signal storage circuit") 20, a horizontal signal readout circuit (also called a "column scanning circuit") 21, and an inverting amplifier 24. Figure 1 In the illustrated structure, the column signal processing circuit 20, the load circuit 19 and the inverting amplifier 24 are arranged for each column of the two-dimensionally arranged unit pixel cells 11. That is, in this example, the peripheral circuit includes a plurality of column signal processing circuits 20, a plurality of load circuits 19 and a plurality of inverting amplifiers 24.

[0127] The vertical scanning circuit 16 is connected to the address signal line 30 and the reset signal line 26. The vertical scanning circuit 16 selects a plurality of unit pixel cells 11 arranged in each row in units of rows by applying a predetermined voltage to the address signal line 30. Thus, the signal voltage of the selected unit pixel cell 11 is read out and the pixel electrode is reset as described later.

[0128] exist Figure 1In the example shown, the vertical scanning circuit 16 is also connected to the feedback control line 28 and the sensitivity adjustment line 32. As described later, by applying a predetermined voltage to the feedback control line 28 by the vertical scanning circuit 16, a feedback circuit that causes the output of the unit pixel unit 11 to be negatively fed back can be formed. In addition, the vertical scanning circuit 16 can supply a predetermined voltage to multiple unit pixel units 11 via the sensitivity adjustment line 32. As described in detail later, in the present invention, the unit pixel unit 11 has one or more capacitor elements in each pixel. In this specification, "capacitor" means a structure in which a dielectric such as an insulating film is sandwiched between electrodes. The "electrode" in this specification is not limited to an electrode formed of metal, but is interpreted as broadly including a polysilicon layer, etc. The "electrode" in this specification may also be a part of a semiconductor substrate.

[0129] The unit pixel cells 11 arranged in each column are electrically connected to the column signal processing circuit 20 via the vertical signal line 18 corresponding to each column. The load circuit 19 is electrically connected to the vertical signal line 18. The column signal processing circuit 20 performs noise suppression signal processing represented by correlated double sampling and analog-to-digital conversion (AD conversion). The plurality of column signal processing circuits 20 provided corresponding to the columns of the unit pixel cells 11 are electrically connected to the horizontal signal readout circuit 21. The horizontal signal readout circuit 21 sequentially reads out signals from the plurality of column signal processing circuits 20 to the horizontal common signal 123.

[0130] exist Figure 1 In the illustrated structure, a plurality of reverse amplifiers 24 are provided corresponding to each column. The negative input terminal of the reverse amplifier 24 is connected to the corresponding vertical signal line 18. A predetermined voltage (for example, a positive voltage of IV or near IV) Vref is supplied to the positive input terminal of the reverse amplifier 24. In addition, the output terminal of the reverse amplifier 24 is connected to a plurality of unit pixel units 11 connected to the negative input terminal of the reverse amplifier 24 via a feedback line 25 provided corresponding to each column. The reverse amplifier 24 constitutes a part of a feedback circuit for negatively feeding back the output from the unit pixel unit 11. The reverse amplifier 24 is also referred to as a feedback amplifier. The reverse amplifier 24 includes a gain adjustment terminal 24a for changing the reverse amplification gain. The operation of the reverse amplifier 24 will be described later.

[0131] Figure 2 express Figure 1 2 is an exemplary circuit structure of the unit pixel unit 11. The unit pixel unit 11 includes a photoelectric conversion unit 15 and a signal detection circuit SC.

[0132] The photoelectric conversion unit 15 typically has a structure in which a photoelectric conversion film 15b is sandwiched between a first electrode 15a and a second electrode (pixel electrode) 15c. As described later with reference to the accompanying drawings, the photoelectric conversion film 15b is stacked on a semiconductor substrate forming the unit pixel unit 11. The photoelectric conversion film 15b is formed of an organic material or an inorganic material such as amorphous silicon. The photoelectric conversion film 15b may also include a layer composed of an organic material and a layer composed of an inorganic material.

[0133] A first electrode 15a is provided on the light-receiving surface side of the photoelectric conversion film 15b. The first electrode 15a is formed of a transparent conductive material such as ITO. A second electrode 15c is provided on the side opposite to the first electrode 15a across the photoelectric conversion film 15b. The second electrode 15c collects the charge generated by photoelectric conversion in the photoelectric conversion film 15b. The second electrode 15c is formed of a metal such as aluminum or copper, a metal nitride, or polycrystalline silicon that is given conductivity by doping with impurities.

[0134] like Figure 2 As shown, the first electrode 15a is connected to the accumulation control line 17, and the second electrode 15c is connected to the charge accumulation node (also called "floating diffusion node") 44. By controlling the potential of the first electrode 15a via the accumulation control line 17, the second electrode 15c can be used to collect one of the holes and electrons in the hole-electron pairs generated by photoelectric conversion. In the case of using holes as signal charges, it is sufficient to make the potential of the first electrode 15a higher than that of the second electrode 15c. The following is an example of using holes as signal charges. For example, a voltage of about 10V is applied to the first electrode 15a via the accumulation control line 17. As a result, the signal charge is accumulated in the charge accumulation node 44. Of course, electrons can also be used as signal charges.

[0135] The signal detection circuit SC of the unit pixel unit 11 includes an amplifying transistor (first transistor) 34 and a first reset transistor (second transistor) 36. In addition, the unit pixel unit 11 includes a capacitor circuit 45 in which a first capacitor element (first capacitor) 41 and a second capacitor element (second capacitor) 42 are connected in series. Figure 2 In the structure shown in FIG. 1 , the second capacitor element 42 has a larger capacitance value than the first capacitor element 41. Figure 2 In the illustrated structure, one of the source and drain of the first reset transistor 36 and one electrode of the first capacitor 41 are connected to the charge storage node 44. That is, they are electrically connected to the second electrode 15c. The other of the source and drain of the first reset transistor 36 and the other electrode of the first capacitor 41 are connected to one electrode of the second capacitor 42. Hereinafter, the node including the connection point between the first capacitor 41 and the second capacitor 42 may be referred to as the reset drain node 46.

[0136] The electrodes of the second capacitor 42 that are not connected to the reset drain node 46 are connected to the sensitivity adjustment line 32. The potential of the sensitivity adjustment line 32 is set to, for example, 0 V (reference potential). The potential of the sensitivity adjustment line 32 does not need to be fixed when the imaging device 101 is in operation. For example, a pulse voltage may be supplied from the vertical scanning circuit 16. As described later, the sensitivity adjustment line 32 can be used to control the potential of the charge storage node 44. Of course, the potential of the sensitivity adjustment line 32 may also be fixed when the imaging device 101 is in operation.

[0137] like Figure 2 As shown in FIG. 1 , the gate of the amplifier transistor 34 is connected to the charge storage node 44. In other words, the gate of the amplifier transistor 34 is electrically connected to the second electrode 15c. One of the source and drain of the amplifier transistor 34 (the drain in the case of an N-channel MOS) is connected to the power supply wiring (source follower power supply) 22, and the other is connected to the vertical signal line 18. The amplifier transistor 34 and the load circuit 19 (in Figure 2 Not shown in the figure, refer to Figure 1 ) forms a source follower circuit. The amplifier transistor 34 amplifies the signal generated by the photoelectric conversion unit 15.

[0138] like Figure 2 As shown, the unit pixel unit 11 includes an address transistor (third transistor) 40. The source or drain of the address transistor 40 is connected to the source and drain of the amplifier transistor 34 that are not connected to the power supply wiring 22. The gate of the address transistor 40 is connected to the address signal line 30. Figure 2 In the illustrated structure, the address transistor 40 constitutes a part of the signal detection circuit SC.

[0139] A voltage corresponding to the amount of signal charge accumulated in the charge accumulation node 44 is applied to the gate of the amplifier transistor 34. The amplifier transistor 34 amplifies the voltage. The voltage amplified by the amplifier transistor 34 is selectively read out by the address transistor 40 as a signal voltage.

[0140] exist Figure 2 In the illustrated structure, the unit pixel unit 11 further includes a second reset transistor (fourth transistor) 38 having one of a source and a drain connected to the reset drain node 46 and the other connected to the feedback line 25. Figure 2 In the structure shown, one of the source and drain of the first reset transistor 36, which is connected to the reset drain node 46, is connected to the feedback line 25 via the second reset transistor 38. The gate of the second reset transistor 38 is connected to the feedback control line 28. By controlling the voltage of the feedback control line 28 as described in detail later, a feedback circuit FC that negatively feeds back the output of the signal detection circuit SC can be formed.

[0141] In addition, the amplifier transistor 34, the first reset transistor 36, the address transistor 40, and the second reset transistor 38 may be either an N-channel MOS or a P-channel MOS. It is not necessary for all of them to be either an N-channel MOS or a P-channel MOS. Hereinafter, the amplifier transistor 34, the first reset transistor 36, the address transistor 40, and the second reset transistor 38 are exemplified as N-channel MOS. As transistors, bipolar transistors may be used in addition to field effect transistors (FETs).

[0142] (Overview of Operation of Image Capture Device 101)

[0143] Next, an example of the operation of the imaging device 101 will be described with reference to the drawings. Figure 2 The illustrated configuration can switch between two operation modes with different sensitivities by appropriately controlling the gate voltages of the first reset transistor 36 and the second reset transistor 38. The two operation modes described here are a first mode capable of imaging with relatively high sensitivity and a second mode capable of imaging with relatively low sensitivity.

[0144] First, the operation of the camera device 101 in the first mode is briefly described. The first mode is a mode suitable for shooting under low illumination. Under low illumination, higher sensitivity is beneficial. However, if the sensitivity is relatively high, noise may also be amplified. According to an embodiment of the present invention, a relatively high sensitivity can be achieved, and the influence of kTC noise can be reduced and / or eliminated.

[0145] Figure 3 1 is a timing chart for explaining an example of the operation of the transistor in the first mode. Figure 3 In FIG. 1 , ADD, RST1, RST2, and GCNT schematically represent an example of changes in the gate voltage of the address transistor 40, the gate voltage of the first reset transistor 36, the gate voltage of the second reset transistor 38, and the voltage applied to the gain adjustment terminal 24a of the reverse amplifier 24, respectively. Figure 3 In the example shown, at time t0, the address transistor 40, the first reset transistor 36, and the second reset transistor 38 are all OFF. In addition, the voltage of the gain adjustment terminal 24a of the inverting amplifier 24 is a predetermined value. For simplicity, the description of the operation of the electronic shutter is omitted below.

[0146] First, the potential of the address signal line 30 is controlled to turn on the address transistor 40 (time t1). At this time, the signal charge accumulated in the charge accumulation node 44 is read out.

[0147] Next, by controlling the potential of the reset signal line 26 and the feedback control line 28, the first reset transistor 36 and the second reset transistor 38 are turned on (time t2). As a result, the charge storage node 44 and the feedback line 25 are connected via the first reset transistor 36 and the second reset transistor 38, forming a feedback circuit FC that negatively feeds back the output of the signal detection circuit SC. The formation of the feedback circuit FC is performed on one of the plurality of unit pixel cells 11 that share the feedback line 25. By controlling the gate voltage of the address transistor 40, the unit pixel cell 11 that is the object of the formation of the feedback circuit FC can be selected.

[0148] Here, the feedback circuit FC is a negative feedback amplifier circuit including the amplifier transistor 34, the inverting amplifier 24, and the second reset transistor 38. The address transistor 40 turned on at time t1 supplies the output of the amplifier transistor 34 as an input to the feedback circuit FC.

[0149] The charge storage node 44 is reset by electrically connecting the charge storage node 44 to the feedback line 25. At this time, the output of the signal detection circuit SC is negatively fed back, so that the voltage of the vertical signal line 18 converges to the voltage Vref applied to the positive input terminal of the inverting amplifier 24. That is, in this example, the reference voltage in the reset is the voltage Vref. Figure 2 In the illustrated configuration, the voltage Vref can be set arbitrarily within the range of the power supply voltage (eg, 3.3 V) and ground (0 V). In other words, any voltage (eg, a voltage other than the power supply voltage) can be used as the reference voltage for resetting as long as it is within a certain range.

[0150] Furthermore, at time t2, the potential of the gain adjustment terminal 24a of the inverting amplifier 24 is controlled to reduce the gain of the inverting amplifier 24. In the inverting amplifier 24, since the product G×B of the gain G and the bandwidth B is constant, if the gain G is reduced, the bandwidth B becomes wider (the cutoff frequency becomes higher). Therefore, the above-mentioned convergence in the negative feedback amplifier circuit can be accelerated.

[0151] Next, the first reset transistor 36 is turned off (time t3). Hereinafter, there is a period from when the first reset transistor 36 and the second reset transistor 38 are turned on at time t2 to when the first reset transistor 36 is turned off ( Figure 3 The period from time t2 to time t3 in the above example is called the "reset period". Figure 3 In FIG. 1 , the reset period is schematically indicated by an arrow Rst. By turning OFF the first reset transistor 36 at time t3, kTC noise is generated. Therefore, kTC noise is added to the voltage of the charge storage node 44 after reset.

[0152] Reference Figure 2It can be seen that the feedback circuit FC is continuously formed while the second reset transistor 38 is ON. Therefore, if the gain of the feedback circuit FC is A, the kTC noise generated by turning off the first reset transistor 36 at time t3 is eliminated to a magnitude of 1 / (1+A).

[0153] In this example, the voltage of the vertical signal line 18 immediately before the first reset transistor 36 is turned off (immediately before the noise elimination starts) is substantially equal to the voltage Vref applied to the negative input terminal of the inverting amplifier 24. In this way, by making the voltage of the vertical signal line 18 at the start of noise elimination close to the target voltage Vref after the noise elimination, the kTC noise can be eliminated in a relatively short time. The following is the period from when the first reset transistor 36 is turned off to when the second reset transistor 38 is turned off ( Figure 3 The period from time t3 to time t4 in the figure is called the "noise elimination period". Figure 3 In FIG. 1 , the noise elimination period is schematically indicated by an arrow Nc1.

[0154] Furthermore, at time t3, the gain of the inverting amplifier 24 is in a reduced state. Therefore, noise can be eliminated at a high speed in the early stage of the noise elimination period.

[0155] Next, at time t3', the potential of the gain adjustment terminal 24a of the reverse amplifier 24 is controlled to increase the gain of the reverse amplifier 24. As a result, the noise level is further reduced. At this time, since the product G×B of the gain G and the bandwidth B is constant, the bandwidth B becomes narrower (the cut-off frequency becomes lower) by increasing the gain G. In other words, time is required for the convergence of the negative feedback amplifier circuit. However, since the voltage of the vertical signal line 18 has been controlled near the convergence level during the period t3 to t3', the width of the voltage to be converged becomes smaller, which can suppress the increase in convergence time caused by the narrowing of the bandwidth.

[0156] As described above, according to the embodiment of the present invention, the kTC noise generated by turning off the reset transistor can be reduced, and the generated kTC noise can be eliminated in a relatively short time.

[0157] Next, the second reset transistor 38 is turned off (time t4), and exposure is performed during a predetermined period. By turning off the second reset transistor 38 at time t4, kTC noise is generated. The magnitude of the kTC noise added to the voltage of the charge storage node 44 at this time is (Cfd / C2) when the first capacitor 41 and the second capacitor 42 are not provided in the unit pixel unit 11 and the second reset transistor 38 is directly connected to the charge storage node 44. 1 / 2×(C1 / (C1+Cfd)) times. In the above formula, Cfd, Cl and C2 represent the capacitance value of the charge storage node 44, the capacitance value of the first capacitor 41 and the capacitance value of the second capacitor 42, respectively. In addition, the "×" in the formula represents multiplication. In this way, the larger the capacitance value C2 of the second capacitor 42, the smaller the noise itself generated, and the smaller the capacitance value C1 of the first capacitor 41, the greater the attenuation rate. Therefore, according to an embodiment of the present invention, by appropriately setting the capacitance value C1 of the first capacitor 41 and the capacitance value C2 of the second capacitor 42, the kTC noise generated by turning OFF the second reset transistor 38 can be fully reduced.

[0158] exist Figure 3 In the figure, the exposure period is schematically indicated by the arrow Exp. During the exposure period, the reset voltage from which the kTC noise is eliminated is read at a predetermined timing (time t5). In addition, since the time required for reading the reset voltage is short, the reset voltage can also be read while the address transistor 40 is continuously in the ON state.

[0159] By taking the difference between the signal read out between time t1 and time t2 and the signal read out at time t5, a signal from which the fixed noise has been removed is obtained. In this way, a signal from which the kTC noise and the fixed noise have been removed is obtained.

[0160] In addition, when the first reset transistor 36 and the second reset transistor 38 are turned off, the second capacitor 42 is connected to the charge accumulation node 44 via the first capacitor 41. Here, it is assumed that the charge accumulation node 44 is directly connected to the second capacitor 42 without the first capacitor 41. In this case, the capacitance value of the overall accumulation area of ​​the signal charge when the second capacitor 42 is directly connected is (Cfd+C2). That is, if the second capacitor 42 has a relatively large capacitance value C2, the capacitance value of the overall accumulation area of ​​the signal charge also becomes a relatively large value, so a higher conversion gain (also a higher SN ratio) cannot be obtained. Therefore, in an embodiment of the present invention, the second capacitor 42 is connected to the charge accumulation node 44 via the first capacitor 41. The capacitance value of the overall accumulation area of ​​the signal charge in such a structure is expressed as (Cfd+(C1C2) / (C1+C2)). Here, when the first capacitor 41 has a relatively small capacitance value C1 and the second capacitor 42 has a relatively large capacitance value C2, the capacitance value of the entire signal charge storage area is approximately (Cfd+Cl). That is, the increase in the capacitance value of the entire signal charge storage area is small. In this way, by connecting the second capacitor 42 to the charge storage node 44 via the first capacitor 41 having a relatively small capacitance value, the decrease in conversion gain can be suppressed.

[0161] In this case as well, it is possible to obtain the effect of canceling the kTC noise generated by turning OFF the first reset transistor 36 and the effect of reducing the kTC noise generated by turning OFF the second reset transistor 38 .

[0162] Next, refer to Figure 4 The operation of the camera device 101 in the second mode in which the camera can perform video recording at a relatively low sensitivity is briefly described. The second mode is a mode suitable for video recording under high illumination. Under high illumination, a low sensitivity is advantageous. Under a relatively low sensitivity, the influence of noise is small, but on the other hand, the capacitance of the entire storage area of ​​the signal charge is required to be large.

[0163] Figure 4 2 is a timing chart for explaining an example of the operation of the transistor in the second mode. Figure 3 In the first mode described above, the charge storage node 44 is reset using the first reset transistor 36. In contrast, in the second mode, the charge storage node 44 is reset using the second reset transistor 38 while the first reset transistor 36 is turned on as described below.

[0164] like Figure 4 As shown, in the second mode, the first reset transistor 36 is always turned on. Also, at time t1, the address transistor 40 is turned on as in the first mode. At this time, the signal charge accumulated in the charge accumulation node 44 is read out. The gain adjustment terminal 24a of the inverting amplifier 24 is a certain predetermined value.

[0165] Next, the second reset transistor 38 is turned on (time t2). Thus, a feedback circuit FC is formed for negatively feeding back the output of the signal detection circuit SC, and the charge storage node 44 is reset. At this time, the reference voltage for resetting is the voltage Vref applied to the positive input terminal of the inverting amplifier 24.

[0166] Furthermore, at time t2, the potential of the gain adjustment terminal 24a of the inverting amplifier 24 is controlled to reduce the gain of the inverting amplifier 24. In the inverting amplifier 24, since the product G×B of the gain G and the bandwidth B is constant, if the gain G is reduced, the bandwidth B becomes wider (the cutoff frequency becomes higher). Therefore, the above-mentioned convergence in the negative feedback amplifier circuit can be accelerated.

[0167] Next, the second reset transistor 38 is turned OFF (time t4). By turning OFF the second reset transistor 38, kTC noise is generated. In this example, at time t4, the gain of the reverse amplifier 24 is reduced. Therefore, the convergence in the negative feedback amplifier circuit can be performed at a high speed. At time t2, the gain of the reverse amplifier 24 can also be increased by controlling the potential of the gain adjustment terminal 24a of the reverse amplifier 24. In this case, the convergence of the negative feedback amplifier circuit takes time, but the bandwidth B can be narrowed (the cut-off frequency can be lowered). The potential of the gain adjustment terminal 24a (it can also be said to be the gain of the reverse amplifier 24) can be appropriately set as long as the time that can be allowed in the reduction of noise is considered.

[0168] Then, exposure is performed during a predetermined period, and the reset voltage is read at a predetermined timing during the exposure period (time t5).

[0169] In the second mode, there is no noise elimination period. However, in the second mode used for imaging under high illumination, scattered noise is dominant and the influence of kTC noise is small. By taking the difference between the signal read out between time t1 and time t2 and the signal read out at time t5, a signal with fixed noise removed can be obtained.

[0170] According to the above description, Figure 2 In the illustrated structure, the first reset transistor 36 has both the function of a reset transistor for resetting the charge accumulation node 44 and the function of a switch for switching the first mode and the second mode. In this way, by switching the first reset transistor 36 ON and OFF, it is possible to switch whether the second capacitor 42 is connected to the charge accumulation node 44 via the first reset transistor 36 or the second capacitor 42 is connected to the charge accumulation node 44 via the first capacitor 41. In addition, the second capacitor 42 has both the function of reducing the kTC noise in the first mode and the function of increasing the capacitance of the entire storage area of ​​the signal charge. According to an embodiment of the present invention, the increase in the number of elements in the pixel can be suppressed, and the dynamic range can be expanded with a simple structure. This is particularly beneficial in the miniaturization of pixels.

[0171] (Device Structure of Unit Pixel Unit 11 and Method of Manufacturing Image Capture Device 101)

[0172] Next, refer to Figure 5 and Figure 6 An example of the device structure of the unit pixel unit 11 will be described.

[0173] Figure 5 An example of the layout of each element in the unit pixel unit 11 is schematically shown. Figure 6 To indicate Figure 5As already described, the unit pixel unit 11 is arranged on the semiconductor substrate. Here, the semiconductor substrate 2 (see Figure 6 ) is an example of using a P-type silicon (Si) substrate.

[0174] exist Figure 5 In the illustrated structure, four transistors, namely, an amplifier transistor 34, a first reset transistor 36, a second reset transistor 38, and an address transistor 40, are arranged in the unit pixel cell 11. The unit pixel cell 11 is isolated by the element isolation regions 2S formed in the semiconductor substrate 2, respectively.

[0175] Here, the amplifier transistor 34 and the first reset transistor 36 are both formed on the semiconductor substrate 2. In addition, in the example described here, the second reset transistor 38 and the address transistor 40 are also formed on the semiconductor substrate 2. For example, if we focus on the second reset transistor 38, the second reset transistor 38 includes an impurity region (here, an N-type region) 2d formed in the semiconductor substrate 2. These impurity regions 2d function as the source or drain of the second reset transistor 38, respectively. The impurity region 2d is typically a diffusion layer formed in the semiconductor substrate 2. In the following, there is a case where the impurity region 2d in the semiconductor substrate 2 is referred to as a "source / drain diffusion layer 2d". In Figure 5 In the illustrated structure, one of the two source / drain diffusion layers 2d constituting the source and drain of the second reset transistor 38 is connected to the feedback line 25 (at Figure 5 Not shown in the figure, refer to Figure 2 ).

[0176] A first capacitor 41 and a second capacitor 42 are also formed on the semiconductor substrate 2. Figure 5 In the illustrated structure, the second capacitor element 42 occupies a relatively large area in the unit pixel unit 11. Thus, a relatively large capacitance value is achieved. Figure 5 As shown in FIG. 1 , when viewed from the normal direction of the semiconductor substrate, the first capacitor element 41 is formed at a position overlapping with the second capacitor element 42. As described in detail later, the upper electrode 41w of the first capacitor element 41 is a part of the wiring (conductive layer) that electrically connects the source or drain (source / drain diffusion layer 2d) of the first reset transistor 36 and the gate electrode 34e of the amplifier transistor 34.

[0177] Reference Figure 6 .like Figure 6 As shown in FIG. 1 , the unit pixel unit 11 has a photoelectric conversion unit 15 on a semiconductor substrate 2. 6 PlaceIn the example shown, interlayer insulating layers 4s, 4a, 4b, and 4c are stacked on the semiconductor substrate 2, and a photoelectric conversion film 15b of the photoelectric conversion unit 15 is stacked on them. In the photoelectric conversion film 15b, a first electrode 15a is provided on a light receiving surface 15h on the side where light from the subject is incident. A second electrode 15c is arranged on the surface on the opposite side of the light receiving surface 15h. The second electrode 15c is electrically separated between the plurality of unit pixel units 11.

[0178] exist Figure 6 In the illustrated structure, the semiconductor substrate 2 has a well 2w (here, a P-type impurity region) with a relatively high acceptor concentration and a source / drain diffusion layer 2d (here, an N-type impurity region). 6 As shown in FIG. 1 , the second reset transistor 38 includes two source / drain diffusion layers 2d, a gate insulating film 38g formed on the semiconductor substrate 2, and a gate electrode 38e formed on the gate insulating film 38g. A channel region 38c is formed between the two source / drain diffusion layers 2d serving as the source or drain. Similarly, the first reset transistor 36 includes two source / drain diffusion layers 2d, a gate insulating film 36g formed on the semiconductor substrate 2, and a gate electrode 36e formed on the gate insulating film 36g. A channel region 36c is formed between the two source / drain diffusion layers 2d serving as the source or drain. In FIG. 6 In the example shown, the first reset transistor 36 and the second reset transistor 38 share one of the source / drain diffusion layers 2d. In addition, the amplifier transistor 34 also includes two source / drain diffusion layers 2d, a gate insulating film 34g formed on the semiconductor substrate 2, and a gate electrode 34e formed on the gate insulating film 34g. Figure 6 In FIG. 1 , the two source / drain diffusion layers 2d of the amplifier transistor 34 are not shown, and the gate insulating film 34g, the gate electrode 34e, and the channel region 34c formed between the two source / drain diffusion layers 2d are shown. Figure 5 ) can also have a structure roughly the same as that of the amplifier transistor 34.

[0179] The semiconductor substrate 2 has an element isolation region 2S for electrically isolating the elements. In this example, the group of the first reset transistor 36 and the second reset transistor 38 is isolated from the group of the amplifier transistor 34 and the address transistor 40 by the element isolation region 2S (see Figure 5 ).

[0180] The semiconductor substrate 2 has an electrode region 42 c which is electrically isolated from four transistors (the amplification transistor 34 , the first reset transistor 36 , the second reset transistor 38 , and the address transistor 40 ) of the unit pixel unit 11 by being surrounded by the element isolation region 2S.

[0181] exist Figure 6 In the illustrated structure, the second capacitor 42 includes a dielectric layer (first dielectric layer) 42g provided on the electrode region 42c, and an upper electrode 42e opposed to a portion of the semiconductor substrate 2 via the dielectric layer 42g. The upper electrode 42e is electrically connected to the source and drain of the first reset transistor 36, which side is not connected to the charge storage node 44.

[0182] In the embodiment described here, the second capacitor 42 is a so-called MIS (Metal Insulator Semiconductor) capacitor. However, as described later, the upper electrode 42e of the second capacitor 42 is not an electrode formed of metal, but an electrode formed of polysilicon. The portion of the semiconductor substrate 2 that is opposite to the upper electrode 42e functions as one of the electrodes of the second capacitor 42.

[0183] The electrode region 42c and the sensitivity adjustment line 32 (see Figure 2 ) is electrically connected. A predetermined voltage is applied to the electrode region 42c from a voltage source (here, the vertical scanning circuit 16) via the sensitivity adjustment line 32. By controlling the potential of the electrode region 42c, the potential of the charge storage node 44 can be controlled. In other words, by adjusting the voltage supplied to the electrode region 42c via the sensitivity adjustment line 32, the sensitivity of the imaging device 101 can be adjusted.

[0184] In addition, when viewed from the normal direction of the semiconductor substrate 2, the shape and area of ​​the dielectric layer 42g do not need to be consistent with the shape and area of ​​the electrode region 42c. The dielectric layer 42g does not need to cover the entire electrode region 42c. The dielectric layer 42g may also be formed on the element isolation region 2s surrounding the electrode region 42c. For example, the electrode region 42c may be formed as a region having a higher impurity concentration than the portion of the well 2w by ion implantation. Alternatively, the electrode region 42c may be formed as a region of a conductivity type different from that of the well 2w.

[0185] like Figure 6 As shown in FIG. 1 , the upper electrode 41 w electrically connects the source or drain (source / drain diffusion layer 2 d ) of the first reset transistor 36 to the gate electrode 34 e of the amplifier transistor 34 . Figure 6In the illustrated structure, the upper electrode 41w is electrically connected to the second electrode 15c via the contact plug cpa, the wiring layer 6s, the through hole va, the wiring layer 6a, the through hole vb, the wiring layer 6b and the through hole vc. Typically, the contact plug cpa, the wiring layers 6s, 6a and 6b and the through holes va to vc are formed of metal such as copper. The polysilicon plug sp2, the upper electrode 41w, the contact plug cpa, the wiring layers 6s, 6a and 6b, the through holes va to vc, and one of the source and drain of the first reset transistor 36 (here, the drain) function as a charge storage region.

[0186] As shown 6 As shown, the upper electrode 41w extends onto the upper electrode 42e of the second capacitor 42. The first capacitor 41 is formed by the upper electrode 41w, the upper electrode 42e, and the insulating film (second dielectric layer) 41g sandwiched therebetween. In other words, the first capacitor 41 includes the upper electrode 42e of the second capacitor 42, the dielectric layer 41g formed on the upper electrode 42e, and the upper electrode 41w connected to the second electrode 15c of the photoelectric conversion part 15. When viewed from the normal direction of the semiconductor substrate 2, at least a portion of the upper electrode 41w of the first capacitor 41 overlaps with the upper electrode 42e via the dielectric layer 41g.

[0187] In this example, the first capacitor 41 and the second capacitor 42 share one of the two electrodes used to form the capacitor. In addition, the dielectric layer 41g may be a part of the interlayer insulating layer 4s. Thus, the dielectric layer 41g may be a part of the interlayer insulating layer formed on the semiconductor substrate 2, or may be a separate insulating film (or insulating layer) different from the interlayer insulating layer.

[0188] Here, the upper electrode 41w of the first capacitor element 41 is formed by polysilicon, as is the upper electrode 42e of the second capacitor element 42. The CV curve of the capacitor element having a structure in which a dielectric is sandwiched between two electrodes formed by polysilicon has a flat portion in a relatively large voltage range. As the voltage of the charge accumulation node 44 changes corresponding to the amount of light, the voltage between the electrodes of the first capacitor element 41 shows a relatively large change. If the two electrodes constituting the first capacitor element 41 are formed by polysilicon, the increase of the element size can be suppressed, and a high-precision capacitor element with a flat CV characteristic can be realized, so it is useful. In addition, as described later, the advantage of suppressing the increase of the number of processes in the manufacturing process of the camera device can also be obtained.

[0189] Here, refer to Figure 7 and Figure 8 Another example of the device structure of the first embodiment will be described.

[0190] Figure 7Another example of the layout of each element in the unit pixel unit 11 is schematically shown. Figure 8 To indicate Figure 7 The BB' line cross section is shown. Figure 7 and Figure 8 Illustrated Structure and References Figure 5 and Figure 6 The difference in the structure of the description is Figure 7 and Figure 8 The unit pixel unit 11 shown further includes a third capacitor 43 .

[0191] like Figure 7 and Figure 8 As shown in FIG. 1 , the third capacitor element 43 includes an upper electrode 43e disposed on the upper electrode 42e of the second capacitor element 42. Figure 7 and Figure 8 In the illustrated structure, the upper electrode 43e is electrically connected to the electrode region 42c of the semiconductor substrate 2 constituting a part of the second capacitor element 42 via the contact plug cp3. As described later, the upper electrode 43e of the third capacitor element 43 is opposite to the upper electrode 42e of the second capacitor element 42 via the dielectric layer 43g. That is, the third capacitor element 43 and the second capacitor element 42 share one of the two electrodes used to form the capacitor element, and are connected in parallel in an electrically connected manner. Therefore, the capacitance value of the capacitor element connected between the reset drain node 46 and the sensitivity adjustment line 32 can be increased (refer to Figure 2 ). Thus, the kTC noise can be reduced more effectively.

[0192] (Manufacturing Method of Imaging Device 101)

[0193] Next, refer to Figures 9 to 12 An example of a method for manufacturing the imaging device 101 will be described. Figures 9 to 11 is with Figure 5 The figure corresponds to the AA' line cross-sectional view shown. Fig.12 is with Figure 7 The figure corresponds to the BB' line cross-sectional view shown.

[0194] First, a semiconductor substrate 2 is prepared. Here, a P-type silicon substrate is used. Next, a patterned resist mask is formed on the semiconductor substrate 2 using photolithography. Then, acceptors (for example, boron (B)) are ion-implanted under predetermined implantation conditions to form a well 2w.

[0195] Next, a photolithography method is used to form a resist mask (resist pattern) for forming the channel region of the transistor to be configured in the unit pixel unit 11. Here, four transistors, namely, the amplifier transistor 34, the first reset transistor 36, the second reset transistor 38, and the address transistor 40, are formed in the unit pixel unit 11. The resist mask is formed to cover the portion other than the portion that will become the channel region of each transistor. Then, the channel region of each transistor is formed by ion implanting an acceptor or a dopant under specified implantation conditions. Fig. 9 , a channel region 34c of the amplifier transistor 34, a channel region 36c of the first reset transistor 36, and a channel region 38c of the second reset transistor 38 are shown. By using ion implantation, a desired threshold voltage can be realized in each transistor.

[0196] Here, a resist mask having an opening in a predetermined region of the semiconductor substrate 2 is used to ion-implant a dopant (eg, arsenic (As)) into the predetermined region of the semiconductor substrate 2. That is, in this example, the electrode region 42c is formed by ion-implanting the predetermined region of the semiconductor substrate 2.

[0197] Next, gate oxidation is performed, for example, by ISSG (In Situ Steam Generation), to form a gate oxide film on the main surface of the semiconductor substrate 2. Typically, the gate oxide is silicon dioxide (SiO2). Next, a material for forming a gate electrode is deposited on the gate oxide by chemical vapor deposition (CVD). Here, a polysilicon film is formed on the gate oxide.

[0198] Next, a resist mask is formed on the polysilicon film by photolithography, and a gate insulating film (gate insulating films 34g, 36g, 38g) and a gate electrode (gate electrodes 34e, 36e, 36e) are formed from the gate oxide film and the polysilicon film, respectively, by performing dry etching. At this time, patterning is also performed on a region of the semiconductor substrate 2 that is different from the region where the gate insulating film and the gate electrodes of the four transistors are formed to form a stack of gate oxide films and polysilicon films. Thus, a structure in which the first dielectric layer 42g and the upper electrode 42e are sequentially stacked on a portion of the semiconductor substrate 2 can be formed. That is, the second capacitor element 42 (see FIG. 4 ) as a MIS capacitor can be formed in parallel with the formation of the gate insulating film and the gate electrodes of the four transistors. Fig. 9 ) Thus, according to the embodiment of the present invention, the second capacitor 42 can be formed in the unit pixel unit 11 without adding a process.

[0199] Next, a resist mask is formed by photolithography to partially cover the source region and drain region of each transistor. Then, the element separation region 2s is formed by performing acceptor ion implantation under specified implantation conditions. At this time, the acceptor used to form the element separation region 2S is not directly implanted under the gate electrode (gate electrodes 34e, 36e, 36e) of each transistor and the upper electrode 42e of the second capacitor element 42. Here, the element separation region 2S is formed to surround the group of the first reset transistor 36 and the second reset transistor 38, the group of the amplifier transistor 34 and the address transistor 40, and the second capacitor element 42 (refer to Figure 5 ). After the element isolation region 2s is formed, the resist mask is removed.

[0200] Next, a resist mask having openings in the portions to be the source and drain regions of each transistor is formed by photolithography. Then, a source / drain diffusion layer 2d is formed by ion implantation of a dopant under predetermined implantation conditions (see FIG. Fig. 9 ) At this time, the gate electrode of the transistor in the unit pixel unit 11 and / or the upper electrode 42e of the second capacitor 42 may be subjected to ion implantation of the dopant by applying so-called gate implantation.

[0201] Next, an insulating film is formed by CVD to cover the polysilicon layer constituting the gate electrodes of the transistors and the upper electrode 42e of the second capacitor 42, and the semiconductor substrate 2. Typically, the insulating film formed at this time is a silicon dioxide film.

[0202] Next, a resist mask for forming contact holes is formed on the insulating film covering the polysilicon layer and the semiconductor substrate 2 by photolithography. Then, contact holes chg and contact holes chs are formed on the gate electrodes of each transistor and the source / drain diffusion layer 2d, respectively, by dry etching, thereby forming an insulating layer 48 (see Fig.10 ). In addition, a contact hole is also formed on the upper electrode 42e of the second capacitor 42. The contact hole on the upper electrode 42e is provided to electrically connect the upper electrode 42e to the reset drain node 46 (refer to Figure 5 ).

[0203] Next, by performing ion implantation of dopants through the contact holes chs and chg formed in the insulating layer 48, a region having a relatively high impurity concentration is formed on the gate electrode and the source / drain diffusion layer 2d of each transistor (at Fig.10 (not shown in the figure). Then, the implanted impurities are activated by annealing, thereby reducing the resistance of the region having a relatively high impurity concentration.

[0204] Next, a polysilicon film containing a high concentration of N-type impurities is deposited on the insulating layer 48 by CVD or the like. At this time, polysilicon is also deposited inside the contact holes (contact holes chs, chg) provided in the insulating layer 48.

[0205] Next, a resist mask is formed by photolithography. After the resist mask is formed, a polysilicon layer is formed on the insulating layer 48 by dry etching, and polysilicon plugs (polysilicon plugs spl, sp2) connecting the polysilicon layer on the insulating layer 48 to the source / drain diffusion layer 2d and polysilicon plugs (polysilicon plugs sp3) connecting the polysilicon layer on the insulating layer 48 to the gate electrodes (gate electrodes 34e, 36e, 38e) of each transistor are formed. In addition, as a connection with the charge storage node 44 (for example, see Figure 5 ) is connected to the source / drain diffusion layer 2d of a part of the semiconductor layer 2. By using a plug formed of polysilicon, the influence of crystal defects caused by the metal / semiconductor interface when a metal plug is used can be avoided, so the advantage of suppressing dark current can be obtained. Then, the surface of the polysilicon layer on the insulating layer 48 is silicided to reduce resistance, forming a polysilicon layer s1 as a conductive layer (see Fig.11 ).

[0206] At this time, a conductive portion (polysilicon wiring) connecting the source or drain of the first reset transistor 36 to the gate electrode 34e of the amplifier transistor 34 is formed by patterning of polysilicon. The patterning is performed in a manner that at least a portion of the conductive portion overlaps with the upper electrode 42e of the second capacitor 42 via the insulating layer 48. Thus, a first capacitor 41 having a structure in which an insulating film is sandwiched between two polysilicon layers can be formed. According to the above structure, the upper electrode 41w of the first capacitor 41 can be a part of the polysilicon layer s1. In addition, the second dielectric layer 41g of the first capacitor 41 can be a part of the insulating layer 48. According to the first embodiment of the present invention, the first capacitor 41 can be formed in the unit pixel unit 11 without adding a process.

[0207] In addition, if Fig.12As shown, the patterning of polysilicon can also be performed in a manner that a conductive portion different from the upper electrode 41w is formed at a position overlapping with the upper electrode 42e of the second capacitor element 42. By electrically connecting the conductive portion to the electrode region 42c of the semiconductor substrate 2, the conductive portion can function as the upper electrode 43e of the third capacitor element 43. The dielectric layer 43g of the third capacitor element 43 can be a part of the insulating layer 48, similar to the second dielectric layer 41g of the first capacitor element 41. In this way, according to an embodiment of the present invention, a third capacitor element 43 that exhibits a flat CV characteristic in a relatively large voltage range can be formed in the unit pixel unit 11 without adding a dedicated process. In addition, the expansion of the pixel size can be suppressed, and the combined capacitance of the second capacitor element 42 and the third capacitor element 43 can be increased.

[0208] After the formation of the polysilicon layer s1, the interlayer insulating layer 4s, the contact plug cpa for connecting the wiring layer 6s and the upper electrode 41w, the wiring layer 6s, the interlayer insulating layer 4a, the through hole va, the wiring layer 6a, the interlayer insulating layer 4b, the through hole vb, the wiring layer 6b, the interlayer insulating layer 4c and the through hole vc are formed in sequence. In addition, the number of interlayer insulating layers can be set arbitrarily and does not need to be 4 layers. By forming the photoelectric conversion part 15 on the interlayer insulating layer 4c, it is possible to obtain Figure 6 or Figure 8 The unit pixel unit 11 is shown.

[0209] As described above, the imaging device 101 can be manufactured using a well-known semiconductor manufacturing technology. The imaging device 101 obtained in this way and the optical system that forms the image of the subject on the light receiving surface 15h of the photoelectric conversion film 15b can constitute a camera system. A protective film, a color filter, a lens (microlens), etc. can also be formed on the first electrode 15a of the photoelectric conversion unit 15.

[0210] (Variation of the first embodiment)

[0211] Reference Fig.13 A modification of the imaging device according to the first embodiment of the present invention will be described.

[0212] Fig.13 An exemplary circuit configuration of the unit pixel unit 12 of the imaging device according to the first embodiment is schematically shown. Fig.13 The illustrated structure and Figure 2 The illustrated structure is different in that the source and drain of the first reset transistor 36 , whichever is not connected to the second electrode 15 c (charge storage node 44 ), is connected to the feedback line 25 instead of the reset drain node 46 .

[0213] exist Fig.13 In the illustrated structure, no reference is made Figure 3 and Figure 4 However, since the side of the source and drain of the first reset transistor 36 that is not connected to the charge storage node 44 is directly connected to the feedback line 25, the advantage of improving the degree of freedom in designing the impurity distribution for ensuring the driving force of the first reset transistor 36 can be obtained. In addition, Fig.13 The operation timing of each transistor in the illustrated structure is the same as that in the above-mentioned first mode.

[0214] In reference Figure 2 In the structure shown in the figure, one of the electrodes of the first capacitor element 41 is directly connected to one of the source and drain of the first reset transistor 36, and the other of the electrodes of the first capacitor element 41 is directly connected to the other of the source and drain of the first reset transistor 36. Fig.13 As shown in FIG. 1 , the first reset transistor 36 does not necessarily have to be connected in parallel with the first capacitor 41 .

[0215] Fig.13 The layout and device structure of each element in the unit pixel unit 12 shown in FIG. Figure 5 and Figure 7 Layout and reference of instructions Figure 6 and Figure 8 The device structures described are substantially the same, so description thereof will be omitted. Fig.13 The manufacturing method of the unit pixel unit 12 shown in FIG. Figures 9 to 12 The manufacturing method described is the same.

[0216] (Second embodiment)

[0217] Fig.14 FIG. 2 schematically shows an exemplary circuit structure of the unit pixel unit 13 of the imaging device according to the second embodiment. Fig.14 As shown in the example, the imaging device of the second embodiment replaces the inverting amplifier 24 (see Figure 2 and Fig.13 ) is provided with a switching circuit 50. Therefore, in the plurality of unit pixel cells 13 constituting each column of the imaging device according to the second embodiment, the feedback line 25 does not connect the unit pixel cells 13 to each other.

[0218] In each unit pixel unit 13, the feedback line 25 is connected to the side of the source or drain of the second reset transistor 38 that is not connected to the reset drain node 46. The address transistor 40 is provided between one of the source or drain of the amplifier transistor 34 and the feedback line 25. The source or drain of the address transistor 40 connected to the feedback line 25 is connected to the vertical signal line 18. The following mainly describes the differences from the imaging device 101 of the first embodiment.

[0219] The switching circuit 50 includes switch elements 51, 51' connected in parallel with the power supply wiring 22, and switch elements 52', 52 connected in parallel with the vertical signal line 18. The switch elements 51, 51' are connected to the power supply voltage (AVDD) and the reference potential (AVSS), respectively. In addition, the switch elements 52', 52 are connected to the power supply voltage (AVDD) and the reference potential (AVSS) via the constant current sources 27', 27, respectively.

[0220] In the unit pixel unit 13, when a signal is read, a voltage is applied to the gate of the address transistor 40 via the address signal line 30, thereby selecting one of the unit pixel units 13 in each column. In addition, by turning on the switch element 51 and the switch element 52 of the switching circuit 50, a current flows from the constant current source 27 in a direction from the amplifier transistor 34 toward the address transistor 40, for example, and the potential of the charge storage node 44 amplified by the amplifier transistor 34 is detected.

[0221] On the other hand, in the reset operation, by turning on the switch element 51' and the switch element 52' of the switching circuit 50, a current in the opposite direction to that in the signal readout flows through the address transistor 40 and the amplifier transistor 34. Thus, a feedback circuit FC including the amplifier transistor 34, the address transistor 40, the feedback line 25, the second reset transistor 38, and the first reset transistor 36 is formed. At this time, since the address transistor 40 and the amplifier transistor 34 are gate-cathode connected, a large gain can be obtained. Therefore, the feedback circuit FC can perform noise elimination with a large gain.

[0222] The imaging device of this embodiment can operate in a first mode capable of imaging with relatively high sensitivity and a second mode capable of imaging with relatively low sensitivity, similarly to the imaging device of the first embodiment, by controlling the first reset transistor 36 and the second reset transistor 38. In addition, the imaging device of this embodiment can reduce kTC noise, similarly to the first embodiment.

[0223] In addition, according to the image pickup device of this embodiment, the reverse amplifier 24 is not provided, and the address transistor 40 and the amplifying transistor 34 also serve as the amplifiers of the signal detection circuit SC and the feedback circuit FC. Therefore, the area of ​​the circuit constituting the image pickup device can be reduced. In addition, the power consumption of the image pickup device can be reduced. Furthermore, a larger gain can be obtained by the gate-cathode connection, so even when the capacitance of the first capacitor element 41 and the second capacitor element 42 is small, the kTC noise can be reduced.

[0224] Fig.14 The layout of each element in the unit pixel unit 13 shown can be similar to that of the reference Figure 5 and Figure 7 The layout of the unit pixel unit 11 described above is substantially the same. In addition, the device structure of each element in the unit pixel unit 13 can be the same as that in the reference Figure 6 and Figure 8 The device structure in the unit pixel unit 11 described above is substantially the same. Therefore, the layout and device structure of each element in the unit pixel unit 13 are omitted. The manufacturing method of the unit pixel unit 13 can be the same as that of the reference numeral 14. Figures 9 to 12 The manufacturing method of the unit pixel unit 11 described above is the same. Therefore, the description of the manufacturing method of the unit pixel unit 13 is omitted.

[0225] (Third embodiment)

[0226] Fig.15 FIG. 2 shows an exemplary circuit structure of the unit pixel unit 14 of the imaging device according to the third embodiment. As in the second embodiment, the imaging device according to the third embodiment replaces the inverting amplifier 24 (see FIG. 2 ) in each column of the unit pixel unit 14. Figure 2 and Fig.13 ) is provided with a switching circuit 50'. In addition, in the plurality of unit pixel cells 14 constituting each column, the feedback line 25 does not connect the unit pixel cells 14 to each other.

[0227] In each unit pixel unit 14, the feedback line 25 is connected to the side of the source or drain of the second reset transistor 38 that is not connected to the reset drain node 46. One side of the source or drain of the address transistor 40 is connected to the constant current source 27 via the vertical signal line 18. The other side of the source or drain of the address transistor 40 is connected to the feedback line 25 and one side of the source or drain of the amplifier transistor 34. The other side of the source or drain of the amplifier transistor 34 is connected to the switching circuit 50' via the power supply wiring 22.

[0228] The switching circuit 50 ′ is connected to switch elements 51 , 51 ′ connected in parallel, and the switch elements 51 , 51 ′ are connected to a power supply voltage (AVDD) and a reference potential (AVSS), respectively.

[0229] The imaging device of this embodiment can also operate in a first mode capable of imaging with relatively high sensitivity and a second mode capable of imaging with relatively low sensitivity, similar to the imaging device 101 of the first embodiment.

[0230] Fig.16 1 is a timing chart for explaining an example of the operation of the transistor in the first mode. Fig.16 In FIG. 1 , ADD, RST1, and RST2 schematically represent an example of changes in the gate voltage of the address transistor 40, the gate voltage of the first reset transistor 36, and the gate voltage of the second reset transistor 38, respectively. Fig.16 In the example shown, at time t0, the address transistor 40, the first reset transistor 36, and the second reset transistor 38 are all OFF. For simplicity, the description of the operation of the electronic shutter is omitted below.

[0231] First, the potential of the address signal line 30 is controlled to turn on the address transistor 40 (time t1). At this time, the signal charge accumulated in the charge accumulation node 44 is read out.

[0232] Next, the address transistor 40 is turned off (time t1'). Then, by controlling the potential of the reset signal line 26 and the feedback control line 28, the first reset transistor 36 and the second reset transistor 38 are turned on (time t2). In addition, the switching circuit 50' is controlled to apply a reference potential (AVSS) to one of the source and drain of the amplifier transistor 34. At this time, the address transistor 40 remains in the OFF state. As a result, in the unit pixel unit 14, the charge accumulation node 44 and the feedback line 25 are connected via the first reset transistor 36 and the second reset transistor 38, forming a feedback circuit FC that negatively feeds back the output of the signal detection circuit SC including the amplifier transistor 34.

[0233] At time t3, the first reset transistor 36 is turned off (time t3). At time t3, kTC noise is generated by turning off the first reset transistor 36. Therefore, the voltage of the charge storage node 44 after reset is added with kTC noise. If the gain of the feedback circuit FC is set to A, the kTC noise generated by turning off the first reset transistor 36 is eliminated to a size of 1 / (1+A). By setting the potential of the feedback control line 28 so that the operating bandwidth of the second reset transistor 38 becomes the first bandwidth which is a wide bandwidth, noise can be quickly suppressed.

[0234] Next, at time t3', the potential of the feedback control line 28 is set to a potential intermediate between the high level and the low level. As a result, the operating bandwidth of the second reset transistor 38 becomes a second bandwidth narrower than the first bandwidth.

[0235] Here, at time t4, kTC noise is generated by turning off the second reset transistor 38. Therefore, kTC noise is further added to the voltage of the charge storage node 44 after reset. The generated kTC noise is suppressed by the feedback circuit FC in a state where the second bandwidth is lower than the operating bandwidth of the amplifier transistor 34, and is eliminated to 1 / (1+A) 1 / 2 size.

[0236] Next, at time t5, the address transistor 40 is turned on. In addition, the switching circuit 50' is controlled so that one of the source and drain of the amplifier transistor 34 is connected to the power supply voltage (AVDD). Thus, for example, a current flows from the constant current source 27 in a direction from the amplifier transistor 34 toward the address transistor 40, and the potential of the charge storage node 44 amplified by the amplifier transistor 34 is detected. The detected potential is output to the constant current source 27 via the vertical signal line 18 (column signal processing circuit 20, see Figure 1 ).exist Fig.16 In the figure, the exposure period is schematically indicated by the arrow Exp. During the exposure period, the reset voltage from which the kTC noise is eliminated is read at a predetermined timing (time t5'). In addition, since the time required for reading the reset voltage is short, the reset voltage can also be read while the address transistor 40 is continuously in the ON state.

[0237] By taking the difference between the signal read out between time t1 and time t1' and the signal read out at time t5', a signal from which fixed noise has been removed can be obtained. In this way, a signal from which kTC noise and fixed noise have been removed can be obtained.

[0238] Fig.17 This is a timing chart for explaining an example of the operation of a transistor in the second mode capable of capturing images with relatively low sensitivity. As described in the first embodiment, except that the first reset transistor 36 is always turned on, it is driven in the same manner as in the first mode, and in each unit pixel unit 14, kTC noise is suppressed by a feedback circuit.

[0239] The camera device of this embodiment is also the same as the first embodiment, and the first reset transistor 36 has both the function of a reset transistor for resetting the charge storage node 44 and the function of a switch for switching between the first mode and the second mode. In addition, the second capacitor 42 has both the function of reducing the kTC noise in the first mode and the function of increasing the capacitance of the entire storage area of ​​the signal charge. According to this embodiment, it is possible to suppress the increase in the number of elements in the pixel and expand the dynamic range with a simple structure. This is particularly useful in the miniaturization of pixels.

[0240] (Variation of the third embodiment)

[0241] Fig.18 FIG. 1 schematically shows an exemplary circuit structure of a unit pixel unit 14a in an image pickup device according to a modified example of the third embodiment. Fig.18 As shown, in this example, the reverse amplifier 24 is also omitted (see Figure 2 and Fig.13 ), the feedback line 25 connects the side of the source or drain of the second reset transistor 38 that is not connected to the reset drain node 46 to the source or drain of the amplifier transistor 34. Fig.18 In the illustrated configuration, the output of the amplifier transistor 34 is used as a reference voltage during resetting.

[0242] In the figure 18 In the structure shown in FIG. 1 , a voltage switching circuit 54 is connected to the power supply wiring 22. The voltage switching circuit 54 includes a set of a first switch 53a and a second switch 53b. The voltage switching circuit 54 switches which of the first voltage Va1 and the second voltage Va2 is supplied to the power supply wiring 22. The first voltage Va1 is, for example, 0 V (ground), and the second voltage Va2 is, for example, a power supply voltage. The voltage switching circuit 54 may be provided for each pixel or may be shared among a plurality of pixels.

[0243] With such a circuit configuration, the kTC noise can be reduced similarly to the first embodiment.

[0244] Fig.19 FIG. 1 schematically shows an exemplary circuit structure of a unit pixel unit 14b in an image pickup device according to another modified example of the third embodiment. Fig.19 In the illustrated structure, Fig.13 Similarly to the circuit configuration described above, the source and drain of the first reset transistor 36 that are not connected to the charge storage node 44 are connected not to the reset drain node 46 but to the feedback line 25. With such a circuit configuration, kTC noise can be reduced similarly to the first embodiment.

[0245] Fig.15 The unit pixel unit 14 shown, Fig.18 The unit pixel unit 14a and Fig.19 The layout of each element in the unit pixel unit 14b shown can be similar to that of the reference Figure 5 and Figure 7 The layout of the unit pixel unit 11 described above is substantially the same. In addition, the device structure of each element in the unit pixel unit 14, 14a and 14b can be the same as that in the reference Figure 6 and Figure 8 The device structure in the described unit pixel unit 11 is substantially the same. Therefore, the description of the layout and device structure of each element in the unit pixel units 14, 14a, and 14b will be omitted. Fig.15 The unit pixel unit 14 shown, Fig.18 The unit pixel unit 14a and Fig.19 The manufacturing method of the unit pixel unit 14b shown in FIG. Figures 9 to 12 The manufacturing method of the unit pixel unit 11 described above is the same. Therefore, the description of the manufacturing method of the unit pixel units 14, 14a, and 14b will be omitted.

[0246] (Fourth embodiment)

[0247] In the above embodiment, an electrode region 42c is provided on the semiconductor substrate 2, and the second capacitor element 42 is formed as a so-called MIS capacitor. However, the structure of the high-capacitance capacitor element in the signal detection circuit SC is not limited to the above example. As described below, a capacitor element having a structure in which a dielectric is sandwiched between two electrodes formed by a metal or a metal compound may be arranged in an interlayer insulating layer arranged between the semiconductor substrate 2 and the photoelectric conversion part 15. Hereinafter, there is a case where a structure in which a dielectric is sandwiched between two electrodes formed by a metal or a metal compound is referred to as a "MIM (Metal-Insulator-Metal) structure". By forming the capacitor element arranged in the interlayer insulating layer between the semiconductor substrate 2 and the photoelectric conversion part 15 into a capacitor element having a so-called MIM structure, a larger capacitance value can be easily obtained. The device structure described below is applicable to the above-mentioned first to third embodiments.

[0248] Fig. 20 Another example of the device structure of the unit pixel unit is schematically shown. Fig. 20 The layout of the components on the semiconductor substrate 2 in the unit pixel unit 60A shown in FIG. Figure 5 The layout in the illustrated unit pixel unit 11 is the same. Fig. 20 is with Figure 5 The CC' line cross-sectional view shown corresponds to the figure.

[0249] Fig. 20 The unit pixel unit 60A shown in the figure has a capacitor element 62 disposed between the semiconductor substrate 2 and the second electrode 15c. The capacitor element 62 includes an upper electrode 62u, a lower electrode 62b, and a dielectric layer 62d disposed between the upper electrode 62u and the lower electrode 62b. Fig. 20 As shown, the lower electrode 62b is arranged farther from the second electrode 15c than the upper electrode 62u (i.e., closer to the semiconductor substrate 2 than the upper electrode 62u). In addition, the terms "upper" and "lower" in this specification are used to indicate the relative arrangement between components, and are not intended to limit the posture of the imaging device of the present invention.

[0250] Here, the lower electrode 62b is formed on the interlayer insulating layer 4c, and the capacitor 62 is covered by the interlayer insulating layer 4d provided between the interlayer insulating layer 4c and the photoelectric conversion film 15b. In this way, by arranging the lower electrode 62b and the upper electrode 62u between the photoelectric conversion unit 15 and the gate electrode 34e of the amplifier transistor 34, it is possible to suppress interference between the wiring layer including the gate electrode 34e of the amplifier transistor 34 and the lower electrode 62b and the upper electrode 62u. Therefore, it is possible to form the capacitor 62 having a relatively large electrode area.

[0251] The lower electrode 62b is typically a metal electrode or a metal nitride electrode. Examples of materials used to form the lower electrode 62b are Ti, TiN, Ta, TaN, Mo, Ru, and Pt. The lower electrode 62b may also be a part of a wiring layer provided in the interlayer insulating layer 4d.

[0252] A dielectric layer 62d is stacked on the lower electrode 62b. In this example, the dielectric layer 62d covers the surface and side surfaces of the lower electrode 62b that face the second electrode 15c.

[0253] The dielectric layer 62d may also be formed of a material (e.g., a metal oxide or a metal nitride) different from the material (typically, silicon dioxide) constituting the interlayer insulating layer 4d. If the capacitor 62 is disposed in the interlayer insulating layer provided between the semiconductor substrate 2 and the photoelectric conversion unit 15, it is relatively easy to use a material having a relatively high dielectric constant as the material used to form the dielectric layer 62d. Therefore, it is easy to achieve a relatively large capacitance value. Examples of materials used to form the dielectric layer 62d include oxides or nitrides containing one or more selected from the group consisting of Zr, Al, La, Ba, Ta, Ti, Bi, Sr, Si, Y, and Hf. The material used to form the dielectric layer 62d may be a binary compound, a ternary compound, or a quaternary compound. As materials used to form the dielectric layer 62d, for example, materials having a relatively high dielectric constant such as HfO2, Al2O3, ZrO2, TiO2, SrTiO3, etc. may be used. The dielectric layer 62d may include two or more layers formed of mutually different materials.

[0254] An upper electrode 62u is stacked on the dielectric layer 62d. In this example, the upper electrode 62u covers the surface and side surface of the dielectric layer 62d on the side opposite to the second electrode 15c. The upper electrode 62u is typically a metal electrode or a metal nitride electrode. That is, the capacitor element 62 has a so-called MIM structure. As a material for forming the upper electrode 62u, the same material as that for forming the lower electrode 62b can be used. The upper electrode 62u can also be a part of the wiring layer arranged in the interlayer insulating layer 4d.

[0255] A protective layer made of metal such as Cu, Al or polysilicon may be disposed between the upper electrode 62u and the dielectric layer 62d. By disposing the protective layer between the upper electrode 62u and the dielectric layer 62d, damage to the dielectric layer 62d during the manufacturing process can be suppressed, so that the occurrence of leakage current between the upper electrode 62u and the lower electrode 62b can be suppressed.

[0256] The upper electrode 62u has an opening AP. In the opening AP, a through hole vd, a connecting portion 66u, and a connecting portion 66b are arranged. The connecting portion 66u and the connecting portion 66b are in the same layer as the upper electrode 62u and the lower electrode 62b, respectively. 20 As shown, the second electrode 15c of the photoelectric conversion unit 15 is connected to the through hole vc having a connection with the gate electrode 34e of the amplifier transistor 34 via the through hole vd, the connection portion 66u and the connection portion 66b. The through hole vd can be formed of a metal such as copper. The through hole vd, the connection portion 66u and the connection portion 66b constitute a part of the charge storage region in the unit pixel unit 60A.

[0257] exist Fig. 20 In the illustrated structure, the portion of the lower electrode 62b shown on the right side of the through hole vd is connected to the upper electrode 42e of the second capacitor 42 via the through hole vc1, the wiring layer 6b, the through hole vb1, the wiring layer 6a, the through hole va1, the wiring layer 6s, and the contact plug cpb provided in the interlayer insulating layer 4s. That is, the lower electrode 62b has the same Fig. 20 Here, the lower electrode 62b is a single electrode provided for each unit pixel unit 60A (see the following description). Fig.21 ),exist Fig. 20 The two parts of the lower electrode 62b shown separately on the left and right sides of the opening AP are at the same potential.

[0258] In this example, the upper electrode 62u covers the connection portion 64b formed in the same layer as the lower electrode 62b. The connection portion 64b is connected to the wiring 6z which is a part of the wiring layer 6s via the through hole vc3, the wiring layer 6b, the through hole vb3, the wiring layer 6a and the through hole va3. The wiring 6z has a Fig. 20 That is, the capacitor element 62 is electrically connected in parallel with the second capacitor element 42 described above, and functions in the same manner as the second capacitor element 42. That is, in this example, the unit pixel unit 60A has a capacitor circuit in which the first capacitor element 41 is connected in series with the capacitor element 62 and the second capacitor element 42.

[0259] By providing the capacitor element 62 in the unit pixel unit, the second capacitor element 42 can be omitted. When the second capacitor element 42 is omitted, it is not necessary to ensure an area for the electrode region 42c in the semiconductor substrate 2. Therefore, the degree of freedom in the design of the element layout in the semiconductor substrate 2 is improved. For example, by omitting the electrode region 42c, the pixel size can be reduced. Alternatively, the size of the transistor (such as the amplifying transistor 34) on the semiconductor substrate 2 can be enlarged. By enlarging the size of the transistor, the deviation of the characteristics of the transistor can be reduced, so the sensitivity deviation between the unit pixel units can be reduced. In addition, by enlarging the size of the transistor, the driving capability is improved (it can also be said that the mutual conductance gm is improved), so the noise can be further reduced.

[0260] In this example, the upper electrode 62u is electrically connected to the through hole vc3 on the surface opposite to the surface facing the second electrode 15c of the photoelectric conversion unit 15. In this way, by providing a contact for electrical connection between the upper electrode 62u and the sensitivity adjustment line 32 on the surface closer to the semiconductor substrate 2, it is possible to avoid complication of wiring. In addition, since the distance between the upper electrode 62u and the second electrode 15c of the photoelectric conversion unit 15 can be reduced, the parasitic capacitance between the charge storage regions between adjacent pixels can be reduced.

[0261] When the imaging device 101 is in operation, a predetermined voltage is applied to the upper electrode 62u via the sensitivity adjustment line 32. Here, the upper electrode 62u is a single electrode provided for each unit pixel unit 60A similarly to the lower electrode 62b (see the following description). Fig.21 ),exist Fig. 20 In the figure, two parts of the upper electrode 62u shown separately on the left and right sides of the opening AP are at the same potential.

[0262] Fig.21 FIG. 6 shows an example of the arrangement of the upper electrode 62u, the dielectric layer 62d, and the lower electrode 62b when the unit pixel unit 60A is viewed from the normal direction of the semiconductor substrate 2. Fig.21 Zhongyu Figure 5 It also indicates the C-C' cutting line. Fig.21 As shown, the shape of the upper electrode 62u and the shape of the lower electrode 62b when viewed from the normal direction of the semiconductor substrate 2 do not need to be consistent. When viewed from the normal direction of the semiconductor substrate 2, the upper electrode 62u only needs to include a portion that is opposed to at least a portion of the lower electrode 62b.

[0263] In this example, the lower electrode 62b and the upper electrode 62u occupy a larger area in the unit pixel unit 60A. Therefore, by forming at least one of the lower electrode 62b and / or the upper electrode 62u as a light-shielding electrode, the lower electrode 62b or the upper electrode 62u can function as a light-shielding layer. For example, by making the upper electrode 62u function as a light-shielding layer, light that has passed through the gap formed between the second electrodes 15c can be shielded by the upper electrode 62u. Thus, it is possible to suppress the light that has passed through the gap formed between the second electrodes 15c from being incident on the channel region of the transistor (for example, the amplifier transistor 34) on the semiconductor substrate 2. For example, by forming a TaN electrode with a thickness of 100nm as the upper electrode 62u, sufficient light-shielding properties can be achieved.

[0264] According to the fourth embodiment, it is possible to suppress the incidence of stray light on the channel region of the transistor on the semiconductor substrate 2 and suppress the change in the characteristics of the transistor (for example, the change in the threshold voltage). By suppressing the incidence of stray light on the channel region of the transistor on the semiconductor substrate 2, the characteristics of the transistor of each pixel are stabilized, and the deviation of the operation of the transistor between multiple pixels can be reduced. In this way, suppressing the incidence of stray light on the channel region of the transistor on the semiconductor substrate 2 contributes to the improvement of the reliability of the imaging device.

[0265] exist Fig.21 In the illustrated structure, the upper electrodes 62u are electrically separated between the unit pixel units 60A by spatially separating the upper electrodes 62u. That is, in this example, there is a slight gap between the upper electrodes 62u adjacent to each other. However, here, the upper electrodes 62u are respectively configured to be supplied with a prescribed voltage via the sensitivity adjustment line 32. Therefore, the distance between the upper electrodes 62u adjacent to each other can be made sufficiently smaller than the distance between the second electrodes 15c adjacent to each other. Therefore, most of the light that passes through the gap formed between the second electrodes 15c can be blocked by the upper electrode 62u. In addition, in Figure 1 In the circuit structure shown in the example, a common voltage is applied to the upper electrodes 62u in the unit pixel units belonging to the same row. Therefore, a plurality of strip-shaped electrodes extending in the row direction in a plurality of columns may be used as the upper electrodes 62u. Of course, Fig.21 As shown, the upper electrode 62u is spatially separated for each unit pixel unit 60A, and an independent voltage is supplied to each upper electrode 62u.

[0266] In this example, the opening AP of the upper electrode 62u is formed below the unit pixel unit 60A in the figure. However, the configuration of the opening AP is not limited to this example. For example, the opening AP may be arranged in the center of the unit pixel unit 60A to form the upper electrode 62u in a manner that surrounds the connecting portion 66u and the connecting portion 66b. If the opening AP is arranged in the center of the unit pixel unit 60A so that the shape of the upper electrode 62u is highly symmetrical about the connecting portion 66u, it is beneficial to reduce the bias of the capacitance within the unit pixel unit 60A. The shape of the upper electrode 62u when viewed from the normal direction of the semiconductor substrate 2 is not limited to Fig.21 For example, the upper electrode 62u may include a plurality of parts. The same is true for the dielectric layer 62d and the lower electrode 62b.

[0267] As described above, in this example, since the upper electrode 62u is connected to the sensitivity adjustment line 32, the potential of the upper electrode 62u can be made constant when the imaging device 101 is operating by supplying a certain voltage to the upper electrode 62u via the sensitivity adjustment line 32. Therefore, by forming the upper electrode 62u so as to surround the connection portion 66u and the connection portion 66b and applying a certain voltage to the upper electrode 62u, the upper electrode 62u can function as a shielding electrode. By the upper electrode 62u functioning as a shielding electrode, it is possible to suppress the mixing of noise into the charge storage node 44.

[0268] As described above, in the fourth embodiment, the capacitor 62 is arranged between the upper electrode 41w and the second electrode 15c of the photoelectric conversion unit 15 as a capacitor connected between the reset drain node 46 and the sensitivity adjustment line 32. Fig. 20 As shown in the example, the capacitor element 62 is arranged in the interlayer insulating layer (for example, the interlayer insulating layer 4d) of the unit pixel unit. Therefore, the capacitor element 62 can be formed as a capacitor element having a so-called MIM structure. That is, it is easy to obtain a relatively large capacitance value in the capacitor element 62. According to such a structure, as in the above-mentioned first to third embodiments, the increase in the capacitance value of the entire storage area of ​​the signal charge can be suppressed, and the kTC noise that accompanies the reset can be reduced. In addition, if the capacitor element 62 is a high capacitor, the capacitance of the entire storage area of ​​the signal charge can be increased, so it is beneficial for photography under high illumination.

[0269] (Method of Forming Capacitor Element 62)

[0270] The following is an overview of a method for manufacturing an imaging device having the unit pixel unit 60A. The manufacturing process up to the formation of the through hole vc can be substantially the same as that of the first embodiment, and thus the description thereof will be omitted. Fig.12As described above, the upper electrode 43e electrically connected to the electrode region 42c may be formed at a position overlapping with the upper electrode 42e of the second capacitor 42. Here, in parallel with the formation of the through hole vc, the through holes vc1 and vc3 are also formed.

[0271] After the formation of the through holes vc, vcl and vc3, the lower electrode 62b, the connecting portion 66b and the connecting portion 64b are formed on the interlayer insulating layer 4c. As the material for forming the lower electrode 62b, the connecting portion 66b and the connecting portion 64b, TaN is used here. In the formation of the lower electrode 62b, the connecting portion 66b and the connecting portion 64b on the interlayer insulating layer 4c, the photolithography method introduced in the general semiconductor process can be adopted. Then, the dielectric film is formed by depositing the material of the dielectric layer 62d, and the dielectric film is patterned.

[0272] In the formation of the dielectric film, for example, an atomic layer deposition method (ALD) can be used. According to ALD, different atoms can be stacked by several atoms each. Here, a film of Hf oxide is formed as a dielectric film. In the formation of the film of Hf oxide, tetrakis(ethylmethylamino)hafnium is used as a precursor, and plasma discharge is performed after the introduction of the precursor. By performing plasma discharge in an oxygen environment, the oxidation of Hf is promoted. By repeatedly performing the above steps, HfO2 is stacked layer by layer. For example, by repeatedly introducing a gaseous precursor and plasma discharge 250 times, a film with a thickness of 22nm is formed.

[0273] The dielectric film can be patterned by photolithography introduced in a common semiconductor process. The dielectric layer 62d is formed by patterning the dielectric film. The dielectric layer 62d can be a continuous single film or include a plurality of portions arranged at different locations on the lower electrode 62b.

[0274] After the dielectric layer 62d is formed, the upper electrode 62u and the connecting portion 66u are formed in the same manner as the lower electrode 62b. Then, the interlayer insulating layer 4d and the through hole vd are formed, and the photoelectric conversion portion 15 is formed on the interlayer insulating layer 4d. Fig. 20 The device structure shown.

[0275] The second electrode 15c of the photoelectric conversion unit 15 may also be formed using metal nitrides such as TiN, TaN, and WN. Metal nitrides have good compactness and are not prone to the movement and / or mixing of impurity elements even at high temperatures. Therefore, by forming the upper electrode 62u located above the dielectric layer 62d using a metal nitride (here, TaN), and forming the second electrode 15c using a metal nitride, the mixing of carriers caused by impurities into the dielectric layer 62d can be suppressed. By suppressing the mixing of impurities into the dielectric layer 62d, the leakage current between the upper electrode 62u and the lower electrode 62b in the capacitor 62 can be reduced.

[0276] In addition, since metal nitrides are not prone to migration during sputtering, it is easy to form a flat surface. If the second electrode 15c of the photoelectric conversion unit 15 is formed using a metal nitride, bonding via a flat interface can be achieved. By suppressing the surface unevenness of the second electrode 15c, smooth charge transfer between the second electrode 15c and the photoelectric conversion film 15b can be achieved. In addition, the generation of energy levels caused by interface defects can be suppressed, and dark current can be suppressed. In this way, if both the upper electrode 62u of the capacitor 62 and the second electrode 15c of the photoelectric conversion unit 15 are formed using metal nitrides, it is beneficial from the perspective of reducing leakage current and dark current. Furthermore, if the lower electrode 62b of the capacitor 62 is formed using a metal nitride, the flatness of the upper electrode 62u can be further improved, so it is beneficial. In addition, since the oxidation of the dielectric layer 62d can be suppressed, it is beneficial.

[0277] (First variation of the fourth embodiment)

[0278] Fig. 22 Still another example of the device structure of the unit pixel unit is schematically shown. Fig.23 Indicates that Fig. 22 The unit pixel cell 60B shown is an example of the arrangement of the upper electrode 62 u , the dielectric layer 62 d , and the lower electrode 62 b when viewed from the normal direction of the semiconductor substrate 2 . Fig. 22 is with Fig.23 The CC' line cross-sectional view shown corresponds to the figure. Fig. 22 and Fig.23 The unit pixel unit 60B shown in FIG. Fig. 20 and Fig.21 The main difference between the unit pixel cell 60A described above is that the upper electrode 62 u and the lower electrode 62 b are connected to the reset drain node 46 and the sensitivity adjustment line 32 , respectively.

[0279] like Fig. 22As shown in FIG. 1 , in this example, the upper electrode 62u is connected to the wiring 6w which is a part of the wiring layer 6s via the connection portion 64b, the through hole vc2, the wiring layer 6b, the through hole vb2, the wiring layer 6a, and the through hole va2. The wiring 6w has a connection with the reset drain node 46. That is, the upper electrode 62u has a connection with the reset drain node 46. On the other hand, the lower electrode 62b is connected to the wiring 6z via the through hole vc3, the wiring layer 6b, the through hole vb3, the wiring layer 6a, and the through hole va3. The wiring 6z has a connection with the sensitivity adjustment line 32. That is, the lower electrode 62b has a connection with the sensitivity adjustment line 32. That is, the capacitor element 62 is also connected between the reset drain node 46 and the sensitivity adjustment line 32 in this example. Therefore, the capacitor element 62 functions in the same manner as the second capacitor element 42 described above. In this example, since the lower electrode 62b is connected to the sensitivity adjustment line 32, the potential of the lower electrode 62b can be controlled via the sensitivity adjustment line 32. By controlling the potential of the lower electrode 62b, the potential of the charge storage node 44 can be controlled and the sensitivity of the imaging device can be adjusted. In addition, when a certain voltage is supplied to the lower electrode 62b via the sensitivity adjustment line 32 during the operation of the imaging device, the lower electrode 62b can function as a shielding electrode.

[0280] like Fig. 22 As shown, in this example, the upper electrode 41x connecting the source or drain (source / drain diffusion layer 2d) of the first reset transistor 36 and the gate electrode 34e of the amplifier transistor 34 does not extend above the upper electrode 42e of the second capacitor 42. In other words, when viewed from the normal direction of the semiconductor substrate 2, the upper electrode 41x and the upper electrode 42e do not overlap. Therefore, the unit pixel unit 60B does not have the first capacitor 41 composed of two mutually opposed polysilicon layers and an insulating film sandwiched therebetween in the interlayer insulating layer 4s.

[0281] Here, if we focus on the photoelectric conversion unit 15 and the capacitor 62, the second electrode 15c of the photoelectric conversion unit 15 and the upper electrode 62u of the capacitor 62 are opposed to each other via the interlayer insulating layer 4d. As described above, in this example, the upper electrode 62u is connected to the reset drain node 46. That is, the capacitor 41B formed by the second electrode 15c, the upper electrode 62u and the interlayer insulating layer 4d can be regarded as a capacitor connected between the charge storage node 44 and the reset drain node 46. For example, according to Figure 2 As can be seen from the circuit structure shown, the capacitor element 41B functions in the same manner as the first capacitor element 41. That is, in this example, the capacitor element 41B is connected in series with the capacitor element 62 and the second capacitor element 42 to form a capacitor circuit.

[0282] In this way, the capacitor formed between the second electrode 15c of the photoelectric conversion part 15 and the upper electrode 62u of the capacitor 62 can be used as a low-capacitance capacitor instead of the first capacitor 41. In such a structure, as long as a sufficiently large capacitance value can be obtained by the capacitor 62, the second capacitor 42 formed as a so-called MIS capacitor can be omitted.

[0283] In addition, for example, Fig. 20 The upper electrode 41x is extended to the upper portion 42e of the second capacitor 42, as shown in the upper electrode 41w. However, from the viewpoint of reducing noise and suppressing the decrease in conversion gain, it is more advantageous that the upper electrode 41x does not overlap with the upper electrode 42e of the second capacitor 42.

[0284] The manufacturing method of the unit pixel unit 60B can be substantially the same as the manufacturing method of the unit pixel unit 60A, except that the pattern of the resist mask used to form the upper electrode 41x and the pattern of the resist mask used to form the wiring layer 6s are different. Therefore, the description of the manufacturing method of the unit pixel unit 60B is omitted.

[0285] (Second variation of the fourth embodiment)

[0286] Fig.24 Still another example of the device structure of the unit pixel unit is schematically shown. Fig.25 Indicates that Fig.24 The unit pixel cell 60C shown is an example of the arrangement of the upper electrode 62 u , the dielectric layer 62 d , and the lower electrode 62 b when viewed from the normal direction of the semiconductor substrate 2 . Fig.24 is with Fig.25 The CC' line cross-sectional view shown corresponds to the figure. Fig.24 and Fig.25 The unit pixel unit 60C shown is similar to the reference Fig. 20 and Fig.21 The main difference between the unit pixel cell 60A described above is that a low-capacitance capacitor 41C having a lower electrode 62 b as one electrode is formed in the interlayer insulating layer instead of the first capacitor 41 .

[0287] exist Fig.24 In the illustrated unit pixel unit 60C, Fig. 20 Similarly to the unit pixel unit 60A described above, the lower electrode 62b and the upper electrode 62u are connected to the reset drain node 46 and the sensitivity adjustment line 32, respectively. Fig. 22 The unit pixel unit 60B described above similarly does not include the first capacitor 41 in the interlayer insulating layer 4 s .

[0288] exist Fig.24 In the illustrated structure, the wiring layer 6b formed in the interlayer insulating layer 4b includes an electrode 6bx disposed between the via vc and the via vb. Fig.24 and Fig.25 As schematically shown in FIG. 2 , when viewed from the normal direction of the semiconductor substrate 2, the electrode 6bx has a portion overlapping with the lower electrode 62b. That is, at least a portion of the electrode 6bx is opposite to at least a portion of the lower electrode 62b across at least a portion of the interlayer insulating layer 4c. Thus, a capacitor 41C is formed between the capacitor 62 and the wiring layer (here, the electrode 6bx) disposed in the interlayer insulating layer (here, the interlayer insulating layer 4c). The portion of the interlayer insulating layer 4c sandwiched by the lower electrode 62b and the electrode 6bx functions as a dielectric layer in the capacitor 41C. Since the lower electrode 62b has a connection with the reset drain node 46 and the electrode 6bx has a connection with the second electrode 15c, the capacitor 41C functions in the same manner as the first capacitor 41 described above. That is, in this example, a capacitor circuit is formed by connecting the capacitor 41C in series with the capacitor 62 and the second capacitor 42.

[0289] In this way, a capacitor element can also be formed between capacitor element 62 and the wiring layer arranged in the interlayer insulating layer. According to such a structure, a capacitor element with low capacitance (for example, about 0.5fF) can be relatively easily arranged in the unit pixel unit. In this example, a part of wiring layer 6b (here, electrode 6bx) is used as an electrode of one side of the low capacitance capacitor element, but the electrode of one side of the low capacitance capacitor element can also be a part of other wiring layers such as wiring layer 6a or 6s. In reference to Fig.24 and Fig.25 In the described structure, as long as a sufficiently large capacitance value can be obtained by the capacitor 62, the second capacitor 42 formed as a so-called MIS capacitor can be omitted.

[0290] The method for manufacturing the unit pixel unit 60C is substantially the same as the method for manufacturing the unit pixel unit 60A, except that the patterns of the resist mask for forming the upper electrode 41x and the resist mask for forming the electrode 6bx are different. Therefore, the description of the method for manufacturing the unit pixel unit 60C is omitted.

[0291] (Fifth embodiment)

[0292] Reference Fig.26 The camera system 105 according to this embodiment will be described.

[0293] Fig.26An example of the configuration of the camera system 105 according to the present embodiment is schematically shown. The camera system 105 includes a lens optical system 601 , an imaging device 602 , a system controller 603 , and a camera signal processing unit 604 .

[0294] The lens optical system 601 includes, for example, an autofocus lens, a zoom lens, and an aperture. The lens optical system 601 focuses light onto an imaging surface of an imaging device 602. As the imaging device 602, the imaging devices of the first to fourth embodiments described above can be widely used.

[0295] The system controller 603 controls the entire camera system 105. The system controller 603 can be realized by, for example, a microcomputer.

[0296] The camera signal processing unit 604 functions as a signal processing circuit that processes the output signal from the imaging device 602. The camera signal processing unit 604 performs, for example, gamma correction, color interpolation processing, spatial interpolation processing, automatic white balance, etc. The camera signal processing unit 604 can be implemented by, for example, a DSP (Digital Signal Processor) or the like.

[0297] According to the camera system of this embodiment, by using the imaging device of the first to fourth embodiments, reset noise (kTC noise) during readout can be appropriately suppressed. As a result, charges can be accurately read out, and a good image can be obtained.

[0298] Furthermore, as described in detail in the first embodiment, a camera system can be realized that can switch between a mode in which a subject is bright and can be imaged with a relatively low sensitivity and a mode in which a subject is dark and can be imaged with a relatively high sensitivity for image taking.

[0299] Industrial Applicability

[0300] According to the embodiment of the present invention, kTC noise can be reduced. In addition, since the dynamic range can be expanded with a simple structure, it is useful for digital cameras and the like.

[0301] Description of symbols

[0302] 2 Semiconductor substrate

[0303] 2d Drain diffusion layer

[0304] 2s Component separation area

[0305] 2w Trap

[0306] 4a~4d、4s interlayer insulation layer

[0307] 6a, 6b, 6s wiring layer

[0308] 6bx Electrode

[0309] 6w, 6z wiring

[0310] 11~14, 14a, 14b unit pixel unit

[0311] 15 Photoelectric conversion unit

[0312] 15a 1st electrode

[0313] 15b Photoelectric conversion film

[0314] 15c Second electrode

[0315] 15h light receiving surface

[0316] 16 Vertical scanning circuit

[0317] 17 Accumulation control line

[0318] 18 vertical signal lines

[0319] 19 Load Circuit

[0320] 20 columns of signal processing circuits

[0321] 21 Horizontal signal readout circuit

[0322] 22 Power Wiring

[0323] 23 Horizontal common signal line

[0324] 24 Inverting Amplifier

[0325] 24a Gain adjustment terminal

[0326] 25 Feedback line

[0327] 26 Reset signal line

[0328] 27, 27' Constant current source

[0329] 28 Feedback control line

[0330] 30 Address signal lines

[0331] 32 Sensitivity adjustment line

[0332] 34 Amplifier transistor

[0333] 34c Channel region

[0334] 34e Gate electrode

[0335] 34g Gate insulation film

[0336] 36 1st reset transistor

[0337] 36c Channel area

[0338] 36e Gate electrode

[0339] 36g Gate insulation film

[0340] 38 2nd reset transistor

[0341] 38c Channel region

[0342] 38e Gate electrode

[0343] 38g Gate insulation film

[0344] 40 Address transistor

[0345] 41, 41B, 41C First capacitor element

[0346] 41g Dielectric layer

[0347] 41w, 41x upper electrode

[0348] 42 Second capacitor element

[0349] 42c Electrode area

[0350] 42e Upper electrode

[0351] 42g Dielectric layer

[0352] 43. The third capacitor element

[0353] 43e Upper electrode

[0354] 43g Dielectric layer

[0355] 44 Charge storage node

[0356] 45 Capacitor Circuit

[0357] 46 Reset drain node

[0358] 50, 50' switching circuit

[0359] 51 Switching element

[0360] 51' Switching element

[0361] 52 Switching elements

[0362] 52' Switching element

[0363] 53a 1st switch

[0364] 53b 2nd switch

[0365] 54 Voltage switching circuit

[0366] 60A~60C Unit pixel unit

[0367] 62 Capacitor element

[0368] 62b Lower electrode

[0369] 62d Dielectric layer

[0370] 62u Upper electrode

[0371] 101, 602 Camera device

[0372] 105 Camera System

[0373] 601 Lens Optical System

[0374] 602 Camera

[0375] 603 System Controller

[0376] 604 Camera signal processing unit

Claims

1. A camera device, It is characterized in that have: A photoelectric conversion unit that performs photoelectric conversion on incident light and generates electric charges; an amplifying transistor, the gate of which is electrically connected to the photoelectric conversion unit and outputs an electrical signal corresponding to the charge; a first reset transistor, one of a source and a drain of the first reset transistor being electrically connected to the photoelectric conversion unit; a first capacitor connected between the source and the drain of the first reset transistor; a second capacitor connected between the other of the source and the drain of the first reset transistor and a reference potential; as well as a second reset transistor having one of a source and a drain connected to the other of the source and the drain of the first reset transistor.

2. The imaging device according to claim 1, It is characterized in that An inverting amplifier is provided, and the inverting amplifier is connected between one of the source and the drain of the amplification transistor and the other of the source and the drain of the second reset transistor.

3. The imaging device according to claim 2, It is characterized in that A fourth transistor is further provided. The fourth transistor is connected between one of the source and the drain of the amplifying transistor and the inverting amplifier and selectively reads out the output of the amplifying transistor.

4. The imaging device according to claim 1, It is characterized in that One of the source and the drain of the amplifying transistor is electrically connected to the other of the source and the drain of the second reset transistor.

5. The imaging device according to claim 4, It is characterized in that A voltage switching circuit is provided, the voltage switching circuit being electrically connected to the other of the source and the drain of the amplifying transistor and switching between two voltages for supply.

6. The imaging device according to claim 5, It is characterized in that A constant current source is provided, and the constant current source is electrically connected to one of the source and the drain of the amplifying transistor.

7. The imaging device according to any one of claims 1 to 6, It is characterized in that A charge storage region for storing the charge generated by the photoelectric conversion unit; By turning on and off the first reset transistor, the amount of change in the potential of the charge storage region is switched.

8. The imaging device according to any one of claims 1 to 6, It is characterized in that The photoelectric conversion section includes a photoelectric conversion film, a first electrode formed on a light-receiving surface side of the photoelectric conversion film, and a second electrode formed on a surface of the photoelectric conversion film opposite to the first electrode.

9. The imaging device according to any one of claims 1 to 6, It is characterized in that The capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor.

Images