A normally closed heterojunction field effect transistor with high threshold voltage and high drain operating current and a preparation method thereof

Abstract

The present invention discloses a normally closed heterojunction field effect transistor structure with high threshold voltage and high drain operating current and a preparation method thereof, which comprises, from bottom to top, a substrate, an AlN nucleation layer, an AlGaN buffer layer, a GaN channel layer with an NPN bipolar transistor structure, and an AlGaN barrier layer; a passivation layer is provided at both ends of the AlGaN barrier layer, and a GaN cap layer is provided on the AlGaN barrier layer; a gate electrode with a Schottky contact is led out from above the GaN cap layer, and a source electrode and a drain electrode with a Schottky contact are led out from both ends of the gate GaN channel layer. Compared with conventional devices, the present invention creatively introduces an NPN bipolar transistor structure in the GaN channel layer below the gate position, which can simultaneously increase the threshold voltage and drain operating current of the device.

Description

Technical Field

[0001] The present invention relates to the field of third generation wide bandgap semiconductor power devices, and in particular to a normally closed heterojunction field effect transistor with high threshold voltage and high drain operating current and a preparation method thereof. Background Art

[0002] With the development of the information age, the semiconductor field is also developing rapidly. Compared with the first-generation semiconductor materials (silicon, germanium) and the second-generation semiconductor materials (gallium arsenide, indium phosphide, etc.), the third-generation semiconductor material gallium nitride (GaN) has become the preferred material for high-power devices in extreme environments due to its wide bandgap, high charge density, high voltage resistance, high electron mobility and other excellent properties. Studies have found that the aluminum gallium nitrogen / gallium nitride (AlGaN / GaN) heterojunction interface can form a two-dimensional electron gas with high electron concentration and high mobility, showing good high-frequency characteristics and high-power characteristics. The heterojunction field effect transistor based on this structure has superior performance compared with the silicon heterojunction HFET. Therefore, the AlGaN / GaN HFET formed by the GaN base has stronger application potential and better market prospects.

[0003] AlGaN / GaN HFET is generally a normally-on device. This device is in the on state when there is no external bias. A positive or negative bias needs to be applied to the gate to deplete the conductive channel inside the device, thereby forming a closed state. It is generally used in low-voltage and high-frequency devices. However, in order to apply it to the switch of power devices, the device needs to be improved to a normally closed device to ensure a safe operating mechanism and a simple gate drive configuration. This device is in the off state when there is no external bias. A positive or negative bias needs to be applied to the gate to form a conductive channel inside the device and turn on the device. The power device switch based on the above function not only needs to significantly increase the threshold voltage, but also needs to not affect the drain operating current of the device. In recent years, people have conducted extensive research on the production of normally-off AlGaN / GaN HFETs and proposed a lot of production schemes. In order to obtain a normally closed HFET device with a large turn-on voltage, it is necessary to deplete only the two-dimensional electron gas below the gate region, such as etching the AlGaN in the gate region with local plasma to reduce the two-dimensional electron gas in the gate region, and injecting fluorine ions below the gate to promote the depletion of the two-dimensional electron gas to obtain a normally closed p-GaN / AlGaN / GaN HFET. The only method used for commercial manufacturing is to grow a p-GaN cap layer on the gate region of the AlGaN surface to deplete the two-dimensional electron gas on the GaN channel surface below the gate region. The introduction of this method has greatly promoted the development of normally closed p-GaN / AlGaN / GaN HFET.

[0004] Theoretically, the thickness of the p-GaN cap layer increases, and the concentration of the two-dimensional electron gas that can be depleted increases. However, since the gate applied voltage needs to regulate the two-dimensional electron gas in the channel, the p-GaN cap layer grown on the gate region of the AlGaN surface cannot be too thick, otherwise the gate applied voltage will find it difficult to regulate the two-dimensional electron gas at the heterojunction interface, and it will be difficult to obtain a sufficiently good drain operating current. Therefore, this treatment method has limited improvement in the normally-off HFET device.

[0005] In order to improve the threshold voltage of the normally closed HFET device while increasing the drain operating current of the device, the present invention creatively introduces an NPN bipolar transistor structure in the gate GaN channel layer, which is composed of the gate GaN channel layer, the P+ channel region and the N+ channel region. The P+ channel region forms a PN junction with the upper GaN channel layer, and the hole concentration in the P+ channel region is much greater than the electron concentration in the GaN channel layer, which can further deplete the two-dimensional electron gas under the gate. When a sufficiently large gate voltage is applied, the emitter junction in the bipolar transistor structure is in a forward biased state, the collector junction is in a reverse biased state, and the bipolar transistor is in a forward amplification region. At this time, the N+ channel region will input a large amount of electrons into the GaN channel region, and the input electron concentration is much greater than the depleted two-dimensional electron gas concentration, thereby increasing the drain operating current of the device. In particular, when the doping concentration and thickness in the P+ channel region increase, the threshold voltage of the device will be improved; when the doping concentration and thickness in the N+ channel region increase, the drain operating current of the device will be improved. By adjusting the doping concentration and thickness in the P+ channel region and the N+ channel region within an appropriate range, a normally closed HFET device with different functional requirements can be obtained. Therefore, this invention provides a feasible exploration idea for improving the threshold voltage and drain operating current of a normally closed HFET device. Summary of the invention

[0006] The purpose of the present invention is to provide a normally-off heterojunction field effect transistor (p-GaN / AlGaN / GaN HFET) with high threshold voltage and high drain operating current and a preparation method thereof, so as to solve the technical problem in the prior art that the threshold voltage and drain operating current of the normally-off heterojunction field effect transistor cannot be effectively improved at the same time.

[0007] A normally closed heterojunction field effect transistor with high threshold voltage and high drain operating current, comprising, from bottom to top, a substrate, an AlN nucleation layer, an AlGaN buffer layer, a GaN channel layer with an NPN bipolar transistor structure, and an AlGaN barrier layer; passivation layers are provided at both ends of the AlGaN barrier layer, and a GaN cap layer is provided on the AlGaN barrier layer;

[0008] The GaN channel layers of the NPN bipolar transistor structure are sequentially composed of a first GaN channel layer, a second GaN channel layer and an n-type doped gate GaN channel layer from bottom to top; the middle of the second GaN channel layer has a through groove channel, and the bottom surface of the groove channel is covered with an n-type heavily doped N + Channel region, N + The channel region is covered with p-type heavily doped P + The GaN cap layer is disposed on the AlGaN barrier layer and the N + Channel region and P + The corresponding position of the channel region;

[0009] A gate electrode with Schottky contact is led out from the GaN cap layer, and a source electrode and a drain electrode with Schottky contact are led out from both ends of the gate GaN channel layer.

[0010] Furthermore, the N + The channel region is doped with Si at a concentration of 5×10 16 ~5×10 18 cm -3 GaN with a thickness of 0.015 to 0.15 μm.

[0011] Furthermore, the P + The channel region is doped with Mg at a concentration of 3×10 16 ~5×10 19 cm -3 GaN with a thickness of 0.05 to 0.185 μm.

[0012] Furthermore, the first GaN channel layer and the second GaN channel layer are both unintentionally doped GaN, the thickness of the first GaN channel layer is 0.01-0.04 μm; the thickness of the second GaN channel layer is 0.055-0.2 μm.

[0013] Furthermore, the gate GaN channel layer is Si doped with a concentration of 10 14 ~10 16 cm -3 GaN with a thickness of 0.005 to 0.02 μm.

[0014] Furthermore, the barrier layer material is Si doping concentration of 1×10 17 ~5×10 18 cm -3 Al x Ga 1-x The N and Al components x are 0.05 to 0.25, and the thickness is 0.01 to 0.03 μm.

[0015] Furthermore, the p-GaN cap layer material is Mg doped with a concentration of 1×1017 ~5×10 19 cm -3 GaN with a thickness of 0.02 to 0.2 μm.

[0016] Furthermore, the passivation layer is unintentionally doped SiN with a thickness of 0.05-0.5 μm.

[0017] Furthermore, the substrate is unintentionally doped SiC with a thickness of 0.5 to 2 μm; the AlN nucleation layer is unintentionally doped with a thickness of 0.01 to 0.05 μm; the AlGaN buffer layer is unintentionally doped Al x Ga 1-x N, Al component x is 0.05 to 0.2, and the thickness is 0.05 to 0.5 μm.

[0018] The method for preparing the normally closed heterojunction field effect transistor with high threshold voltage and high drain operating current comprises the following steps:

[0019] S1: prepare substrate;

[0020] S2: sequentially growing an AlN nucleation layer, an AlGaN buffer layer, and a first GaN channel layer on the substrate;

[0021] S3: cleaning the sample obtained in step S2;

[0022] S4: Growing N on the first GaN channel layer using a selective epitaxial process + Channel area;

[0023] S5: Using the selective epitaxial process on N + Growing P on the channel region + Channel area;

[0024] S6: Removing N from the first GaN channel layer + Channel region and P + A second GaN channel layer is grown outside the channel region, and a gate GaN channel layer is grown on the second GaN channel layer;

[0025] S7: growing an AlGaN barrier layer on the gate GaN channel layer by MOCVD;

[0026] S8: growing a GaN cap layer on the AlGaN barrier layer by MOCVD;

[0027] S9: growing a passivation layer on the AlGaN barrier layer except for the GaN cap layer by PECVD;

[0028] S10: Photolithography of source and drain patterns;

[0029] S11: A gate is fabricated on the GaN cap layer, and a drain and a source are fabricated at both ends of the gate GaN channel layer.

[0030] Beneficial Effects

[0031] The method for preparing a normally closed heterojunction field effect transistor with a high threshold voltage and a high drain operating current described in the present invention is to first grow an N+ channel region and a P+ channel region in sequence on a substrate on which a portion of a GaN channel layer has been grown, and then grow the remaining channel layer, thereby preparing an NPN-type bipolar transistor structure, wherein the P+ channel region forms a PN junction with the upper GaN channel layer, and the hole concentration in the P+ channel region is much greater than the electron concentration in the gate GaN channel layer, which can further deplete the two-dimensional electron gas under the gate to obtain a larger threshold voltage; and when a sufficiently large gate voltage is applied, the emitter junction in the bipolar transistor structure is in a forward biased state, the collector junction is in a reverse biased state, and the bipolar transistor is in a forward amplification region. At this time, the N+ channel region will input electrons equivalent to the two-dimensional electron gas concentration into the GaN channel region, thereby increasing the drain operating current of the device. In particular, when the doping concentration and thickness of the P+ channel region increase, the threshold voltage of the device will be improved; and when the doping concentration and thickness of the N+ channel region increase, the drain operating current of the device will be improved. By adjusting the doping concentration and thickness of the P+ channel region and the N+ channel region within an appropriate range, a normally closed HFET device with different functional requirements can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The present invention is a flow chart of a method for preparing a normally closed heterojunction field effect transistor with high threshold voltage and high drain operating current.

[0033] Figure 2 The schematic diagram of the cross-sectional structure of a normally closed heterojunction field effect transistor with high threshold voltage and high drain operating current of the present invention.

[0034] Figure 3 The energy band diagram of the gate region of a conventional device and a normally-off heterojunction field effect transistor with high threshold voltage and high drain operating current in Example 1 of the present invention.

[0035] Figure 4 Graph showing the transfer characteristics of a conventional device (a) and a normally-off heterojunction field effect transistor with high threshold voltage and high drain operating current in Example 1 of the present invention.

[0036] Legend: 1. substrate; 2. AlN nucleation layer; 3. AlGaN buffer layer; 4. first GaN channel layer; 5. N + Channel region; 6, P +Channel region 2; 7, second GaN channel layer; 8, gate GaN channel layer; 9, AlGaN barrier layer; 10, p-GaN cap layer; 11, passivation layer; 12, gate; 13, drain; 14, source. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with specific embodiments.

[0038] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways than those described herein. Therefore, the present invention is not limited to the specific embodiments of the following disclosure.

[0039] A method for preparing a normally closed heterojunction field effect transistor, see Figure 1 , including the following steps:

[0040] S1: prepare substrate 1;

[0041] In an embodiment, the substrate 1 is a SiC substrate 1 .

[0042] S2: growing an AlN nucleation layer 2, an AlGaN buffer layer 3 and a first GaN channel layer 4 in sequence on the substrate 1 by MOCVD.

[0043] Specifically, in the embodiment, the SiC substrate 1 is placed in a MOCVD reactor and 2 and NH 3 Annealing is performed at about 970°C in an atmosphere.

[0044] On SiC, trimethylaluminum (TMAl), trimethylgallium (TMGa), ammonia (NH 3 ) as Al source, Ga source, and N source, respectively, and hydrogen (H 2 ) and nitrogen (N 2 ) as a carrier gas, an AlN nucleation layer 2, an AlGaN buffer layer 3 and a first GaN channel layer 4 are grown in sequence by MOCVD.

[0045] In one embodiment, the composition of Al in the grown AlGaN is changed by controlling the gas flow of TMAl and TMGa.

[0046] S3: Clean the sample:

[0047] In an embodiment, the cleaning includes organic cleaning and inorganic cleaning, wherein the organic cleaning step is: first, the sample is placed in a mixture of concentrated sulfuric acid and hydrogen peroxide (concentrated sulfuric acid: hydrogen peroxide = 7:3) and soaked for 10 minutes, and then the sample is placed in a diluted ammonia (20%) and hydrogen peroxide mixture (diluted ammonia: hydrogen peroxide = 6:1), heated in a water bath for 10 minutes, and the water bath temperature is set to 85°C; then the sample is placed in an aqueous solution of KOH: hydrogen peroxide = 1:2 and soaked for 10 minutes, and finally washed with deionized water;

[0048] The inorganic cleaning steps are as follows: firstly, the sample is ultrasonically treated in acetone for 10 minutes with a power of 100 W to remove organic impurities on the surface of the sample; then, the sample is ultrasonically treated in an ethanol solution for 10 minutes with a power of 100 W; finally, the sample is cleaned in deionized water and stored in an oven (100° C.) for 4 minutes.

[0049] S4: Epitaxial growth N + Channel region 5

[0050] In the implementation mode, the specific steps are:

[0051] a. Using plasma enhanced chemical vapor deposition (PECVD) to deposit a layer of SiO2 with a thickness of about 800 nm on the first GaN channel layer 4 2 mask layer;

[0052] b. Use conventional photolithography and wet etching techniques to etch away the SiO2 below the gate region to be grown. 2 A mask layer, exposing the first GaN channel layer 4 in this area;

[0053] c. Place the substrate in the MOCVD reactor, set the temperature to 600°C, and introduce a certain amount of TMGa and NH into the reactor at normal pressure. 3 and tetrahydrosilane (SiH 4 ) and other reaction precursors to generate the required N + Channel region 5. TMGa and NH 3 It is the main reaction source for the growth of GaN, SiH 4 It is an n-type doping source. The growth rate and doping concentration can be adjusted by adjusting their respective flow rates.

[0054] d. Etch away the GaN polycrystalline layer and the mask layer using selective etching technology;

[0055] In this step, the GaN polycrystalline layer is first etched away with a NaOH aqueous solution, and then the mask layer is etched away with an aqueous solution containing HF. + The selective etching ratio of the channel region 5 in the NaOH aqueous solution is very large, and SiO 2 Mask layer and N+ The selective etching ratio of the channel region 5 and the first GaN channel layer 4 is very large. Therefore, in this process, the first GaN channel layer 4 and the N + The channel region 5 is not etched at all.

[0056] S5: Growth of P using selective epitaxial process + Channel region 6;

[0057] In the implementation mode, the specific steps are:

[0058] a. Use PECVD to deposit a layer of SiO2 with a thickness of about 800 nm on the substrate. 2 mask layer;

[0059] b. Use conventional photolithography and wet etching techniques to etch away the SiO2 below the gate region to be grown. 2 Mask layer, exposing the N + Channel region 5;

[0060] c. Place the substrate in the MOCVD reactor, set the temperature to 600°C, and introduce a certain amount of TMGa and NH into the reactor at normal pressure. 3 and Cp 2 Mg and other reaction precursors to generate the required P + Channel region 6. TMGa and NH 3 It is the main reaction source for the growth of GaN, Cp 2 Mg is a p-type doping source. The growth rate and doping concentration can be adjusted by adjusting their respective flow rates.

[0061] d. Etch away the GaN polycrystalline layer and the mask layer using selective etching technology;

[0062] In this step, the GaN polycrystalline layer is first etched away with a NaOH aqueous solution, and then the mask layer is etched away with an aqueous solution containing HF. + The selective etching ratio of the channel region 6 in the NaOH aqueous solution is very large, and SiO 2 The mask layer and the first GaN channel layer 4, P + The selective etching ratio of the channel region 6 is very large, so in this process, the first GaN channel layer 4, P + The channel region 6 is not etched at all.

[0063] S6: growing the remaining channel layer;

[0064] In the implementation mode, the specific steps are:

[0065] a. Use PECVD to deposit a layer of SiO2 with a thickness of about 800 nm on the substrate. 2 mask layer;

[0066] b. Use conventional photolithography and wet etching techniques to etch away the SiO2 below the gate region. 2 A mask layer, exposing the first GaN channel layer 4 in this area;

[0067] c. Place the substrate in the MOCVD reactor, set the temperature to 600°C, and introduce a certain amount of TMGa and NH into the reactor at normal pressure. 3 and other reaction precursors to generate the desired second GaN channel layer 7. Among them, TMGa and NH 3 It is the main reaction source for growing GaN, and adjusting their respective flow rates can adjust the growth rate.

[0068] d. Etch away the GaN polycrystalline layer and the mask layer using selective etching technology;

[0069] In this step, the GaN polycrystalline layer is first etched away with a NaOH aqueous solution, and then the mask layer is etched away with an aqueous solution containing HF. + The selective etching ratio of the channel region 6 in the NaOH aqueous solution is very large, and SiO 2 The mask layer and the second GaN channel layer 7, P + The selective etching ratio of the channel region 6 is very large, so in this process, the second GaN channel layer 7, P + The channel region 6 is not etched at all.

[0070] e. A gate GaN channel layer 8 is grown by MOCVD;

[0071] In this step, the substrate is placed in a MOCVD reactor, the temperature is set to rise to 600°C, and a certain amount of TMGa and NH are introduced into the reactor under normal pressure. 3 and SiH 4 The required gate GaN channel layer 8 is generated by reacting precursors such as TMGa and NH 3 It is the main reaction source for the growth of GaN, SiH 4 It is an n-type doping source. The growth rate and doping concentration can be adjusted by adjusting their respective flow rates.

[0072] S7: AlGaN barrier layers 9 are sequentially grown by MOCVD.

[0073] Specifically, in an embodiment, the substrate is placed in a MOCVD reactor and heated under H 2 and NH 3 Annealing is performed at about 600°C in an atmosphere.

[0074] A certain amount of TMGa and NH4+ are introduced into the reactor under normal pressure. 3 ,TMAl and SiH 4The required AlGaN barrier layer 9 is formed by reacting precursors such as TMGa, TMAl and NH 3 It is the main reaction source for the growth of AlGaN, SiH 4 It is an n-type doping source. The growth rate and doping concentration can be adjusted by adjusting their respective flow rates.

[0075] S8: growing a p-GaN cap layer 10 by MOCVD;

[0076] Specifically, in an implementation manner, the S8 comprises the following steps:

[0077] a. Place the substrate in the MOCVD reactor, set the temperature to 600°C, and introduce a certain amount of TMGa, NH3 and Cp into the reactor at normal pressure. 2 Mg and other reaction precursors to generate the required p-type GaN. Among them, TMGa and NH 3 It is the main reaction source for the growth of GaN, Cp 2 Mg is a p-type doping source, and adjusting the respective flow rates can adjust the growth rate and doping concentration.

[0078] b. Etch the p-GaN except the gate region using inductively coupled plasma (ICP) etching technology;

[0079] In one embodiment, the photolithography machine uses AZ1500, and after photolithography and development to expose the non-gate area, the photoresist and developer adhering to the device surface are washed away with deionized water, and dried at 90° C. for 4 minutes to solidify the photoresist;

[0080] c. Use ICP etcher to remove Cl 2 As the main etching gas, Cl 2 , BCl 3 The volume flow rates of Ar and Ar were 14, 10, and 6 cm 2 / min, temperature of 10°C, ICP coil power of 600W, chamber pressure of 4mTorr, and etching rate of 40nm / min, the exposed p-GaN is etched away, and then the photoresist is removed;

[0081] S9: growing a passivation layer 11 by PECVD;

[0082] Specifically, in an implementation manner, the S9 includes the following steps:

[0083] a. Place the substrate in a PECVD reactor and place it under H 2 and NH 3 Annealing is performed at about 300°C in an atmosphere.

[0084] b. Using SiH on SiC 4NH 3 As Si source and N source, N 2 As a carrier gas, the SiN passivation layer 11 is grown by PECVD.

[0085] c. Etching the SiN passivation layer 11 in the gate 12 region using ICP etching technology;

[0086] S10: Photolithography of the drain 13 and the source 14;

[0087] In the implementation method, the photolithography machine uses AZ1500. After photolithography and development to expose the drain 13 and source 14 electrode regions, the photoresist and developer adhering to the device surface are washed away with deionized water, and then dried at 90° C. for 4 minutes to solidify the photoresist.

[0088] Then use ICP etcher to remove Cl 2 As the main etching gas, Cl 2 , BCl 3 The volume flow rates of Ar and Ar were 14, 10, and 6 cm 2 / min, temperature of 10°C, ICP coil power of 600W, chamber pressure of 4mTorr, and etching rate of 40nm / min, the SiN passivation layer 11 and the AlGaN barrier layer 9 in the region where the drain 13 and the source 14 are to be grown are etched away, and the thickness of the GaN channel layer 8 is etched to 0.02μm, and then the photoresist is removed;

[0089] S11: A gate 12 is fabricated on the GaN cap layer 10, and a drain 13 and a source 14 are fabricated on both sides of the device.

[0090] Specifically, in the implementation mode, a PVD electron beam evaporation station is used to evaporate Al in the gate 12, drain 13, and source 14 regions with a thickness of 70 nm, so that the drain 13 and source 14 metals form Schottky contacts with the GaN channel layer 8, and the gate 12 metal forms Schottky contacts with the p-GaN cap layer 10;

[0091] The present application also provides a normally closed heterojunction field effect transistor structure, which is prepared using the above-mentioned preparation method. Figure 2 .

[0092] like Figure 2 The figure shows a cross-sectional view of a normally closed normally closed heterojunction field effect transistor device in an embodiment. The working principle is: when the gate 12 voltage is zero or the gate 12 voltage is lower than the threshold voltage, the two-dimensional electron gas in the channel layer below the gate 12 is depleted by the p-GaN cap layer 10 above, and the normally closed heterojunction field effect transistor is in a closed state, showing typical normally closed heterojunction field effect transistor characteristics; when the gate 12 voltage slowly increases, the partially recovered two-dimensional electron gas below the gate 12 is again depleted by the p-GaN cap layer 10 above.+ The channel region 6 is depleted and still in a closed state; when the gate 12 voltage is greater than the threshold voltage, the two-dimensional electron gas below the gate 12 is restored. The restored two-dimensional electron gas connects the two-dimensional electron gas at the interface of the GaN channel layer 8 and the AlGaN barrier layer 9 on both sides below the gate 12, and the normally closed heterojunction field effect transistor is in an open state; when the gate 12 voltage is further increased, the NPN bipolar transistor structure is in an amplification region, providing more electrons for the channel region, thereby increasing the drain operating current of the device.

[0093] The three embodiments were simulated using Sentaurus TCAD simulation software. The sStructureEditor module and sDevice module in the software were used to write codes to construct device structures and physical models, and electrical analysis was performed on the constructed device structures.

[0094] Example 1: High Threshold Voltage Normally Off GaN Heterojunction Field Effect Transistor

[0095] The device of Example 1 is manufactured using the manufacturing process in the specific implementation. Specifically, in Example 1, the SiC substrate 1 is unintentionally doped SiC with a thickness of 1 μm; the AlN nucleation layer 2 is 0.01 μm thick and unintentionally doped; the AlGaN buffer layer 3 is made of unintentionally doped Al 0.05 Ga 0.95 N, with a thickness of 0.05 μm; the first GaN channel layer 4 is non-intentionally doped GaN, with a thickness of 0.015 μm; the N + The material of channel region 5 is Si with a doping concentration of 5×10 18 cm -3 GaN with a thickness of 0.02 μm; the second GaN channel layer 7 is unintentionally doped GaN with a thickness of 0.06 μm; the P + The material of channel region 6 is Mg doped with a concentration of 3×10 19 cm -3 GaN with a thickness of 0.04 μm; the gate channel layer 8 is made of Si with a doping concentration of 10 15 cm -3 GaN with a thickness of 0.005 μm; the barrier layer 9 is made of Si with a doping concentration of 10 18 cm -3 Al 0.23 Ga 0.77 N, with a thickness of 0.015 μm; the p-GaN cap layer 10 is made of Mg with a doping concentration of 3×10 17 cm -3GaN with a thickness of 0.11 μm; the passivation layer 11 is made of unintentionally doped SiN with a thickness of 0.2 μm.

[0096] Depend on Figure 3 It can be seen that the distance between the conduction band and the Fermi level on the upper surface of the channel layer in Example 1 is much higher than that of the conduction band and the Fermi level of the conventional device. + The Fermi level in the channel region has been raised above the conduction band, but due to the N + The channel region only exists under the gate and cannot participate in conduction, so the device in this case is still a normally closed device. It can be seen that the threshold voltage of Example 1 is much higher than the threshold voltage of the traditional device. Figure 4 It can be seen that the threshold voltage of the conventional device is about 1.4V, while the threshold voltage of Example 1 reaches about 3V, which is increased to about 210% of the threshold voltage of the conventional device, which shows that the threshold voltage of the device in this case has been greatly improved. The working drain current of the conventional device is about 0.35A, while the working drain current of Example 1 is only 0.15A. Therefore, Example 1 is a normally closed gallium nitride heterojunction field effect transistor with a high threshold voltage.

[0097] Example 2: Normally-off GaN heterojunction field effect transistor with high operating drain current

[0098] The device of Example 2 is manufactured using the manufacturing process in the specific implementation. Specifically, in Example 2, the SiC substrate 1 is unintentionally doped SiC with a thickness of 1 μm; the AlN nucleation layer 2 is 0.01 μm thick and unintentionally doped; the AlGaN buffer layer 3 is made of unintentionally doped Al 0.05 Ga 0.95 N, with a thickness of 0.05 μm; the first GaN channel layer 4 is non-intentionally doped GaN, with a thickness of 0.015 μm; the N + The material of channel region 5 is Si with a doping concentration of 1×10 16 cm -3 GaN with a thickness of 0.015 μm; the second GaN channel layer 7 is unintentionally doped GaN with a thickness of 0.065 μm; the P + The material of channel region 6 is Mg doped with a concentration of 1×10 16 cm -3 GaN with a thickness of 0.05 μm; the gate channel layer 8 is made of Si with a doping concentration of 10 15 cm -3 GaN with a thickness of 0.005 μm; the barrier layer 9 is made of Si with a doping concentration of 10 18 cm -3 Al 0.23 Ga 0.77N, with a thickness of 0.015 μm; the p-GaN cap layer 10 is made of Mg with a doping concentration of 3×10 17 cm -3 GaN with a thickness of 0.11 μm; the passivation layer 11 is made of unintentionally doped SiN with a thickness of 0.2 μm.

[0099] Depend on Figure 3 It can be seen that the conduction band heights of the embodiment 2 and the conventional device are almost equal at the upper surface of the channel layer, indicating that the threshold voltages of the two are almost equal at this time. Figure 4 It can be seen that the threshold voltage of Example 2 is about 1.6V, which is only 0.2V higher than that of the conventional device, but the working drain current of Example 2 is about 0.65A, which is 185% of the original device, indicating that Example 2 is a normally closed gallium nitride heterojunction field effect transistor with high working drain current.

[0100] Example 3: Normally-off GaN heterojunction field effect transistor with high threshold voltage and high operating drain current

[0101] The device of Example 3 is manufactured using the manufacturing process in the specific implementation. Specifically, in Example 3, the SiC substrate 1 is unintentionally doped SiC with a thickness of 1 μm; the AlN nucleation layer 2 is 0.01 μm thick and unintentionally doped; the AlGaN buffer layer 3 is made of unintentionally doped Al 0.05 Ga 0.95 N, with a thickness of 0.05 μm; the first GaN channel layer 4 is Si doped with a concentration of 10 14 cm -3 GaN, with a thickness of 0.015 μm; the N + The material of channel region 5 is Si with a doping concentration of 1×10 18 cm -3 GaN with a thickness of 0.015 μm; the second GaN channel layer 7 is unintentionally doped GaN with a thickness of 0.065 μm; the P + The material of channel region 6 is Mg doped with a concentration of 1×10 18 cm -3 GaN with a thickness of 0.05 μm; the gate channel layer 8 is made of Si with a doping concentration of 10 15 cm -3 GaN with a thickness of 0.005 μm; the barrier layer 9 is made of Si with a doping concentration of 10 18 cm -3 Al 0.23 Ga 0.77 N, with a thickness of 0.015 μm; the p-GaN cap layer 10 is made of Mg with a doping concentration of 3×10 17 cm -3GaN with a thickness of 0.11 μm; the passivation layer 11 is made of unintentionally doped SiN with a thickness of 0.2 μm.

[0102] Depend on Figure 3 It can be seen that the conduction band height of Example 2 at the upper surface of the channel layer is higher than that of the conventional device, but much lower than that of Example 1, indicating that the threshold voltage of the device of Example 3 is higher than that of the conventional device, but much lower than that of the device of Example 1. Figure 4 It can be concluded that when the external gate voltage reaches about 1.4V, the conventional device is turned on, while the device of Example 3 is turned on when the external gate voltage is about 2.2V, that is, Example 3 increases the threshold voltage to about 157% of the threshold voltage of the conventional device. At the same time, the working drain current of Example 3 is about 0.42A, which is about 120% of the drain working current of the conventional device. This shows that Example 3 is a normally closed gallium nitride heterojunction field effect transistor with high threshold voltage and high working drain current.

[0103] Based on the above, Example 3 achieves the purpose of increasing the device threshold voltage while increasing the device transfer efficiency.

[0104] The present application provides a normally closed gallium nitride heterojunction field effect transistor structure with high threshold voltage and high drain operating current and a preparation method thereof. An NPN bipolar transistor structure is introduced into the GaN channel layer below the gate position. The structure consists of a gate GaN channel layer, a P + Channel region and N + The channel region can simultaneously increase the threshold voltage and drain current of the device. + The channel region can deplete the electrons in the GaN channel layer of the gate part to increase the threshold voltage of the device; when the external gate voltage is large enough, the bipolar transistor structure is in the forward amplification region, N + A large number of electrons in the channel region flow into the gate GaN channel layer, and the concentration of the two-dimensional electron gas on the surface of the channel layer increases, thereby increasing the drain operating current of the device. In particular, by changing P + Channel region and N + The concentration and thickness of the channel region can be adjusted to obtain devices with different threshold voltages and drain operating currents.

[0105] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention shall be included in the scope of the claims of the present invention.

Claims

1. A normally-off heterojunction field effect transistor with high threshold voltage and high drain operating current, characterized in that: The transistor comprises, from bottom to top, a substrate (1), an AlN nucleation layer (2), an AlGaN buffer layer (3), a GaN channel layer having an NPN bipolar transistor structure, and an AlGaN barrier layer (9); passivation layers (11) are provided at both ends of the AlGaN barrier layer (9), and a GaN cap layer (10) is provided on the AlGaN barrier layer (9); a passivation layer (11) is grown on the AlGaN barrier layer (9) except for the position of the GaN cap layer (10); The GaN channel layer with an NPN bipolar transistor structure comprises, from bottom to top, a first GaN channel layer (4), a second GaN channel layer (7), and an n-type doped gate GaN channel layer (8); the second GaN channel layer (7) has a through groove channel in the middle, and the bottom surface of the groove channel is covered with an n-type heavily doped N + Channel region (5), N + The channel region (5) is covered with p-type heavily doped P + The GaN cap layer (10) is disposed on the AlGaN barrier layer (9) and is connected to the N + Channel region (5) and P + The position corresponding to the channel region (6); A gate electrode (12) with a Schottky contact is led out from above the GaN cap layer (10), and a source electrode (14) and a drain electrode (13) with Schottky contact are led out from above both ends of the gate GaN channel layer (8).

2. A normally-off heterojunction field effect transistor with high threshold voltage and high drain operating current according to claim 1, characterized in that: The N + The channel region (5) is Si doped at a concentration of 5×10 16 ~5×10 18 cm -3 GaN with a thickness of 0.015~0.04μm.

3. A normally-off heterojunction field effect transistor with high threshold voltage and high drain operating current according to claim 1, characterized in that: The P + The channel region (6) is doped with Mg at a concentration of 3×10 16 ~5×10 19 cm -3 GaN with a thickness of 0.05~0.06μm.

4. A normally-off heterojunction field effect transistor with high threshold voltage and high drain operating current according to claim 1, characterized in that: The first GaN channel layer (4) and the second GaN channel layer (7) are both non-intentionally doped GaN; the thickness of the first GaN channel layer (4) is 0.01-0.04 μm; and the thickness of the second GaN channel layer (7) is 0.02-0.2 μm.

5. The normally-off heterojunction field effect transistor with high threshold voltage and high drain operating current according to claim 1, characterized in that: The gate GaN channel layer (8) is Si doped at a concentration of 10 14 ~10 16 cm -3 GaN with a thickness of 0.005~0.02 μm.

6. A normally-off heterojunction field effect transistor with high threshold voltage and high drain operating current according to claim 1, characterized in that: The barrier layer (9) is made of Si with a doping concentration of 1×10 17 ~5×10 18 cm -3 Al x Ga 1-x N, Al component x is 0.05~0.25, and the thickness is 0.01~0.03 μm.

7. A normally-off heterojunction field effect transistor with high threshold voltage and high drain operating current according to claim 1, characterized in that: The GaN cap layer (10) is made of Mg doped with a concentration of 1×10 17 ~5×10 19 cm -3 GaN with a thickness of 0.02~0.2 μm.

8. The normally-off heterojunction field effect transistor with high threshold voltage and high drain operating current according to claim 1, characterized in that: The passivation layer (11) is non-intentionally doped SiN and has a thickness of 0.05-0.5 μm.

9. The normally-off heterojunction field effect transistor with high threshold voltage and high drain operating current according to claim 1, characterized in that: The substrate (1) is unintentionally doped SiC with a thickness of 0.5-2 μm; the AlN nucleation layer (2) is unintentionally doped with a thickness of 0.01-0.05 μm; the AlGaN buffer layer (3) is unintentionally doped Al x Ga 1-x N, Al component x is 0.05~0.2, and thickness is 0.05~0.5 μm.

10. The method for preparing a normally-off heterojunction field effect transistor with high threshold voltage and high drain operating current according to any one of claims 1 to 9, characterized in that: The following steps are involved: S1: Prepare substrate (1); S2: sequentially growing an AlN nucleation layer (2), an AlGaN buffer layer (3), and a first GaN channel layer (4) on the substrate (1); S3: cleaning the sample obtained in step S2; S4: Growing N on the first GaN channel layer (4) using a selective epitaxial process + Channel region (5); S5: Using the selective epitaxial process on N + Growing P on the channel region (5) + Channel region (6); S6: Remove N from the first GaN channel layer (4) + Channel region (5) and P + A second GaN channel layer (7) is grown outside the channel region (6), and a gate GaN channel layer (8) is then grown on the second GaN channel layer (7); S7: growing an AlGaN barrier layer (9) on the gate GaN channel layer (8) by MOCVD; S8: growing a GaN cap layer (10) on the AlGaN barrier layer (9) by MOCVD; S9: growing a passivation layer (11) on the AlGaN barrier layer (9) except for the GaN cap layer (10) by PECVD; S10: Photolithography of the source electrode (14) and the drain electrode (13); S11: a gate electrode (12) is fabricated on the GaN cap layer (10), and a drain electrode (13) and a source electrode (14) are fabricated at both ends of the gate GaN channel layer (8).

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