A system for generating irreducible polynomials and hashing algorithms based on FPGA

Abstract

The present invention discloses a system for generating irreducible polynomials and hash algorithms based on an FPGA, relating to the field of information security. The system includes an irreducible polynomial unit and a hash algorithm unit. After detecting a flag data bit indicating the start of transmission, the system extracts irreducible polynomial parameters and inputs them into the irreducible polynomial unit. The irreducible polynomial unit then judges the irreducible polynomial parameters. Irreducible polynomial parameters that meet the requirements are input into the hash algorithm unit. The irreducible polynomial parameters, a key, and data to be encrypted are calculated by the hash algorithm unit to ultimately output a hash value. The system can not only quickly generate irreducible polynomials, but also quickly, securely, and efficiently implement hash algorithm encryption based on the irreducible polynomials.

Description

Technical Field

[0001] The present invention relates to the field of information security, and in particular to a system for generating irreducible polynomials and hash algorithms based on FPGA. Background Art

[0002] With the widespread adoption of networks and computers, information exchange has exploded. This process has given rise to numerous information security issues, such as information loss, leakage, and tampering. These issues not only impact personal privacy and corporate assets, but also threaten the security of national economies and military forces. Therefore, as a primary means of ensuring information security, information encryption and authentication technologies are crucial barriers to protecting the information security of individuals, businesses, and even the nation. Reliable and efficient information encryption systems are a persistent goal for businesses and nations alike, offering broad market prospects and enormous economic and scientific value.

[0003] Among these, irreducible polynomials, a core element of information encryption technology, boast a wide range of applications and high value. In coding, irreducible polynomials serve as the generator polynomials for error-correcting codes such as BCH codes, Gopa codes, and Reed-Solomon codes, forming the foundation of error-correcting codes. In cryptography and encryption, irreducible polynomials underlie the construction of hash algorithms (Secure Hash Algorithms), and these hash algorithm cryptographic systems are resistant to quantum attacks. The resulting McEliece cipher public-key cryptography system was even selected as a candidate for the third round of the National Security Agency's post-quantum cryptography standards. In communications and computing, irreducible polynomials can be used as characteristic functions of linear shift registers (LFSRs) to rapidly generate pseudo-random sequences.

[0004] Secure hash algorithm, also known as hash algorithm, is an important information encryption algorithm that can effectively block illegal and spam information and improve the security of the entire system.

[0005] Despite the significant value of irreducible polynomials and hash algorithms, there is still a lack of systems capable of rapidly generating them, let alone hash algorithms based on irreducible polynomials. Furthermore, most hash algorithm chips currently used in the market are based on single algorithm logic or are developed from fixed irreducible polynomials, posing a risk of being cracked and failing to meet the growing demand for information security.

[0006] Therefore, a new solution is now needed. Summary of the Invention

[0007] Purpose of the Invention: This invention provides an FPGA-based system for generating irreducible polynomials and hash algorithms. This system addresses the market gap in rapidly generating irreducible polynomials and hash algorithms, solves the challenge of building hash algorithms based on irreducible polynomials, and addresses the current challenges faced by hash algorithm chips, which are mostly based on single algorithm logic or developed from fixed irreducible polynomials, resulting in decryption risks and a failure to meet the needs of information security. This system not only rapidly generates irreducible polynomials but also implements hash algorithm encryption based on these irreducible polynomials in a fast, secure, and efficient manner.

[0008] Technical solution: A system for generating irreducible polynomials and hash algorithms based on FPGA. The system includes an irreducible polynomial unit and a hash algorithm unit. After the system detects the flag data bit for starting transmission, it extracts the irreducible polynomial parameters and inputs them into the irreducible polynomial unit. The irreducible polynomial unit judges the irreducible polynomial parameters. Irreducible polynomial parameters that meet the conditions are input into the hash algorithm unit. The irreducible polynomial parameters, the key and the data to be encrypted are calculated by the hash algorithm unit to finally output the resulting hash value.

[0009] Furthermore, the irreducible polynomial unit includes a square operation module, a modulo operation module, a counting judgment module, a cyclic modulo operation module and a result judgment module. The square operation module performs a square operation on the input data; the modulo operation module performs a modulo operation on the input square operation module data and the input irreducible polynomial parameters; the counting judgment module is used to record the number of times the square operation module and the modulo operation module are passed and record the data results of a specific number of times according to the judgment result; the cyclic modulo operation module performs a cyclic modulo operation on the input counting judgment module data and the input irreducible polynomial parameters; the result judgment module judges whether the irreducible polynomial parameters meet the requirements. If they do not meet the requirements, the irreducible polynomial parameters are added with the number 2 and the irreducible polynomial parameters are re-judged by the irreducible polynomial unit until the irreducible polynomial parameters are confirmed to meet the requirements.

[0010] Furthermore, the square operation process is as follows: set parameters S and D, determine whether the n-th bit of parameter D is 0, if so, the n-th bit data of parameter S is 0, if not, the n-th bit data of parameter S is the parameter D shifted left by n bits, and as above, judge and operate each bit of parameter D, and finally perform XOR operation on the results of the calculation of each bit to obtain the final square result.

[0011] Furthermore, the data length of the key is m bits. A fixed address parameter G is preset in the FPGA, and the length of the fixed parameter G is m bits. After the fixed parameter G is squared, a data X with a length of 2m bits is obtained. The data X will be transmitted to the modulo operation module. The modulo operation module will perform a judgment on the 2m-bit data of the data X to determine whether the high-m bits of the data are all 0. If so, the low-m bits of the data X are taken and input into the counting judgment module. If not, the input irreducible polynomial parameters are shifted and XORed.

[0012] Furthermore, the irreducible polynomial parameter shift processing and XOR operation are as follows: the highest bit 1 of the irreducible polynomial parameter is aligned with the highest bit 1 of the data X, and an XOR operation is performed. The data following the highest bit 1 of the data X generates a new data. The new data is again aligned with the highest bit 1 of the irreducible polynomial parameter and an XOR operation is performed. The above operation is repeated until the high-order m bits of the generated new data X′ are all 0, and the low-order m bits of the data X′ are taken as the result and input into the counting judgment module.

[0013] Furthermore, the input data of the counting judgment module will be input into the counting judgment module again through the square operation module and the modulo operation module. Each time after passing through the square operation module and the modulo operation module, the counting judgment module will add 1 to the count, and the m-bit data input of the modulo operation module is the first count. During the Zth count, it is necessary to judge whether the output result of the modulo operation module is 2. If so, it directly indicates an error output, and the error output is input into the result judgment module. If not, the output result of the modulo operation module is XORed with the 2-bit binary number 10, and the result is saved as parameter L. During the Yth count, it is necessary to judge whether the output result of the modulo operation module is 2. If not, it directly indicates an error output, and the error output is input into the result judgment module. If so, the parameter L is judged whether it is 1. If so, it directly indicates a correct output, and the correct output is input into the result judgment module. If not, the parameter L is input into the cyclic modulo operation module, wherein The data length of the key is m bits, and m in Z and Y corresponds to the key length.

[0014] Furthermore, the cyclic modulo operation module obtains intermediate parameters A and B after the irreducible polynomial parameter and parameter L are shifted by the most significant bit 1. The number of bits where the most significant bits 1 of A and B are located remains consistent, and XOR is performed to obtain parameter C. If C is 0 or 1, C is input into the result judgment module. Otherwise, it is determined whether C is less than B. If so, B is assigned the value P' and C is assigned the value L'. If not, C is assigned the value P' and B is assigned the value L'. P' and L' are shifted by the most significant bit 1 again, and the above operation is repeated until the final result is 0 or 1, and the result is transmitted to the result judgment module.

[0015] Furthermore, the result judgment module has a counting result input, and judges whether the counting result is wrong or correct. If the counting result is correct, it means that the input irreducible polynomial parameter meets the irreducible condition. If the counting result is wrong, it means that the input irreducible polynomial parameter does not meet the irreducible condition. The result judgment module does not have a counting result input, and judges based on the result input of the cyclic modulo operation module. If the result is 1, the irreducible polynomial parameter meets the irreducible condition. If the result is 0, the irreducible polynomial parameter does not meet the irreducible condition.

[0016] Furthermore, the irreducible polynomial parameters that meet the conditions are input into the hash algorithm unit, and the operation process of the hash algorithm unit is as follows: 1. The irreducible polynomial parameters and the key generate a Topelitz matrix; 2. The data to be encrypted is subjected to matrix operation with the matrix to obtain data H; 3. If all the data to be encrypted have undergone matrix operation, the hash value is output; if not all the data to be encrypted have undergone matrix operation, a new round of operation is performed; 4. In the new round of operation, the previous round H is used as the key data and the irreducible polynomial parameters to generate a new Topelitz matrix, and then the above operation process operations 2 and 3 are repeated. If all the data to be encrypted have undergone matrix operation, the hash value is output. If not all the data to be encrypted have undergone matrix operation, a new round of operation will be performed again; 5. The above operation is repeated until all the data to be encrypted have undergone matrix operation, and the obtained data H is the final hash calculation result of the data to be encrypted.

[0017] Beneficial effects of the present invention:

[0018] 1. The present invention can be divided into two parts. The first part is to generate irreducible polynomials based on FPGA; the second part is to implement the hash algorithm based on FPGA and the generated irreducible polynomials;

[0019] 2. The present invention can quickly generate irreducible polynomials, generating more than 10,000 irreducible polynomials every 0.4 seconds;

[0020] 3. The FPGA-based hash algorithm can quickly obtain the result of the hash algorithm (hash value) by relying on the FPGA's ultra-high computing speed;

[0021] 4. In the present invention, the hash algorithm built on the basis of irreducible polynomials is not only secure, but also because the irreducible polynomials in the system change with the input parameters, the structure of the hash algorithm and the FPGA circuit structure that implements the algorithm also change with each change in the input parameters, thus ensuring the security and anti-decryption characteristics of the system to the greatest extent;

[0022] 5. The present invention is a hardware system, which is essentially similar to a logic circuit. When data is input, the result is given. It does not have an operating system like software. It cannot use instructions to retrieve information about the algorithm in the system, nor can it be hosted by Trojan viruses and the like to intercept important information. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a simplified flow chart of a system for generating irreducible polynomials and hashing algorithms based on FPGA in the present invention;

[0024] Figure 2 It is a schematic diagram of the operation flow of irreducible polynomial unit;

[0025] Figure 3 This is a schematic diagram of the operation flow of the square operation module;

[0026] Figure 4 This is a schematic diagram of the modular operation module operation flow;

[0027] Figure 5 This is a schematic diagram of the operation flow of the counting and judgment module;

[0028] Figure 6 This is a schematic diagram of the operation flow of the cyclic modulo operation module;

[0029] Figure 7 This is a schematic diagram of the operation flow of the result judgment module;

[0030] Figure 8 Schematic diagram of the operation flow of the hash algorithm unit;

[0031] Figure 9 Flowchart for generating a Topelitz matrix based on a key and an irreducible polynomial. DETAILED DESCRIPTION

[0032] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0033] The key, irreducible polynomial parameters, the flag data bit for starting transmission, and the data to be encrypted are all written into the FPGA.

[0034] According to the pre-agreed address, the host computer writes the key, irreducible polynomial parameters, a data flag indicating the start of transmission, and the data to be encrypted into a storage space at a specific address. The present invention first writes the data to be encrypted into the FPGA's external DDR memory, and then writes the key, irreducible polynomial parameters, and a data flag indicating the start of transmission into the FPGA's internal dual-port BRAM. In the present invention, the data lengths of the data to be encrypted, the data flag indicating the start of transmission, the key, and the irreducible polynomial parameters can be selected. For example, the key can be 128 bits, the irreducible polynomial parameters can be 129 bits, and the data flag indicating the start of transmission can be 2 bits. The size of the data to be encrypted cannot exceed the DDR storage space. BRAM processes data quickly, but has a small storage capacity. For encrypting large amounts of data, storing data in DDR is more efficient.

[0035] like Figure 1 As shown, the system includes an irreducible polynomial unit and a hash algorithm unit. After detecting the flag data bit for starting transmission from the internal BRAM, the system extracts the irreducible polynomial parameters and inputs them into the irreducible polynomial unit. The irreducible polynomial unit judges the irreducible polynomial parameters. The irreducible polynomial parameters that meet the conditions are input into the hash algorithm unit. The input irreducible polynomial parameters, the key and the data to be encrypted read from the external DDR memory are calculated by the hash algorithm unit to finally output the resulting hash value.

[0036] like Figure 2 As shown, the irreducible polynomial unit includes a square operation module, a modulo operation module, a counting judgment module, a cyclic modulo operation module and a result judgment module. The square operation module performs a square operation on the input data; the modulo operation module performs a modulo operation on the input square operation module data and the input irreducible polynomial parameters; the counting judgment module is used to record the number of times the square operation module and the modulo operation module are passed and record the data results of a specific number of times according to the judgment result; the cyclic modulo operation module performs a cyclic modulo operation on the input counting judgment module data and the input irreducible polynomial parameters; the result judgment module judges whether the irreducible polynomial parameters meet the requirements. If they do not meet the requirements, the irreducible polynomial parameters are added with the number 2 and the irreducible polynomial unit operation is repeated until it is confirmed that the irreducible polynomial parameters meet the requirements.

[0037] The irreducible polynomial unit consists of five modules and can realize two main functions: 1. Determine the irreducible polynomial parameters. If the input parameter represents an irreducible polynomial, the result is output; 2. If the input parameter is not an irreducible polynomial parameter, the binary number 10 (that is, the number 2) is added to the parameter, and then the irreducible polynomial unit calculates and determines until the first irreducible polynomial parameter greater than the original parameter is obtained and output.

[0038] like Figure 2 As shown, the present invention will set a fixed parameter in the BRAM in advance. In the first round of operation, after the system receives the start signal, the square operation module will first extract the fixed parameter G of the preset address and perform a square operation. The length of the fixed parameter G is m bits. After the square operation of the fixed parameter G, a data X with a length of 2m bits is obtained. The data X will be transmitted to the modulus operation module. In the present invention, the key is selected as 128 bits, and the data length of the key is m bits, that is, the data length of the key is 128 bits, and the data length of the fixed parameter G is set to 128 bits and the value size is 2. 64 , the data length of data X is 256 bits and the value size is 2 128 .

[0039] like Figure 2 、 Figure 3 As shown, the square operation process is as follows: 1. Set parameter D; 2. Set parameter S; 3. Input the nth bit of parameter D and determine whether it is 0. If not, then the nth bit of S = D shifted left by n bits. If it is 0, then the nth bit of S = 0; 4. Then input the n+1th bit of parameter D and determine whether it is 0. If not, then the n+1th bit of S = D shifted left by n+1 bits. If it is 0, then the n+1th bit of S = 0; 5. Repeat the above operations for each bit of parameter D, and finally perform an XOR operation on the results of the bit calculations to obtain the final square result. In the first round of calculations in this system, parameter D is the fixed parameter G. Parameter D is m bits long, and parameter S is 2m bits long. Sn[2m] represents the data at the nth bit of parameter S, which is 2m bits long.

[0040] Here we take 8-bit data as an example and perform square operations as follows:

[0041]

[0042] Looking at the data being squared, bits 0, 1, 2, and 4 are all 1, and bit 3 is 0. Multiplying the data by these 0, 1, 2, and 4 gives 1, 2, 4, and 16 times the value, respectively. This corresponds to shifting the data left by 0, 1, 2, and 4 bits in binary. Since bit 3 is 0, the multiplication results are all 0. Finally, performing an XOR operation on the results of each bit calculation yields the final square result.

[0043] like Figure 4As shown, the modulo operation module performs a check on the 2m bits of data X to determine whether the upper m bits are all 0. If so, the lower m bits of data X are taken and input into the counting judgment module. If not, the input irreducible polynomial parameters are shifted and XORed. In the present invention, the data length of data X is 256 bits. The modulo operation module performs a check on the 256 bits of data X to determine whether the upper 128 bits are all 0.

[0044] like Figure 4 As shown, the irreducible polynomial parameter shift processing and XOR operation process is as follows: 1. Search the first data of data X from high to low that is 1; 2. Search the first data of the irreducible polynomial parameter from high to low that is 1; 3. Align the irreducible polynomial parameter with the highest bit 1 of data X and perform XOR operation, so that the data before the highest bit 1 of data X becomes 0, and the data after it generates a new data; 4. The generated new data will repeat the operation process 1-3 again until the high m bits of the generated new data X' are all 0; 5. The low m bits of data X' are taken as the result and input into the counting judgment module. In the present invention, the irreducible polynomial parameter shift processing and XOR operation are performed until the high 128 bits of the generated new data X' are all 0, and the low 128 bits of data X' are taken as the result and input into the counting judgment module. In the present invention, the 128th bit of the square number of the first input modulo operation module is 1, and the data is irreducible to the highest bit of the polynomial parameter XOR operation, then the data from 128 to 255 bits of X' are all 0, and the data from 0 to 127 bits are output.

[0045] like Figure 5 As shown, the input data of the counting judgment module will be input into the counting judgment module again through the square operation module and the modulus operation module. Each time after passing through the square operation module and the modulus operation module, the counting judgment module will add 1 to the count. After the m-bit data of the modulus operation module is input into the counting judgment module, the counting judgment module will judge the number of times of the square operation module and the modulus operation module. The first counting process is the m-bit data input of the modulus operation module and judges whether it is the first Hedi The result of the second time is not the first time. Hedi The result of the second count is then processed again by the square operation module and the modulus operation module, and then input into the counting judgment module again. This is the second counting process. Repeat the above operation until the The key in the present invention can be selected as 128 bits, and Where m corresponds to the key length, then is equal to 58, If the result is equal to 122, the 128-bit data of the modulo operation module is input into the counting judgment module. If it is determined that it is not the 58th and 122nd result, the 128-bit data will be input into the counting judgment module again through the square operation module and the modulo operation module until the 58th result.

[0046] like Figure 5 As shown, for The output result of the modulo operation module is judged. If it is 2, it directly indicates an error output, and the error output is input to the result judgment module; if it is not 2, the The output result of the modulo operation module is XORed with the 2-bit binary number 10 (ie, the number 2), and the result is saved as the parameter L. Count to the 58th time, and judge the 58th output result of the modulo operation module.

[0047] like Figure 5 As shown, the counting judgment module judges the number of times of the square operation module and the modulus operation module until the The results of the second The output of the modulo operation module is judged. If it is not 2, it directly indicates an error output and is input to the result judgment module. If it is 2, the parameter L is judged. If the parameter L is 1, it directly indicates a correct output and is input to the result judgment module. If the parameter L is not 1, the parameter L is input to the loop modulo operation module. Count to 122 times and judge the output of the 122nd modulo operation module.

[0048] like Figure 6 As shown, the irreducible polynomial parameters are extracted and input into the cyclic modulo operation module. The irreducible polynomial parameters and parameter L are modulo operated. After the irreducible polynomial parameters and parameter L are shifted by the highest bit 1, the intermediate parameters A and B are obtained. The number of bits of the highest bit 1 of A and B is consistent, and XOR is performed to obtain parameter C. It is judged whether C is 1 or 0. If C is 0 or 1, C is input into the result judgment module. If C is neither 0 nor 1, C is judged to determine whether C is less than B. If C is less than B, B is assigned the value P' and C is assigned the value L'. If C is not less than B, C is assigned the value P' and B is assigned the value L'. After the assignment is completed, P' and L' are equivalent to the irreducible polynomial parameters and parameter L and the modulo operation is performed again. The assignments in the subsequent modulo operation are also equivalent to the irreducible polynomial parameters and parameter L and the above-mentioned modulo operation is performed again until the final result is 0 or 1, and the result is transmitted to the result judgment module. Because the alignment process is similar to shifting the highest bit 1 of parameter L to the left, this left-shifted data can be regarded as the intermediate value B, and the first intermediate value B is equal to L.

[0049] like Figure 7As shown, the result judgment module has a counting result input, and judges whether the counting result is wrong or correct. If the counting result is correct, it means that the input irreducible polynomial parameter meets the irreducible condition. If the counting result is wrong, it means that the input irreducible polynomial parameter does not meet the irreducible condition. The result judgment module does not have a counting result input, and judges according to the result input of the cyclic modulo operation module. If the result is 1, the irreducible polynomial parameter meets the irreducible condition. If the result is 0, the irreducible polynomial parameter does not meet the irreducible condition.

[0050] like Figure 8 As shown, the irreducible polynomial parameters that meet the conditions are input into the hash algorithm unit, and the operation process of the hash algorithm unit is as follows: 1. The irreducible polynomial parameters and the key generate a Topelitz matrix; 2. The data to be encrypted is subjected to matrix operation with the matrix to obtain data H; 3. If all the data to be encrypted have undergone matrix operation, the hash value is output; if not all the data to be encrypted have undergone matrix operation, a new round of operation is performed; 4. In the new round of operation, the previous round H is used as the key data and the irreducible polynomial parameters to generate a new Topelitz matrix, and then the above operation processes 2 and 3 are repeated. If all the data to be encrypted have undergone matrix operation, the hash value is output. If not all the data to be encrypted have undergone matrix operation, a new round of operation is performed again; 5. The above operation is repeated until all the data to be encrypted have undergone matrix operation, and the obtained data H is the final hash calculation result of the data to be encrypted.

[0051] The present invention selects the data length for single calculation to be 64 bits, thus generating a 128*64 matrix. Here, it is assumed that the input key data is t1...t 128 , the irreducible polynomial is G(x)=x 29 +x 27 +x 2 +1, then the Topelitz matrix generation process is as follows Figure 9As shown. After generating the Topelitz matrix, take the 64-bit data to be encrypted and perform a matrix operation with the matrix to obtain a 128-bit data H. The obtained H is used to determine the length of the data to be encrypted, or in other words, to determine how many 64-bit data there are. If there are only 64 bits of data to be encrypted, or less than 64 bits but padded with zeros to 64 bits, H is the output hash value. If 64 bits are not all the data, a new round of operation is performed. In the new round of operation, the previous round H is used as the key data and the irreducible polynomial parameters to generate a new Topelitz matrix in the above manner. Then, the matrix is ​​used to perform a matrix operation with the data to be encrypted to obtain a new result H. The number of times the 64-bit data is passed through is counted until all the data, that is, all the 64-bit data, have undergone the matrix operation, and a 128-bit value H is obtained. This H is the final hash calculation result of the data to be encrypted.

[0052] The system of the present invention can be built on KINTEX-xc7k325. The circuit implemented with a 200M clock completes the encryption of 1G data and can complete all calculations and give results within 1 second. Compared with the algorithm flow composed of software, FPGA has a larger data bit width, and software is limited by the operating system, such as a 64-bit operating system. Each calculation process requires splicing 128 bits of data, and as the data bit width increases, the efficiency of the software implementation process will continue to decrease; secondly, to implement processes such as generating Topelitz, FPGA can operate in multiple threads and complete the calculation of the generating matrix within one clock; finally, during the calculation process, such as shifting, XOR and other calculations, the software needs to retrieve data, establish suffixes, etc., which will consume a lot of CPU resources, have high requirements on the computer CPU performance, and the difference in software compilers will also have different calculation efficiency. In summary, the generation polynomial and hash algorithm system based on FPGA has the characteristics of greater security and efficiency.

Claims

1. A system for generating irreducible polynomials and hashing algorithms based on FPGA, characterized in that: The system includes an irreducible polynomial unit and a hash algorithm unit. After detecting a flag data bit indicating the start of transmission, the system extracts irreducible polynomial parameters and inputs them into the irreducible polynomial unit. The irreducible polynomial unit judges the irreducible polynomial parameters. Irreducible polynomial parameters that meet the conditions are input into the hash algorithm unit. The irreducible polynomial parameters, the key, and the data to be encrypted are calculated by the hash algorithm unit and the hash value is finally output. The irreducible polynomial unit includes a square operation module, a modulo operation module, a counting and judging module, a cyclic modulo operation module and a result judging module. The square operation module performs a square operation on the input data; the modulo operation module performs a modulo operation on the input square operation module data and the input irreducible polynomial parameter; the counting and judging module is used to record the number of times the square operation module and the modulo operation module are passed and the data result of a specific number of times is recorded according to the judgment result; the cyclic modulo operation module performs a cyclic modulo operation on the input counting and judging module data and the input irreducible polynomial parameter; the result judging module judges whether the irreducible polynomial parameter meets the requirements. If it does not meet the requirements, the irreducible polynomial parameter is added with a number 2 and the irreducible polynomial parameter is judged again by the irreducible polynomial unit until it is confirmed that the irreducible polynomial parameter meets the requirements; The key data length is m bits. A fixed address parameter G is preset in the FPGA. The fixed parameter G is m bits long. After the fixed parameter G is squared, a data X with a length of 2m bits is obtained. The data X is transmitted to the modulo operation module. The modulo operation module performs a judgment on the 2m bits of data X to determine whether the high m bits of data are all 0. If so, the low m bits of data X are taken and input into the counting judgment module. If not, the input irreducible polynomial parameters are shifted and XORed.

2. The system for generating irreducible polynomials and hashing algorithms based on FPGA according to claim 1, characterized in that: The square operation process is as follows: set parameters S and D, and determine whether the n-th bit of parameter D is 0. If so, the n-th bit of parameter S is 0. If not, the n-th bit of parameter S is the data of parameter D shifted left by n bits. As above, each bit of parameter D is judged and operated, and finally the results of the bit calculations are XORed to obtain the final square result.

3. The system for generating irreducible polynomials and hashing algorithms based on FPGA according to claim 1, characterized in that: The irreducible polynomial parameter shift processing and XOR operation are as follows: the highest bit 1 of the irreducible polynomial parameter is aligned with the highest bit 1 of the data X, and an XOR operation is performed. The data following the highest bit 1 of the data X generates a new data. The new data is again aligned with the highest bit 1 of the irreducible polynomial parameter and an XOR operation is performed. The above operation is repeated until the high-order m bits of the generated new data X' are all 0, and the low-order m bits of the data X' are taken as the result and input into the counting judgment module.

4. The system for generating irreducible polynomials and hashing algorithms based on FPGA according to claim 3, characterized in that: The input data of the counting judgment module will be input into the counting judgment module again through the square operation module and the modulo operation module. Each time after passing through the square operation module and the modulo operation module, the counting judgment module will add 1 to the count. The m-bit data input of the modulo operation module is the first count. During the Zth count, it is necessary to judge whether the output result of the modulo operation module is 2. If so, it directly indicates an error output and inputs the error output into the result judgment module. If not, the output result of the modulo operation module is XORed with the 2-bit binary number 10, and the result is saved as parameter L. During the Yth count, it is necessary to judge whether the output result of the modulo operation module is 2. If not, it directly indicates an error output and inputs the error output into the result judgment module. If so, the parameter L is judged whether it is 1. If so, it directly indicates a correct output and inputs the correct output into the result judgment module. If not, the parameter L is input into the cyclic modulo operation module, where Z= ,Y=( ).

5. The system for generating irreducible polynomials and hashing algorithms based on FPGA according to claim 4, characterized in that: The cyclic modulo operation module obtains intermediate parameters A and B after shifting the irreducible polynomial parameters and parameter L by the highest bit 1. The number of bits where the highest bits 1 of A and B are located remains the same, and XOR is performed to obtain parameter C. If C is 0 or 1, C is input to the result judgment module. Otherwise, it is determined whether C is less than B. If so, B is assigned the value P' and C is assigned the value L'. If not, C is assigned the value P' and B is assigned the value L'. P' and L' are again shifted by the highest bit 1, and the above operation is repeated until the final result is 0 or 1, and the result is transmitted to the result judgment module.

6. The system for generating irreducible polynomials and hashing algorithms based on FPGA according to claim 5, characterized in that: The result judgment module has a counting result input, and judges whether the counting result is wrong or correct. If the counting result is correct, it means that the input irreducible polynomial parameter meets the irreducible condition. If the counting result is wrong, it means that the input irreducible polynomial parameter does not meet the irreducible condition. The result judgment module does not have a counting result input, and judges according to the result input of the circular modulo operation module. If the result is 1, the irreducible polynomial parameter meets the irreducible condition. If the result is 0, the irreducible polynomial parameter does not meet the irreducible condition.

7. The system for generating irreducible polynomials and hashing algorithms based on FPGA according to claim 1, characterized in that: The irreducible polynomial parameters that meet the requirements are input into the hash algorithm unit. The hash algorithm unit operates as follows:

1. The irreducible polynomial parameters and the key generate a Topelitz matrix; 2. The data to be encrypted is subjected to matrix operations with the matrix to obtain data H; 3. If all the data to be encrypted has undergone matrix operations, the hash value is output; if not all the data to be encrypted has undergone matrix operations, a new round of operations is performed.

4. In a new round of calculation, the previous round H is used as the key data and the irreducible polynomial parameter to generate a new Topelitz matrix. Then the above 2 and 3 operation processes are repeated. If all the data to be encrypted have undergone matrix operations, the hash value is output. If not all the data to be encrypted have undergone matrix operations, a new round of calculation will be performed again.

5. Repeat the above operations until all the data to be encrypted have undergone matrix operations. The data H obtained is the final hash calculation result of the data to be encrypted.

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