Memory and method of manufacturing the same, memory system

Abstract

The embodiments of the present disclosure disclose a memory, a manufacturing method thereof and a memory system. The memory has a first region and a second region, and comprises: a first semiconductor layer comprising a first part and a second part arranged side by side along a first direction; wherein the first part is located in the first region, and the second part is located in the second region; along a second direction, the length of the first part is less than the length of the second part; each memory cell comprises a first transistor; wherein the first transistor is located in the first region, and the channel of the first transistor extends along the second direction; a peripheral circuit located in the second region and coupled to the memory cell array, comprising: at least two second transistors; at least one isolation structure penetrating through the second part along the second direction and located between two adjacent second transistors, for electrically isolating the two adjacent second transistors; wherein along the second direction, the length of the isolation structure is greater than the length of the channel of the first transistor.

Description

[0001] Cross-reference to related applications

[0002] This application is based on PCT international applications: PCT / CN2021 / 115594, filed on August 31, 2021, entitled "MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME"; PCT / CN2021 / 115545, filed on August 31, 2021, entitled "MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME"; and PCT / CN2021 / 115652, filed on August 31, 2021, entitled "MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME". PCT international applications for "SAME"; PCT international application number PCT / CN2021 / 115704, filed on August 31, 2021, entitled "MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME"; PCT international application number PCT / CN2021 / 115743, filed on August 31, 2021, entitled "MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME"; PCT international application number PCT / CN2021 / 115775, filed on August 31, 2021, entitled "MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME". PCT international application for “SAME”; PCT international application with application number PCT / CN2021 / 115820, application date August 31, 2021, and invention title “MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME”;Application number PCT / CN2021 / 122022, filed on September 30, 2021, entitled "MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME," is filed and claims priority to the aforementioned PCT international application. The entire contents of the aforementioned PCT international application are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of integrated circuits, and more particularly to a memory and its manufacturing method, and a memory system. Background Technology

[0004] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication techniques. However, as the feature size of memory cells approaches its lower limit, planar processes and fabrication technologies become challenging and costly. Therefore, the storage density of planar memory cells is approaching its upper limit.

[0005] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture comprises a memory array and peripheral circuitry to facilitate its operation. As memory device size decreases and cell density increases, the interconnect structure between the memory array and peripheral circuitry becomes more complex, impacting associated circuit design and / or manufacturing processes. Summary of the Invention

[0006] According to a first aspect of the present disclosure, a memory is provided, the memory having a first region and a second region, the memory comprising:

[0007] A first semiconductor layer includes: a first portion and a second portion arranged side-by-side along a first direction; wherein the first portion is located in the first region and the second portion is located in the second region; along a second direction, the length of the first portion is less than the length of the second portion; the first direction is parallel to the plane in which the first semiconductor layer is located, and the second direction is perpendicular to the plane in which the first semiconductor layer is located;

[0008] A memory cell array includes: a plurality of memory cells arranged in an array, each memory cell including a first transistor and an energy storage element coupled to the first transistor; wherein the first transistor is located in a first region, and the channel of the first transistor extends along a second direction;

[0009] The peripheral circuitry, located in the second region and coupled to the memory cell array, includes at least two second transistors;

[0010] At least one isolation structure extends through the second portion along the second direction and is located between two adjacent second transistors for electrically isolating the two adjacent second transistors;

[0011] Wherein, along the second direction, the length of the isolation structure is greater than the length of the channel of the first transistor.

[0012] According to a second aspect of the present disclosure, a memory system is provided, comprising:

[0013] The memory described in any of the above embodiments is configured to store data;

[0014] A memory controller, coupled to the memory, is configured to control the memory.

[0015] According to a third aspect of the present disclosure, a method for manufacturing a memory is provided, the memory having a first region and a second region, the method comprising:

[0016] A first semiconductor layer is provided; wherein the first semiconductor layer includes a first portion and a second portion arranged side by side along a first direction; the first portion is located in a first region, and the second portion is located in a second region; the first direction is parallel to the plane in which the first semiconductor layer is located;

[0017] A memory cell array is formed; wherein the memory array includes a plurality of memory cells arranged in an array, each memory cell including a first transistor and an energy storage element coupled to the first transistor, the first transistor being located in a first region, and the channel of the first transistor extending along a second direction; the second direction is perpendicular to the plane where the first semiconductor layer is located;

[0018] A peripheral circuit is formed; wherein the peripheral circuit is located in the second region and coupled to the memory cell array; the peripheral circuit includes at least two second transistors;

[0019] At least one isolation structure is formed; wherein the isolation structure is located in the second portion and between two adjacent second transistors for electrically isolating the two adjacent second transistors; along the second direction, the length of the isolation structure is greater than the length of the channel of the first transistor;

[0020] The first portion is thinned on the side relatively away from the storage cell array; wherein, along the second direction, the length of the thinned first portion is less than the length of the second portion.

[0021] In this embodiment, by providing a first semiconductor layer, since the first portion of the first semiconductor layer is located in the first region of the memory and the second portion is located in the second region of the memory, and the length of the first portion is less than the length of the second portion along the second direction, even if the length of the isolation structure and the length of the first transistor channel are inconsistent, the isolation structure can be placed in the second portion, which is longer than the first portion. During the process of thinning the first portion to expose the channel of the first transistor, the isolation structure located in the second portion is hardly removed or the removed portion is very small and negligible, ensuring good electrical isolation performance of the isolation structure. Thus, the impact of the more complex interconnection structure between the memory array and peripheral circuits on the memory manufacturing process can be reduced, which is beneficial for better meeting the needs of memory size reduction and performance improvement. Attached Figure Description

[0022] Figure 1 This is a schematic diagram illustrating a method for manufacturing a memory according to an exemplary embodiment;

[0023] Figure 2 This is a flowchart illustrating a method for manufacturing a memory according to an embodiment of the present disclosure;

[0024] Figures 3 to 9 This is a schematic diagram of a method for manufacturing a memory according to an embodiment of the present disclosure;

[0025] Figure 10 This is a schematic diagram of the structure of a memory according to an embodiment of the present disclosure;

[0026] Figure 11 This is a partially enlarged view of a memory according to an embodiment of the present disclosure. Detailed Implementation

[0027] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0028] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0029] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0030] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0031] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0032] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0033] As memory technology advances, its size continues to shrink, moving towards a three-dimensional form. Current memory technologies, using buried gate technology, can achieve a 6F^2 structure. With increasing demands for size reduction and performance improvement, memory is gradually shifting towards a 4F^2 structure. This requires making the memory cell array a vertical structure and bringing the array out from the back. Wafer bonding and backside thinning technologies have become methods for realizing the 4F^2 structure.

[0034] Figure 1 This is a schematic diagram illustrating a method for manufacturing a memory according to an exemplary embodiment. (Refer to...) Figure 1 As shown, the fabrication method includes at least: bonding a first semiconductor structure and a substrate 102, and thinning the first semiconductor structure from the side of the first semiconductor structure that is relatively far from the substrate 102 to bring out the memory cell array.

[0035] The first semiconductor structure includes a substrate 101 and a memory cell array and peripheral circuitry located between the substrate 101 and the substrate 102. The substrate 101 includes a first region 101-1 and a second region 101-2 arranged side by side along the Y direction. The first region 101-1 is used to form the memory cell array, and the second region 101-2 is used to form the peripheral circuitry.

[0036] The memory cell array includes multiple memory cells, each memory cell including a first transistor 108 and an energy storage element coupled to the first transistor. The first transistor 108 is located in a first region 101-1, and the channel 110 of the first transistor extends along the Z direction. The peripheral circuitry includes at least two second transistors 112.

[0037] The first semiconductor structure further includes: at least one isolation structure 114 located in the second region 101-2 and between two adjacent second transistors 112 for electrically isolating the two adjacent second transistors 112; the length of the isolation structure 114 is greater than the length of the channel 110 along the Z direction.

[0038] For example, refer to Figure 1 As shown, the substrate 101 is thinned from the side of the substrate 101 that is relatively far away from the substrate 102 until the channel 110 of the first transistor 108 is exposed. The exposed channel 110 is doped to form a source (or drain) and a conductive structure electrically connected to the source is formed to bring out the memory cell array.

[0039] However, along the Z-direction, the length of the channel 110 of the first transistor 108 is typically on the nanometer scale, while the length of the isolation structure 114 is typically on the micrometer scale. Because the lengths of the channel 110 and the isolation structure 114 are not identical, during the thinning of the substrate 101 to expose the channel 110, the length of the channel 110... Figure 1 The isolation structure between the planes containing the two dashed lines is removed, which leads to a decrease in the electrical isolation performance of the isolation structure and affects the normal operation of the memory.

[0040] In view of this, the present disclosure provides a method for manufacturing a memory.

[0041] Figure 2 This is a flowchart illustrating a method for manufacturing a memory according to an embodiment of the present disclosure. The memory has a first region and a second region, as shown in the attached diagram. Figure 2 As shown, the method includes at least the following steps:

[0042] S100: A first semiconductor layer is provided; wherein the first semiconductor layer includes a first portion and a second portion arranged side by side along a first direction; the first portion is located in a first region, and the second portion is located in a second region; the first direction is parallel to the plane in which the first semiconductor layer is located;

[0043] S200: Forming a memory cell array; wherein the memory cell array includes a plurality of memory cells arranged in an array, each memory cell includes a first transistor and an energy storage element coupled to the first transistor, the first transistor is located in a first region, and the channel of the first transistor extends along a second direction; the second direction is perpendicular to the plane where the first semiconductor layer is located;

[0044] S300: Forming a peripheral circuit; wherein the peripheral circuit is located in the second region and coupled to the memory cell array; the peripheral circuit includes at least two second transistors;

[0045] S400: Form at least one isolation structure; wherein the isolation structure is located in the second part and between two adjacent second transistors for electrically isolating the two adjacent second transistors; along the second direction, the length of the isolation structure is greater than the length of the channel of the first transistor;

[0046] S500: Thinning the first part relative to the side of the memory cell array; wherein, along the second direction, the length of the thinned first part is less than the length of the second part.

[0047] In this embodiment, by thinning the side of the first portion relatively far from the memory cell array, even if the length of the isolation structure and the length of the first transistor channel are not the same, during the process of thinning the first portion to expose the channel of the first transistor, the isolation structure located in the second portion is hardly removed or the removed portion is very small and negligible, thus ensuring good electrical isolation performance of the isolation structure. This reduces the impact of the more complex interconnect structure between the memory array and peripheral circuits on the memory manufacturing process, and is beneficial for better meeting the needs of memory size reduction and performance improvement.

[0048] Furthermore, since the channel of the first transistor extends along a second direction perpendicular to the first semiconductor layer, a vertical memory cell array can be formed, thereby realizing a 4F^2 memory structure, which is beneficial to improving the integration and bit density of the memory.

[0049] Figures 3 to 9 This is a schematic diagram illustrating a method for manufacturing a memory according to an embodiment of this disclosure. The following will be combined with... Figure 2 , Figures 3 to 9 Further details will be provided regarding this disclosure.

[0050] First, refer to Figure 3 As shown, step S100 is performed: a first semiconductor layer 210 is provided; wherein, the first semiconductor layer 210 includes a first portion 2101 and a second portion 2102 arranged side by side along a first direction; the first portion 2101 is located in a first region 210-1, and the second portion 2102 is located in a second region 210-2; the first direction is parallel to the plane in which the first semiconductor layer 210 is located.

[0051] The constituent materials of the first semiconductor layer 210 include: elemental semiconductor materials (e.g., silicon, germanium), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. In this example, the first semiconductor layer 210 is single-crystal silicon.

[0052] The first region 210-1 and the second region 210-2 are arranged side by side along the Y direction. The first region 210-1 can be a region in the memory used to form a memory cell array, and the second region 210-2 can be a region in the memory used to form peripheral circuits.

[0053] In this disclosure, "Y direction" refers to the first direction, "Z direction" refers to the second direction, and "X direction" refers to the third direction. "Y direction" and "X direction" are parallel to the plane where the first semiconductor layer is located, and "Z direction" is perpendicular to the plane where the first semiconductor layer is located. This will not be repeated hereafter.

[0054] Secondly, combining Figures 3 to 5 As shown, step S200 is executed: forming a memory cell array; wherein, the memory cell array includes a plurality of memory cells arranged in an array, each memory cell includes a first transistor 230 and an energy storage element 240 coupled to the first transistor 230, the first transistor 230 is located in a first region 210-1, and the channel of the first transistor 230 extends along a second direction, the second direction being perpendicular to the plane where the first semiconductor layer is located.

[0055] For example, a memory cell array can be formed using processes such as thin film deposition, photolithography, and etching. The memory cell array is used for operations such as reading, writing, or erasing information. Although only a cross-sectional view of the memory cell array along the ZY plane is shown in the accompanying drawings, it should be understood that multiple memory cells are arranged in an array in the top view of the XY plane to form the memory cell array.

[0056] Thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof. Photolithography processes include, but are not limited to, I-line lithography, KrF lithography, ArF lithography, or immersion ArF lithography. Etching processes include, but are not limited to, dry etching, wet etching, or combinations thereof.

[0057] In one example, the memory cell array may be a Dynamic Random Access Memory (DRAM) cell array, the memory cells may be DRAM cells, and the energy storage element 240 may be a DRAM element. For example, the energy storage element 240 is a capacitor used to store charge.

[0058] In one example, the storage cell array may be a phase change memory (PCM) cell array, the storage cells may be phase change memory cells, and the energy storage element 240 may be a phase change memory element. For example, the energy storage element 240 stores information based on the difference in resistivity between the crystalline and amorphous phases of the phase change material (e.g., chalcogenide compounds).

[0059] In one example, the storage cell array can be a ferroelectric random access memory (FRAM) cell array, the storage cells can be ferroelectric random access memory cells, and the energy storage element 240 can be a ferroelectric random access memory element. For example, the energy storage element 240 stores information based on the switching between two polarization states of the ferroelectric material under the action of an external electric field.

[0060] In some embodiments, step S200 includes:

[0061] In the first region 210-1, a plurality of transistor pillars 231 extending along a second direction are formed; wherein, the transistor pillar 231 includes a first end 231a and a second end 231b opposite to each other along the second direction, and at least one side 231c located between the first end 231a and the second end 231b;

[0062] A gate structure 233 is formed on at least one side 231c of the transistor pillar 231.

[0063] For example, by etching the first portion 2101, a structure such as Figure 4 The diagram shows multiple transistor pillars 231 arranged in an array in the XY plane. The shape of the projection of each transistor pillar 231 in the XY plane includes: circle, ellipse, rectangle, or square, etc. The shape of the projection of each transistor pillar 231 in the ZY plane includes: rectangle, trapezoid, or inverted trapezoid, etc. It is understood that the constituent material of the transistor pillars 231 is the same as the constituent material of the first semiconductor layer.

[0064] For example, a gate dielectric structure 232 and a gate structure 233 are sequentially formed on the side surface 231c of the transistor pillar 231. The gate dielectric structure 232 is composed of an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The gate structure 233 is composed of a conductive material. The gate structure 233 can be a single film layer, such as tungsten metal or polycrystalline silicon, or it can be a composite film layer, such as... Figure 4As shown, the gate structure 233 includes an adhesion layer 2331 and a gate layer 2332. The adhesion layer 2331 is located between the gate dielectric structure 232 and the gate layer 2332, and is used to increase the adhesion between the gate dielectric structure 232 and the gate layer 2332. The materials constituting the adhesion layer 2331 include titanium nitride, tungsten nitride, or tantalum nitride, and the materials constituting the gate layer 2332 include tungsten, platinum, nickel, titanium, etc.

[0065] For example, the source or drain of the first transistor 230 is formed at the first end 231a, and the drain or source of the first transistor 230 is formed at the second end 231b. The gate structure 233 is electrically insulated from the source of the first transistor 230 and from the drain of the first transistor 230.

[0066] In some embodiments, forming a gate structure 233 on at least one side 231c of the transistor pillar 231 includes:

[0067] A gate dielectric structure 232 is formed on the side of the transistor pillar 231;

[0068] A gate structure 233 is formed covering at least one side of the gate dielectric structure 232; wherein the gate dielectric structure 232 is located between the transistor pillar 231 and the gate structure 233.

[0069] For example, the transistor pillar 231 includes a source, a channel, and a drain arranged side-by-side along the Z direction. The gate dielectric structure 232 completely covers the side of the channel, and the gate structure 233 covers at least one side of the gate dielectric structure 232. The following description assumes that the transistor pillar 231 is rectangular when projected onto the XY plane and rectangular when projected onto the ZY plane, and that the transistor pillar 231 includes at least four side surfaces located between the first end 231a and the second end 231b.

[0070] When the gate structure 233 covers only one side of the gate dielectric structure 232, a single-gate first transistor can be formed in the first region 210-1. When the gate structure 233 covers two sides of the gate dielectric structure 232 (including two opposite sides or two adjacent sides), a double-gate first transistor can be formed in the first region 210-1. When the gate structure 233 covers three sides of the gate dielectric structure 232, a triple-gate first transistor can be formed in the first region 210-1. When the gate structure 233 covers all four sides of the gate dielectric structure 232, a first transistor with a fully surrounding gate can be formed in the first region 210-1. In practical applications, the choice can be made according to design requirements, and this disclosure does not impose any limitations. Preferably, a first transistor with a fully surrounding gate is formed in the first region 210-1, which increases the control capability of the gate structure over the channel of the first transistor.

[0071] In one example, an ion implantation process or an ion diffusion process can be used to dope the first end 231a of the transistor pillar 231 to form a source (S) and the second end 231b of the transistor pillar 231 to form a drain (D).

[0072] In another example, an ion implantation process or an ion diffusion process can be used to dope the first end 231a of the transistor pillar 231 to form a drain, and to dope the second end 231b of the transistor pillar 231 to form a source.

[0073] Then, combine Figures 3 to 5 As shown, steps S300 and S400 are performed: forming a peripheral circuit; wherein the peripheral circuit is located at least in the second region 210-2 and coupled to the memory cell array; the peripheral circuit includes at least two second transistors 221;

[0074] At least one isolation structure 222 is formed; wherein the isolation structure 222 is located in the second part 2102 and between two adjacent second transistors 221, for electrically isolating the two adjacent second transistors 221; along the second direction, the length of the isolation structure 222 is greater than the length of the channel of the first transistor 230.

[0075] For example, refer to Figure 3 As shown, ion implantation or ion diffusion processes can be used to form a first doped region and a second doped region in the second portion 2102. The first doped region can serve as the source or drain of the second transistor 221, and the second doped region can serve as the drain or source of the second transistor 221. The second portion located between the first and second doped regions can serve as the channel of the second transistor 221. The depth of the first and / or second doped regions can be controlled by controlling the parameters of the ion implantation process (e.g., ion implantation time, ion implantation energy, etc.).

[0076] For example, a gate dielectric layer 234 covering a first semiconductor layer 210, a first doped region, and a second doped region, and a sacrificial layer 235 are sequentially formed by a thin film deposition process, and the gate of a second transistor 221 is formed in the sacrificial layer 235. Subsequently, an interconnect structure 250 electrically connected to the source, drain, and gate of the second transistor 221 is formed to couple the peripheral circuit to the memory cell array.

[0077] For example, the sacrificial layer 235, the gate dielectric layer 234, and the second region 210-2 are etched downward along the Z direction to form a plurality of isolation trenches arranged side by side along the Y direction. At least one isolation trench is located between two adjacent second transistors 221. The isolation trenches are filled with insulating material to form an isolation structure 222 for electrically isolating two adjacent second transistors 221.

[0078] In one example, along the Z-direction, the plane containing the top of the isolation trench is above the plane containing the top of the transistor pillar 231, and the plane containing the bottom of the isolation trench is below the plane containing the bottom of the transistor pillar 231. For example, the plane containing the top of the isolation trench is substantially flush with the surface of the sacrificial layer 235 that is relatively far from the first semiconductor layer 210.

[0079] It should be noted that, along the Z direction, the length of the isolation structure 222 in the second region 210-2 is typically on the micrometer scale, and the length of the transistor pillar 231 in the first region 210-1 is typically on the nanometer scale. Therefore, the plane at the bottom of the isolation trench is located below the plane at the bottom of the transistor pillar 231.

[0080] In one example, the conductivity type of the second transistor 221 is controlled by controlling the type of dopant particles (e.g., P-type or N-type dopant particles). The second transistor 221 can be either a P-type or N-type transistor. Figure 5 The diagram shows two second transistors 221 arranged side by side along the Y direction. It should be understood that the number of second transistors 221 is not limited to two, but can also be three, four or even more.

[0081] In some embodiments, combined with Figure 4 and Figure 5 As shown, step S200 includes:

[0082] A first dielectric layer 255 is formed covering the first transistor 230;

[0083] A plurality of energy storage elements 240 are formed in the first dielectric layer 255; wherein each energy storage element 240 includes a first electrode layer 241, an energy storage structure 242 and a second electrode layer 243, the energy storage structure 242 being located between the first electrode layer 241 and the second electrode layer 243; the first electrode layer 241 is coupled to the first transistor 230, and the second electrode layer 243 is coupled to the peripheral circuit or ground terminal.

[0084] Exemplarily, a first dielectric sublayer is formed covering the sacrificial layer 235 and the first transistor 230. A plurality of first electrode layers 241 are formed in the first dielectric sublayer, each first electrode layer 241 being coupled to the drain (or source) of the first transistor 230. A second dielectric sublayer is formed covering the first dielectric sublayer and the first electrode layers 241. A plurality of energy storage structures 242 are formed in the second dielectric sublayer, each energy storage structure 242 having one end coupled to the first electrode layer 241. A third dielectric sublayer is formed covering the second dielectric sublayer and the energy storage structures 242. A plurality of second electrode layers 243 are formed in the third dielectric sublayer, each second electrode layer 243 being coupled to the other end of the energy storage structure 242.

[0085] Here, the first dielectric layer 255 includes the aforementioned first dielectric sublayer, second dielectric sublayer, and third dielectric sublayer. The constituent material of the first dielectric layer 255 includes an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The constituent materials of any two of the first dielectric sublayer, second dielectric sublayer, and third dielectric sublayer may be the same or different. In this example, the first dielectric sublayer, second dielectric sublayer, and third dielectric sublayer are silicon oxide.

[0086] In one example, the second electrode layer 243 is coupled to the peripheral circuitry via interconnect structure 250. In another example, the second electrode layer 243 is coupled to the ground terminal via other interconnect structures (not shown).

[0087] Finally, combining Figures 5 to 8 As shown, step S500 is performed: the first part 2101 is thinned on the side relatively away from the memory cell array; wherein, along the second direction, the length of the thinned first part 2101 is less than the length of the second part 2102.

[0088] In some embodiments, the first semiconductor layer 210 includes: a first surface 210a and a second surface 210b disposed opposite to each other; after forming the isolation structure 222 and before thinning the first portion 2101, the above fabrication method further includes:

[0089] A first dielectric layer 255 is formed to cover the peripheral circuit and the isolation structure 222; wherein the first dielectric layer 255 is relatively close to the first surface 210a;

[0090] An interconnect structure 250 is formed in the first dielectric layer 255; wherein the interconnect structure 250 is coupled to the peripheral circuit.

[0091] For example, refer to Figure 5 As shown, after forming the peripheral circuit, a fourth dielectric sublayer is formed covering the sacrificial layer and the gate of the second transistor 221, and a plurality of first conductive pillars 251 are formed that penetrate at least through the fourth dielectric sublayer. For example, the first first conductive pillar 251 penetrates the fourth dielectric sublayer, the sacrificial layer, and the gate dielectric layer 234, and is electrically connected to the source of the second transistor 221; the second first conductive pillar 251 penetrates the fourth dielectric sublayer, the sacrificial layer, and the gate dielectric layer, and is electrically connected to the drain of the second transistor 221; and the third first conductive pillar 251 penetrates the fourth dielectric sublayer and is electrically connected to the gate of the second transistor 221.

[0092] Exemplarily, a fifth dielectric sublayer is formed covering a fourth dielectric sublayer and a plurality of first conductive pillars 251. A plurality of first conductive lines 252 are formed in the fifth dielectric sublayer, with one end of each first conductive line 252 coupled to a first conductive pillar 251. A sixth dielectric sublayer is formed covering the fifth dielectric sublayer and the plurality of first conductive lines 252. A plurality of second conductive pillars 253 are formed in the sixth dielectric sublayer, with each second conductive pillar 253 coupled to the other end of a first conductive line 252. A seventh dielectric sublayer is formed covering the sixth dielectric sublayer and the plurality of second conductive pillars 253. A plurality of second conductive lines 254 are formed in the seventh dielectric sublayer, with each second conductive line 254 coupled to at least one second conductive pillar 253.

[0093] Here, the first dielectric layer 255 further includes the aforementioned fourth dielectric sublayer, fifth dielectric sublayer, sixth dielectric sublayer, and seventh dielectric sublayer. The constituent materials of any two of the fourth, fifth, sixth, and seventh dielectric sublayers may be the same or different. In this example, the fourth, fifth, sixth, and seventh dielectric sublayers are silicon oxide.

[0094] The interconnect structure 250 includes the first conductive post 251, the first conductive line 252, the second conductive post 253, and the second conductive line 254. The interconnect structure 250 is composed of conductive materials, such as tungsten, copper, aluminum, platinum, titanium, and nickel. The materials of any two of the first conductive post 251, the first conductive line 252, the second conductive post 253, and the second conductive line 254 can be the same or different. In this example, the first conductive post 251, the first conductive line 252, and the second conductive post 253 are tungsten, and the second conductive line 254 is copper.

[0095] In some embodiments, after forming the isolation structure 222 and before thinning the first portion 2101, the method further includes:

[0096] The first semiconductor layer 210 and the substrate 202 are bonded together; wherein the memory cell array and peripheral circuits are located between the substrate 202 and the first semiconductor layer 210.

[0097] Step S500 includes:

[0098] Thinning is performed on the side of the first semiconductor layer 210 that is relatively far from the substrate 202;

[0099] After the thinning process, an etching process is performed on the side of the first portion 2101 that is relatively far away from the substrate 202.

[0100] The first dielectric layer 255 also includes an eighth dielectric sublayer covering the third dielectric sublayer, the second electrode layer 243, the seventh dielectric sublayer, and the second conductive line 254. The eighth dielectric sublayer may be silicon oxide.

[0101] For example, refer to Figure 5 As shown, an eighth dielectric material layer is formed covering the third dielectric sublayer, the second electrode layer 243, the seventh dielectric sublayer, and the second conductive line 254, and the eighth dielectric material layer is planarized to form the eighth dielectric sublayer. The substrate 202 is bonded to the first semiconductor layer 210 to form... Figure 6 The structure is shown. Specifically, substrate 202 is surface-bonded to the eighth dielectric sublayer after planarization, such that the memory cell array and peripheral circuitry are located between substrate 202 and the first semiconductor layer 210. Substrate 202 is used to protect the memory cell array and peripheral circuitry during the thinning of the first region 210-1.

[0102] In one specific example, the substrate 202 and the first semiconductor layer 210 can be bonded together using bonding adhesive. In another specific example, the substrate 202 and the first semiconductor layer 210 can be bonded together using a hybrid bonding method.

[0103] For example, refer to Figure 6 As shown, the first semiconductor layer 210 can be thinned from the second surface 210b to reduce the thickness of the first semiconductor layer 210, and then an etching process is performed on the first portion 2101 to expose the first transistor. Here, by first thinning and removing part of the first semiconductor layer, and then etching the first portion 2101, a thinning process and an etching process are combined.

[0104] In some embodiments, the above-described thinning process on the side of the first semiconductor layer 210 relatively far from the substrate 202 includes: performing a thinning process on the side of the first semiconductor layer 210 relatively far from the substrate to expose the isolation structure. (Refer to...) Figure 6 As shown, the first semiconductor layer 210 is planarized from its second surface 210b to form a structure as shown in the figure. Figure 7 The structure shown, although in Figure 7 In the example shown, the ends of the isolation structure 222 are exposed after the thinning process. However, it should be emphasized that this thinning process is used to reduce the thickness of the first semiconductor layer (i.e., its length along the Z direction) to reduce the size of the memory along the Z direction, and is not necessarily used to expose the isolation structure 222. Here, the thinning process can be a planarization process, including mechanical polishing or chemical mechanical polishing, etc.

[0105] In other examples, the isolation structure 222 includes a first end (relatively far from the second surface) and a second end (relatively close to the second surface) disposed opposite each other along the Z direction. The second end of the isolation structure 222 is not exposed after the thinning process, depending on the planarization process conditions.

[0106] For example, after the thinning process, a patterned photoresist layer (not shown) is formed covering the second portion 2102 and the isolation structure 222. The side of the first portion 2101 that is relatively away from the substrate 202 is etched to form a patterned photoresist layer (not shown). Figure 8 The structure shown is as follows. Here, the second part 2102 is not etched, and along the Z direction, the length of the second part 2102 is greater than the length of the etched first part.

[0107] For example, refer to Figure 8 As shown, after etching, the second end of transistor pillar 231 is doped to form the source or drain of the first transistor.

[0108] Compared to etching away only the side of the first portion that is relatively far from the substrate, the present embodiment uses a process that combines thinning and etching, which helps to save on the manufacturing cost of the memory.

[0109] In addition, during the thinning process, simultaneously thinning the side of the first and second regions that is relatively far from the substrate can reduce the vertical dimensions of the memory, which is beneficial for improving the integration and bit density of the memory.

[0110] In some embodiments, after thinning the first portion 2101, the above manufacturing method further includes:

[0111] A second dielectric layer 263 is formed covering the first semiconductor layer 210, the isolation structure 222, and the first transistor 230; wherein the second dielectric layer 263 is relatively close to the second surface;

[0112] A first conductive structure 260 is formed in the second dielectric layer 263; wherein, the first conductive structure 260 includes a first conductive layer 261 and a first contact plug 262; the first conductive layer 261 is located in the second dielectric layer 263; the first contact plug 262 penetrates a portion of the second dielectric layer 263 and the second portion 2102, and is located between the first conductive layer 261 and the interconnect structure 250, for coupling the first conductive layer 261 and the interconnect structure 250.

[0113] In some embodiments, combined with Figure 8 and Figure 9As shown, the formation of the first conductive structure 260 includes: forming a ninth dielectric sublayer covering the second portion 2102 and the isolation structure 222; forming a first contact via penetrating the ninth dielectric sublayer and the second portion 2102; forming a first electrical isolation layer covering the sidewall of the first contact via; filling the first contact via with the first electrical isolation layer with conductive material to form a first contact plug 262; forming a tenth dielectric sublayer covering the ninth dielectric sublayer, the first electrical isolation layer and the first contact plug 262; forming a first opening penetrating the tenth dielectric sublayer, the first opening exposing the first contact plug 262; and forming a first conductive layer 261 filling the first opening.

[0114] Here, the second dielectric layer 263 includes the aforementioned ninth and tenth dielectric sublayers. The constituent materials of the second dielectric layer 263 include insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride. The constituent materials of the ninth and tenth dielectric sublayers may be the same or different; in this example, the ninth and tenth dielectric sublayers are silicon oxide.

[0115] The first electrical isolation layer is composed of insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride, and is used to electrically isolate the first contact plug 262 and the second part 2102.

[0116] The first conductive layer 261 is coupled to the interconnect structure 250 through the first contact plug 262. Specifically, the first conductive layer 261 is electrically connected to the first conductive post 251 through the first contact plug 262.

[0117] The first conductive layer 261 and the first contact plug 262 are composed of conductive materials, such as tungsten, copper, aluminum, platinum, titanium, nickel, etc. In this example, the first conductive layer 261 is copper and the first contact plug 262 is tungsten.

[0118] In this embodiment of the present disclosure, by forming an interconnect structure coupled to the peripheral circuit in the first dielectric layer, and the first dielectric layer being relatively close to the first surface, and forming a first conductive structure including a first conductive layer and a first contact plug, since the first conductive layer is located in the second dielectric layer and the second dielectric layer is relatively close to the second surface, the first contact plug penetrates a portion of the second dielectric layer and the second portion, and is electrically connected to the first conductive layer and the interconnect structure respectively, the memory cell array can be led out from the back side of the first semiconductor layer (i.e., the second surface), thereby meeting the requirements of size reduction and performance improvement, which is beneficial to realizing a 4F^2 structure memory and improving the integration and operation performance of the memory.

[0119] In some embodiments, the above manufacturing method further includes:

[0120] A second conductive structure 270 is formed in the second dielectric layer 263; wherein, the second conductive structure 270 includes a second conductive layer 271 and a second contact plug 272; the second conductive layer 271 is located in the second dielectric layer 263 and is arranged side by side with the first conductive layer 261 along a first direction; the second contact plug 272 penetrates a portion of the second dielectric layer 263 and the second portion 2102, and is located between the second conductive layer 271 and the interconnect structure 250, for coupling the second conductive layer 271 and the interconnect structure 250;

[0121] Bit lines 273 are formed in the second dielectric layer 263; wherein, bit lines 273 are coupled to the second conductive layer 271 and the first transistor 230, respectively.

[0122] For example, the aforementioned ninth dielectric sublayer also covers the first transistor 230, and a bit line 273 electrically connected to the first transistor 230 is formed in the ninth dielectric sublayer covering the first transistor 230 (e.g., ...). Figure 9 (As shown).

[0123] In one example, multiple bit lines 273 arranged side-by-side along a third direction (i.e., the X direction) can be formed in the ninth dielectric sublayer, each bit line 273 extending along a first direction (i.e., the Y direction). Figure 9 As shown, bit line 273 is electrically connected to a plurality of first transistors 230 arranged in parallel along the Y direction, and the plurality of first transistors share bit line 273 extending along the Y direction.

[0124] In one example, a plurality of bit lines arranged side-by-side along a first direction (i.e., the Y direction) may be formed in the ninth dielectric sublayer, each bit line extending along a third direction (i.e., the X direction). The bit lines are electrically connected to a plurality of first transistors arranged side-by-side along the X direction, the plurality of first transistors sharing the bit lines extending along the X direction.

[0125] For example, a second contact via is formed through the ninth dielectric sublayer and the second portion 2102, and the second contact via is arranged side by side with the first contact via along a first direction; a second electrical isolation layer is formed covering the sidewall of the second contact via; a conductive material is filled into the second contact via to form a second contact plug 272, and the second electrical isolation layer is used to electrically isolate the second contact plug 272 and the second portion 2102.

[0126] Here, the first contact through hole and the second contact through hole can be formed simultaneously or separately, the first electrical isolation layer and the second electrical isolation layer can be formed simultaneously or separately, and the first contact plug 262 and the second contact plug 272 can be formed simultaneously or separately. This disclosure does not impose any restrictions on these aspects.

[0127] Preferably, the first contact via and the second contact via are formed simultaneously, the first electrical isolation layer and the second electrical isolation layer are formed simultaneously, the first contact plug 262 and the second contact plug 272 are formed simultaneously, the first electrical isolation layer and the second electrical isolation layer are made of the same material, and the first contact plug 262 and the second contact plug 272 are made of the same material. This reduces the number of manufacturing steps in the memory and saves manufacturing costs.

[0128] For example, a third contact via is formed through the ninth dielectric sublayer, with exposed bit line 273; wherein the third contact via is arranged side-by-side with the first and second contact vias along a first direction, and the second contact via is located between the first and third contact vias; a conductive material is filled into the third contact via to form a third contact plug. The composition of the third contact plug may be the same as that of the first contact plug 262 and the second contact plug 272.

[0129] For example, the tenth dielectric sublayer further covers the second contact plug 272 and the third contact plug, forming a second opening through the tenth dielectric sublayer. The second opening is arranged side by side with the first opening along the first direction, and the second opening exposes the second contact plug 272 and the third contact plug; a second conductive layer 271 is formed to fill the second opening.

[0130] Here, the first opening and the second opening can be formed simultaneously or separately, and the first conductive layer 261 and the second conductive layer 271 can be formed simultaneously or separately; this disclosure does not impose any limitations. Preferably, the first opening and the second opening are formed simultaneously, the first conductive layer 261 and the second conductive layer 271 are formed simultaneously, and the first conductive layer 261 and the second conductive layer 271 are made of the same material. This reduces the number of fabrication steps in the memory and saves manufacturing costs.

[0131] In this embodiment of the present disclosure, by forming a bit line coupled to the first transistor in the second dielectric layer, and forming a second conductive structure including a second conductive layer and a second contact plug, since the second conductive layer is located in the second dielectric layer and coupled to the bit line, and the second contact plug penetrates a portion of the second dielectric layer and the second portion, and is electrically connected to the second conductive layer and the interconnect structure respectively, the first transistor can be made into a vertical structure, and thus the memory cell array can be made into a vertical structure, which is beneficial to realize a 4F^2 structure memory and improve the integration and operation performance of the memory.

[0132] In some embodiments, refer to Figure 9 As shown, the above manufacturing method also includes:

[0133] A third dielectric layer is formed covering the first conductive structure 260, the second conductive structure 270, and the second dielectric layer 263;

[0134] A pad structure coupled to the first conductive structure 260 is formed in the third dielectric layer; wherein the pad structure includes solder balls 281 and pads 282; the solder balls 281 are located between the first conductive structure 260 and the pads 282 for coupling the first conductive structure 260 and the pads 282.

[0135] Here, since the first conductive structure is coupled to both the interconnect structure and the pad structure, the pad structure can lead out peripheral circuits through the first conductive structure and the interconnect structure. Since the second conductive structure is coupled to both the interconnect structure and the bit line, the peripheral circuit can apply electrical signals to the bit line through the interconnect structure and the second conductive structure.

[0136] The solder balls 281 and pads 282 are made of conductive materials, such as tungsten, copper, aluminum, platinum, titanium, nickel, etc. In this example, the solder balls 281 and pads 282 are made of aluminum.

[0137] Figure 10 and Figure 11 This is a schematic diagram of the structure of a memory 300 according to an embodiment of the present disclosure. Figure 10 This is a cross-sectional view of memory 300. Figure 11 This is a magnified view of a portion of memory 300, combined with... Figure 10 and Figure 11 As shown, the memory has a first region 310-1 and a second region 310-2, and the memory 300 includes:

[0138] The first semiconductor layer 310 includes: a first portion 3101 and a second portion 3102 arranged side by side along a first direction; wherein the first portion 3101 is located in a first region 310-1, and the second portion 310-2 is located in a second region 310-2; along a second direction, the length of the first portion 3101 is less than the length of the second portion 3102; the first direction is parallel to the plane on which the first semiconductor layer 310 is located; and the second direction is perpendicular to the plane on which the first semiconductor layer 310 is located.

[0139] The memory cell array includes: a plurality of memory cells arranged in an array, each memory cell including a first transistor 330 and an energy storage element 340 coupled to the first transistor 330; wherein the first transistor 330 is located in a first region 310-1, and the channel 331 of the first transistor 330 extends along a second direction.

[0140] The peripheral circuitry, located in the second region 310-2 and coupled to the memory cell array, includes at least two second transistors 321.

[0141] At least one isolation structure 322 extends through the second portion 3102 along the second direction and is located between two adjacent second transistors 321 for electrically isolating the two adjacent second transistors 321;

[0142] Along the second direction, the length of the isolation structure 322 is greater than the length of the channel 331 of the first transistor 330.

[0143] Reference Figure 10 As shown, the memory 300 includes a first region 310-1 and a second region 310-2. The first region 310-1 may be a portion of the memory 300 used to set up a memory cell array, which is configured to read, write, or erase information. The second region 310-2 may be a portion of the memory 300 used to set up peripheral circuitry, which is configured to perform logical operations (e.g., read, write, or erase operations) on the memory cell array.

[0144] Although only the first region 310-1 and the second region 310-2 are shown in the figure, the memory 300 may also include other regions for setting up test structures (Testkey) and / or setting up cutting tracks, etc.

[0145] The first semiconductor layer 310 includes a first portion 3101 and a second portion 3102 arranged side by side along the Y direction. The first portion 3101 is located in the first region 310-1, and the second portion 3102 is located in the second region 310-2.

[0146] In some embodiments, the first surface of the first portion 3101 is substantially flush with the first surface of the second portion 3102, and the second surface of the first portion 3101 is not flush with the second surface of the second portion 3102. Here, the first surface is relatively close to the memory cell array or peripheral circuitry, and the second surface is relatively far from the memory cell array or peripheral circuitry.

[0147] The first surface of the first part 3101 is substantially flush with the first surface of the second part 3102, including: the first surface of the first part 3101 is completely flush with the first surface of the second part 3102, or the distance between the first surface of the first part 3101 and the first surface of the second part 3102 is very small and negligible.

[0148] The fact that the second surface of the first part 3101 is not flush with the second surface of the second part 3102 means that the distance between the second surface of the first part 3101 and the first surface of the first part 3101 is smaller than the distance between the second surface of the second part 3102 and the first surface of the second part 3102.

[0149] It should be pointed out that, although Figure 10 The image only shows a cross-sectional view of the memory cell array along the ZY plane, but it should be understood that the top view of multiple memory cells in the XY plane is an array arrangement.

[0150] The first transistor 330 includes a source 334, a channel 331, a drain 335, and a gate structure 333 located on at least one side 331c of the channel 331, arranged side-by-side along the Z direction. The channel 331 extends along the Z direction, and its shape projected onto the XY plane includes: a circle, an ellipse, a rectangle, or a square, etc. The shape projected onto the ZY plane or ZX plane includes: a rectangle, a trapezoid, or an inverted trapezoid, etc. It should be understood that the first part 3101 includes the source 334, the channel 331, and the drain 335 of the first transistor 330.

[0151] The first transistor 330 further includes a gate dielectric structure 332 located on a side 331c of the channel 331; wherein the gate dielectric structure 332 is located between the channel 331 and the gate structure 333. The gate structure 333 covers at least one side of the gate dielectric structure 332.

[0152] The gate dielectric structure 332 is composed of insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride. The gate structure 333 is composed of conductive materials. The gate structure 333 can be a single film layer, such as tungsten metal or polycrystalline silicon, or it can be a composite film layer, such as… Figure 11 As shown, the gate structure 333 includes an adhesion layer 3331 and a gate layer 3332. The adhesion layer 3331 is located between the gate dielectric structure 332 and the gate layer 3332, and is used to increase the adhesion between the gate dielectric structure 332 and the gate layer 3332. The materials comprising the adhesion layer 3331 include titanium nitride, tungsten nitride, or tantalum nitride, and the materials comprising the gate layer 3332 include tungsten, platinum, nickel, titanium, etc.

[0153] In one example, the peripheral circuitry is located in the second region 310-2 and includes at least two second transistors 321, for example, Figure 10 The two second transistors 321 are arranged side-by-side along the Y direction. Although Figure 10 Only two second transistors 321 are shown, but the number of second transistors in the peripheral circuit is not limited to two; it can also be three, four, or even more. The second transistors 321 include P-type transistors or N-type transistors.

[0154] The isolation structure 322 is located between two adjacent second transistors 321 for electrically isolating the two adjacent second transistors 321; the isolation structure 322 is also located between the second transistors 321 and the first transistor 330 for electrically isolating the second transistors 321 and the first transistor 330.

[0155] Along the Z direction, the length (L1) of the channel 331 is less than or equal to the length (H1) of the first part 3101, i.e., L1≤H1. The length (L2) of the isolation structure 322 is greater than or equal to the length (H2) of the second part 3102, i.e., L2≥H2. Since H1 is less than H2, the length of the isolation structure 322 is greater than the length of the channel 331 along the Z direction.

[0156] The constituent materials of the first semiconductor layer 310 include: elemental semiconductor materials (e.g., silicon, germanium), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. In this example, the first semiconductor layer 310 is single-crystal silicon.

[0157] In this embodiment, by providing a first semiconductor layer, since the first portion of the first semiconductor layer is located in the first region of the memory and the second portion is located in the second region of the memory, and the length of the first portion is less than the length of the second portion along the second direction, even if the length of the isolation structure and the length of the first transistor channel are inconsistent, the isolation structure can be placed in the second portion, which is longer than the first portion. During the process of thinning the first portion to expose the channel of the first transistor, the isolation structure located in the second portion is hardly removed or the removed portion is very small and negligible, ensuring good electrical isolation performance of the isolation structure. Thus, the impact of the more complex interconnection structure between the memory array and peripheral circuits on the memory manufacturing process can be reduced, which is beneficial for better meeting the needs of memory size reduction and performance improvement.

[0158] In some embodiments, the end of the isolation structure 322 that is relatively close to the peripheral circuit is substantially flush with the end of the first transistor 330 that is relatively close to the peripheral circuit.

[0159] In one example, the end of the first transistor 330 that is relatively closer to the peripheral circuit can be the drain of the first transistor, and the end of the first transistor 330 that is relatively farther away from the peripheral circuit can be the source of the first transistor. The end of the isolation structure 322 that is relatively closer to the peripheral circuit is substantially flush with the drain of the first transistor 330.

[0160] In another example, the end of the first transistor 330 that is relatively closer to the peripheral circuit can be the source of the first transistor, and the end of the first transistor 330 that is relatively farther away from the peripheral circuit can be the drain of the first transistor. The end of the isolation structure 322 that is relatively closer to the peripheral circuit is substantially flush with the source of the first transistor 330.

[0161] Here, the statement that the end of the isolation structure that is relatively close to the peripheral circuit is basically flush with the end of the first transistor that is relatively close to the peripheral circuit includes: the end of the isolation structure that is relatively close to the peripheral circuit is completely flush with the end of the first transistor that is relatively close to the peripheral circuit, or the distance between the end of the isolation structure that is relatively close to the peripheral circuit and the end of the first transistor that is relatively close to the peripheral circuit is very small and can be ignored.

[0162] In some embodiments, the first transistor 330 includes at least one of the following: a full-around gate transistor; a tri-gate transistor; a dual-gate transistor; and a single-gate transistor. The following description uses an example where the channel 331 is rectangular when projected onto the XY plane and rectangular when projected onto the ZY and ZX planes, and the channel 331 includes four sides located between the source 334 and the drain 335.

[0163] For example, the gate structure 333 covers only one side of the gate dielectric structure 332, and the first transistor 330 is a single-gate transistor. For example, the gate structure 333 covers two sides of the gate dielectric structure 332 (including two opposite sides or two adjacent sides), and the first transistor 330 is a dual-gate transistor. For example, the gate structure 333 covers three sides of the gate dielectric structure 332, and the first transistor 330 is a tri-gate transistor. For example, the gate structure 333 covers all four sides of the gate dielectric structure 332, and the first transistor 330 is a full-around-gate transistor. In practical applications, the selection can be made according to design requirements, and this disclosure does not impose any limitations. Preferably, the first transistor 330 is a full-around-gate transistor, which increases the control capability of the gate structure over the channel of the first transistor.

[0164] In some embodiments, the energy storage element 340 includes at least one of the following: a dynamic random access memory (DRAM); a phase change memory (PCM); and a ferroelectric random access memory (FRAM).

[0165] In one example, the memory cell array may be a Dynamic Random Access Memory (DRAM) cell array, the memory cells may be DRAM cells, and the energy storage element 340 may be a DRAM element. For example, the energy storage element 340 is a capacitor used to store charge.

[0166] In one example, the storage cell array may be a phase change memory (PCM) cell array, the storage cells may be phase change memory cells, and the energy storage element 340 may be a phase change memory element. For example, the energy storage element 340 stores information based on the difference in resistivity between the crystalline and amorphous phases of the phase change material (e.g., chalcogenide compounds).

[0167] In one example, the storage cell array can be a ferroelectric random access memory (FRAM) cell array, the storage cells can be ferroelectric random access memory cells, and the energy storage element 340 can be a ferroelectric random access memory element. For example, the energy storage element 340 stores information based on the switching between two polarization states of the ferroelectric material under the action of an external electric field.

[0168] In some embodiments, refer to Figure 10 As shown, the first semiconductor layer 310 includes: a first surface 310a and a second surface 310b disposed opposite to each other; the memory 300 further includes:

[0169] The first dielectric layer 355 covers the peripheral circuit and the isolation structure 322; wherein the first dielectric layer 355 is relatively close to the first surface 310a;

[0170] The second dielectric layer 363 covers the first semiconductor layer 310, the isolation structure 322, and the first transistor 330; wherein the second dielectric layer 363 is relatively close to the second surface 310b.

[0171] Interconnect structure 350 is located in the first dielectric layer 355 and is coupled to the peripheral circuit;

[0172] The first conductive structure 360 ​​includes:

[0173] The first conductive layer 361 is located in the second dielectric layer 363;

[0174] The first contact plug 362 penetrates the second dielectric layer 363 and the second portion 3102, and is located between the first conductive layer 361 and the interconnect structure 350, for coupling the first conductive layer 361 and the interconnect structure 350.

[0175] For example, the interconnect structure 350 includes a plurality of sub-interconnect structures spaced apart along the Y direction. Each sub-interconnect structure includes a first conductive post 351, a first conductive line 352, a second conductive post 353, and a second conductive line 354. For example, the first sub-interconnect structure is coupled to the source of the second transistor 321, the second sub-interconnect structure is coupled to the drain of the second transistor 321, and the third sub-interconnect structure is coupled to the gate of the second transistor 321.

[0176] The interconnect structure 350 is composed of conductive materials, such as tungsten, copper, aluminum, platinum, titanium, nickel, etc. The materials of any two of the first conductive post 351, the first conductive line 352, the second conductive post 353, and the second conductive line 354 can be the same or different. In this example, the first conductive post 351, the first conductive line 352, and the second conductive post 353 are tungsten, and the second conductive line 354 is copper.

[0177] For example, the first conductive layer 361 is coupled to the interconnect structure 350 via the first contact plug 362. Specifically, the first conductive layer 361 is electrically connected to the first conductive post 351 via the first contact plug 362. It should be emphasized that a first electrical isolation layer for electrically isolating the first contact plug 362 and the second region 310-2 is also provided between the first contact plug 362 and the second region 310-2.

[0178] The first conductive layer 361 and the first contact plug 362 are composed of conductive materials, such as tungsten, copper, aluminum, platinum, titanium, nickel, etc. In this example, the first conductive layer 361 is copper, and the first contact plug 362 is tungsten. The first electrical isolation layer is composed of insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0179] In this embodiment, by providing an interconnect structure coupled to the peripheral circuit in the first dielectric layer, and the first dielectric layer being relatively close to the first surface, and providing a first conductive structure including a first conductive layer and a first contact plug, since the first conductive layer is located in the second dielectric layer and the second dielectric layer is relatively close to the second surface, and the first contact plug penetrates a portion of the second dielectric layer and the second portion, and is electrically connected to the first conductive layer and the interconnect structure respectively, the memory cell array can be led out from the back side of the first semiconductor layer (i.e., the second surface), thereby meeting the requirements of size reduction and performance improvement, which is beneficial to realizing a 4F^2 structure memory and improving the integration and operation performance of the memory.

[0180] In some embodiments, the memory 300 further includes:

[0181] The second conductive structure 370 includes:

[0182] The second conductive layer 371 is located in the second dielectric layer 363 and is arranged side by side with the first conductive layer 361 along the first direction;

[0183] The second contact plug 372 penetrates the second dielectric layer 363 and the second portion 3102, and is located between the second conductive layer 371 and the interconnect structure 350, for coupling the second conductive layer 371 and the interconnect structure 350;

[0184] Bit line 373 is located in the second dielectric layer 363 and is coupled to the second conductive layer 371 and the first transistor 330, respectively.

[0185] For example, the second conductive layer 371 and the first conductive layer 361 are arranged side by side along the Y direction, and the second contact plug 372 and the first contact plug 362 are arranged side by side along the Y direction. The second conductive layer 371 is coupled to the interconnect structure 350 through the second contact plug 372. Specifically, the second conductive layer 371 is electrically connected to the first conductive post 351 through the second contact plug 372.

[0186] It should be emphasized that a second electrical isolation layer for electrically is provided between the second contact plug 372 and the second part 3102 for electrically isolating the second contact plug 372 and the second region 310-2.

[0187] The material of the second contact plug 372 may be the same as that of the first contact plug 362, and the material of the second conductive layer 371 may be the same as that of the first conductive layer 361. The material of the second electrical isolation layer may be the same as that of the first electrical isolation layer.

[0188] One end of bit line 373 is connected to the second conductive layer 371 through a third contact plug. The third contact plug, the first contact plug 362, and the second contact plug 372 are arranged side by side along the Y direction. The second contact plug 372 is located between the first contact plug 362 and the third contact plug. The other end of bit line 373 is electrically connected to the first transistor.

[0189] In this example, memory 300 includes a plurality of bit lines 373 arranged side-by-side along a third direction (i.e., the X direction), each bit line 373 extending along a first direction (i.e., the Y direction). Figure 10 As shown, bit line 373 is electrically connected to a plurality of first transistors 330 arranged in parallel along the Y direction, and the plurality of first transistors share bit line 373 extending along the Y direction.

[0190] In other examples, memory 300 includes a plurality of bit lines arranged side-by-side along a first direction (i.e., the Y direction), each bit line extending along a third direction (i.e., the X direction). The bit lines are electrically connected to a plurality of first transistors arranged side-by-side along the X direction, the plurality of first transistors sharing the bit lines extending along the X direction.

[0191] In this embodiment of the present disclosure, by setting a bit line coupled to the first transistor in the second dielectric layer, and setting a second conductive structure including a second conductive layer and a second contact plug, since the second conductive layer is located in the second dielectric layer and coupled to the bit line, and the second contact plug penetrates part of the second dielectric layer and the second part, and is electrically connected to the second conductive layer and the interconnection structure respectively, the first transistor can be made into a vertical structure, and the memory cell array can be made into a vertical structure, which is beneficial to realize a 4F^2 structure memory and improve the integration and operation performance of the memory.

[0192] In some embodiments, the memory 300 further includes:

[0193] The pad structure, located in the third dielectric layer, includes: solder ball 381 and pad 382; wherein, solder ball 381 is located between the first conductive structure 360 ​​and pad 382, ​​for coupling the first conductive structure 360 ​​and pad 382; the second dielectric layer 363 is located between the third dielectric layer and the first semiconductor layer 310.

[0194] The solder ball 381 and solder pad 382 are made of conductive materials, such as tungsten, copper, aluminum, platinum, titanium, nickel, etc. In this example, the solder ball 381 and solder pad 382 are made of aluminum.

[0195] This disclosure also provides a memory system, including:

[0196] The memory 300 in any of the above embodiments is configured to store data;

[0197] A memory controller, coupled to memory 300, is configured to control memory 300.

[0198] The memory system can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0199] In some embodiments, the memory controller is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0200] In some embodiments, the memory controller is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0201] The memory controller can be configured to control the operation of the memory 300, such as read, erase, and program operations. The memory controller can also be configured to manage various functions relating to data stored or to be stored in the memory 300, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller is also configured to handle error correction codes (ECC) relating to data read from or written to the memory 300.

[0202] The memory controller can also perform any other suitable functions, such as formatting the memory. The memory controller can communicate with external devices (e.g., a host) according to specific communication protocols. For example, the memory controller can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0203] The memory controller and one or more memories can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package).

[0204] In some embodiments, the memory system further includes:

[0205] The host, coupled to the memory controller, is configured to send or receive data.

[0206] The host can be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host can be configured to send data to memory. Alternatively, the host can be configured to receive data from memory.

[0207] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, The memory has a first region and a second region, the memory comprising: A first semiconductor layer includes: a first portion and a second portion arranged side-by-side along a first direction; wherein the first portion is located in the first region and the second portion is located in the second region; along a second direction, the length of the first portion is less than the length of the second portion; the first direction is parallel to the plane in which the first semiconductor layer is located, and the second direction is perpendicular to the plane in which the first semiconductor layer is located; A memory cell array includes: a plurality of memory cells arranged in an array, each memory cell including a first transistor and an energy storage element coupled to the first transistor; wherein the first transistor is located in a first region, and the channel of the first transistor extends along a second direction; The peripheral circuitry, located in the second region and coupled to the memory cell array, includes at least two second transistors; At least one isolation structure extends through the second portion along the second direction and is located between two adjacent second transistors for electrically isolating the two adjacent second transistors; Wherein, along the second direction, the length of the isolation structure is greater than the length of the channel of the first transistor.

2. The memory according to claim 1, characterized in that, The end of the isolation structure that is relatively close to the peripheral circuit is substantially flush with the end of the first transistor that is relatively close to the peripheral circuit.

3. The memory according to claim 1, characterized in that, The surface of the first portion that is relatively close to the memory cell array is substantially flush with the surface of the second portion that is relatively close to the peripheral circuit. The surface of the first portion, which is relatively far from the memory cell array, is not flush with the surface of the second portion, which is relatively far from the peripheral circuit.

4. The memory according to claim 1, characterized in that, The first semiconductor layer includes: a first surface and a second surface disposed opposite to each other; the memory further includes: A first dielectric layer covers the peripheral circuit and the isolation structure; wherein the first dielectric layer is relatively close to the first surface; A second dielectric layer covers the first semiconductor layer, the isolation structure, and the first transistor; wherein the second dielectric layer is relatively close to the second surface; An interconnect structure is located in the first dielectric layer and coupled to the peripheral circuit. The first conductive structure includes: The first conductive layer is located in the second dielectric layer; A first contact plug penetrates a portion of the second dielectric layer and the second portion, and is located between the first conductive layer and the interconnect structure, for coupling the first conductive layer and the interconnect structure.

5. The memory according to claim 4, characterized in that, The memory also includes: The second conductive structure includes: The second conductive layer is located in the second dielectric layer and is arranged side by side with the first conductive layer along the first direction; The second contact plug extends through a portion of the second dielectric layer and the second portion, and is located between the second conductive layer and the interconnect structure, for coupling the second conductive layer and the interconnect structure; Bit lines are located in the second dielectric layer and are coupled to the second conductive layer and the first transistor, respectively.

6. The memory according to claim 1, characterized in that, The first transistor includes at least one of the following: a fully all-around gate transistor; a tri-gate transistor; a dual-gate transistor; and a single-gate transistor.

7. A memory system, characterized in that, include: The memory as described in any one of claims 1 to 6 is configured to store data; A memory controller, coupled to the memory, is configured to control the memory.

8. The memory system according to claim 7, characterized in that, The memory system also includes: A host, coupled to the memory controller, is configured to send or receive the data.

9. A method for manufacturing a memory, characterized in that, The memory has a first region and a second region, and the method includes: A first semiconductor layer is provided; wherein the first semiconductor layer includes a first portion and a second portion arranged side by side along a first direction; the first portion is located in a first region, and the second portion is located in a second region; the first direction is parallel to the plane in which the first semiconductor layer is located; A memory cell array is formed; wherein the memory cell array includes a plurality of memory cells arranged in an array, each memory cell including a first transistor and an energy storage element coupled to the first transistor, the first transistor being located in a first region, and the channel of the first transistor extending along a second direction; the second direction is perpendicular to the plane where the first semiconductor layer is located; A peripheral circuit is formed; wherein the peripheral circuit is located in the second region and coupled to the memory cell array; the peripheral circuit includes at least two second transistors; At least one isolation structure is formed; wherein the isolation structure is located in the second portion and between two adjacent second transistors for electrically isolating the two adjacent second transistors; along the second direction, the length of the isolation structure is greater than the length of the channel of the first transistor; The first portion is thinned on the side relatively away from the storage cell array; wherein, along the second direction, the length of the thinned first portion is less than the length of the second portion.

10. The method according to claim 9, characterized in that, After forming the isolation structure and before thinning the first portion, the method further includes: The first semiconductor layer and the substrate are bonded together; wherein the memory cell array and the peripheral circuit are located between the substrate and the first semiconductor layer; The thinning of the first portion on the side relatively far from the memory cell array includes: Thinning is performed on the side of the first semiconductor layer that is relatively far from the substrate; After the thinning process, an etching process is performed on the side of the first portion that is relatively far away from the substrate.

11. The method according to claim 10, characterized in that, The thinning process performed on the side of the first semiconductor layer relatively away from the substrate includes: Thinning is performed on the side of the first semiconductor layer that is relatively far from the substrate to expose the isolation structure.

12. The manufacturing method according to claim 9, characterized in that, The formation of the storage cell array includes: In the first region, a plurality of transistor pillars extending along the second direction are formed; wherein, the transistor pillars include a first end and a second end, and at least one side located between the first end and the second end; A gate structure is formed on at least one side of the transistor pillar.

13. The manufacturing method according to claim 9, characterized in that, The formation of the memory cell array includes: A first dielectric layer is formed covering the first transistor; A plurality of energy storage elements are formed in the first dielectric layer; wherein each energy storage element includes a first electrode layer, an energy storage structure and a second electrode layer, the energy storage structure being located between the first electrode layer and the second electrode layer; the first electrode layer is coupled to the first transistor, and the second electrode layer is coupled to the peripheral circuit or ground terminal.

14. The manufacturing method according to claim 9, characterized in that, The first semiconductor layer includes: a first surface and a second surface disposed opposite to each other; after forming the isolation structure and before thinning the first portion, the fabrication method further includes: A first dielectric layer is formed to cover the peripheral circuit and the isolation structure; wherein the first dielectric layer is relatively close to the first surface; An interconnect structure is formed in the first dielectric layer; wherein the interconnect structure is coupled to the peripheral circuit. After thinning the first portion, the manufacturing method further includes: A second dielectric layer is formed covering the first semiconductor layer, the isolation structure, and the first transistor; wherein the second dielectric layer is relatively close to the second surface; A first conductive structure is formed in the second dielectric layer; wherein the first conductive structure includes a first conductive layer and a first contact plug; the first conductive layer is located in the second dielectric layer; the first contact plug penetrates a portion of the second dielectric layer and the second portion, and is located between the first conductive layer and the interconnect structure, for coupling the first conductive layer and the interconnect structure.

15. The manufacturing method according to claim 14, characterized in that, After thinning the first portion, the manufacturing method further includes: A second conductive structure is formed in the second dielectric layer; wherein the second conductive structure includes a second conductive layer and a second contact plug; the second conductive layer is located in the second dielectric layer and is arranged side by side with the first conductive layer along the first direction; the second contact plug penetrates a portion of the second dielectric layer and the second portion, and is located between the second conductive layer and the interconnect structure, for coupling the second conductive layer and the interconnect structure; Bit lines are formed in the second dielectric layer; wherein the bit lines are coupled to the second conductive layer and the first transistor, respectively.

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