Microphone bias circuits, microphones and electronics

Abstract

The present application relates to a microphone bias circuit, a microphone and an electronic device. The microphone bias circuit includes a first boost circuit and a second boost circuit; the input end of the first boost circuit is connected to the power module, the output end of the first boost circuit is connected to the input end of the second boost circuit, and the output end of the second boost circuit is connected to the MEMS chip. The present application boosts the output voltage of the power module to a first voltage through the first boost circuit, filters the second part of the first voltage through the second boost circuit, obtains only the first part of the first voltage, and increases the first part of the first voltage to a target voltage, effectively improving the rate of increase of the target voltage output by the second boost circuit, making the target voltage stabilize quickly, so that the microphone has good stability and sensitivity, and improves the performance of the microphone product.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of microphone circuits, and more specifically, to a microphone bias circuit, a microphone, and an electronic device. Background Art

[0002] The microphone is composed of a MEMS (Micro-Electro-Mechanical System) chip and an ASIC (Application Specific Integrated Circuit) chip. In order for the MEMS chip to work properly, a stable and low-noise bias voltage is required. In order for the MEMS chip to have good sensitivity, the bias circuit inside the ASIC chip is required to provide a stable and low-noise bias voltage to the MEMS chip. However, the existing bias circuit has a slow stabilization speed when boosting. This causes the sensitivity of the microphone product to change slowly over a long period of time. At this time, the sensitivity is unstable, which affects the performance of the microphone product. Summary of the invention

[0003] An object of the embodiments of the present application is to provide a new technical solution for a microphone bias circuit, a microphone, and an electronic device.

[0004] According to a first aspect of the present application, a microphone bias circuit is provided, the microphone bias circuit comprising a first boost circuit and a second boost circuit;

[0005] The input end of the first boost circuit is connected to the power module, the output end of the first boost circuit is connected to the input end of the second boost circuit, the first boost circuit is used to boost the output voltage of the power module into a first voltage, and the first voltage is output to the second boost circuit; wherein the first voltage includes a first part with a higher level and a second part with a lower level;

[0006] The output end of the second boost circuit is connected to the MEMS chip. The second boost circuit is used to obtain the first part and boost the first part to a target voltage, and the target voltage is output to the MEMS chip; wherein the target voltage is a bias voltage required for the MEMS chip to operate.

[0007] Optionally, the first boost circuit includes N stages of charge pump circuits connected in series in sequence; wherein N is a positive integer, and N≥2;

[0008] The charge pump circuit comprises a first diode and a first capacitor, wherein the anode of the first diode is the input terminal of the charge pump circuit, and the cathode of the first diode is the output terminal of the charge pump circuit;

[0009] The positive electrode of the first diode is connected to the output end of the previous stage charge pump circuit, and the negative electrode of the first diode is connected to the input end of the next stage charge pump circuit;

[0010] A first end of the first capacitor is connected to a clock signal, and a second end of the first capacitor is connected to a cathode of the first diode.

[0011] Optionally, the clock signal includes a first clock signal and a second clock signal, and a phase of the first clock signal is opposite to a phase of the second clock signal;

[0012] The first end of the first capacitor of one of the two adjacent charge pump circuits is connected to the first clock signal, and the first end of the first capacitor of the other charge pump circuit is connected to the second clock signal.

[0013] Optionally, the first voltage is a pulse voltage, a high voltage portion of the pulse voltage is the first portion, and a low voltage portion of the pulse voltage is the second portion.

[0014] Optionally, the second boost circuit includes a first control module, a second control module, a third control module and a fourth control module;

[0015] The input end of the first control module is connected to the output end of the first boost circuit, and the output end of the first control module is connected to the input end of the second control module and the input end of the fourth control module respectively;

[0016] The output end of the second control module is connected to the input end of the third control module;

[0017] The output end of the third control module is connected to the input end of the fourth control module;

[0018] The output end of the fourth control module is the output end of the second boost circuit, and the output end of the fourth control module is connected to the MEMS chip.

[0019] Optionally, the first control module takes the first voltage, the third clock signal and the fourth clock signal as inputs to obtain the first part, and obtains a second voltage according to the first part, and the second voltage is output to the second control module and the fourth control module respectively; wherein the second voltage is equal to the first part;

[0020] The first control module includes a second capacitor, a third capacitor, a first PMOS transistor, a second PMOS transistor and a third PMOS transistor;

[0021] A first end of the second capacitor is connected to the third clock signal, and a second end of the second capacitor is connected to the gate of the first PMOS transistor and the gate of the third PMOS transistor respectively;

[0022] A first end of the third capacitor is connected to the fourth clock signal, and a second end of the third capacitor is connected to the gate of the second PMOS tube;

[0023] The source of the first PMOS tube is connected to the output end of the first voltage, and the drain of the first PMOS tube is the output end of the second voltage;

[0024] The source of the second PMOS tube is connected to the drain of the first PMOS tube; the drain of the second PMOS tube is connected to the second end of the capacitor;

[0025] The source of the third PMOS tube is connected to the drain of the first PMOS tube, and the drain of the third PMOS tube is connected to the second end of the third capacitor.

[0026] Optionally, the second control module takes the second voltage and the fifth clock signal as input, and is used to boost the second voltage to a third voltage, and the third voltage is output to the third control module; wherein the third voltage is a pulse voltage, and the third voltage includes a third part with a higher level and a fourth part with a lower level;

[0027] The second control module includes a fourth capacitor and a fourth PMOS tube;

[0028] A first end of the fourth capacitor is connected to the fifth clock signal, and a second end of the fourth capacitor is connected to the gate of the fourth PMOS tube;

[0029] The source of the fourth PMOS tube is connected to the output end of the second voltage, and the drain of the fourth PMOS tube is the output end of the third voltage.

[0030] Optionally, the third control module takes the third voltage, the third clock signal and the fourth clock signal as inputs, is used to obtain the third part, and obtains a fourth voltage according to the third part, and the fourth voltage is output to the fourth control module; wherein the fourth voltage is equal to the third part;

[0031] The third control module includes a fifth capacitor, a sixth capacitor, a seventh capacitor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor and an eighth PMOS transistor;

[0032] A first end of the fifth capacitor is connected to the fourth clock signal, and a second end of the fifth capacitor is respectively connected to the gate of the fifth PMOS tube, the gate of the seventh PMOS tube, and the gate of the eighth PMOS tube;

[0033] A first end of the sixth capacitor is connected to the third clock signal, and a second end of the sixth capacitor is connected to the gate of the sixth PMOS tube;

[0034] The source of the fifth PMOS tube is connected to the output end of the third voltage, the drain of the fifth PMOS tube is connected to the source of the eighth PMOS tube, and the drain of the eighth PMOS tube is the output end of the fourth voltage;

[0035] The source of the sixth PMOS tube is connected to the drain of the fifth PMOS tube, and the drain of the sixth PMOS tube is connected to the second end of the fifth capacitor;

[0036] The source of the seventh PMOS tube is connected to the drain of the fifth PMOS tube, and the drain of the seventh PMOS tube is connected to the second end of the sixth capacitor;

[0037] A first end of the seventh capacitor is connected to the drain of the fifth PMOS tube, and a second end of the seventh capacitor is grounded.

[0038] Optionally, the fourth control module takes the second voltage, the fourth voltage and the sixth clock signal as inputs, and is used to output a target voltage, and the target voltage is output to the MEMS chip;

[0039] The fourth control module includes an eighth capacitor, a ninth PMOS tube, a second diode and a third diode;

[0040] A first end of the eighth capacitor is connected to the sixth clock signal, and a second end of the eighth capacitor is connected to the gate of the ninth PMOS tube;

[0041] The source of the ninth PMOS tube is connected to the output end of the second voltage, and the drain of the ninth PMOS tube is the output end of the target voltage;

[0042] The anode of the second diode is connected to the source of the ninth PMOS tube, the cathode of the second diode is connected to the anode of the third diode, and the cathode of the third diode is connected to the drain of the ninth PMOS tube.

[0043] According to a second aspect of the present application, a microphone is further provided. The microphone comprises a housing and a MEMS chip disposed in the housing, and the microphone bias circuit as described in the first aspect;

[0044] The bias circuit is connected to the MEMS chip, and is used to provide a bias voltage to the MEMS chip.

[0045] According to a third aspect of the present application, an electronic device is also provided, comprising the microphone as described in the second aspect.

[0046] A beneficial effect of an embodiment of the present application is that the output voltage of the power module is boosted to a first voltage through a first boost circuit, the second part of the first voltage is filtered through a second boost circuit, only the first part of the first voltage is obtained, and the first part of the first voltage is boosted to a target voltage, thereby effectively improving the rising rate of the target voltage output by the second boost circuit, making the target voltage stabilize quickly, thereby making the microphone have good stability and sensitivity, and improving the performance of the microphone product.

[0047] Other features and advantages of the embodiments of the present application will become apparent from the following detailed description of exemplary embodiments of the present application with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the description, serve to explain the principles of the embodiments of the present application.

[0049] Figure 1 A circuit block diagram of a microphone bias circuit provided in an embodiment of the present invention;

[0050] Figure 2 A circuit structure diagram of a first boost circuit provided in an embodiment of the present invention;

[0051] Figure 3 A circuit structure diagram of a second boost circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0053] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0054] like Figure 1 As shown, the present invention provides a microphone bias circuit, which includes a first boost circuit U1 and a second boost circuit U2.

[0055] The input end of the first boost circuit U1 is connected to the power module U3, and the output end of the first boost circuit U1 is connected to the input end of the second boost circuit U2. The first boost circuit U1 is used to boost the output voltage Vi of the power module U3 into a first voltage V1, and the first voltage V1 is output to the second boost circuit U2; wherein the first voltage V1 includes a first part with a higher level and a second part with a lower level.

[0056] The output end of the second boost circuit U2 is connected to the MEMS chip U4. The second boost circuit U2 is used to obtain the first part and boost the first part to a target voltage Vout. The target voltage Vout is output to the MEMS chip U4. The target voltage Vout is the bias voltage required for the MEMS chip U4 to work.

[0057] In this embodiment, the first boost circuit U1 is used to boost the output voltage Vi of the power module U3 and output a first voltage V1, which is a pulse voltage with a sudden voltage change; the second boost circuit U2 is used to filter the first voltage V1 output by the first boost circuit U1 and boost it again to output a target voltage Vout, and the target voltage Vout output by the second boost circuit U2 is used to provide a bias voltage to the MEMS chip U4.

[0058] Specifically, during the operation of the microphone, the first boost circuit U1 takes the output voltage Vi of the power module U3, the first clock signal CLK1 and the second clock signal CLK2 as inputs, and is used to boost the output voltage Vi of the power module U3 into a first voltage V1, wherein the first voltage V1 includes a first part with a higher level and a second part with a lower level; the second boost circuit U2 filters the second part of the first voltage V1, obtains only the first part of the first voltage V1, and boosts the first part of the first voltage V1 to the target voltage Vout, thereby effectively improving the rising rate of the target voltage Vout output by the second boost circuit U2, so that the target voltage Vout stabilizes quickly, thereby making the microphone have good stability and sensitivity, and improving the performance of the microphone product.

[0059] In this embodiment, the microphone bias circuit further includes a clock generation circuit, which may include an oscillator, such as an RC oscillator. The oscillator may generate a clock signal of corresponding amplitude and frequency according to the requirements of the actual application. Exemplarily, the clock generation circuit may generate 2 or more clock phases.

[0060] like Figure 2 As shown, in one embodiment, the first boost circuit U1 includes N stages of charge pump circuits U11 connected in series in sequence; wherein N is a positive integer, and N≥2.

[0061] The charge pump circuit U11 includes a first diode D1 and a first capacitor C1. The anode of the first diode D1 is the input end of the charge pump circuit U11, and the cathode of the first diode D1 is the output end of the charge pump circuit U11.

[0062] The anode of the first diode D1 is connected to the output end of the previous stage charge pump circuit U11 , and the cathode of the first diode D1 is connected to the input end of the next stage charge pump circuit U11 .

[0063] A first end of the first capacitor C1 is connected to the clock signal, and a second end of the first capacitor C1 is connected to the cathode of the first diode D1.

[0064] In this embodiment, the first boost circuit U1 is composed of N-stage charge pump circuits U11, and the N-stage charge pump circuits U11 are respectively recorded as the first-stage charge pump circuit 1-1, the second-stage charge pump circuit 1-2, ..., the N-stage charge pump circuit 1-N; wherein the input end of the first-stage charge pump circuit 1-1 is the input end of the first boost circuit U1, and the output end of the N-stage charge pump circuit 1-N is the output end of the first boost circuit U1.

[0065] In this embodiment, the input end of the first-stage charge pump circuit 1 - 1 is connected to the output end of the power module U3 , and the output end of the N-th-stage charge pump circuit 1 -N is connected to the input end of the second boost circuit U2 .

[0066] In this embodiment, the first boost circuit U1 takes the output voltage Vi of the power module U3 as the input voltage, and uses the first clock signal CLK1 and the second clock signal CLK2 generated by the clock generating circuit U5 to control the charging and discharging of the first capacitor C1 in the N-stage charge pump circuit U11, thereby improving the rising speed of the first voltage V1 output by the first boost circuit U1 and saving time; at the same time, by setting different levels of charge pump circuits U11, a higher output voltage can be provided to the second boost circuit U2.

[0067] In this embodiment, each stage of the charge pump circuit U11 includes a first diode D1 and a first capacitor C1. In the first boost circuit U1, multiple charge pump circuits U11 are coupled in series, and the more the number of charge pump circuits U11 coupled in series, the greater the first voltage V1 outputted from the output end of the first boost circuit U1.

[0068] In this embodiment, for any stage of the charge pump circuit U11, when the anode potential of the first diode D1 is greater than the cathode potential of the first diode D1, the first diode D1 is turned on, and the charge is charged from the anode of the first diode D1 to the cathode of the first diode D1, so that the cathode potential of the first diode D1 is equal to the anode potential of the first diode D1; however, when the anode potential of the first diode D1 is less than the cathode potential of the first diode D1, since the first diode D1 has a unidirectional conduction characteristic, the charge will not flow back from the cathode of the first diode D1 to the anode of the first diode D1.

[0069] In this embodiment, the voltage of the clock signal varies between 0 and Vi. When the voltage of the clock signal is 0, the clock signal is at a low level; when the voltage of the clock signal is Vi, the clock signal is at a high level.

[0070] In this embodiment, the working principles of the N-stage charge pump circuit U11 are the same. Taking the first-stage charge pump circuit 1-1 as an example, in the first-stage charge pump circuit 1-1, the anode potential of the first diode D1 is Vi. When the voltage of the first clock signal CLK1 is 0, the cathode potential of the first diode D1 is 0. At this time, the anode potential of the first diode D1 is greater than the cathode potential of the first diode D1. The first diode D1 is turned on, and the charge is charged from the anode of the first diode D1 to the cathode of the first diode D1, so that the cathode potential of the first diode D1 is equal to the anode potential of the first diode D1. The potential of the negative electrode of D1 rises to Vi, that is, the potential of the second end of the first diode D1 is Vi, and the output voltage of the first-stage charge pump circuit 1-1 is Vi; when the voltage of the first clock signal CLK1 rises to Vi, since the voltage across the first capacitor C1 remains unchanged, at this time, the potential of the second end of the first capacitor C1 rises from Vi to 2Vi, that is, the potential of the second end of the first diode D1 is 2Vi, and the output voltage of the first-stage charge pump circuit 1-1 is 2Vi; therefore, the output voltage of the first-stage charge pump circuit 1-1 is Vi~2Vi, thereby achieving a voltage boost on the output voltage Vi of the power module U3.

[0071] In this embodiment, different numbers of charge pump circuits U11 can be selected to be connected in series to form the first boost circuit U1 according to the bias voltage actually required by the microphone, and this application does not make any specific limitation on this.

[0072] like Figure 2 As shown, in one embodiment, the clock signal includes a first clock signal CLK1 and a second clock signal CLK2 , and the phase of the first clock signal CLK1 is opposite to the phase of the second clock signal CLK2 .

[0073] A first end of a first capacitor C1 of one of two adjacent charge pump circuits U11 is connected to the first clock signal CLK1 , and a first end of a first capacitor C1 of the other charge pump circuit U11 is connected to the second clock signal CLK2 .

[0074] In this embodiment, the first clock signal CLK1 and the second clock signal CLK2 are both generated by a clock generating circuit, and the phase of the first clock signal CLK1 is opposite to the phase of the second clock signal CLK2; for example, when the first clock signal CLK1 is at a low level, the second clock signal CLK2 is at a high level; when the first clock signal CLK1 is at a high level, the second clock signal CLK2 is at a low level.

[0075] In this embodiment, the voltages of the first clock signal CLK1 and the second clock signal CLK2 vary between 0 and Vi respectively. When the voltage of the first clock signal CLK1 is 0, the voltage of the second clock signal CLK2 is Vi; when the voltage of the first clock signal CLK1 is Vi, the voltage of the second clock signal CLK2 is 0.

[0076] In this embodiment, the working principle of the first boost circuit U1 is as follows: Taking N=2 as an example, the first boost circuit U1 includes two charge pump circuits U11 connected in series:

[0077] When the voltage of the first clock signal CLK1 is 0, the voltage of the second clock signal CLK2 is Vi. At this time, the first diode D1 of the first-stage charge pump circuit 1-1 is turned on, and the output voltage of the first-stage charge pump circuit 1-1 is Vi; the first diode D1 of the second-stage charge pump circuit 1-2 is turned off, and the output voltage of the second-stage charge pump circuit 1-2 is equal to the voltage of the second clock signal CLK2, that is, the output voltage of the second-stage charge pump circuit 1-2 is Vi;

[0078] When the voltage of the first clock signal CLK1 rises to Vi, the voltage of the second clock signal CLK2 drops to 0. At this time, the output voltage of the first-stage charge pump circuit 1-1 rises to 2Vi. The first diode D1 of the second-stage charge pump circuit 1-2 is turned on, and the output voltage 2Vi of the first-stage charge pump circuit 1-1 is transmitted to the second-stage charge pump circuit 1-2, so that the output voltage of the second-stage charge pump circuit 1-2 is 2Vi.

[0079] When the voltage of the first clock signal CLK1 drops to 0 again, the voltage of the second clock signal CLK2 rises to Vi again, the output voltage of the first-stage charge pump circuit 1-1 drops from 2Vi to Vi, and the potential of the second end of the first capacitor C1 of the second-stage charge pump circuit 1-2 rises to 3Vi, so that the output voltage of the second-stage charge pump circuit 1-2 rises to 3Vi;

[0080] When the voltage of the first clock signal CLK1 rises to Vi again, the voltage of the second clock signal CLK2 drops to 0 again, the output voltage of the first-stage charge pump circuit 1-1 rises from Vi to 2Vi, and the output voltage of the second-stage charge pump circuit 1-2 drops from 3Vi to 2Vi; as the clock cycles of the first clock signal CLK1 and the second clock signal CLK2 are continuously flipped, charges are continuously transmitted to the output end of the second-stage charge pump circuit 1-2, and the output voltage of the second-stage charge pump circuit 1-2 jumps between 2Vi and 3Vi. At this time, the output end of the second-stage charge pump circuit 1-2 is the output end of the first boost circuit U1, that is, charges are continuously transmitted to the output end of the first boost circuit U1, so that the output voltage of the first boost circuit U1 continuously rises, so as to achieve the purpose of increasing the output voltage of the first boost circuit U1.

[0081] In this embodiment, when the first boosting circuit U1 includes N stages of charge pump circuits U11 connected in series, the output voltage of the first boosting circuit U1 jumps between NVi and N+1Vi.

[0082] In one embodiment, the first voltage V1 is a pulse voltage, a high voltage portion of the pulse voltage is a first portion, and a low voltage portion of the pulse voltage is a second portion.

[0083] In this embodiment, the first voltage V1 is a square wave pulse voltage.

[0084] In this embodiment, the output voltage of the first voltage V1 jumps between NVi and N+1Vi, the first part of the first voltage V1 is the part where the output voltage of the first voltage V1 is equal to N+1Vi, and the second part of the first voltage V1 is the part where the output voltage of the first voltage V1 is equal to NVi.

[0085] like Figure 3 As shown, in one embodiment, the second boost circuit U2 includes a first control module U21, a second control module U22, a third control module U23 and a fourth control module U24.

[0086] The input end of the first control module U21 is connected to the output end of the first boost circuit U1 , and the output end of the first control module U21 is connected to the input end of the second control module U22 and the input end of the fourth control module U24 .

[0087] The output end of the second control module U22 is connected to the input end of the third control module U23.

[0088] The output end of the third control module U23 is connected to the input end of the fourth control module U24.

[0089] The output end of the fourth control module U24 is the output end of the second boost circuit U2 , and the output end of the fourth control module U24 is connected to the MEMS chip U4 .

[0090] In this embodiment, the first part of the first voltage V1 is obtained through the first control module U21, and the second voltage V2 is obtained based on the first part of the first voltage V1. The second voltage V2 is output to the second control module U22 and the fourth control module U24, respectively, so that the second voltage V2 output to the fourth control module U24 is a stable voltage, which can effectively increase the rising speed of the target voltage Vout output by the fourth control module U24, thereby providing a stable speed for the microphone product.

[0091] In this embodiment, the second voltage V2 is boosted to a third voltage V3 by the second control module U22, and the third voltage V3 is output to the third control module U23. The third voltage V3 includes a third part with a higher level and a fourth part with a lower level.

[0092] In this embodiment, the third part of the third voltage V3 is obtained by the third control module U23, and the third part of the third voltage V3 is increased to a fourth voltage V4, and the fourth voltage V4 is output to the fourth control module U24, and the fourth voltage V4 is equal to the third part of the third voltage V3.

[0093] In this embodiment, the second voltage V2 is increased to a target voltage Vout by the fourth control module U24 , and the target voltage Vout is output to the MEMS chip U4 .

[0094] like Figure 3 As shown, in one embodiment, the first control module U21 takes the first voltage V1, the third clock signal CLK3 and the fourth clock signal CLK4 as inputs to obtain the first part, and obtains the second voltage V2 based on the first part, and the second voltage V2 is output to the second control module U22 and the fourth control module U24 respectively; wherein the second voltage V2 is equal to the first part.

[0095] The first control module U21 includes a second capacitor C2, a third capacitor C3, a first PMOS transistor M1, a second PMOS transistor M2 and a third PMOS transistor M3.

[0096] A first end of the second capacitor C2 is connected to the third clock signal CLK3 , and a second end of the second capacitor C2 is connected to the gate of the first PMOS transistor M1 and the gate of the third PMOS transistor M3 , respectively.

[0097] A first end of the third capacitor C3 is connected to the fourth clock signal CLK4 , and a second end of the third capacitor C3 is connected to the gate of the second PMOS transistor M2 .

[0098] The source of the first PMOS tube M1 is connected to the output end of the first voltage V1 , and the drain of the first PMOS tube M1 is the output end of the second voltage V2 .

[0099] The source of the second PMOS tube M2 is connected to the drain of the first PMOS tube M1 ; the drain of the second PMOS tube M2 is connected to the second end of the capacitor C2 .

[0100] The source of the third PMOS transistor M3 is connected to the drain of the first PMOS transistor M1 , and the drain of the third PMOS transistor M3 is connected to the second end of the third capacitor C3 .

[0101] In this embodiment, when the first voltage V1 jumps to the first part, the first voltage V1 is at a high level, and when the first voltage V1 jumps to the second part, the first voltage V1 is at a low level.

[0102] In this embodiment, the phase of the third clock signal CLK3 is opposite to the phase of the first voltage V1 , and the phase of the fourth clock signal CLK4 is the same as the first voltage V1 .

[0103] In this embodiment, the third clock signal CLK3 and the fourth clock signal CLK4 include a high level signal and a low level signal, respectively.

[0104] In this embodiment, the second capacitor C2 and the third capacitor C3 are both coupling capacitors.

[0105] In this embodiment, when the gate of the PMOS tube is at a low level, the PMOS tube is turned on.

[0106] In this embodiment, the working principle of the first control module U21 is:

[0107] When the first voltage V1 is at a high level, the third clock signal CLK3 is at a low level. Through the coupling effect of the second capacitor C2, V2-1 is at a low level. At this time, the first PMOS tube M1 is turned on, and the charge flows from the output end of the first boost circuit U1 to the output end of the first control module U21, so that the second voltage V2 = the first voltage V1;

[0108] When the first voltage V1 is at a low level, the third clock signal CLK3 is at a high level. Through the coupling effect of the second capacitor C2, V2-1 is at a high level, the first PMOS tube M1 is turned off, and the charge cannot flow back from the output end of the first control module U21 to the output end of the first boost circuit U1. Therefore, the second voltage V2 output by the first control module U21 will not decrease, thereby achieving the acquisition of the first part of the first voltage V1 and filtering out the second part of the first voltage V1, so that the second voltage V2 is a stable voltage, and the second voltage V2 is prevented from changing with the change of the first voltage V1.

[0109] In this embodiment, V2-1 is a suspended point. During the operation of the first control module U21, it is necessary to continuously charge the V2-1 point, that is, to charge the second capacitor C2, so that the charge value of the second capacitor C2 remains unchanged, thereby avoiding the discharge of the second capacitor C2 and affecting the normal operation of the first control module U21.

[0110] In this embodiment, when the third clock signal CLK3 is at a low level, the first PMOS tube M1 and the third PMOS tube M3 are turned on respectively, and the second voltage V2 and the point V2-2 are charged respectively through the first voltage V1; at this time, the fourth clock signal CLK4 is at a high level, and the second PMOS tube M2 is turned off; wherein, by charging the point V2-2, the charge value of the third capacitor C3 remains unchanged.

[0111] In this embodiment, when the third clock signal CLK3 is at a high level, the fourth clock signal CLK4 is at a low level, the first PMOS transistor M1 and the third PMOS transistor M3 are respectively turned off, and the second PMOS transistor M2 is turned on to charge the second capacitor C2 through the second voltage V2.

[0112] like Figure 3 As shown, in one embodiment, the second control module U22 takes the second voltage V2 and the fifth clock signal CLK5 as input, and is used to boost the second voltage V2 to a third voltage V3, and the third voltage V3 is output to the third control module U23; wherein the third voltage V3 is a pulse voltage, and the third voltage V3 includes a third part with a higher level and a fourth part with a lower level.

[0113] The second control module U22 includes a fourth capacitor C4 and a fourth PMOS transistor M4.

[0114] A first end of the fourth capacitor C4 is connected to the fifth clock signal CLK5 , and a second end of the fourth capacitor C4 is connected to the gate of the fourth PMOS transistor M4 .

[0115] The source of the fourth PMOS transistor M4 is connected to the output end of the second voltage V2 , and the drain of the fourth PMOS transistor M4 is the output end of the third voltage V3 .

[0116] In this embodiment, the third voltage V3 is a square wave pulse voltage.

[0117] In this embodiment, the fifth clock signal CLK5 includes a high level signal and a low level signal.

[0118] In this embodiment, the fourth capacitor C4 is a coupling capacitor.

[0119] In this embodiment, during the charging stage of the microphone bias circuit, that is, when the output voltage of the second boost circuit U2 is less than the target voltage Vout, the fifth clock signal CLK5 is turned off. If the second voltage V2 is greater than the third voltage V3, the charge flows from the output end of the first control module U21 to the output end of the second control module U22, so that the third voltage V3 = the second voltage V2.

[0120] In this embodiment, in the stable stage of the microphone bias circuit, that is, when the output voltage of the second boost circuit U2 = the target voltage Vout, the phase of the fifth clock signal CLK5 is opposite to the phase of the first voltage V1, and the third voltage V3 output by the second control module U22 fluctuates with the fifth clock signal CLK5;

[0121] When the fifth clock signal CLK5 is at a low level, the fourth PMOS transistor M4 is turned on, and the third voltage V3 = the second voltage V2;

[0122] When the fifth clock signal CLK5 is at a high level, the fourth PMOS transistor M4 is turned off, V3 = V2 + V CLK5 ; Among them, V CLK5 is the voltage of the fifth clock signal CLK5 when the fifth clock signal CLK5 is at a high level; as the clock cycle of the fifth clock signal CLK5 continues to flip, the third voltage V3 output by the second control module U22 is between V2 and V2+V CLK5 Jump between.

[0123] In this embodiment, the third part of the third voltage V3 is the third voltage V3 equal to V2+V CLK5 The fourth part of the third voltage V3 is the part where the third voltage V3 is equal to V2.

[0124] like Figure 3 As shown, in one embodiment, the third control module U23 takes the third voltage V3, the third clock signal CLK3 and the fourth clock signal CLK4 as inputs to obtain the third part, and obtains the fourth voltage V4 based on the third part, and the fourth voltage V4 is output to the fourth control module U24; wherein the fourth voltage V4 is equal to the third part.

[0125] The third control module includes a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7 and an eighth PMOS transistor M8.

[0126] A first end of the fifth capacitor C5 is connected to the fourth clock signal CLK4 , and a second end of the fifth capacitor C5 is respectively connected to the gate of the fifth PMOS transistor M5 , the gate of the seventh PMOS transistor M7 , and the gate of the eighth PMOS transistor M8 .

[0127] A first end of the sixth capacitor C6 is connected to the third clock signal CLK3 , and a second end of the sixth capacitor C6 is connected to the gate of the sixth PMOS transistor M6 .

[0128] The source of the fifth PMOS tube M5 is connected to the output end of the third voltage V3 , the drain of the fifth PMOS tube M5 is connected to the source of the eighth PMOS tube M8 , and the drain of the eighth PMOS tube M8 is the output end of the fourth voltage V4 .

[0129] The source of the sixth PMOS transistor M6 is connected to the drain of the fifth PMOS transistor M5 , and the drain of the sixth PMOS transistor M6 is connected to the second end of the fifth capacitor C5 .

[0130] The source of the seventh PMOS tube M7 is connected to the drain of the fifth PMOS tube M5 , and the drain of the seventh PMOS tube M7 is connected to the second end of the sixth capacitor C6 .

[0131] A first end of the seventh capacitor C7 is connected to the drain of the fifth PMOS transistor M5 , and a second end of the seventh capacitor C7 is grounded.

[0132] In this embodiment, the fifth capacitor C5, the sixth capacitor C6 and the seventh capacitor C7 are all coupling capacitors.

[0133] In this embodiment, in the charging stage, when the first voltage V1 is at a low level, the fourth clock signal CLK4 is at a low level, the fifth PMOS tube M5, the seventh PMOS tube M7 and the eighth PMOS tube M8 are turned on respectively, and the fourth voltage V4 output by the third control module U23 is equal to the third voltage V3 and equal to the second voltage V2;

[0134] When the first voltage V1 is at a high level, the fourth clock signal CLK4 is at a high level, the fifth PMOS tube M5, the seventh PMOS tube M7 and the eighth PMOS tube M8 are all turned off, the fourth voltage V4 output by the third control module U23 will not decrease, and the fourth voltage V4 output by the third control module U23 = the third voltage V3 = the second voltage V2.

[0135] In this embodiment, in the stable stage, when the first voltage V1 is at a low level, the fourth clock signal CLK4 is at a low level, the fifth clock signal CLK5 is at a high level, the fifth PMOS tube M5, the seventh PMOS tube M7 and the eighth PMOS tube M8 are turned on respectively, and the fourth voltage V4 output by the third control module U23 is equal to the third voltage V3 = V2 + V CLK5 ;

[0136] When the first voltage V1 is at a high level, the fourth clock signal CLK4 is at a high level, the fifth PMOS tube M5, the seventh PMOS tube M7 and the eighth PMOS tube M8 are all turned off, and the fourth voltage V4 output by the third control module U23 will not decrease. The fourth voltage V4 output by the third control module U23 = V2 + V CLK5 .

[0137] like Figure 3 As shown, in one embodiment, the fourth control module U24 takes the second voltage V2, the fourth voltage V4 and the sixth clock signal CLK6 as inputs to output a target voltage Vout, and the target voltage Vout is output to the MEMS chip U4.

[0138] The fourth control module includes an eighth capacitor C8, a ninth PMOS transistor M9, a second diode D2 and a third diode D3.

[0139] A first end of the eighth capacitor C8 is connected to the sixth clock signal CLK6 , and a second end of the eighth capacitor C8 is connected to the gate of the ninth PMOS transistor M9 .

[0140] The source of the ninth PMOS transistor M9 is connected to the output end of the second voltage V2 , and the drain of the ninth PMOS transistor M9 is the output end of the target voltage.

[0141] The anode of the second diode D2 is connected to the source of the ninth PMOS tube M9 , the cathode of the second diode D2 is connected to the anode of the third diode D3 , and the cathode of the third diode D3 is connected to the drain of the ninth PMOS tube M9 .

[0142] In this embodiment, the sixth clock signal CLK6 includes a high level signal and a low level signal.

[0143] In this embodiment, the eighth capacitor C8 is a coupling capacitor.

[0144] In this embodiment, during the charging phase, the phase of the sixth clock signal CLK6 is opposite to the phase of the first voltage V1;

[0145] When the first voltage V1 is at a high level, the sixth clock signal CLK6 is at a low level, the ninth PMOS tube M9 is turned on, and the fourth control module U24 outputs a target voltage Vout to the MEMS chip U4, and the target voltage Vout=the second voltage V2;

[0146] When the first voltage V1 is at a low level, the sixth clock signal CLK6 is at a high level, and the fourth voltage V4 output by the third control module U23 = the third voltage V3 = the second voltage V2, that is, the high level of the sixth clock signal CLK6 is V2. At this time, the gate voltage of the ninth PMOS tube M9 = the source voltage of the ninth PMOS tube M9, the ninth PMOS tube M9 is turned off, the output voltage of the fourth control module U24 remains unchanged, and the fourth control module U24 continues to output the target voltage Vout to the MEMS chip U4.

[0147] In this embodiment, in the stable stage, the sixth clock signal CLK6 is turned off, no matter the first voltage V1 is at a low level or a high level, the gate voltage of the ninth PMOS tube M9 is always kept at a high level, the gate voltage of the ninth PMOS tube M9=the fourth voltage V4=V2+VCLK5, the gate voltage of the ninth PMOS tube M9>the source voltage of the ninth PMOS tube M9, the ninth PMOS tube M9 is in a deep cutoff state, and the ninth PMOS tube M9 is equivalent to a large resistor in the deep cutoff state, so in the stable stage of the microphone bias circuit, the ninth PMOS tube M9 is always equivalent to a large resistor.

[0148] In this embodiment, in the stable stage, the second diode D2 and the third diode D3 are equivalent to resistors. The second diode D2 and the third diode D3 are connected in series and then connected in parallel with the ninth PMOS tube M9, so that the ninth PMOS tube M9, the second diode D2 and the third diode D3 in the fourth control module are equivalent to large resistors, which effectively reduces the noise of the microphone bias circuit in the stable stage.

[0149] In one embodiment, the present invention provides a microphone, comprising a housing, a MEMS chip disposed in the housing, and the aforementioned microphone bias circuit.

[0150] The bias circuit is connected to the MEMS chip, and is used to provide a bias voltage to the MEMS chip.

[0151] In one embodiment, the present invention provides an electronic device, which includes the aforementioned microphone.

[0152] In this embodiment, the electronic device may be a mobile phone, a tablet computer, a laptop computer, a wearable device, etc.

[0153] Embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the present invention is defined by the appended claims.

Claims

1. A microphone bias circuit, characterized in that: include: A first boost circuit (U1) and a second boost circuit (U2); The input end of the first boost circuit (U1) is connected to the power module (U3), the output end of the first boost circuit (U1) is connected to the input end of the second boost circuit (U2), the first boost circuit (U1) is used to boost the output voltage (Vi) of the power module (U3) into a first voltage (V1), and the first voltage (V1) is output to the second boost circuit (U2); wherein the first voltage (V1) includes a first part with a higher level and a second part with a lower level; The output end of the second boost circuit (U2) is connected to the MEMS chip (U4), and the second boost circuit (U2) is used to filter the second part of the first voltage, obtain the first part, and boost the first part to a target voltage (Vout), and the target voltage (Vout) is output to the MEMS chip (U4); wherein the target voltage (Vout) is a bias voltage required for the MEMS chip (U4) to work. Wherein, the second boost circuit (U2) comprises a first control module (U21), a second control module (U22), a third control module (U23) and a fourth control module (U24); The input end of the first control module (U21) is connected to the output end of the first boost circuit (U1), and the output end of the first control module (U21) is respectively connected to the input end of the second control module (U22) and the input end of the fourth control module (U24); The output end of the second control module (U22) is connected to the input end of the third control module (U23); The output end of the third control module (U23) is connected to the input end of the fourth control module (U24); The output end of the fourth control module (U24) is the output end of the second boost circuit (U2), and the output end of the fourth control module (U24) is connected to the MEMS chip (U4). The first part of the first voltage (V1) is obtained through the first control module (U21), and the second voltage (V2) is obtained according to the first part of the first voltage (V1), and the second voltage (V2) is output to the second control module (U22) and the fourth control module (U24), respectively.

2. The microphone bias circuit according to claim 1, characterized in that: The first boost circuit (U1) comprises N stages of charge pump circuits (U11) connected in series in sequence; wherein N is a positive integer, and N≥2; The charge pump circuit (U11) comprises a first diode (D1) and a first capacitor (C1), the anode of the first diode (D1) being the input end of the charge pump circuit (U11), and the cathode of the first diode (D1) being the output end of the charge pump circuit (U11); The positive electrode of the first diode (D1) is connected to the output end of the previous stage charge pump circuit (U11), and the negative electrode of the first diode (D1) is connected to the input end of the next stage charge pump circuit (U11); A first end of the first capacitor (C1) is connected to a clock signal, and a second end of the first capacitor (C1) is connected to a cathode of the first diode (D1).

3. The microphone bias circuit according to claim 2, characterized in that: The clock signal comprises a first clock signal (CLK1) and a second clock signal (CLK2), and the phase of the first clock signal (CLK1) is opposite to the phase of the second clock signal (CLK2); The first end of the first capacitor (C1) of one of the two adjacent charge pump circuits (U11) is connected to the first clock signal (CLK1), and the first end of the first capacitor (C1) of the other charge pump circuit (U11) is connected to the second clock signal (CLK2).

4. The microphone bias circuit according to claim 1, characterized in that: The first voltage (V1) is a pulse voltage, a high voltage portion of the pulse voltage is the first portion, and a low voltage portion of the pulse voltage is the second portion.

5. The microphone bias circuit according to claim 1, characterized in that: The first control module (U21) takes the first voltage (V1), the third clock signal (CLK3) and the fourth clock signal (CLK4) as inputs, is used to obtain the first part, and obtain a second voltage (V2) according to the first part, and the second voltage (V2) is output to the second control module (U22) and the fourth control module (U24) respectively; wherein the second voltage (V2) is equal to the first part; The first control module (U21) comprises a second capacitor (C2), a third capacitor (C3), a first PMOS transistor (M1), a second PMOS transistor (M2) and a third PMOS transistor (M3); The first end of the second capacitor (C2) is connected to the third clock signal (CLK3), and the second end of the second capacitor (C2) is respectively connected to the gate of the first PMOS transistor (M1) and the gate of the third PMOS transistor (M3); The first end of the third capacitor (C3) is connected to the fourth clock signal (CLK4), and the second end of the third capacitor (C3) is connected to the gate of the second PMOS tube (M2); The source of the first PMOS tube (M1) is connected to the output end of the first voltage (V1), and the drain of the first PMOS tube (M1) is the output end of the second voltage (V2); The source of the second PMOS tube (M2) is connected to the drain of the first PMOS tube (M1); the drain of the second PMOS tube (M2) is connected to the second end of the second capacitor (C2); The source of the third PMOS tube (M3) is connected to the drain of the first PMOS tube (M1), and the drain of the third PMOS tube (M3) is connected to the second end of the third capacitor (C3).

6. The microphone bias circuit according to claim 5, characterized in that: The second control module (U22) takes the second voltage (V2) and the fifth clock signal (CLK5) as input, and is used to boost the second voltage (V2) to a third voltage (V3), and the third voltage (V3) is output to the third control module (U23); wherein the third voltage (V3) is a pulse voltage, and the third voltage (V3) includes a third part with a higher level and a fourth part with a lower level; The second control module (U22) comprises a fourth capacitor (C4) and a fourth PMOS tube (M4); The first end of the fourth capacitor (C4) is connected to the fifth clock signal (CLK5), and the second end of the fourth capacitor (C4) is connected to the gate of the fourth PMOS tube (M4); The source of the fourth PMOS tube (M4) is connected to the output end of the second voltage (V2), and the drain of the fourth PMOS tube (M4) is the output end of the third voltage (V3).

7. The microphone bias circuit according to claim 6, characterized in that: The third control module (U23) takes the third voltage (V3), the third clock signal (CLK3) and the fourth clock signal (CLK4) as inputs, is used to obtain the third part, and obtain a fourth voltage (V4) according to the third part, and the fourth voltage (V4) is output to the fourth control module (U24); wherein the fourth voltage (V4) is equal to the third part; The third control module includes a fifth capacitor (C5), a sixth capacitor (C6), a seventh capacitor (C7), a fifth PMOS tube (M5), a sixth PMOS tube (M6), a seventh PMOS tube (M7) and an eighth PMOS tube (M8); The first end of the fifth capacitor (C5) is connected to the fourth clock signal (CLK4), and the second end of the fifth capacitor (C5) is respectively connected to the gate of the fifth PMOS transistor (M5), the gate of the seventh PMOS transistor (M7), and the gate of the eighth PMOS transistor (M8); The first end of the sixth capacitor (C6) is connected to the third clock signal (CLK3), and the second end of the sixth capacitor (C6) is connected to the gate of the sixth PMOS transistor (M6); The source of the fifth PMOS tube (M5) is connected to the output end of the third voltage (V3), the drain of the fifth PMOS tube (M5) is connected to the source of the eighth PMOS tube (M8), and the drain of the eighth PMOS tube (M8) is the output end of the fourth voltage (V4); The source of the sixth PMOS tube (M6) is connected to the drain of the fifth PMOS tube (M5), and the drain of the sixth PMOS tube (M6) is connected to the second end of the fifth capacitor (C5); The source of the seventh PMOS tube (M7) is connected to the drain of the fifth PMOS tube (M5), and the drain of the seventh PMOS tube (M7) is connected to the second end of the sixth capacitor (C6); A first end of the seventh capacitor (C7) is connected to the drain of the fifth PMOS transistor (M5), and a second end of the seventh capacitor (C7) is grounded.

8. The microphone bias circuit according to claim 7, characterized in that: The fourth control module (U24) takes the second voltage (V2), the fourth voltage (V4) and the sixth clock signal (CLK6) as inputs, and is used to output a target voltage (Vout), and the target voltage (Vout) is output to the MEMS chip (U4); The fourth control module includes an eighth capacitor (C8), a ninth PMOS tube (M9), a second diode (D2) and a third diode (D3); The first end of the eighth capacitor (C8) is connected to the sixth clock signal (CLK6), and the second end of the eighth capacitor (C8) is connected to the gate of the ninth PMOS tube (M9); The source of the ninth PMOS tube (M9) is connected to the output end of the second voltage (V2), and the drain of the ninth PMOS tube (M9) is the output end of the target voltage; The anode of the second diode (D2) is connected to the source of the ninth PMOS tube (M9), the cathode of the second diode (D2) is connected to the anode of the third diode (D3), and the cathode of the third diode (D3) is connected to the drain of the ninth PMOS tube (M9).

9. A microphone, characterized in that: Comprising a housing and a MEMS chip arranged in the housing, and a microphone bias circuit as claimed in any one of claims 1 to 8; The bias circuit is connected to the MEMS chip, and is used to provide a bias voltage to the MEMS chip.

10. An electronic device, characterized in that: Comprising the microphone as claimed in claim 9.

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