A reference sampling phase-locked loop adapted for low-voltage applications

By introducing a low-pass filter and a high-level boost inverter into the reference sampling phase-locked loop, the phase noise and clock jitter problems of the phase-locked loop under low voltage are solved, enabling normal sample-and-hold and high-frequency operation under low voltage, and improving the operating speed of the reference spurious and frequency divider.

CN115549676BActive Publication Date: 2026-07-03XIDIAN UNIV
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Patent Information

Application Number
CN202211029887.8
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-08-25
Publication Date
2026-07-03
Estimated Expiration
2042-08-25

AI Technical Summary

Technical Problem

Traditional phase-locked loops (PLLs) suffer from phase noise and clock jitter issues in low-voltage applications. Improving performance requires sacrificing power consumption and filter area. Subsampling PLLs and injection-locked PLLs have small phase detection ranges and are affected by spurious harmonics. Reference sampling PLLs cannot function properly under low voltage, leading to sample-and-hold functionality failure and reduced frequency divider operating speed.

Method used

The system employs a reference sampling phase detector module, a low-pass filter module, a voltage-controlled oscillator, a frequency divider module, and a clock signal generation module. By adding a low-pass filter to the output of the reference sampling phase detector, high-frequency poles are introduced. A high-level boost inverter is used to reduce the on-resistance of the sampling switch, and two types of frequency dividers are used to increase the operating frequency.

Benefits of technology

Without affecting the phase margin, the reference spurious is improved, the sampler can achieve normal sample-and-hold function under low voltage, the operating frequency of the phase-locked loop is increased and the clock jitter is reduced, and high-frequency phase-locked loop operation under low voltage is achieved.

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Abstract

This invention relates to a reference sampling phase-locked loop (PLL) adapted for low-voltage applications, comprising: a reference sampling phase detector module, a low-pass filter module, a voltage-controlled oscillator (VCO), a frequency divider module, and a clock signal generation module. This invention achieves normal sample-and-hold functionality by employing a high-level boost inverter to reduce the on-resistance of the sampling switch and decrease the sampling time constant under low voltage. Simultaneously, it allows for the use of a larger sampling capacitor to improve noise, enabling normal sampling operation of the PLL under low voltage and superior clock jitter performance. Furthermore, by adding a low-pass filter at the output of the reference sampling phase detector, high-frequency poles are introduced, improving reference spurious signals without affecting the phase margin. Finally, a combination of a current-mode logic divider and a multi-mode programmable divider is used to ensure normal operation of the reference sampling PLL under low voltage and superior spurious and clock jitter performance.
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