A reference sampling phase-locked loop adapted for low-voltage applications

By introducing a low-pass filter and a high-level boost inverter into the reference sampling phase-locked loop, the problem of sample-and-hold function failure under low voltage was solved, the high-frequency poles were improved and the operating frequency of the frequency divider was increased, thus improving the performance of the phase-locked loop.

CN115549676BActive Publication Date: 2026-07-03XIDIAN UNIV
View PDF 2 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
XIDIAN UNIV
Filing Date
2022-08-25
Publication Date
2026-07-03

AI Technical Summary

Technical Problem

Existing reference sampling phase-locked loops cannot achieve normal sample-and-hold functionality in low-voltage applications, resulting in deteriorated phase noise and reduced frequency divider operating speed, thus limiting the operating frequency of the phase-locked loop.

Method used

The system employs a combination of a reference sampling phase detector module, a low-pass filter module, a voltage-controlled oscillator, a frequency divider module, and a clock signal generation module. By adding a low-pass filter to the output of the reference sampling phase detector to introduce high-frequency poles, using a high-level boost inverter to reduce the on-resistance of the sampling switch, and using two types of frequency dividers to increase the operating frequency.

Benefits of technology

Improve reference spurious emissions without affecting phase margin, achieve normal sample-and-hold function under low voltage, increase the operating frequency of the phase-locked loop and reduce noise performance.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN115549676B_ABST
    Figure CN115549676B_ABST
Patent Text Reader

Abstract

This invention relates to a reference sampling phase-locked loop (PLL) adapted for low-voltage applications, comprising: a reference sampling phase detector module, a low-pass filter module, a voltage-controlled oscillator (VCO), a frequency divider module, and a clock signal generation module. This invention achieves normal sample-and-hold functionality by employing a high-level boost inverter to reduce the on-resistance of the sampling switch and decrease the sampling time constant under low voltage. Simultaneously, it allows for the use of a larger sampling capacitor to improve noise, enabling normal sampling operation of the PLL under low voltage and superior clock jitter performance. Furthermore, by adding a low-pass filter at the output of the reference sampling phase detector, high-frequency poles are introduced, improving reference spurious signals without affecting the phase margin. Finally, a combination of a current-mode logic divider and a multi-mode programmable divider is used to ensure normal operation of the reference sampling PLL under low voltage and superior spurious and clock jitter performance.
Need to check novelty before this filing date? Find Prior Art

Citation Information

Patent Citations

  • Phase-locked loop clock generator

    CN107623521A

  • Fractional frequency division reference sampling frequency synthesizer based on voltage mean value

    CN113037282A