A bit line leakage current compensation and BCAM multiplexing circuit and compensation method

By designing bit line leakage current compensation and multiplexing circuits in SRAM and BCAM, voltage compensation is used to compensate with PMOS tubes and compensation capacitors, and address determination is combined with sensitive amplifiers, the performance degradation and addressing errors caused by bit line leakage current is solved, and stable data reading and area optimization are achieved.

CN115798532BActive Publication Date: 2025-08-22ANHUI UNIV
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Patent Information

Application Number
CN202211418384.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-11-14
Publication Date
2025-08-22
Estimated Expiration
2042-11-14

AI Technical Summary

Technical Problem

In the prior art In the face of static random access memory (SRAM) and content addressable memory (BCAM), existing compensation methods usually sacrifice read time or power consumption, and the BCAM addressing determination module occupies a large area.

Method used

A bit line leakage current compensation and BCAM multiplexing circuit is designed, including a compensation module and a sensitive amplifier module. The leakage current compensation is performed through the SRAM cell array of shared bit lines, and switches in SRAM read and write and BCAM modes. The voltage compensation is used for PMOS tubes and compensation capacitors, and the address determination is performed in combination with a sensitive amplifier.

Benefits of technology

It realizes that when the bit line leakage current is large, the correct data is read stably, which reduces the reading time and power consumption, reduces the addressing error rate, and reduces the module area.

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Abstract

The present invention relates to a bitline leakage current compensation and BCAM multiplexing circuit and compensation method. The bitline leakage current compensation and BCAM multiplexing circuit includes a storage array composed of multiple SRAM cells and a compensation module. Each column of SRAM cells shares a bit line and constitutes a basic storage module. The compensation module includes eight PMOS transistors P0 to P7 and two compensation capacitors C1 and C2. The drains of P0, P1, P2, and P3 serve as the four input terminals of the compensation module and are connected to the four bit lines of the storage module. The upper plate connection terminals out and outb of C1 and C2 serve as the result output terminals when the storage module performs normal read and write operations. The lower plate connection terminals bout and boutb of C1 and C2 serve as the result output terminals when the storage module performs BCAM addressing operations. The compensation module of the present invention can reduce addressing or reading errors caused by leakage current.
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