Verification method of consumable chip and inkjet printing device

Abstract

The application provides a kind of verification method of consumable chip and inkjet printing equipment, the method includes sending verification instruction, and determining the verification period of verification response signal;And, the voltage signal of data signal line is acquired, and in the verification period, according to the voltage signal, it is judged whether the output state of data signal line is high resistance state possible state, if not, and the actual level state of data signal line is consistent with the target verification level state, it is confirmed that consumable chip passes verification, otherwise, it is confirmed that consumable chip is abnormal.Inkjet printing equipment includes main controller, which is connected with serial communication bus, and the level signal of data signal line is acquired;And, the inkjet printing equipment is also provided with first switching device, and the main controller outputs conduction control signal to the first switching device to make the first switching device conductive, the first switching device is connected between the first resistance and the data signal line, and one end of the first resistance is connected to the direct current power supply.The application can improve the accuracy of ink cartridge chip verification.

Description

Technical Field

[0001] This invention relates to the technical field of printing equipment, and more specifically, to a method for verifying consumable chips in a printing device, and to an inkjet printing device for implementing this method. Background Technology

[0002] Printing equipment, as a common office tool, provides great convenience for modern offices. Common printing equipment is divided into inkjet printers and laser printers. Inkjet printers use ink cartridges containing ink as consumable containers to spray ink onto paper to form the text or pattern to be printed on the paper; laser printers use toner cartridges containing toner as consumable containers to form the text or pattern to be printed on the medium.

[0003] See Figure 1 A color inkjet printing device has a housing 11. Figure 1 The inkjet printer shown omits the tray of the housing 11. The housing 11 houses the inkjet printer's mechanism 12 and includes a slide bar. The printing carriage 14 is mounted on a motor (…). Figure 1 Driven by the invisible component, it reciprocates along the slide bar. The printing carriage 14 contains the main control circuit board (…). Figure 1 (Not visible in the middle), the main control circuit board communicates with the mechanism 12 through the ribbon cable 13.

[0004] Multiple ink cartridges 15 are detachably mounted on the printing carriage 14, each containing ink of a different color. The structure of the ink cartridge 15 is as follows: Figure 2 As shown. The ink cartridge 15 has a housing 16, which forms a cavity for containing ink. The lower end of the cavity is provided with an ink outlet 17. The ink in the cavity flows out through the ink outlet 17 and supplies ink to the ink supply needle of the printing carriage 14.

[0005] A chip 18 is mounted on the outer wall of the cartridge body 16 of the ink cartridge 15. The chip 18 has a substrate, and one side of the substrate has multiple connection terminals 19 for electrical connection with the contact pins on the print carriage 14. The other side of the substrate has a memory (…). Figure 2 (Not visible in the image) Typically, this memory is a non-volatile memory, such as EEPROM or FLASH, which stores information related to the ink cartridge, including variable information and invariant information. Variable information is information that changes continuously with the printing operation, such as ink level, printing time, and number of sheets printed. Invariant information is information that does not change with the printing operation, such as ink cartridge signal, applicable inkjet printer signal, and ink color.

[0006] After ink cartridge 15 is installed into the print carriage 14 of the inkjet printer, the inkjet printer powers on the chip 18 and reads the data stored in the memory of the chip 18 to determine whether the signal of ink cartridge 15 is appropriate and whether the remaining ink in ink cartridge 15 is sufficient. Only after determining that the signal of ink cartridge 15 is appropriate and that there is sufficient ink in ink cartridge 15 can the inkjet printer perform the printing operation.

[0007] Since the print carriage 14 typically houses multiple ink cartridges 15, the installation status of each cartridge 15 may differ. For example, some cartridges may be correctly installed, while others may not, preventing communication with the inkjet printer. Therefore, the inkjet printer needs to verify each cartridge 15, such as checking if it is correctly installed. Typically, the inkjet printer sends a verification command to each cartridge. Upon receiving the command, the cartridge must respond within a specified timeframe, sending a correct verification response signal within the designated verification period. Only when the inkjet printer receives a correct verification response signal from a cartridge within its designated verification period will it consider the cartridge correctly installed and proceed with subsequent communication operations. If the inkjet printer deems a cartridge incorrectly installed, it issues an alarm and cannot perform any further communication or printing operations.

[0008] A current inkjet printer communicates with each ink cartridge by sending a clock signal via a clock signal line, see [link to relevant documentation]. Figure 3 The clock signal SCK is a periodically changing square wave signal. Each ink cartridge chip communicates synchronously with the inkjet printer based on the clock signal SCK. When the inkjet printer sends a verification command, it sends the same level signal on the data signal line SDA for two consecutive transmission cycles. Each transmission cycle consists of nine clock cycles; for example, the first transmission cycle consists of nine clock cycles D1 to D9, and the second transmission cycle also consists of nine clock cycles D1 to D9. In the first transmission cycle, when the inkjet printer sends a verification command for the first color ink cartridge, the data signal SDA1 sent to the data signal line includes high-level signals in the first clock cycle D1, the eighth clock cycle D8, and the ninth clock cycle D9, and low-level signals in the other clock cycles. In the second transmission cycle, the inkjet printer also sends high-level signals in the first clock cycle D1, the eighth clock cycle D8, and the ninth clock cycle D9, and low-level signals in the other clock cycles. If the first color ink cartridge receives three high-level signals in three corresponding clock cycles D1, D8, and D9 within two consecutive transmission cycles, it is considered that the inkjet printer has sent a verification command for the first color ink cartridge, and a verification response signal needs to be sent within the specified verification period.

[0009] See Figure 4In the existing technical solution, the verification period corresponding to the first color ink cartridge is the latter half of the eighth clock cycle within the first response cycle and the entire period of the eighth clock cycle within the second response cycle. Based on half a clock cycle, the verification period corresponding to the first color ink cartridge can include three verification periods, namely verification periods T1, T2, and T3. Among them, verification period T1 is the latter half of the eighth clock cycle within the first response cycle, verification period T2 is the first half of the eighth clock cycle within the second response cycle, and verification period T3 is the latter half of the eighth clock cycle within the second response cycle.

[0010] from Figure 4 It can be seen that during the first verification period T1, the ink cartridge needs to output a low-level signal to the data signal line; during the first verification period T2, the ink cartridge needs to output a high-level signal to the data signal line; and during the first verification period T3, the ink cartridge needs to output a low-level signal to the data signal line. During other time periods, since the inkjet printer does not detect the level of the data signal line SDA1, the ink cartridge does not need to output a level to the data signal line. At this time, the data signal line exhibits a high-impedance state, i.e. Figure 4 The area indicated by the dotted line. If the ink cartridge fails to output the corresponding level signal as described above, the inkjet printer will consider it incorrectly installed, affecting subsequent communication operations.

[0011] For the second color ink cartridge, the verification command sent by the inkjet printer is a high-level signal sent during the first transmission cycle of the data signal SDA2, the first clock cycle D1 of the second transmission cycle, the seventh clock cycle D7, and the ninth clock cycle D9. The three verification periods T1, T2, and T3 of the second color ink cartridge are the latter half of the seventh clock cycle in the first response cycle, the first half of the seventh clock cycle in the second response cycle, and the latter half of the seventh clock cycle in the second response cycle, respectively. The level signals of the three verification periods are low level, high level, and low level, respectively.

[0012] Similarly, for the third color ink cartridge, the verification command sent by the inkjet printer is a high-level signal sent during the first transmission cycle of data signal SDA3, the first clock cycle D1 of the second transmission cycle, the sixth clock cycle D6, and the ninth clock cycle D9. The three verification periods T1, T2, and T3 for the third color ink cartridge are the second half of the sixth clock cycle in the first response cycle, the first half of the sixth clock cycle in the second response cycle, and the second half of the sixth clock cycle in the second response cycle, respectively. Similarly, the level signals for the three verification periods are low level, high level, and low level, respectively.

[0013] For each cartridge chip, the inkjet printer only acquires the verification voltage during three verification periods, T1, T2, and T3. During other periods, it does not detect the level of the data signal lines. Typically, the cartridge chip does not apply signals to the data signal lines during these other periods, resulting in a high-impedance state for the data signal lines. Figure 5 As shown, the data signal line is grounded through a resistor R13. Typically, resistor R13 is very large, causing the main controller 60 of the inkjet printer to recognize the data signal line as a low-level signal when it is in a high-impedance state. However, even when the data signal line is in a high-impedance state, it will still appear as a low level due to the pull-down effect of the large resistor R13 inside the inkjet printer. Therefore, the high-impedance state can be considered equivalent to a weak pull-down state; thus, resistor R13 is actually a pull-down resistor.

[0014] However, because the clock signal line continuously transmits the clock signal, and the clock signal line is adjacent to the data signal line, when the data signal line is in a high-impedance state, a high-frequency pulse signal will be generated on the clock signal line, resulting in an interference signal coupled onto the data signal line. This interference signal has the same frequency as the clock signal, but its amplitude is very low, for example, only 0.4V. Figure 6 As shown. Since the voltage detection threshold of inkjet printers is usually above 1V, this interference signal is often identified as a low-level signal.

[0015] On the other hand, if a short circuit occurs between the data signal line and the clock signal line, the data signal line's voltage level during the three verification periods T1, T2, and T3 will be consistent with the clock signal line, i.e., high, low, and high respectively. Similarly, if a short circuit occurs between the data signal line and the power supply terminal or chip select terminal, the data signal line's voltage level during the three verification periods T1, T2, and T3 will all be high. If the inkjet printer receives a low-level signal during T1, T2, and T3, it is considered that the ink cartridge is not installed. Detailed judgment criteria are shown in Table 1.

[0016] Table 1

[0017]

[0018] In Table 1, Hi_Z represents a high impedance state, and Hi_Z→L indicates that although the ink cartridge chip outputs a high impedance state, it is recognized as a low-level signal due to the weak pull-down effect inside the inkjet printer.

[0019] However, when no ink cartridge is installed, the verification periods T1, T2, and T3 should ideally be in a high-impedance state. But if a high-level signal is incorrectly applied to verification period T2, or if external strong interference causes verification period T2 to be incorrectly identified as a high-level signal, and the high-impedance states of verification periods T1 and T3 are incorrectly identified as low-level signals, then the verification voltage will be the same as when the ink cartridge is installed in the inkjet printer. The inkjet printer will then incorrectly identify that the ink cartridge is correctly installed. If the ink cartridge is not installed correctly, or if the ink cartridge chip is malfunctioning, the inkjet printer will be unable to correctly recognize this, affecting the operation of the inkjet printer, impacting print quality, and potentially even damaging the inkjet printer. Summary of the Invention

[0020] The first objective of this invention is to provide a verification method that can correctly identify whether a consumable chip in a consumable container is correctly installed.

[0021] A second objective of this invention is to provide an inkjet printing device that applies the verification method for the aforementioned consumable chip.

[0022] To achieve the first objective mentioned above, the verification method for consumable chips provided by the present invention includes sending a verification command and determining the verification period of the verification response signal; and acquiring the voltage signal of the data signal line, and determining whether the output state of the data signal line is a high impedance state within the verification period based on the voltage signal. If not, and the actual level state of the data signal line is consistent with the target verification level state, the consumable chip is confirmed to have passed the verification; otherwise, the consumable chip is confirmed to be abnormal.

[0023] As can be seen from the above scheme, by judging the output state of the data signal line during the verification period, especially if it may be a high impedance state, or if the actual level state of the data signal line is inconsistent with the target verification level state, the consumable chip is confirmed to be abnormal, thus avoiding the mistaken identification of a high impedance state as a low level state and passing the verification of the consumable chip.

[0024] Furthermore, when a positive DC voltage is applied to the data signal line during the verification period, the voltage of the data signal line changes. If the data signal line is in a high-impedance state, its level will be high under the influence of the DC voltage. If the consumable chip outputs a low-level signal to the data signal line (i.e., grounds the data signal line), even if a positive DC voltage is applied, it will still be low-level because the data signal line is grounded. Therefore, this method can distinguish whether the consumable chip is outputting a low-level signal or has its data signal line in a high-impedance state, thus ensuring the accuracy of the consumable chip verification.

[0025] A preferred embodiment is that the verification period includes a first verification period, a second verification period, and a third verification period. During the first and third verification periods, a conduction control signal is output to the first switching device to turn on the first switching device. During the second verification period, a cutoff control signal is output to the first switching device to turn off the first switching device. The first switching device is connected between a first resistor and a data signal line, and one end of the first resistor is connected to a DC power supply.

[0026] Therefore, during the first and third verification periods, controlling the first switching device to conduct will result in the data signal line output being in a high-impedance state, which will be pulled up to a high-level state by the first resistor. During the second verification period, controlling the first switching device to cut off will result in the data signal line output being in a low-impedance state, which will be weakly pulled down to a low-level state by the large resistor inside the inkjet printer. If any of these three verification periods is in a high-impedance state, the actual voltage level will differ from the target verification voltage level, thus ensuring the accuracy of the consumable chip verification.

[0027] A further solution is to ground the data signal line through a pull-down resistor, with the resistance value of the first resistor being less than that of the pull-down resistor.

[0028] As can be seen, the resistance value of the first resistor is relatively small. When the data signal line is in a high-impedance state, after applying a positive DC voltage, the voltage of the data signal line received by the inkjet printer is a high-level signal, thus distinguishing whether the current state of the data signal line is a low-level output state or a high-impedance state.

[0029] An alternative approach is to output a turn-on control signal to the second and third switching devices during the verification period to turn them on. The second switching device is connected in series with the second resistor between the DC power supply and the data signal line, and the third switching device is connected in series with the third resistor between the data signal line and ground.

[0030] Therefore, it can be seen that by controlling the on / off state of two different switching devices and dividing the DC power supply with two resistors, the voltage applied to the data signal line can be controlled.

[0031] A further approach is to ground the data signal line through a pull-down resistor, with the second resistor having a lower resistance value than the pull-down resistor, and the third resistor having a lower resistance value than the pull-down resistor.

[0032] A further approach is to include the following: acquiring the voltage value of the data signal line during the verification period, and determining whether the voltage value of the data signal line is within a preset voltage division range; if so, confirming that the output state of the data signal line is high impedance during the verification period.

[0033] Since the DC voltage applied to the data signal line is in a high-impedance state when the data signal line is in a high-impedance state, the DC voltage applied to the data signal line is a DC power supply after voltage division. By judging the voltage value on the data signal line, it is possible to identify whether the data signal line is in a high-impedance state, which makes the identification more accurate.

[0034] A preferred approach is that determining whether the output state of the data signal line is in a high-impedance state based on the voltage signal during the verification period may also include: comparing the actual voltage with the upper limit threshold of the detection voltage range and comparing the actual voltage with the lower limit threshold of the detection voltage range; based on the comparison result, confirming whether the actual voltage of the data signal line during the verification period is within the preset detection voltage range; if it is within the preset detection voltage range, then confirming that the output state of the data signal line is in a high-impedance state during the verification period.

[0035] Furthermore, the upper limit threshold of the detection voltage range is less than the high-level state voltage threshold; and the lower limit threshold of the detection voltage range is greater than the ground voltage.

[0036] To achieve the second objective mentioned above, the inkjet printing device provided by the present invention includes a printing carriage on which a consumable container is detachably mounted, and a consumable chip is disposed on the consumable container; it also includes a verification circuit, which includes a main controller connected to a serial communication bus and acquires the voltage signal of the data signal line; wherein, after sending a verification command, the verification circuit determines the verification period of the verification response signal, acquires the voltage value of the data signal line during the verification period, and determines the current output state of the consumable chip based on the voltage value of the data signal line. If the current output state is a high impedance state, or the actual level state is inconsistent with the target verification level state, then the consumable chip is confirmed to be abnormal.

[0037] As can be seen from the above scheme, if the data signal line is in a high-impedance state during the verification period, it indicates that the ink cartridge is not installed on the printer carriage, or the ink cartridge chip is not correctly sending a low-level signal. In this case, the consumable chip is confirmed to be abnormal, which can ensure the accuracy of the ink cartridge chip verification.

[0038] A preferred embodiment is that the verification period includes a first verification period, a second verification period, and a third verification period. During the first and third verification periods, a conduction control signal is output to the first switching device to turn on the first switching device. During the second verification period, a cutoff control signal is output to the first switching device to turn off the first switching device. The first switching device is connected between a first resistor and a data signal line, and one end of the first resistor is connected to a DC power supply.

[0039] As can be seen from the above scheme, by applying a positive DC voltage to the data signal line during the first and third verification periods, the voltage of the data signal line changes. If the data signal line is in a high-impedance state, its level will be high under the influence of the DC voltage. During the second verification period, no positive DC voltage is applied to the data signal line. If the consumable chip outputs a high-impedance state to the data signal line, it will also present a low level due to the weak pull-down effect of the large resistance inside the inkjet printer. Therefore, by using the above method, the actual level of the consumable chip when it outputs a high-impedance state during any verification period will be inconsistent with the target verification level, thereby ensuring the accuracy of the consumable chip verification.

[0040] An alternative approach is to further configure a second and a third switching device in the verification circuit. The main controller outputs a conduction control signal to the second and third switching devices to enable them to conduct. The second switching device is connected in series with the second resistor between the DC power supply and the data signal line, and the third switching device is connected in series with the third resistor between the data signal line and ground.

[0041] As can be seen from the above scheme, the voltage applied to the data signal line can be controlled by controlling the on / off state of two different switching devices and by dividing the DC power supply with two resistors.

[0042] In a preferred embodiment, the main controller also receives the voltage value of the voltage signal from the data signal line.

[0043] An alternative approach is to include a comparison circuit in the verification circuit. The comparison circuit includes a first comparison branch and a second comparison branch. The first comparison branch compares the actual voltage of the data signal line with the upper limit threshold of a preset detection voltage range. The second comparison branch compares the actual voltage of the data signal line with the lower limit threshold of the detection voltage range. The comparison circuit outputs a comparison result signal to the main controller.

[0044] As can be seen from the above scheme, by detecting the actual voltage of the data signal line, it can be determined whether the actual voltage is within the preset detection voltage range, thereby identifying whether the data signal line is in a high-impedance state.

[0045] In a preferred embodiment, the comparison circuit further includes an AND gate, which receives the signals output from the first comparison branch and the second comparison branch, and outputs the AND result signal to the main controller. Attached Figure Description

[0046] Figure 1 This is a structural diagram of an existing inkjet printing device.

[0047] Figure 2 This is a structural diagram of an existing ink cartridge.

[0048] Figure 3 This is a waveform timing diagram of existing inkjet printing equipment sending verification commands.

[0049] Figure 4 This is a waveform timing diagram of the verification response signal sent by the existing consumable chip.

[0050] Figure 5 This is a circuit diagram of the data signal lines of an existing inkjet printer.

[0051] Figure 6 This is a waveform timing diagram of an existing inkjet printer when its data signal line is interfered with.

[0052] Figure 7 This is the electrical schematic diagram of the consumable chip verification circuit in the first embodiment of the inkjet printing device of the present invention.

[0053] Figure 8 This is a waveform timing diagram of the verification response signal received by the inkjet printing device in the first embodiment of the consumable chip verification method of the present invention.

[0054] Figure 9 This is the electrical schematic diagram of the consumable chip verification circuit in the second embodiment of the inkjet printing device of the present invention.

[0055] Figure 10 This is a waveform timing diagram of the verification response signal received by the inkjet printing device in the second embodiment of the consumable chip verification method of the present invention.

[0056] Figure 11 This is the electrical schematic diagram of the consumable chip verification circuit in the third embodiment of the inkjet printing device of the present invention.

[0057] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0058] The consumable chip verification method of the present invention can be applied to printing equipment such as inkjet printing equipment. For example, the consumable chip is an ink cartridge chip installed on the side wall of the ink cartridge. Multiple ink cartridge chips can be installed on the inkjet printing equipment. Preferably, the inkjet printing equipment and the ink cartridge chip communicate with each other via a serial bus.

[0059] First embodiment:

[0060] In this embodiment, the consumable container is a removable ink cartridge that can be installed into the inkjet printer. The ink cartridge contains an ink cartridge chip, which serves as the consumable chip. One surface of the ink cartridge chip has multiple connection terminals, including clock terminals, data terminals, power terminals, chip select terminals, and ground terminals. The inkjet printer's printhead carriage has a stylus holder with multiple stylus pins. The connection terminals of the ink cartridge chip can be electrically connected to these stylus pins. The inkjet printer communicates with the multiple ink cartridge chips serially via an SPI bus. For example, the serial bus includes clock signal lines and data signal lines. The inkjet printer outputs a clock signal SCK to the clock signal line. Each ink cartridge chip receives the clock signal through its respective clock terminal and communicates synchronously with the inkjet printer based on the clock signal.

[0061] In addition, each color ink cartridge chip transmits data signals to the inkjet printer via a data signal line. For example, the data signal between the inkjet printer and the first color ink cartridge is SDA1, the data signal with the second color ink cartridge is SDA2, the data signal with the third color ink cartridge is SDA3, and so on. This embodiment only uses the SDA1 used by one color ink cartridge as an example for explanation.

[0062] It should be noted that SDA1, SDA2, and SDA3 can be the same data signal line. In the diagram, SDA1, SDA2, and SDA3 represent signals on the data signal line during different time periods. That is, the signal used by the inkjet printer to communicate with the first color ink cartridge on the data signal line during the first time period is SDA1. Similarly, the signal used by the inkjet printer to communicate with the second color ink cartridge on the data signal line during the second time period is SDA2, and the signal used by the inkjet printer to communicate with the third color ink cartridge on the data signal line during the third time period is SDA3. At the same time, SDA1, SDA2, and SDA3 can also be different data signal lines. Different color ink cartridges are connected to the inkjet printer through different data signal lines, and the inkjet printer communicates with different color ink cartridges synchronously or asynchronously.

[0063] After the ink cartridges are installed on the printing carriage, the inkjet printer needs to verify the installation of each cartridge, that is, to determine whether each cartridge is installed correctly. Specifically, the inkjet printer sends verification commands to each cartridge chip, for example, sending a high-level signal in the preset clock cycle of the first sending cycle and a high-level signal in the preset clock cycle of the second sending cycle. Usually, the preset clock cycles of the two sending cycles are the same. Figure 3 As shown, for the first color ink cartridge chip, the preset clock cycle is the eighth clock cycle D8, for the second color ink cartridge chip, the preset clock cycle is the seventh clock cycle D7, and so on.

[0064] After receiving the corresponding verification command, the ink cartridge chip needs to respond within a specified time, that is, output a verification response signal to the inkjet printer. As mentioned earlier, the first color ink cartridge needs to output a low-level signal in the second half of the eighth clock cycle D8 of the first response cycle, and output a high-level signal in the first half of the eighth clock cycle D8 of the second response cycle, and output a low-level signal in the second half of the eighth clock cycle D8 of the second response cycle.

[0065] Therefore, the cartridge chip needs to determine the verification period corresponding to the received verification command. For example, the second half of the eighth clock cycle D8 of the first response cycle is the first verification period T1, the first half of the eighth clock cycle D8 of the second response cycle is the second verification period T2, and the second half of the eighth clock cycle D8 of the second response cycle is the second verification period T3. Furthermore, the cartridge chip also needs to determine the verification voltage for each verification period. For example, a low-level signal should be output in the first verification period T1, a high-level signal should be output in the second verification period T2, and a low-level signal should be output in the third verification period T3.

[0066] To prevent the inkjet printer from incorrectly identifying a high-impedance data signal line as a low-level signal, this embodiment improves the inkjet printer by incorporating a special verification circuit. See also... Figure 7 The verification circuit 20 of the inkjet printer includes a main controller 21. The main controller 21 has a terminal SDA_IN for receiving data signals, which is connected to the data signal line and receives the data signal SDA transmitted by the data signal line. It should be noted that the terminal SDA_IN for receiving data signals can also be set to the terminal SDA_OUT for transmitting data signals at different times, depending on whether the inkjet printer needs to transmit or receive data signals at the current moment. Of course, when the inkjet printer does not need to receive or transmit data signals, it can also be set to a floating state. In the prior art, when the data signal line of the inkjet printer is set as input, its internal circuitry is equivalent to... Figure 5The circuit shown is not a true floating input. For example, the equivalent resistance R13 of the data signal line to ground is very large, approximately 10M to 100M ohms, which is the so-called "weak pull-down". Therefore, the equivalent resistance R13 constitutes the pull-down resistor in this embodiment. At this time, if there is a clock pulse signal on the clock signal line, the data signal line will be affected by the coupling effect of the clock signal and form an interference signal. The main controller 21 will receive these interference signals. In order to avoid the interference signal affecting the cartridge chip verification and to distinguish whether the data signal line is in a "weak pull-down" state or is input with a low level, in this embodiment, the main controller 21 outputs a high level at the terminal PULL_EN in the first verification period T1 and the third verification period T3, thereby putting the field-effect transistor Q1 into the conducting state, and outputs a low level in the second verification period T2, thereby putting the field-effect transistor Q1 into the cut-off state.

[0067] If the ink cartridge chip is correctly installed and outputs a low-level signal, a high-level signal, and a low-level signal respectively during the three verification periods T1, T2, and T3, then during the period when the high-level signal is output, on the one hand, the DC power supply VCC applies a positive DC voltage to the data signal line through the resistor R1, and on the other hand, the high-level signal is directly input to the terminal SDA_IN of the main controller 21 through the data signal line. At this time, the terminal SDA_IN of the main controller 21 receives the high-level signal.

[0068] When the ink cartridge chip applies a low-level signal to the data signal line, since the low-level signal output by the ink cartridge chip is generally close to 0V, the equivalent resistance R13 is short-circuited, and the voltage on the data signal line is approximately 0. The main controller 21 recognizes that the ink cartridge chip outputs a low-level signal at this time.

[0069] If the data signal line is in a high-impedance state during the first verification period T1 and the third verification period T3, then resistor R1 and equivalent resistor R13 are connected to the data signal line. The voltage output by the DC power supply VCC is divided by the first resistor R1 and the equivalent resistor R13. However, since the resistance value of the equivalent resistor R13 is much greater than the resistance value of the first resistor R1, the voltage formed on the SDA_IN terminal of the main controller 21 is relatively high, close to the voltage of the DC power supply VCC. At this time, the inkjet printer recognizes it as a high level.

[0070] If the data signal line T2 is in a high-impedance state during the second verification period, the data signal line will still be in a weak pull-down state because the field-effect transistor Q1 is cut off. The main controller 21 recognizes that the ink cartridge chip outputs a low-level signal at this time.

[0071] like Figure 8As shown, if the data signal line is in a high-impedance state, it will be high during verification periods T1 and T3, and low during the second verification period T2. Even if a high level is incorrectly applied during the second verification period T2, the inkjet printer will still recognize a short circuit in the cartridge chip because all three verification periods T1, T2, and T3 output high-level signals, which is equivalent to a short circuit between the data signal line and the power supply terminal or chip select terminal. This avoids situations where the cartridge chip passes verification even when it is in a high-impedance state during verification periods T1 and T3.

[0072] When verifying the ink cartridge chip, the system determines whether the signal level is low, high, and low respectively during the three verification periods T1, T2, and T3. If so, the ink cartridge chip is considered to have passed the verification; otherwise, it is considered to be faulty. Detailed determinations in this embodiment are shown in Table 2.

[0073] Table 2

[0074]

[0075] It is understood that this embodiment needs to determine whether the output state of the data signal line is a possible high-impedance state during the verification periods T1, T2, and T3. A possible high-impedance state is a state that can be a high-impedance state. For example, during verification periods T1 and T3, if the main controller 21 receives a high-level signal at terminal SDA_IN, it indicates that the output state of the data signal line may be high or high impedance. In this case, the output state of the data signal line during verification periods T1 and T3 is considered to be a possible high impedance state. Only when the output state of the data signal line is low is the possibility of a high impedance state ruled out, and it is determined that verification periods T1 and T3 are not possible high impedance states. Similarly, during the second verification period T2, if the main controller 21 receives a low-level signal at terminal SDA_IN, it indicates that the output state of the data signal line may be low or high impedance. In this case, the output state of the data signal line during the second verification period T2 is considered to be a possible high impedance state. Only when the output state of the data signal line is high is the possibility of a high impedance state ruled out, and it is determined that the second verification period T2 is not a possible high impedance state.

[0076] During the verification period, the data signal line is not in a high-impedance output state and the actual level of the data signal line is consistent with the target verification level. The target verification level is the level that meets the verification requirements in advance. For example, the low-level signal, high-level signal, and low-level signal are output in the three verification periods T1, T2, and T3, respectively. If both of the above conditions are met at the same time, the ink cartridge chip is confirmed to have passed the verification. Otherwise, the ink cartridge chip is confirmed to have an abnormality.

[0077] In a preferred embodiment, the data signal line can be pulled down to ground via a resistor during the second verification period T2, while remaining pulled up during the first verification periods T1 and T3. This pull-down method significantly reduces the impact of external interference on the data signal line. Similarly, only when the second verification period T2 is confirmed to output a high level can the possibility of a high-impedance output on the data signal line be ruled out. Since the target verification level for the second verification period T2 is a high level, the accuracy of the consumable chip verification can also be ensured.

[0078] In other embodiments, the field-effect transistor Q1 can be turned on in all three verification periods T1, T2, and T3. This reduces the computational processing requirements of the inkjet printer. Even if the first resistor R1 pulls the data signal line on in the second verification period T2, the high impedance state is identified as a high level state. That is, the high level state in the second verification period T2 is a possible high impedance state, but it will also be identified as a high level state when the data signal line is in the high impedance state in the first verification period T1 and the third verification period T3. And it is different from the target verification level. Therefore, the inkjet printer will still indicate that the ink cartridge chip is abnormal.

[0079] Second embodiment:

[0080] In the first embodiment, although the inkjet printing device can distinguish whether the data signal line outputs a high impedance state or a low level signal, the determination result is the same as when the clock terminal is short-circuited. In order to overcome this problem, the circuit has been improved in this embodiment.

[0081] See Figure 9 In the inkjet printing device of this embodiment, the verification circuit 30 is provided with a field-effect transistor Q2 as a second switching device and a field-effect transistor Q3 as a third switching device, and is also provided with a second resistor R2 and a third resistor R3. The main controller 31's terminal PULL_EN simultaneously outputs control signals to the field-effect transistors Q2 and Q3, such as outputting a high level or a low level to the gate of the field-effect transistors Q2 and Q3 to control the field-effect transistors Q2 and Q3 to be in the on state or the off state.

[0082] Field-effect transistor Q2 is connected in series with the second resistor R2 and is connected between the DC power supply VCC and the data signal line. Field-effect transistor Q3 is connected in series with the third resistor R3 and is connected between the data signal line and ground. In addition, the main controller 31 also samples the voltage of the data signal line through the terminal ADC, that is, it specifically detects the voltage magnitude of the data signal line.

[0083] In this embodiment, after the field-effect transistors Q2 and Q3 are turned on and the data signal line is in a high-impedance state, the second resistor R2 and the third resistor R3 divide the DC power supply VCC and apply the divided voltage to the data signal line. Furthermore, the resistances of the second resistor R3 and the third resistor R3 are much smaller than the resistance of the equivalent resistance R13; for example, the second resistor R2 is 10K ohms and the third resistor R3 is 20K ohms.

[0084] When the ink cartridge chip is being verified, for example during the first verification period T1 of the first response cycle, the second verification period T2 of the second response cycle, and the third verification period T3, the main controller 21 controls the field-effect transistors Q2 and Q3 to be in the on state, and controls the field-effect transistors Q2 and Q3 to be in the off state during other periods.

[0085] If the cartridge chip is correctly installed and outputs low-level, high-level, and low-level signals respectively during the three verification periods T1, T2, and T3, then during the period when the high-level signal is output, on the one hand, the DC power supply VCC applies a positive DC voltage to the data signal line through resistors R2 and R3. This voltage value is equal to R3 / (R2+R3)*VCC. When the second resistor R2 is 10K ohms and the resistance of the third resistor R3 is 20K ohms, this voltage division is 2 / 3VCC. On the other hand, since a high-level signal is also input to the data signal line at the same time, the voltage value of this high-level signal is generally about equal to VCC. The superposition of these two voltages on the data signal line will make the voltage on the data signal line close to VCC. At this time, the SDA_IN terminal of the main controller 31 receives a high-level signal, and the detection result of the ADC is also close to the DC power supply VCC.

[0086] When the ink cartridge chip applies a low-level signal to the data signal line, since the low-level signal output by the ink cartridge chip is generally close to 0V, the third resistor R3 and the equivalent resistor R13 are both short-circuited. The DC power supply VCC forms a loop only through the second resistor R2. The voltage on the SDA_IN terminal of the main controller 31 is very low, close to 0. The main controller 31 recognizes that the ink cartridge chip outputs a low-level signal at this time.

[0087] If the data signal line is in a high-impedance state, the resistance value of the third resistor R3 connected in parallel with the equivalent resistor R13 is close to the resistance value of the third resistor R3. Therefore, the voltage signal formed on the data signal line is approximately 2 / 3 of the DC power supply VCC. Typically, the DC power supply VCC is 3.3V, therefore, the voltage on the data signal line is 2.2V. Since the high-level threshold voltage of the main controller 31 is usually around 1.65V, the main controller 31 will recognize the current level signal as a high-level signal.

[0088] In addition, the main controller 31 also receives the voltage of the data signal line through the terminal ADC and determines whether the voltage of the data signal line is within the preset voltage division range, such as between 2.0V and 2.4V. If so, it considers the data signal line to be in a high impedance state, that is, the ink cartridge chip is abnormal.

[0089] like Figure 10 As shown, if the data signal line is in a high-impedance state, both T1 and T3 will be at a high level, but the voltage value at this high level is only 2 / 3 of the DC power supply VCC. Even if a high level is incorrectly applied in the second verification period T2, the inkjet printer will identify that the ink cartridge chip is not correctly installed because all three verification periods T1, T2, and T3 output high-level signals. This avoids the situation where the ink cartridge chip can still pass verification even though it is in a high-impedance state during verification periods T1 and T3. Furthermore, by setting the ADC to detect the voltage values ​​at times T1 and T3, it is possible to distinguish whether a high level or a high-impedance state is output at times T1 and T3. The detailed determination situation in this embodiment is shown in Table 3.

[0090] Table 3

[0091]

[0092] It is understandable that if the voltage value during the high level of verification periods T1 and T3 is only 2 / 3 of the DC power supply VCC, then it can be considered that there is a possibility of a high-resistance state during verification periods T1 and T3. If the existence of a high-resistance state is confirmed, then the cartridge chip is considered abnormal.

[0093] Of course, in other embodiments, all peripheral circuitry can be eliminated, and only the ADC can be used to sample the voltage signal on the data signal line, and the sampling result can be used to determine whether the current verification period is high-level, low-level, or high-impedance. As mentioned earlier, when the data signal line is in a high-impedance state and the clock signal line is in a high-level state, i.e., during verification periods T1 and T3, a 0.4V interference signal will be coupled onto the data signal line. Therefore, it can be set so that when the voltage is above 1.5V, it is identified as a high-level signal; when the voltage is between 0.2V and 1.0V, it is identified as a high-impedance state; and when the voltage is less than 0.2V, it is identified as a low-level signal. Of course, this method places very high demands on the input impedance, conversion speed, and accuracy of the ADC, and may require the use of specialized discrete ADC components.

[0094] Of course, in other embodiments, field-effect transistors Q2 and Q3 can be kept in the on state throughout the entire response cycle.

[0095] Third embodiment:

[0096] In both the first and second embodiments, when the data signal line outputs a high-impedance state, whether the data signal line is pulled up by a resistor or the voltage signal on the data signal line is divided by a resistor, its original state—the high-impedance state (i.e., the weak pull-down state)—is disrupted. Sometimes, changing the actual state of the data signal line may lead to other unexpected problems. Furthermore, using a high-impedance, high-speed ADC will increase costs.

[0097] To address this issue, this embodiment uses a comparator with a high input impedance to determine the voltage input to the data signal line. See [link to relevant documentation]. Figure 11 In this embodiment, a comparison circuit is provided in the verification circuit 40 of the inkjet printer. The comparison circuit includes a first comparison branch and a second comparison branch. The first comparison branch includes a voltage comparator U1 and an inverter U3. The second comparison branch includes a second comparator U2. The comparison circuit also includes an AND gate U4. The two input terminals of the AND gate U4 receive the signals output by the first comparison branch and the second comparison branch, respectively.

[0098] The first comparison branch compares the actual voltage of the data signal line with the upper threshold of a preset detection voltage range. For example, the positive input of voltage comparator U1 receives the voltage of the data signal line, and the negative input receives the upper threshold of the detection voltage range, such as a 1.5V voltage signal. The output of voltage comparator U1 is connected to inverter U3. The second comparison branch compares the actual voltage of the data signal line with the lower threshold of the detection voltage range. For example, the positive input of voltage comparator U2 receives the voltage of the data signal line, and the negative input receives the lower threshold of the detection voltage range, such as a 0.2V voltage signal. The upper and lower thresholds of the detection voltage can be implemented using a bandgap reference circuit or a low-dropout linear regulator (LDO), which will not be elaborated further here.

[0099] During detection, on one hand, the signal voltage on the data signal line is compared with the upper threshold of the detection voltage range. If the comparison result A1 is true, it indicates that the signal on the data signal line is a low-level signal. On the other hand, the signal voltage on the data signal line is compared with the lower threshold of the detection voltage range. If the comparison result A2 is true, it indicates that the voltage of the signal is greater than 0.2V. Finally, the comparison results A1 and A2 are ANDed by AND gate U4 and input to terminal SEL of the main controller 41 of the verification circuit 40. If the signal received by terminal SEL is high-level, i.e., true, it indicates that the voltage value of the current data signal line is between 0.2V and 1.5V, thus determining whether the current verification period is a low-level signal or a high-impedance state. The detailed determination process in this embodiment is shown in Table 4.

[0100] Table 4

[0101]

[0102]

[0103] It is understandable that if the signal received by terminal SEL is high, it can be assumed that a high-impedance state exists during verification periods T1 and T3, meaning that a high-impedance state is a possible state during verification periods T1 and T3. If a high-impedance state is confirmed, the cartridge chip is considered malfunctioning.

[0104] Since the input impedance of a typical voltage comparator is much higher than that of an ADC and the equivalent pull-down resistor R13 inside an inkjet printer, and it is low in cost, fast in operation, and easier to integrate into control units such as MCUs and FPGAs, the circuit provided in this embodiment allows inkjet printers to more quickly and accurately identify whether the current verification period is low or high impedance. Furthermore, when the current verification period is high impedance, it will not disrupt the current state and avoid the occurrence of other abnormal situations.

[0105] As can be seen, this invention can determine whether the data signal line is in a high-impedance state. If the data signal line is in a high-impedance state during the verification period, it will be considered that the ink cartridge chip is abnormal and an alarm message will be issued in time to avoid the inkjet printer from operating when the ink cartridge is not installed correctly, which would affect the printing quality or cause damage to the inkjet printer.

[0106] Finally, it should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A verification method for consumable chips, applied to inkjet printing equipment, the method comprising: Send a verification command and determine the verification period for the verification response signal; Its features are: The inkjet printer acquires the voltage signal of the data signal line and determines whether the output state of the data signal line is a high-impedance state based on the voltage signal during the verification period. If not, and the actual level state of the data signal line is consistent with the target verification level state, the consumable chip is confirmed to have passed the verification; otherwise, the consumable chip is confirmed to be abnormal.

2. The verification method for consumable chips according to claim 1, characterized in that: The verification period includes a first verification period, a second verification period, and a third verification period. During the first verification period and the third verification period, a conduction control signal is output to the first switching device to make the first switching device conduct. During the second verification period, a cutoff control signal is output to the first switching device to make the first switching device cut off. The first switching device is connected between the first resistor and the data signal line, and one end of the first resistor is connected to a DC power supply.

3. The verification method for consumable chips according to claim 2, characterized in that: The data signal line is grounded through a pull-down resistor, and the resistance value of the first resistor is less than the resistance value of the pull-down resistor.

4. The verification method for consumable chips according to claim 1, characterized in that: During the verification period, a conduction control signal is output to the second and third switching devices to turn them on. The second switching device and the second resistor are connected in series between the DC power supply and the data signal line, and the third switching device and the third resistor are connected in series between the data signal line and ground.

5. The verification method for consumable chips according to claim 4, characterized in that: The data signal line is grounded through a pull-down resistor, the resistance value of the second resistor is less than the resistance value of the pull-down resistor, and the resistance value of the third resistor is less than the resistance value of the pull-down resistor.

6. The verification method for consumable chips according to claim 4 or 5, characterized in that: The method further includes: acquiring the voltage value of the data signal line during the verification period, and determining whether the voltage value of the data signal line is within a preset voltage division range; if so, confirming that the output state of the data signal line is a high-impedance state during the verification period.

7. The verification method for consumable chips according to claim 1, characterized in that: During the verification period, determining whether the output state of the data signal line is in a high-impedance state based on the voltage signal may also include: The actual voltage of the data signal line is compared with the upper limit threshold of the detection voltage range, and the actual voltage is compared with the lower limit threshold of the detection voltage range. Based on the comparison result, it is confirmed whether the actual voltage is within the preset detection voltage range during the verification period. If it is within the preset detection voltage range, it is confirmed that the output state of the data signal line is high impedance during the verification period.

8. The verification method for consumable chips according to claim 7, characterized in that: The upper threshold of the detection voltage range is less than the high-level state voltage threshold. The lower limit threshold of the detection voltage range is greater than the ground voltage.

9. Inkjet printing equipment, including: A printing carriage, on which a consumable container is detachably mounted, and a consumable chip is provided on the consumable container; The verification circuit includes a main controller connected to a serial communication bus and acquiring voltage signals from data signal lines. Its features are: After sending a verification command, the verification circuit determines the verification period of the verification response signal, acquires the voltage value of the data signal line during the verification period, and judges the current output state of the consumable chip based on the voltage value of the data signal line. If the current output state is a high impedance state, or the actual level state is inconsistent with the target verification level state, then the consumable chip is confirmed to be abnormal.

10. The inkjet printing apparatus according to claim 9, characterized in that: The verification period includes a first verification period, a second verification period, and a third verification period. During the first and third verification periods, a conduction control signal is output to the first switching device to turn on the first switching device. During the second verification period, a cutoff control signal is output to the first switching device to turn off the first switching device. The first switching device is connected between a first resistor and the data signal line. One end of the first resistor is connected to a DC power supply.

11. The inkjet printing apparatus according to claim 9, characterized in that: The verification circuit is further provided with a second switching device and a third switching device. The main controller outputs a conduction control signal to the second switching device and the third switching device to turn on the second switching device and the third switching device. The second switching device and the second resistor are connected in series between the DC power supply and the data signal line. The third switching device and the third resistor are connected in series between the data signal line and ground.

12. The inkjet printing apparatus according to claim 11, characterized in that: The main controller also receives the voltage value of the voltage signal of the data signal line.

13. The inkjet printing apparatus according to claim 9, characterized in that: The verification circuit is further provided with a comparison circuit, which includes a first comparison branch and a second comparison branch. The first comparison branch compares the actual voltage of the data signal line with the upper limit threshold of a preset detection voltage range. The second comparison branch compares the actual voltage of the data signal line with the lower limit threshold of the detection voltage range. The comparison circuit outputs a comparison result signal to the main controller.

14. The inkjet printing apparatus according to claim 13, characterized in that: The comparison circuit further includes an AND gate, which receives the signals output from the first comparison branch and the second comparison branch, and outputs the AND result signal to the main controller.

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