Vertical Capacitively Coupled Gate Controlled Junction Field Effect Transistor

Abstract

The embodiment of the present application provides a vertical capacitively coupled gate-controlled junction field effect transistor, comprising: a substrate and an epitaxial layer, the epitaxial layer is located above the substrate; two bottom gates of the second doping type are formed in the epitaxial layer and are arranged at a lateral interval; a combined top gate of the second doping type, the top gate comprises a top gate inner region and a top gate outer region, the top gate inner region is formed from top to bottom in the epitaxial layer, the top gate outer region surrounds the bottom surface and the side surface of the top gate inner region, and there is a gap between the top gate outer region and the bottom gate; wherein the doping concentration of the top gate outer region is less than the doping concentration of the top gate inner region, and the top gate is in a floating state; a dielectric layer is located above the top gate; and a coupling capacitor upper electrode is formed on the dielectric layer. The present application solves the technical problem that the process window of the traditional vertical capacitively coupled gate-controlled junction field effect transistor is extremely small.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a vertical capacitively coupled gate-controlled junction field effect transistor. Background Art

[0002] like Figure 1 As shown, the top gate 8 of the vertical capacitively coupled gate-controlled junction field effect transistor in patent CN117637854B has almost no process window and is extremely difficult to manufacture. Among them, substrate 1-1, epitaxial layer 1-2, bottom gate 1-3, second doping type source region 1-4, channel 1 1-5, channel 2 1-6, first doping type source region 1-7, top gate 1-8, dielectric layer 1-9, coupling capacitor upper electrode 1-10, source 1-12, drain 1-13.

[0003] The problems of the vertical capacitively coupled gate-controlled junction field effect transistor in patent CN117637854B are as follows:

[0004] (1) The process window of top gate 1-8 is small and the manufacturing difficulty is high.

[0005] (2) The on-resistance Ron,sp at high temperature is dozens of times that at room temperature, while practical applications require that the on-resistance Ron,sp at high temperature be within 3 times that at room temperature.

[0006] Therefore, the process window of the traditional vertical capacitive-coupled gate-controlled junction field-effect transistor is extremely small, which is a technical problem that technical personnel in this field urgently need to solve.

[0007] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0008] The embodiment of the present application provides a vertical capacitive-coupled gate-controlled junction field effect transistor to solve the technical problem of extremely small process window of traditional vertical capacitive-coupled gate-controlled junction field effect transistors.

[0009] A vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application includes:

[0010] A substrate of a first doping type and an epitaxial layer of the first doping type, wherein the epitaxial layer is located above the substrate;

[0011] Two bottom gates of the second doping type are formed in the epitaxial layer and are spaced apart in the lateral direction;

[0012] A combined top gate of the second doping type, wherein the top gate comprises a top gate inner region and a top gate outer region, wherein the top gate inner region is formed from top to bottom in the epitaxial layer, the top gate outer region surrounds the bottom surface and the side surface of the top gate inner region, and there is a gap between the top gate outer region and the bottom gate; wherein the doping concentration of the top gate outer region is less than the doping concentration of the top gate inner region, and the top gate is in a floating state;

[0013] A dielectric layer, located above the top gate;

[0014] The upper electrode of the coupling capacitor is formed on the dielectric layer.

[0015] The embodiment of the present application adopts the above technical solution, which has the following technical effects:

[0016] In the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application, the top gate outer region surrounds the bottom and side surfaces of the top gate inner region, and the doping concentration of the top gate outer region is less than the doping concentration of the top gate inner region. In the top gate, since the doping concentration of the top gate outer region is less than the doping concentration of the top gate inner region, the potential change trend is steeper only in the top gate inner region, and the potential change trend is slower in the top gate outer region. That is, if the thickness of the top gate outer region is larger or smaller, the overall potential change of the top gate outer region is smaller, that is, the top gate outer region has a larger process tolerance, so that the entire vertical capacitively coupled gate-controlled junction field effect transistor is a device with a larger process tolerance, thereby making the process window of the entire vertical capacitively coupled gate-controlled junction field effect transistor larger, and realizing the mass production preparation of the vertical capacitively coupled gate-controlled junction field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 It is a schematic diagram of patent CN117637854B in the background technology;

[0019] Figure 2-1 A schematic diagram of a first implementation of a vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0020] Figure 2-2 A schematic diagram of a second implementation of a vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0021] Figure 2-3 A schematic diagram of a third implementation of a vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0022] Figure 2-4 A schematic diagram of a fourth implementation of a vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0023] Figure 3 It is a simulation diagram of the potential curve of the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application and the top gate position of the patent CN117637854B in the background technology;

[0024] Figure 4 This is an energy band simulation diagram of the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application and the top gate position of the patent CN117637854B in the background technology.

[0025] Reference numerals:

[0026] In the background technology:

[0027] Substrate 1-1, epitaxial layer 1-2, bottom gate 1-3, second doping type source region 1-4, channel 1-5,

[0028] Channel 2 1-6, first doping type source region 1-7, top gate inner region 1-8, dielectric layer 1-9,

[0029] Coupling capacitor upper electrode 1-10, source 1-12, drain 1-13;

[0030] In this application:

[0031] Substrate 1, epitaxial layer 2, bottom gate 3, second doping type source region 4, channel 1 5,

[0032] Channel 2 61, current spreading layer 62, first doping type source region 7, top gate inner region 81, top gate outer region 82,

[0033] Dielectric layer 9, buffer layer 100,

[0034] The coupling capacitor has an upper electrode 10 , a gate electrode 11 , a source electrode 12 , and a drain electrode 13 . DETAILED DESCRIPTION

[0035] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. Embodiment 1

[0036] like Figure 2-1 , Figure 2-2 , Figure 2-3 and Figure 2-4As shown, the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application includes:

[0037] A substrate 1 of a first doping type and an epitaxial layer 2 of a first doping type, wherein the epitaxial layer 2 is located above the substrate 1;

[0038] Two bottom gates 3 of the second doping type are formed in the epitaxial layer and are spaced apart in the lateral direction;

[0039] A combined top gate of the second doping type, wherein the top gate comprises a top gate inner region 81 and a top gate outer region 82, wherein the top gate inner region 81 is formed from top to bottom in the epitaxial layer, the top gate outer region 82 surrounds the bottom surface and the side surface of the top gate inner region 81, and there is a gap between the top gate outer region 82 and the bottom gate 3; wherein the doping concentration of the top gate outer region 82 is less than the doping concentration of the top gate inner region 81, and the top gate is in a floating state;

[0040] A dielectric layer 9, located above the top gate;

[0041] A coupling capacitor upper electrode 10 is formed on the dielectric layer 9;

[0042] The top gate is indirectly controlled by the dielectric layer 9 between the upper electrode 10 of the coupling capacitor.

[0043] In the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application, the top gate outer region 82 surrounds the bottom and side surfaces of the top gate inner region 81, and the doping concentration of the top gate outer region 82 is less than the doping concentration of the top gate inner region 81, so that the potential difference of the top gate from the outer surface of the top gate outer region 82 to the top surface of the top gate inner region 81 is relatively slow.

[0044] In the semiconductor field, under the condition of uniform doping, the P-type doping region The electric potential expression at the position The following relationship (1) is satisfied:

[0045]

[0046] Where e is the electron charge, is the doping concentration of the P-type doping region, is the semiconductor dielectric constant, is the position where the electric field E is zero.

[0047] From this, we can see that in two P-type doping regions with different doping concentrations, when the positions where the electric field E is zero in the two P-type doping regions are the same, which P-type doping region is higher? The smaller the The same) potential That is, the smaller the P-type doping region The position is relative to the position where the electric field E is zero The potential difference is small. In this way, the flow channel for carriers increases, widening the process window of the vertical capacitively coupled gate-controlled junction field effect transistor. The process window and current channel widening are achieved simultaneously.

[0048] In this application, the position where the electric field E is zero It is the surface of the top gate inner region 81. The top gate outer region 82 surrounds the bottom and side surfaces of the top gate inner region 81, and the doping concentration of the top gate outer region 82 is less than the doping concentration of the top gate inner region 81, so that the potential difference of the top gate from the outer surface of the top gate outer region 82 to the top surface of the top gate inner region 81 is relatively slow. The process window and the current channel widening are achieved simultaneously. By controlling the concentration of the channel, the magnitude of the on-current can be controlled.

[0049] Taking the vertical capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application as an NMOS transistor as an example, the gate (i.e., the upper electrode 10 of the coupling capacitor) is connected to the positive voltage of the gate voltage (e.g., 15 volts), and the source of the field effect transistor is grounded. When the drain is connected to the positive voltage, an electric field is generated between the drain and the source, thereby generating a conduction current. The direction of the current is as follows: Figure 2-1 , Figure 2-2 , Figure 2-3 and Figure 2-4 shown.

[0050] When the bias voltage of the gate (i.e., the upper electrode 10 of the coupling capacitor) is less than or equal to 0V, the potential of the top gate inner region 81 is less than or equal to 0.8V (i.e., consistent with the bias voltage), and the top gate outer region 82 and the channel ( Figure 2-1 , Figure 2-2 and Figure 2-3 Middle finger channel 15, in Figure 2-1 The PN junction formed by the middle finger epitaxial layer (located between the top gate outer region 82 and the bottom gate 3) is reverse biased, the channel is pinched off, and the vertical capacitively coupled gate-controlled junction field effect transistor of the present application is turned off.

[0051] In addition, through simulation, it can be found that the on-resistance Ron,sp of the vertical capacitive-coupled gate-controlled junction field effect transistor of the embodiment of the present application under high temperature conditions is within 3 times of that at normal temperature, and is compatible with the application of existing SiC MOSFETs. That is, the application scenarios of the vertical capacitive-coupled gate-controlled junction field effect transistor of the embodiment of the present application are compatible with the existing technology and have strong versatility.

[0052] In the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application, the top gate of the JFET region 1 is indirectly controlled by the dielectric layer 9 separated by the coupling capacitor upper electrode 10; that is, a dielectric layer 9 is formed on the top gate, and the coupling capacitor upper electrode 10 serving as the gate electrode is connected to the dielectric layer 9; the potential of the top gate is obtained by capacitive coupling. The gate voltage applied to the coupling capacitor upper electrode 10 is coupled to the top gate by coupling, and since the top gate is in a floating state, the potential of the top gate is lower than the potential of the coupling capacitor upper electrode 10. The potential of the top gate is limited to not exceeding 3V, but by controlling the thickness and material of the dielectric layer 9, the potential of the coupling capacitor upper electrode 10 can be raised to above 3V (exceeding 3V, such as 15V, 18V), and it will not cause the top gate 8 to be in contact with the channel (in Figure 2-1 , Figure 2-2 and Figure 2-3 Middle finger channel 5, in Figure 2-1 The PN junction formed by the epitaxial layer (the middle finger is located between the top gate outer region 82 and the bottom gate 3) is turned on, which will not affect the current characteristics of the device from the drain to the source. At the same time, the transistor current in the present application flows through the channel 5 instead of the interface formed by the epitaxial layer and the dielectric layer 9, and there is no influence of the interface state, so that the transistor of the present application has high reliability.

[0053] Specifically, the top gate inner region 81 is heavily doped.

[0054] The heavily doped top gate inner region 81 is used to disconnect the depletion region on the surface of the top gate, thereby meeting the requirement of blocking withstand voltage.

[0055] In practice, the doping concentration of the top gate outer region 82 is 1 to 2 orders of magnitude lower than the doping concentration of the top gate inner region 81 .

[0056] Specifically, the first doping type is P-type doping, and the second doping type is N-type doping; or the first doping type is N-type doping, and the second doping type is P-type doping.

[0057] In implementation, such as Figure 2-1 , Figure 2-2 , Figure 2-3 and Figure 2-4 As shown, the cross section of the top gate outer region 82 is U-shaped, the inner bottom of the top gate outer region 82 is wrapped around the bottom surface of the top gate inner region 81 , and the inner wall of the top gate outer region 82 is wrapped around the side surface of the top gate inner region 81 .

[0058] In this way, the top gate outer region 82 wraps the bottom and side surfaces of the top gate inner region 81, so that both the bottom and side surfaces of the top gate inner region 81 have the top gate outer region 82 with a slower potential change, making the overall process window of the top gate larger.

[0059] In the implementation, the doping concentration of the top gate outer region 82 is in the range of greater than or equal to 2×10 17 cm-3 Less than or equal to 5×10 18 cm -3 The doping concentration of the top gate inner region 81 is in the range of greater than or equal to 2×10 18 cm -3 Less than or equal to 4×10 20 cm -3 .

[0060] In implementation, the thickness of the bottom of the top gate outer region 82 ranges from 0.02 μm to 0.2 μm, and the thickness of the sidewall of the top gate outer region 82 ranges from 0.02 μm to 0.2 μm.

[0061] The thickness of the top gate inner region 81 ranges from 0.02 μm to equal to 0.1 μm.

[0062] The doping concentration and thickness of the top gate inner region 81 meet the above value range requirements to prevent the depletion region on the surface of the top gate inner region 81 from being connected during blocking, resulting in low withstand voltage. That is, to achieve the depletion region on the surface of the top gate inner region 81 is not connected, and meet the blocking withstand voltage requirements.

[0063] The doping concentration of the top gate outer region 82 , the bottom thickness and the sidewall thickness of the top gate outer region 82 satisfying the above value range requirements is to widen the process window range of the top gate and prevent the process from failing to achieve device performance.

[0064] In implementation, such as Figure 2-1 , Figure 2-2 , Figure 2-3 and Figure 2-4 As shown, the coupling capacitor upper electrode 10, the dielectric layer 9, and the top gate constitute the gate structure of the field effect transistor;

[0065] A top gate of the second doping type, a portion between the top gate and the bottom gate 3, and the bottom gate 3 form a JFET region 1;

[0066] The two bottom gates 3 and the portion between the bottom gates 3 form a second JFET region;

[0067] The top gate of the JFET region 1 is indirectly controlled by the dielectric layer 9 between the upper electrode 10 of the coupling capacitor, so that the JFET region 1 and the JFET region 2 are controlled by the dielectric layer 9 between the upper electrode 10 of the coupling capacitor.

[0068] The first implementation method is Figure 2-1 As shown, the JFET region 1 is specifically formed by the top gate, the portion of the epitaxial layer located between the top gate and the bottom gate 3, and the bottom gate 3;

[0069] The two bottom gates 3 and the portion of the epitaxial layer between the bottom gates 3 form a second JFET region.

[0070] The second implementation method is Figure 2-2 As shown, the field effect transistor also includes:

[0071] A channel 1 5 of a first doping type is formed in a portion between the top gate and the bottom gate 3, wherein the top gate is located above the channel 1;

[0072] Wherein, the JFET region 1 is specifically formed by a top gate, a channel 1 5, and a bottom gate 3;

[0073] The second JFET region is specifically formed by two bottom gates 3 and a portion of the epitaxial layer located between the bottom gates 3 .

[0074] The third implementation method is Figure 2-3 As shown, the field effect transistor also includes:

[0075] A channel 1 5 of a first doping type is formed in a portion between the top gate and the bottom gate 3, wherein the top gate is located above the channel 1;

[0076] A second channel 61 of the first doping type is formed between the two bottom gates;

[0077] The JFET region 1 is specifically formed by a top gate, a channel 1 5 , and a bottom gate 3 , and the JFET region 2 is specifically formed by two bottom gates 3 and a channel 2 61 .

[0078] The third implementation method is Figure 2-4 As shown, the field effect transistor also includes:

[0079] A channel 1 5 of a first doping type is formed in a portion between the top gate and the bottom gate 3, wherein the top gate is located above the channel 1;

[0080] A second channel 61 of the first doping type is formed between the two bottom gates;

[0081] A current spreading layer 62 of the first doping type is formed in the epitaxial layer 2 below the bottom gate 3 and the second channel 61;

[0082] The JFET region 1 is specifically formed by a top gate, a channel 1 5 , and a bottom gate 3 , and the JFET region 2 is specifically formed by two bottom gates 3 , a channel 2 61 , and a current spreading layer 62 .

[0083] The doping concentrations of the first channel 5, the second channel 61 and the current spreading layer 62 are greater than the doping concentration of the epitaxial layer, which is beneficial to reducing the on-resistance of the device and improving the device performance.

[0084] In implementation, such as Figure 2-1 , Figure 2-2 , Figure 2-3 and Figure 2-4As shown, the field effect transistor also includes:

[0085] The drain electrode 13 is arranged on the lower surface of the substrate;

[0086] Two first doping type source regions 7, respectively located on the two bottom gates, and the two first doping type source regions 7 are connected to a portion between the top gate and the bottom gate 3;

[0087] Two second doping type source regions 4 are respectively connected to both sides of the two bottom gates 3, and the second doping type source region 4, the first doping type source region 7 and the bottom gate 3 on the same side are connected;

[0088] Two source electrodes 12, the source electrodes are connected at the junction of the first doping type source region 7 and the second doping type source region 4 on the same side;

[0089] A gate electrode 11 is formed on the coupling capacitor upper electrode 10;

[0090] The buffer layer 100 is formed between the substrate 1 and the epitaxial layer 2 .

[0091] Specifically, the material of the dielectric layer 9 can be silicon dioxide or high-K dielectric. The use of high-K dielectric is more conducive to the control of the P+ type top gate by the upper electrode of the coupling capacitor, thereby improving the device performance.

[0092] Specifically, the coupling capacitor upper electrode 10 may be made of P+ type and N+ type heavily doped polysilicon to reduce the contact resistance with the gate metal and the gate parasitic resistance, thereby improving the device performance.

[0093] High-K dielectrics refer to materials with a high dielectric constant (high relative dielectric constant).

[0094] Specifically, by controlling the doping of the bottom gate 3 of the second doping type and the top gate of the second doping type, when the voltage of the electrode 10 on the coupling capacitor is zero, the region sandwiched by the bottom gate 3 and the top gate is in a depletion state, and the field effect transistor is a normally-off device;

[0095] Alternatively, by controlling the doping of the second doping type bottom gate 3 and the second doping type top gate, when the voltage of the coupling capacitor upper electrode 10 is zero, the region sandwiched by the bottom gate 3 and the top gate is in a conducting state, and the field effect transistor is a normally-on device.

[0096] exist Figure 2-4 In the figure, the horizontal dotted line is the lower surface of the top grid; the vertical dotted line is perpendicular to the horizontal dotted line.

[0097] Figure 3 It is a simulation diagram of the potential curve of the top gate position of the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application and the patent CN117637854B in the background technology.

[0098] Figure 3 The part to the right of coordinate 0 on the horizontal axis corresponds to Figure 2-4 The portion of the middle vertical dashed line that is above the horizontal dashed line; Figure 3 The vertical axis is the potential of the top gate at each position on the horizontal axis, in volts (V).

[0099] like Figure 3 As shown, starting from the lower surface of the top gate, the potential in the patent CN117637854B in the background technology changes rapidly in the top gate; the vertical capacitively coupled gate-controlled junction field effect transistor in the embodiment of the present application first changes slowly in the top gate (i.e., the potential in the top gate outer region 82 changes slowly), and after the potential changes slowly for a distance, the potential changes rapidly again (i.e., the potential in the top gate inner region 81 changes rapidly).

[0100] Figure 4 This is an energy band simulation diagram of the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application and the top gate position of the patent CN117637854B in the background technology.

[0101] Figure 4 The part to the right of coordinate 0 on the horizontal axis corresponds to Figure 2-4 The portion of the middle vertical dashed line that is above the horizontal dashed line; Figure 4 The middle vertical axis is the energy of the top gate at each position of the horizontal axis, in volts (eV). Among them, curve ① is the conduction band Ec curve of the patent CN117637854B in the background technology, curve ② is the valence band Ev curve of the patent CN117637854B in the background technology, and curve ③ is the Fermi level Efn curve of the patent CN117637854B in the background technology; curve ④ is the conduction band Ec curve of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application, curve ⑤ is the valence band Ec curve of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application, and curve ⑥ is the Fermi level Efn curve of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application.

[0102] like Figure 4 As shown, starting from the lower surface of the top gate, the conduction band Ec, valence band Ev, and Fermi level Efn of the patent CN117637854B in the background technology change rapidly in the top gate; the conduction band Ec, valence band Ev, and Fermi level Efn of the vertical capacitively coupled gate-controlled junction field effect transistor in the embodiment of the present application first change slowly in the top gate (i.e., the conduction band Ec, valence band Ev, and Fermi level Efn change slowly in the top gate outer region 82), and after the conduction band Ec, valence band Ev, and Fermi level Efn change slowly for a distance, the conduction band Ec, valence band Ev, and Fermi level Efn change rapidly again (i.e., the conduction band Ec, valence band Ev, and Fermi level Efn change rapidly in the top gate inner region 81).

[0103] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0104] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0105] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0106] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0107] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0108] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A vertical capacitively coupled gate controlled junction field effect transistor, characterized in that: include: A substrate (1) of a first doping type and an epitaxial layer (2) of a first doping type, wherein the epitaxial layer (2) is located above the substrate (1); Two bottom gates (3) of the second doping type are formed in the epitaxial layer and are spaced apart in the lateral direction; A combined top gate of a second doping type, the top gate comprising a top gate inner region (81) and a top gate outer region (82), the top gate inner region (81) being formed from top to bottom in the epitaxial layer, the top gate outer region (82) surrounding the bottom surface and side surfaces of the top gate inner region (81), and a gap being provided between the top gate outer region (82) and the bottom gate (3); wherein the doping concentration of the top gate outer region (82) is less than the doping concentration of the top gate inner region (81), and the top gate is in a floating state; A dielectric layer (9), located above the top gate; The coupling capacitor upper electrode (10) is formed on the dielectric layer (9).

2. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 1, characterized in that: The cross section of the top gate outer region (82) is U-shaped, the inner bottom of the top gate outer region (82) is wrapped around the bottom surface of the top gate inner region (81), and the inner wall of the top gate outer region (82) is wrapped around the side surface of the top gate inner region (81).

3. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 2, characterized in that: The doping concentration of the top gate outer region (82) is 1 to 2 orders of magnitude lower than the doping concentration of the top gate inner region (81).

4. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 2, characterized in that: The doping concentration of the top gate outer region (82) is in the range of greater than or equal to 2×10 17 cm -3 Less than or equal to 5×10 18 cm -3 The doping concentration of the top gate inner region (81) is in the range of greater than or equal to 2×10 18 cm -3 Less than or equal to 4×10 20 cm -3 .

5. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 4, characterized in that: The value range of the bottom thickness of the top gate outer region (82) is greater than or equal to 0.02 μm and less than or equal to 0.2 μm, and the value range of the side wall thickness of the top gate outer region (82) is greater than or equal to 0.02 μm and less than or equal to 0.2 μm; The thickness of the top gate inner region (81) ranges from 0.02 μm to equal to 0.1 μm.

6. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 1, characterized in that: The coupling capacitor upper electrode (10), the dielectric layer (9), and the top gate constitute a gate structure of a field effect transistor; A top gate of the second doping type, a portion between the top gate and the bottom gate (3), and the bottom gate (3) form a JFET region 1; The two bottom gates (3) and a portion located between the bottom gates (3) form a second JFET region; The top gate of the JFET region one is indirectly controlled by the dielectric layer (9) spaced between the coupling capacitor upper electrode (10), so that the JFET region one and the JFET region two are controlled by the dielectric layer (9) spaced between the coupling capacitor upper electrode (10).

7. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 6, characterized in that: Also includes: A channel 1 (5) of a first doping type, formed in a portion between the top gate and the bottom gate (3), the top gate being located above the channel 1; The JFET region 1 is specifically formed by a top gate, a channel 1 (5), and a bottom gate (3), and the JFET region 2 is specifically formed by two bottom gates (3) and a portion of the epitaxial layer located between the bottom gates (3).

8. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 6, characterized in that: Also includes: A channel 1 (5) of a first doping type is formed in a portion between the top gate and the bottom gate (3), the top gate being located above the channel 1; A second channel (61) of the first doping type is formed between the two bottom gates; The JFET region 1 is specifically formed by a top gate, a channel 1 (5), and a bottom gate (3), and the JFET region 2 is specifically formed by two bottom gates (3) and a channel 2 (61).

9. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 6, characterized in that: Also includes: A channel 1 (5) of a first doping type is formed in a portion between the top gate and the bottom gate (3), the top gate being located above the channel 1; A second channel (61) of the first doping type is formed between the two bottom gates; A current spreading layer (62) of a first doping type, formed in the epitaxial layer (2) at a position below the bottom gate (3) and the second channel (61); The JFET region 1 is specifically formed by a top gate, a channel 1 (5), and a bottom gate (3), and the JFET region 2 is specifically formed by two bottom gates (3) and a channel 2 (61).

10. The vertical capacitively coupled gate controlled junction field effect transistor according to any one of claims 6 to 9, characterized in that: Also includes: A drain electrode (13) is arranged on the lower surface of the substrate; Two first doping type source regions (7), respectively located on the two bottom gates, the two first doping type source regions (7) being connected to a portion between the top gate and the bottom gate (3); Two second doping type source regions (4) are respectively connected to both sides of the two bottom gates (3), and the second doping type source region (4), the first doping type source region (7) and the bottom gate (3) on the same side are connected; Two source electrodes (12), the source electrodes being connected at the junction of a first doping type source region (7) and a second doping type source region (4) on the same side; A gate electrode (11) formed on the coupling capacitor upper electrode (10); A buffer layer (100) is formed between the substrate (1) and the epitaxial layer (2).

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