SCR device, process method and chip

Abstract

According to the SCR device, the process method and the chip, compared with a traditional LVTSCR device, the trigger voltage of the SCR device is lower, the maintaining voltage is higher, the deep hysteresis phenomenon can be avoided, the application scene of the SCR device is expanded, and the SCR device can be applied to a high-working-voltage port. In addition, the SCR device can also form a plurality of ESD current discharge paths, so that the ESD current discharge capacity of the chip in unit area is higher, the SCR device has the characteristic of low on-resistance, the area of the chip is effectively saved, and the production cost of the chip is reduced; in addition, the distribution of the ESD current in the SCR device is more uniform due to the plurality of ESD current discharge paths, and the discharge path robustness of the SCR device under large current is effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to an SCR device, a process method and a chip. Background Art

[0002] Electrostatic discharge (ESD) refers to the instantaneous current pulse caused by the accumulation of static electricity. ESD phenomenon can easily damage integrated circuits, so it is necessary to design ESD protection circuits to protect integrated circuits. The ESD protection circuit mainly uses ESD protection devices to discharge electrostatic charges. Among them, the trigger voltage of the ESD protection device should be lower than the failure voltage, and the trigger voltage and maintenance voltage of the ESD protection device should be higher than the working voltage of the port of the ESD protection device to ensure that the circuit is shut down when it is working normally to avoid affecting the circuit operation. In the event of an ESD event, the ESD protection device should clamp the voltage of the port within the failure voltage and discharge the ESD current in time.

[0003] With the development of integrated circuit technology, integrated circuit products with various functions are continuously launched. The working voltage of integrated circuits is getting higher and higher, and the margin between the normal working voltage and the failure voltage is getting smaller and smaller. The safety window of ESD protection device design is getting narrower and narrower. At present, ESD protection devices are required to have a higher self-sustaining voltage to adapt to the ESD protection function of high working voltage ports, and to have lower on-resistance and trigger voltage so that ESD protection devices can be triggered in time and produce a smaller voltage drop when discharging ESD current, so that ESD protection devices can provide protection within a narrower range of working voltage and failure voltage.

[0004] Low trigger voltage SCR (LVTSCR) is an SCR device with grounded gate NMOS (ggNMOS) embedded in the traditional SCR device. The LVTSCR device uses the opening of ggNMOS to trigger the SCR structure. The trigger voltage is lower than that of the traditional SCR device. At the same time, the LVTSCR device also retains the low maintenance voltage of the traditional SCR device, making it widely used in the ESD protection field of low-voltage ports. After the LVTSVR device is triggered, only a small voltage is required to maintain the opening of the SCR structure. However, in order to avoid false triggering and latch-up effects, LVTSCR devices cannot be used in ports with higher operating voltages, and it is difficult to meet the ESD protection requirements of current integrated circuits.

[0005] Therefore, there is an urgent need for an SCR device with low on-resistance and high holding voltage. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a low on-resistance and high holding voltage SCR device, a process method and a chip, aiming to solve the problem in the related art that LVTSCR devices are difficult to apply to ports with higher operating voltages.

[0007] To solve the above technical problems, the present invention is implemented as follows: an SCR device, comprising: a p-type substrate, an n-type deep well region formed in the p-type substrate, a first p-type well region formed in the n-type deep well region, a second p-type well region formed in the p-type substrate, a first n-type well region formed by injecting simultaneously into the n-type deep well region and the p-type substrate at a boundary between the n-type deep well region and the p-type substrate, a first p-heavy doped region formed on the first n-type well region, a first n-heavy doped region formed by injecting simultaneously into the first n-type well region and the first p-type well region at a boundary between the first n-type well region and the first p-type well region, a second p-heavy doped region formed on the first p-type well region, a third p-heavy doped region formed on the first p-type well region, a second n-heavy doped region formed on the first p-type well region, a third n-heavy doped region formed by injecting simultaneously into the first p-type well region and the first n-type well region at a boundary between the first p-type well region and the first n-type well region, and a fourth n-heavy doped region formed on the first n-type well region; The first n-type well region is disposed around the periphery of the first p-type well region, and the second p-type well region is disposed around the periphery of the first n-type well region; The first p heavily doped region, the first n heavily doped region, the second p heavily doped region, the third p heavily doped region, the second n heavily doped region, the third n heavily doped region and the fourth n heavily doped region are arranged at intervals along a first direction, and the first direction is perpendicular to the thickness direction of the p-type substrate; the SCR device also includes a gate dielectric layer, a cathode and an anode; the gate dielectric layer is formed between the second n heavily doped region, the third n heavily doped region and the first p-type well region; the first p heavily doped region and the fourth n heavily doped region are both metal interconnected to the anode; the third p heavily doped region and the second n heavily doped region are both metal interconnected to the cathode; the first n heavily doped region is both metal interconnected to the third n heavily doped region; the second p heavily doped region is metal interconnected to the gate dielectric layer.

[0008] Furthermore, the second p-type well region and the first p heavily doped region, the first p heavily doped region and the first n heavily doped region, the first n heavily doped region and the second p heavily doped region, the second p heavily doped region and the third p heavily doped region, the third p heavily doped region and the second n heavily doped region, the third n heavily doped region and the fourth n heavily doped region, and the fourth n heavily doped region and the second p-type well region are all isolated by a shallow trench dielectric.

[0009] Further, the n-type deep well region, the first p-type well region, the first n-type well region, the second p-type well region, the first p-heavy doped region, the first n-heavy doped region, the second p-heavy doped region, the third p-heavy doped region, the second n-heavy doped region, the third n-heavy doped region and the fourth n-heavy doped region are all formed by ion implantation or diffusion.

[0010] Furthermore, the ion doping concentrations of the first p heavily doped region, the first n heavily doped region, the second p heavily doped region, the third p heavily doped region, the second n heavily doped region, the third n heavily doped region, and the fourth n heavily doped region are all greater than 1×10 18 cm -3 ; The ion doping concentration of the first p-type well region, the first n-type well region and the second p-type well region is 1×10 16 cm -3 ~ 1×10 18 cm -3 ; The ion doping concentration of the n-type deep well region is 1×10 16 cm -3 ~ 1×10 19 cm -3 .

[0011] The present invention also provides a process for an SCR device, comprising the steps of: Preparing a p-type substrate; Etching the p-type substrate to form a plurality of shallow trenches, and injecting a shallow trench dielectric into each of the shallow trenches, wherein the plurality of shallow trenches into which the shallow trench dielectric is injected are spaced apart along a first direction, and the first direction is perpendicular to a thickness direction of the p-type substrate; forming an n-type deep well region in the p-type substrate; A first p-type well region is formed in the n-type deep well region, a second p-type well region is formed in the p-type substrate, and a first n-type well region is formed by injecting into the n-type deep well region and the p-type substrate at the interface between the n-type deep well region and the p-type substrate, wherein the first n-type well region is arranged around the periphery of the first p-type well region, and the second p-type well region is arranged around the periphery of the first n-type well region; A first p-heavy doped region is formed on the first n-type well region, and a first n-heavy doped region is formed by injecting into the first n-type well region and the first p-type well region at the junction of the first n-type well region and the first p-type well region at the same time, and a second p-heavy doped region is formed on the first p-type well region, and a third p-heavy doped region is formed on the first p-type well region, and a second n-heavy doped region is formed on the first p-type well region, and a third n-heavy doped region is formed by injecting into the first p-type well region and the first n-type well region at the junction of the first p-type well region and the first n-type well region at the same time, and a fourth n-heavy doped region is formed on the first n-type well region, wherein the first p-heavy doped region and the first n-heavy doped region , the second p heavily doped region, the third p heavily doped region, the second n heavily doped region, the third n heavily doped region and the fourth n heavily doped region are arranged at intervals along the first direction, and the second p-type well region and the first p heavily doped region, the first p heavily doped region and the first n heavily doped region, the first n heavily doped region and the second p heavily doped region, the second p heavily doped region and the third p heavily doped region, the third p heavily doped region and the second n heavily doped region, the third n heavily doped region and the fourth n heavily doped region, and the fourth n heavily doped region and the second p-type well region are all isolated by the corresponding shallow trench dielectrics; forming the gate dielectric layer between the second n-heavy doped region, the third n-heavy doped region and the first p-type well region; The first p heavily doped region and the fourth n heavily doped region are respectively metal-interconnected with the anode, the third p heavily doped region and the second n heavily doped region are respectively metal-interconnected with the cathode, the first n heavily doped region is metal-interconnected with the third n heavily doped region, and the second p heavily doped region is metal-interconnected with the gate dielectric layer.

[0012] The present invention also provides a chip, comprising the SCR device as described above.

[0013] Compared with the prior art, the SCR device, process method and chip of the present invention have the following beneficial effects: Compared with the traditional LVTSCR device, on the one hand, the SCR device in the present invention forms multiple ESD current discharge paths, so that the trigger voltage of the SCR device is lower and the maintenance voltage is higher, which can avoid the deep hysteresis phenomenon, expand the application scenarios of the SCR device, and enable the SCR device to be applied to high working voltage ports; On the other hand, SCR devices can form multiple ESD current discharge paths, and the ESD current discharge capacity per unit area of ​​the chip is higher, which makes the SCR device have a low on-resistance characteristic, effectively saving the chip area and reducing the chip production cost; in addition, multiple ESD current discharge paths make the ESD current more evenly distributed in the SCR device, and also improve the robustness of the discharge path of the SCR device under large current. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a cross-sectional schematic diagram of a conventional LVTSCR device in an embodiment of the present invention; Figure 2 is a cross-sectional schematic diagram of an SCR device in an embodiment of the present invention; Figure 3 It is a schematic diagram of the discharge of the ESD current along the RC path, the discharge path of the NMOS tube structure, and the discharge path of the NPN transistor structure when ESD occurs at the anode of the SCR device and the cathode is grounded in an embodiment of the present invention; Figure 4 is a schematic diagram of the discharge of the ESD current along the discharge path of the PNP transistor structure when ESD occurs at the anode of the SCR device and the cathode is grounded in an embodiment of the present invention; Figure 5 is a schematic diagram of the discharge of ESD current along the SCR discharge path when ESD occurs at the anode of the SCR device and the cathode is grounded in an embodiment of the present invention; Figure 6 is a schematic diagram of the ESD current being discharged along the auxiliary discharge path of the NMOS tube structure after the SCR discharge path is opened when ESD occurs at the anode of the SCR device and the cathode is grounded in an embodiment of the present invention; Figure 7 is a schematic diagram of the discharge of the ESD current along the discharge path of the PN junction diode structure when ESD occurs at the cathode of the SCR device and the anode is grounded in an embodiment of the present invention; Figure 8 is a schematic diagram of the discharge of the ESD current along the discharge path of the NMOS tube structure when ESD occurs at the cathode of the SCR device and the anode is grounded in an embodiment of the present invention; Fig. 9 is a schematic diagram of the discharge of the ESD current along the discharge path of the PNP transistor structure when ESD occurs at the cathode of the SCR device and the anode is grounded in an embodiment of the present invention; Fig.10 It is a flow chart of the process method of the SCR device in an embodiment of the present invention.

[0015] In the accompanying drawings, each reference numeral represents: 100, p-type substrate; 110, second p-type well region; 111, first p-type well region; 120, first p heavily doped region; 121, second p heavily doped region; 122, third p heavily doped region; 200, n-type deep well region; 210, first n-type well region; 220, first n heavily doped region; 221, second n heavily doped region; 222, third n heavily doped region; 223, fourth n heavily doped region; 300, gate dielectric layer; 400, first interconnection lead; 401, second interconnection lead; 402, third interconnection lead; 403, fourth interconnection lead; 500, P conductive type silicon substrate; 510, first P conductive type well region; 520, first P conductive type heavily doped region; 521, second P conductive type heavily doped region; 610, first N conductive type well region; 620, first N conductive type heavily doped region; 621, second N conductive type heavily doped region; 622, third N conductive type heavily doped region; 700, gate dielectric layer; 810, first interconnection line; 820, second interconnection line. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0017] See also Figure 1 , traditional LVTSCR devices include: A P conductive type silicon substrate 500, a first N conductive type well region 510 formed on the top of the P conductive type silicon substrate 500, a first P conductive type well region 510 formed on the top of the P conductive type silicon substrate 500, a first N conductive type heavily doped region 620 formed on the top of the first N conductive type well region 510, a first P conductive type heavily doped region 521 formed on the top of the first N conductive type well region 620, a second N conductive type heavily doped region 621 formed by implanting the first N conductive type well region 620 and the first P conductive type well region 510 at the junction of the first N conductive type well region 620 and the first P conductive type well region 510, a third N conductive type heavily doped region 622 formed on the top of the first P conductive type well region 510, a second P conductive type heavily doped region 520 formed on the top of the first P conductive type well region 510, a gate dielectric layer 700, a first interconnection line 810, a second interconnection line 820, a cathode and an anode; The first N conductive type well region 610 and the first P conductive type well region 510 are sequentially arranged along a first direction, and the first direction is perpendicular to the thickness direction of the P conductive type substrate 500; The first N conductive type heavily doped region 620, the first P conductive type heavily doped region 510, the second N conductive type heavily doped region 621, the third N conductive type heavily doped region 622 and the second P conductive type heavily doped region 521 are spaced apart along the first direction, the first N conductive type heavily doped region 620 and the first P conductive type heavily doped region 520 are isolated by a shallow trench dielectric, the first P conductive type heavily doped region 520 and the second N conductive type heavily doped region 621 are isolated by a shallow trench dielectric, and the third N conductive type heavily doped region 622 and the second P conductive type heavily doped region 521 are isolated by a shallow trench dielectric; The gate dielectric layer 700 is formed on top of the second N conductive type heavily doped region 621 , the first P conductive type well region 510 , and the third N conductive type heavily doped region 622 ; The first N conductive type heavily doped region 620, the first P conductive type well region 510, and the anode are connected via a first interconnection line 810; The second P conductive type heavily doped region 521 , the third N conductive type heavily doped region 622 , the gate dielectric layer 700 , and the cathode are connected via a second interconnection line 820 .

[0018] The conventional LVTSCR device includes a first current discharge path and a second current discharge path; The current passes through the anode, the first P conductive type heavily doped region 520, the first N conductive type well region 610, the first P conductive type well region 510, the third N conductive type heavily doped region 622 and the cathode to form a first current discharge path, and the first current discharge path is an SCR discharge path; The current passes through the anode, the first N conductive type heavily doped region 620, the first N conductive type well region 610, the second N conductive type heavily doped region 621, the first P conductive type well region 510, the third N conductive type heavily doped region 622 and the cathode to form a second current discharge path, and the second current discharge path is a ggNMOS path.

[0019] When ESD occurs at the anode of a traditional LVTSCR device and the cathode is grounded, the second current discharge path is turned on and triggers the first current discharge path to start discharging. The first current discharge path is simple, and the first current discharge path overlaps with the second current discharge path, which reduces the voltage to maintain the first current discharge path turned on. However, the overlap between the first current discharge path and the second current discharge path also causes the currents on the two discharge paths to intersect. The current intersection is prone to current concentration effects and causes local overheating, causing device failure, which in turn reduces the ESD current discharge capability of traditional LVTSCR devices. After being triggered, traditional LVTSCR devices only require a small voltage to maintain the on state. In order to avoid false triggering and latch-up effects, traditional LVTSCR devices are often used in ESD protection circuits for low-voltage ports, and are difficult to use in protection circuits for high-voltage ports.

[0020] See also Figures 2 to 9 In this embodiment, an SCR device is provided, including: a p-type substrate 100, an n-type deep well region 200 formed in the p-type substrate 100, a first p-type well region 111 formed in the n-type deep well region 200, a second p-type well region 110 formed in the p-type substrate 100, a first n-type well region 210 formed by simultaneously injecting doped p-type heavy doping regions 120 into the n-type deep well region 200 and the p-type substrate 100 at a boundary between the n-type deep well region 200 and the p-type substrate 100, a first p-heavy doping region 120 formed on the first n-type well region 210, and a first p-heavy doping region 120 formed on the first n-type well region 210 and a first p-type well region 111 formed by simultaneously injecting doped p-type heavy doping regions 120 into the first n-type well region 210 at a boundary between the first n-type well region 210 and the first p-type well region 111. 0 and the first p-type well region 111 to form a first n heavily doped region 220, a second p heavily doped region 121 formed on the first p-type well region 111, a third p heavily doped region 122 formed on the first p-type well region 111, a second n heavily doped region 221 formed on the first p-type well region 111, a third n heavily doped region 222 formed by simultaneously injecting into the first p-type well region 111 and the first n-type well region 210 at the junction of the first p-type well region 111 and the first n-type well region 210, and a fourth n heavily doped region 223 formed on the first n-type well region 210; The first n-type well region 210 is disposed around the outer periphery of the first p-type well region 111 , and the second p-type well region 110 is disposed around the outer periphery of the first n-type well region 210 ; The first p heavily doped region 120, the first n heavily doped region 220, the second p heavily doped region 121, the third p heavily doped region 122, the second n heavily doped region 221, the third n heavily doped region 222 and the fourth n heavily doped region 223 are arranged at intervals along a first direction, and the first direction is perpendicular to the thickness direction of the p-type substrate 100; the SCR device also includes a gate dielectric layer 300, a cathode and an anode; the gate dielectric layer 300 is formed between the second n heavily doped region 221, the third n heavily doped region 222 and the first p-type well region 111; the first p heavily doped region 120 and the fourth n heavily doped region 223 are both metal-interconnected to the anode; the third p heavily doped region 122 and the second n heavily doped region 221 are both metal-interconnected to the cathode; the first n heavily doped region 220 is metal-interconnected to the third n heavily doped region 222; the second p heavily doped region 121 is metal-interconnected to the gate dielectric layer 300.

[0021] It can be understood that, from the perspective of a top view of the SCR device layout, the first n-type well region 210 and the second p-type well region 110 are both in a closed ring shape.

[0022] Specifically, Figure 2 As shown, the SCR device provided in this embodiment forms a variety of structures, including a PNP triode structure, an NPN triode structure, an SCR structure formed by coupling a PNP triode structure with an NPN triode structure, an NMOS tube structure, and multiple PN junction diode structures.

[0023] Among them, Figure 2 As shown, the first p-type heavily doped region 120, the first n-type well region 210, the first p-type well region 111 and the third p-type heavily doped region 122 form a PNP triode structure connected between the cathode and the anode; the second n-type heavily doped region 221, the first p-type well region 111, the first n-type well region 210, the n-type deep well region 200 and the fourth n-type heavily doped region 223 form an NPN triode structure connected between the cathode and the anode; The second n heavily doped region 221, the third n heavily doped region 222, the first p-type well region 111 and the gate dielectric layer 300 form an NMOS tube structure connected between the cathode and the anode; the third p heavily doped region 122, the first p-type well region 111, the third n heavily doped region 222, the second n-type well region and the fourth n heavily doped region 223 form a plurality of PN junction diode structures.

[0024] The SCR device in this embodiment further includes a first interconnection lead 400 , a second interconnection lead 401 , a third interconnection lead 402 and a fourth interconnection lead 403 .

[0025] The first p heavily doped region 120 and the fourth n heavily doped region 223 are metal interconnected with the anode through the first interconnection lead 400; the third p heavily doped region 122 and the second n heavily doped region 221 are metal interconnected with the cathode through the second interconnection lead 401; the first n heavily doped region 220 and the third n heavily doped region 222 are metal interconnected through the third interconnection lead 402; the second p heavily doped region 121 and the gate dielectric layer 300 are metal interconnected through the fourth interconnection lead 403.

[0026] In this embodiment, when ESD occurs at the anode of the SCR device and the cathode is grounded, since the first p heavily doped region 120 and the fourth n heavily doped region 223 are electrically connected to the anode, the current flows from the anode through the first p heavily doped region 120 and the fourth n heavily doped region 223, and the potentials of the first p heavily doped region 120 and the fourth n heavily doped region 223 increase rapidly. Since the third n heavily doped region 222 and the fourth n heavily doped region 223 are both formed on the first n-type well region 210, the third n heavily doped region 222 and the fourth n heavily doped region 223 are electrically connected, and the potential of the third n heavily doped region 222 also increases rapidly along with the fourth n heavily doped region 223. like Figure 3 As shown, there is a first parasitic well resistance generated by the first n-type well region 210 between the fourth n-heavy doped region 223 and the third n-heavy doped region 222, a parasitic capacitance between the gate dielectric layer 300 and the third n-heavy doped region 222, and a second parasitic well resistance generated by the first p-type well region 111 between the second p-heavy doped region 121 and the third p-heavy doped region 122. The first parasitic well resistance, the first parasitic capacitance and the second parasitic well resistance form an RC path. The RC path responds to the ESD current, and the displacement current of the parasitic capacitance accumulates a voltage drop on the first parasitic well resistance, so that the voltage of the gate dielectric layer 300 also increases, which is beneficial to the formation of the NMOS channel region and the opening of the NMOS tube, and accelerates the lateral bipolar breakdown of the NMOS tube structure, that is, accelerates the breakdown between the second n-heavy doped region 221 and the third n-heavy doped region 222.

[0027] like Figure 3 As shown, after the lateral bipolar breakdown of the NMOS tube structure, the anode, the fourth n-heavy doped region 223, the first n-type well region 210, the third n-heavy doped region 222, the first p-type well region 111, the second n-heavy doped region 221 and the cathode sequentially form a discharge path of the NPN triode structure, and the ESD current flows along the discharge path of the NPN triode structure, and the SCR device is turned on.

[0028] Compared with the traditional LVTSCR device, the SCR device in this embodiment introduces an RC path in the SCR device through the gate coupling technology, which accelerates the voltage rise of the gate dielectric layer 300, that is, accelerates the voltage rise of the gate of the NMOS tube structure, further accelerates the bipolar breakdown of the NMOS tube structure, realizes the conduction of the SCR device, and makes the trigger voltage of the SCR device provided in this embodiment lower.

[0029] Subsequently, the ESD current accumulates a voltage drop in the first parasitic resistance formed in the first n-type well region 210, pulling down the potential of the first n-heavy doped region 220 and the third n-heavy doped region 222, so that the PN junction diode structure formed by the first p-heavy doped region 120 and the first n-type well region 210 is forward biased. Figure 4 As shown, a small amount of current flows from the third n heavily doped region 222 to the first n heavily doped region 220 through the third interconnect lead 402, providing current for the first p-type well region 111 of the base of the PNP triode structure, thereby promoting the discharge path of the PNP triode structure. In the discharge path of the PNP triode structure, the ESD current passes through the anode, the first p heavily doped region 120, the first n-type well region 210, the first n heavily doped region 220, the first p-type well region 111 and the third p heavily doped region 122 to reach the cathode.

[0030] The discharge path of the NPN transistor structure and the multiple discharge paths formed by the PNP transistor structure make the ESD current more evenly distributed in the first p-type well region 111, and are also more conducive to further opening the discharge path of the SCR.

[0031] As the discharge paths of the NPN transistor structure and the PNP transistor structure are turned on successively, the degree of opening of the SCR device gradually deepens, the discharge charge of the SCR device increases, the discharge capacity of the SCR device is enhanced, and the ESD current flowing through the SCR device increases. Figure 5 As shown, as the current increases, the current discharged from the first p-type well region 111 to the third p-doped region on the discharge path of the PNP triode structure is extracted by the forward-biased diode formed by the first p-type well region 111 and the second n-heavy doped region 221, and finally triggers the main SCR discharge path formed by the anode passing through the first p-heavy doped region 120, the first n-type well region 210, the first p-type well region 111, and the second n-heavy doped region 221, and the parasitic secondary SCR discharge path formed by the anode passing through the first p-heavy doped region 120, the first n-type well region 210, the n-type deep well region 200, the first p-type well region 111, and the second n-heavy doped region 221. The main SCR discharge path and the secondary SCR discharge path together constitute the SCR discharge path.

[0032] Since the main SCR discharge path is based on the discharge path of the PNP triode structure, the current flowing through the main SCR path is extracted by the discharge path of the PNP triode structure, reducing the current gain of the main SCR path. The NPN structure of the secondary SCR path is composed of an n-type deep well region 200, a first p-type well region 111, and a second n-heavy doped region 221 along the thickness direction of the substrate, and then the n-type deep well region 200 is softly connected to the first n-type well region 210. Therefore, the current amplification capability of the secondary SCR discharge path is weaker than that of the main SCR discharge path. Therefore, the SCR device of the present invention has a higher maintenance voltage than the traditional LVTSCR device, avoiding the deep hysteresis phenomenon.

[0033] Furthermore, if Figure 6 As shown, when the SCR discharge path is turned on, the current injected into the first p-type well region 111 from the first n-type well region 210 and discharged through the SCR discharge path and the discharge path of the PNP transistor structure accumulates voltage on the second parasitic well resistor between the second p-heavy doped region 121 and the third p-heavy doped region 122, so that the gate voltage of the NMOS structure is raised, and the opening of the current discharge channel of the NMOS structure is maintained. At the same time, the current on the SCR path can also flow from the first n-heavy doped region 220 to the third n-heavy doped region 222 with the help of the third interconnection line, and assist the discharge of current through the NMOS channel.

[0034] In the process of discharging ESD current, the SCR discharge path, the discharge path of the PNP transistor structure, the discharge path of the NMOS tube and the discharge path of the NPN transistor work together, so that the SCR device in the present invention has a low on-resistance characteristic, and the ESD current is more evenly distributed inside the SCR device, which reduces the impact of local overheating caused by large current and improves the robustness of the PNP discharge path of the device under large current.

[0035] In this embodiment, Figure 7 As shown, when ESD occurs at the cathode of the SCR device and the anode is grounded, the potentials of the third p heavily doped region 122 and the second n heavily doped region 221 connected to the cathode rise rapidly, and the PN junction diode composed of the first p-type well region 111 and the first n-type well region 210, the PN junction diode composed of the first p-type well region 111 and the first n heavily doped region 220, and the PN junction diode composed of the first p-type well region 111 and the n-type deep well region 200 are all forward biased, and the ESD current is first discharged to the anode by the third p heavily doped region 122, the first p-type well region 111, the third n heavily doped region 222, the first n-type well region 210, and the fourth n heavily doped region 223; the diode structure composed of the third p heavily doped region 122, the first p-type well region 111, and the first n heavily doped region 220 is also forward biased accordingly, and the ESD current also flows to the third n heavily doped region 222 through the third interconnection line; like Figure 8As shown, when the cathode voltage increases, the gate voltage of the NMOS tube structure softly connected to the cathode also increases, and the ESD current can be discharged from the NMOS channel to the third n-heavy doped region 222 through the second n-heavy doped region 221, and then discharged to the anode, that is, the ESD current is discharged along the discharge path of the NMOS tube structure; like Fig. 9 As shown, as the voltage between the cathode and the anode further increases, the discharge path of the PNP transistor structure will be opened, and the ESD current will flow through the cathode, the third p-heavy doped region 122, the first p-type well region 111, the first n-type well region 210, and the first p-heavy doped region 120 to the anode.

[0036] In summary, in this embodiment, compared with the traditional LVTSCR device, on the one hand, the SCR device provided in this embodiment has a lower trigger voltage and a higher maintenance voltage, which can avoid the deep hysteresis phenomenon, expand the application scenarios of the SCR device, and enable the SCR device to be applied to high working voltage ports; On the other hand, SCR devices can form multiple ESD current discharge paths, and the ESD current discharge capacity per unit area of ​​the chip is higher, which makes the SCR device have a low on-resistance characteristic, effectively saving the chip area and reducing the chip production cost; in addition, multiple ESD current discharge paths make the ESD current more evenly distributed in the SCR device, and also improve the robustness of the discharge path of the SCR device under large current.

[0037] Furthermore, the second p-type well region 110 and the first p heavily doped region 120, the first p heavily doped region 120 and the first n heavily doped region 220, the first n heavily doped region 220 and the second p heavily doped region 121, the second p heavily doped region 121 and the third p heavily doped region 122, the third p heavily doped region 122 and the second n heavily doped region 221, the third n heavily doped region 222 and the fourth n heavily doped region 223, and the fourth n heavily doped region 223 and the second p-type well region 110 are all isolated by shallow trench dielectric (STI). The shallow trench dielectric provides an insulating structure between each well region and each heavily doped region, thereby playing an isolation role.

[0038] Furthermore, the n-type deep well region, the first p-type well region, the first n-type well region, the second p-type well region, the first p-heavy doped region, the first n-heavy doped region, the second p-heavy doped region, the third p-heavy doped region, the second n-heavy doped region, the third n-heavy doped region and the fourth n-heavy doped region are all formed by ion implantation or diffusion.

[0039] Preferably, the ion doping concentrations of the first p heavily doped region 120, the first n heavily doped region 220, the second p heavily doped region 121, the third p heavily doped region 122, the second n heavily doped region 221, the third n heavily doped region 222, and the fourth n heavily doped region 223 are all greater than 1×10 18 cm -3 ; The ion doping concentration of the first p-type well region, the first n-type well region and the second p-type well region is 1×10 16 cm -3 ~ 1×10 18 cm -3 ; The ion doping concentration of the n-type deep well region 200 is 1×10 16 cm -3 ~ 1×10 19 cm -3 .

[0040] It can be understood that the ion doping concentration of each heavily doped region, each well region, and the deep well region is affected by the process method for manufacturing the device, and the ion doping concentration provided in this embodiment is only a preferred embodiment.

[0041] See also Fig.10 In this embodiment, a process method for the above SCR device is also provided, comprising the steps of: Step 101, preparing a p-type substrate; Step 102, etching the p-type substrate to form a plurality of shallow trenches, and injecting a shallow trench dielectric into each shallow trench, wherein the plurality of shallow trenches injected with the shallow trench dielectric are spaced apart along a first direction, and the first direction is perpendicular to a thickness direction of the p-type substrate; Step 103, forming an n-type deep well region in the p-type substrate; Step 104, forming a first p-type well region in the n-type deep well region, forming a second p-type well region in the p-type substrate, and simultaneously injecting into the n-type deep well region and the p-type substrate at the interface between the n-type deep well region and the p-type substrate to form a first n-type well region, wherein the first n-type well region is arranged around the periphery of the first p-type well region, and the second p-type well region is arranged around the periphery of the first n-type well region; Step 105, forming a first p heavily doped region on the first n-type well region, implanting the first n-type well region and the first p-type well region at the interface between the first n-type well region and the first p-type well region to form a first n heavily doped region, forming a second p heavily doped region on the first p-type well region, forming a third p heavily doped region on the first p-type well region, forming a second n heavily doped region on the first p-type well region, implanting the first p-type well region and the first n-type well region at the interface between the first p-type well region and the first n-type well region to form a third n heavily doped region, and forming a fourth n heavily doped region on the first n-type well region, wherein the first p heavily doped region The first p-type well region, the second p-type well region, the third p-type well region, the second n-type well region, the third n-type well region and the fourth n-type well region are arranged at intervals along the first direction, and the second p-type well region and the first p-type well region, the first p-type well region and the first n-type well region, the first n-type well region and the second p-type well region, the second p-type well region and the third p-type well region, the third n-type well region and the fourth n-type well region, and the fourth n-type well region and the second p-type well region are isolated by corresponding shallow trench dielectrics; Step 106, forming a gate dielectric layer between the second n-heavy doped region, the third n-heavy doped region and the first p-type well region; Step 107, metal interconnecting the first p heavily doped region and the fourth n heavily doped region to the anode, metal interconnecting the third p heavily doped region and the second n heavily doped region to the cathode, metal interconnecting the first n heavily doped region to the third n heavily doped region, and metal interconnecting the second p heavily doped region to the gate dielectric layer.

[0042] In some embodiments, the n-type deep well region, the first p-type well region, the first n-type well region, the second p-type well region, the first p-heavy doped region, the first n-heavy doped region, the second p-heavy doped region, the third p-heavy doped region, the second n-heavy doped region, the third n-heavy doped region and the fourth n-heavy doped region are all formed by ion implantation or diffusion.

[0043] The first p heavily doped region, the fourth n heavily doped region and the anode, the first n heavily doped region and the third n heavily doped region, and the second p heavily doped region and the gate dielectric layer can be interconnected by wire bonding or metal deposition to form connecting wires.

[0044] In some embodiments, the shallow trench dielectric is injected into each shallow trench, including: An oxide layer is grown on the inner surface of each shallow trench, a shallow trench dielectric is deposited in the shallow trench where the oxide layer is grown, and a surface on one side of the SCR device where the shallow trench dielectric is exposed is polished.

[0045] Among them, the shallow trench dielectric can be silicon dioxide, silicon nitride or other low dielectric constant materials. The shallow trench dielectric can be deposited by various deposition processes such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The chemical mechanical polishing (CMP) process can be used to polish the side surface of the SCR device where the shallow trench dielectric is exposed, which is used to flatten the surface of the SCR device after the shallow trench dielectric is filled.

[0046] It should be noted that the process method provided in this embodiment is only a preferred embodiment. In other embodiments, the process method of the SCR device is not limited to the order of steps in the above embodiments. In other embodiments, those skilled in the art can change the order of steps of the SCR process method according to the actual process, such as changing the injection sequence of each well region, injecting multiple well regions at the same time, etc.

[0047] This embodiment also provides a chip, including the above-mentioned SCR device.

[0048] The chip with the above-mentioned SCR device is suitable for a wider range of application scenarios of electronic equipment and systems, especially high-voltage environments with high stability requirements. In addition, since the SCR device has a low on-resistance characteristic, the chip area is effectively saved, making the production cost of the chip lower.

[0049] It should be noted that each embodiment in the present application is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method embodiment, since it is implemented on the structure based on the product embodiment, the description of some product structures is omitted in the description, and the relevant parts can be referred to the partial description of the product embodiment.

[0050] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An SCR device, characterized in that: include: a p-type substrate, an n-type deep well region formed in the p-type substrate, a first p-type well region formed in the n-type deep well region, a second p-type well region formed in the p-type substrate, a first n-type well region formed by injecting simultaneously into the n-type deep well region and the p-type substrate at a boundary between the n-type deep well region and the p-type substrate, a first p-heavy doped region formed on the first n-type well region, a first n-heavy doped region formed by injecting simultaneously into the first n-type well region and the first p-type well region at a boundary between the first n-type well region and the first p-type well region, a second p-heavy doped region formed on the first p-type well region, a third p-heavy doped region formed on the first p-type well region, a second n-heavy doped region formed on the first p-type well region, a third n-heavy doped region formed by injecting simultaneously into the first p-type well region and the first n-type well region at a boundary between the first p-type well region and the first n-type well region, and a fourth n-heavy doped region formed on the first n-type well region; The first n-type well region is disposed around the periphery of the first p-type well region, and the second p-type well region is disposed around the periphery of the first n-type well region; The first p heavily doped region, the first n heavily doped region, the second p heavily doped region, the third p heavily doped region, the second n heavily doped region, the third n heavily doped region and the fourth n heavily doped region are arranged at intervals along a first direction, and the first direction is perpendicular to the thickness direction of the p-type substrate; the SCR device also includes a gate dielectric layer, a cathode and an anode; the gate dielectric layer is formed between the second n heavily doped region, the third n heavily doped region and the first p-type well region; the first p heavily doped region and the fourth n heavily doped region are both metal interconnected to the anode; the third p heavily doped region and the second n heavily doped region are both metal interconnected to the cathode; the first n heavily doped region is both metal interconnected to the third n heavily doped region; the second p heavily doped region is metal interconnected to the gate dielectric layer.

2. The SCR device according to claim 1, characterized in that: The second p-type well region and the first p heavily doped region, the first p heavily doped region and the first n heavily doped region, the first n heavily doped region and the second p heavily doped region, the second p heavily doped region and the third p heavily doped region, the third p heavily doped region and the second n heavily doped region, the third n heavily doped region and the fourth n heavily doped region, and the fourth n heavily doped region and the second p-type well region are all isolated by shallow trench dielectrics.

3. The SCR device according to claim 1, characterized in that: The n-type deep well region, the first p-type well region, the first n-type well region, the second p-type well region, the first p-heavy doped region, the first n-heavy doped region, the second p-heavy doped region, the third p-heavy doped region, the second n-heavy doped region, the third n-heavy doped region and the fourth n-heavy doped region are all formed by ion implantation or diffusion.

4. The SCR device according to claim 1, characterized in that: The ion doping concentrations of the first p heavily doped region, the first n heavily doped region, the second p heavily doped region, the third p heavily doped region, the second n heavily doped region, the third n heavily doped region, and the fourth n heavily doped region are all greater than 1×10 18 cm -3 ; The ion doping concentration of the first p-type well region, the first n-type well region and the second p-type well region is 1×10 16 cm -3 ~ 1×10 18 cm -3 ; The ion doping concentration of the n-type deep well region is 1×10 16 cm -3 ~ 1×10 19 cm -3 .

5. A process for producing an SCR device according to any one of claims 1 to 4, characterized in that: Includes steps: Preparing a p-type substrate; Etching the p-type substrate to form a plurality of shallow trenches, and injecting a shallow trench dielectric into each of the shallow trenches, wherein the plurality of shallow trenches into which the shallow trench dielectric is injected are spaced apart along a first direction, and the first direction is perpendicular to a thickness direction of the p-type substrate; forming an n-type deep well region in the p-type substrate; A first p-type well region is formed in the n-type deep well region, a second p-type well region is formed in the p-type substrate, and a first n-type well region is formed by injecting into the n-type deep well region and the p-type substrate at the interface between the n-type deep well region and the p-type substrate, wherein the first n-type well region is arranged around the periphery of the first p-type well region, and the second p-type well region is arranged around the periphery of the first n-type well region; A first p-heavy doped region is formed on the first n-type well region, and a first n-heavy doped region is formed by injecting into the first n-type well region and the first p-type well region at the junction of the first n-type well region and the first p-type well region at the same time, and a second p-heavy doped region is formed on the first p-type well region, and a third p-heavy doped region is formed on the first p-type well region, and a second n-heavy doped region is formed on the first p-type well region, and a third n-heavy doped region is formed by injecting into the first p-type well region and the first n-type well region at the junction of the first p-type well region and the first n-type well region at the same time, and a fourth n-heavy doped region is formed on the first n-type well region, wherein the first p-heavy doped region and the first n-heavy doped region , the second p heavily doped region, the third p heavily doped region, the second n heavily doped region, the third n heavily doped region and the fourth n heavily doped region are arranged at intervals along the first direction, and the second p-type well region and the first p heavily doped region, the first p heavily doped region and the first n heavily doped region, the first n heavily doped region and the second p heavily doped region, the second p heavily doped region and the third p heavily doped region, the third p heavily doped region and the second n heavily doped region, the third n heavily doped region and the fourth n heavily doped region, and the fourth n heavily doped region and the second p-type well region are all isolated by the corresponding shallow trench dielectrics; forming the gate dielectric layer between the second n-heavy doped region, the third n-heavy doped region and the first p-type well region; The first p heavily doped region and the fourth n heavily doped region are respectively metal-interconnected with the anode, the third p heavily doped region and the second n heavily doped region are respectively metal-interconnected with the cathode, the first n heavily doped region is metal-interconnected with the third n heavily doped region, and the second p heavily doped region is metal-interconnected with the gate dielectric layer.

6. A chip, characterized in that: The method comprises the SCR device as claimed in any one of claims 1 to 4.

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