Short wave array signal phase control synchronization method based on pulse programming

By adopting a pulse programming method in the short-wave array system, the synchronization signal FPGA and the array signal FPGA work together to generate a pulse group for array signal trigger operation, solving the problem of low synchronization accuracy of multi-channel array signal, and achieving high-precision array signal synchronization and stable array phased synthesis effects.

CN120111646AActive Publication Date: 2025-06-06CHINESE PEOPLES LIBERATION ARMY UNIT 32802
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Patent Information

Application Number
CN202510284497.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-03-11
Publication Date
2025-06-06
Estimated Expiration
2045-03-11

AI Technical Summary

Technical Problem

In short-wave array systems, it is difficult for the prior art to achieve accurate synchronization of multi-channel array signals, resulting in factors such as clock jitter and clock offset that affect the synchronization accuracy, making it difficult to meet the high-precision needs of array synthesis.

Method used

Using a pulse programming method, through the synchronous operation of the synchronization signal FPGA and the array signal FPGA, a pulse group for array signal trigger operation is generated, and errors caused by layout and wiring delay, clock offset and clock jitter are eliminated to achieve accurate synchronization of multi-channel array signals.

Benefits of technology

High-precision synchronization of multi-channel array signals is achieved, which eliminates the influence of adverse factors such as clock jitter, ensures the effect of array phased synthesis, and improves the stability and reliability of the system.

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Abstract

The invention discloses a short wave array signal phase control synchronization method based on pulse programming, which can eliminate errors caused by layout and wiring delay, clock skew and clock jitter through pulse programming and realize accurate array signal synchronization. The main implementation process comprises the following steps: 1) synchronous clock generation: obtaining N + 1 paths of stable and synchronous main clocks through input clock processing, main clock distribution, main clock deviation elimination, driving and buffering, and then generating N + 1 paths of synchronous sub-clocks with different frequencies through clock derivation; 2) programmable pulse generation: after receiving an external signal generation instruction, generating one path of pulse according to a synchronous main clock, and then generating pulses of other main clocks and sub-clocks through pulse programming for synchronous triggering of array signal generation; (3) array signal generation: under the trigger of the sub-clock pulse, the baseband signal is acquired and processed through a modulation source, and a low-rate baseband signal is generated; under the triggering of a main clock pulse, a high-rate baseband signal is obtained through baseband signal processing on a low-rate baseband signal, a carrier signal corresponding to an initial phase is generated according to an array output phase requirement, and quadrature modulation, amplitude adjustment and digital-to-analog conversion are carried out to obtain an array signal for transmission.
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