Wafer level chip system design space construction and fast parameter search method
By combining Bayesian optimization and graph neural networks into a joint model, the problems of low computational efficiency, insufficient global optimization capability, and difficulty in multimodal data processing in wafer-level chip system design are solved. This enables efficient design space exploration and task scheduling optimization, thereby improving the design performance of wafer-level chip systems.
Patent Information
- Application Number
- CN202510366146.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2025-11-11
- Estimated Expiration
- 2045-03-26
AI Technical Summary
Wafer-level chip system design suffers from problems such as low computational efficiency, insufficient global optimization capabilities, difficulties in task mapping and resource scheduling, and insufficient multimodal data processing capabilities. Traditional methods are unable to effectively explore high-dimensional design spaces.
By combining Bayesian optimization algorithms and graph neural networks, a joint model is constructed to generate a solution space and perform fast parameter search through iterative optimization methods of initialization, feature extraction, solution space generation, Bayesian optimization, and model update. A cross-modal attention mechanism is used to process multimodal data, and task partitioning and hardware selection are optimized.
It improves the global optimization capability and computational efficiency of wafer-level chip system design, can effectively handle complex multimodal input data, provides interpretable design results, and is suitable for high-complexity system design and multi-task scheduling optimization.