Noise reduction circuit and gate drive circuit

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a noise reduction circuit and a gate driving circuit, and the noise reduction circuit comprises a first noise reduction module which is used for carrying out the noise reduction processing of the voltage of a driving control node, a driving output end and a stage transmission output end; the first noise reduction module is also used for enabling a noise reduction transistor in the first noise reduction module to be in a reverse bias state under the action of a second noise reduction control signal; the second noise reduction module is used for carrying out noise reduction processing on voltage on the driving control node, the driving output end and the stage transmission output end; the second noise reduction module is also used for enabling a noise reduction transistor in the second noise reduction module to be in a reverse bias state under the action of the first noise reduction control signal; according to the noise reduction circuit, the noise reduction transistors in the two groups of noise reduction modules are in the reverse bias state when not working, so that the forward bias state of the noise reduction transistors in alternate working is counteracted, the problem that the threshold voltage of the noise reduction transistors drifts is solved, and the noise reduction stability of the noise reduction circuit is improved.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display driving, and particularly relates to a noise reduction circuit and a gate driving circuit. Background Art

[0002] TFT-LCD (Thin-Film Transistor Liquid Crystal Display) realizes image display by controlling the light transmittance of pixels in the display area. Specifically: under the action of an applied voltage, the liquid crystal molecules inside a single pixel deflect, thereby changing the light transmittance and presenting colors; the display area is composed of pixels arranged in an array, and dynamic display is achieved by switching the pixel states frame by frame.

[0003] GOA (Gate Driver on Array) is a key circuit for TFT-LCD to achieve progressive scanning. However, the noise reduction circuit for noise reduction processing of each key node is the core module for the reliable operation of GOA. However, the noise reduction transistors in the noise reduction circuit are in a forward gate-source voltage (Vgs) bias state during operation for a long time, which easily causes the threshold voltage (Vth) of the noise reduction transistors to drift, resulting in unstable noise reduction and abnormal GOA output signals, affecting the display effect of the display panel.

[0004] Therefore, how to improve the unstable noise reduction caused by the threshold voltage drift of the noise reduction transistors is the problem to be solved currently in the baseband. Summary of the Invention

[0005] The embodiments of the present application provide a noise reduction circuit and a gate driving circuit. In the present application, the noise reduction transistors in two groups of noise reduction modules are in a reverse bias state when not working, so as to offset the forward bias state of the noise reduction transistors during alternating operation, improve the problem of threshold voltage drift of the noise reduction transistors, and improve the noise reduction stability of the noise reduction circuit.

[0006] In a first aspect, an embodiment of the present application provides a noise reduction circuit, which is applied to a gate driving circuit. The gate driving circuit includes N cascaded gate driving modules. The nth gate driving module includes at least a driving control node, a driving output terminal, a stage transmission output terminal, and a noise reduction circuit. The noise reduction circuit includes: a first noise reduction module, a first input end of the first noise reduction module is connected to a first noise reduction control end, a second input end of the first noise reduction module is connected to the driving control node, a third input end of the first noise reduction module is connected to a second noise reduction control end, and an output end of the first noise reduction module is respectively connected to the driving output terminal, the stage transmission output terminal, and the driving control node, and is configured to perform noise reduction processing on the voltages on the driving control node, the driving output terminal, and the stage transmission output terminal under the action of a first noise reduction control signal output by the first noise reduction control end and the voltage on the driving control node; and is further configured to make the noise reduction transistor in the first noise reduction module in a reverse bias state under the action of a second noise reduction control signal output by the second noise reduction control end; a second noise reduction module, a first input end of the second noise reduction module is connected to the second noise reduction control end, a second input end of the second noise reduction module is connected to the driving control node, a third input end of the second noise reduction module is connected to the first noise reduction control end, and an output end of the second noise reduction module is respectively connected to the driving output terminal, the stage transmission output terminal, and the driving control node, and is configured to perform noise reduction processing on the voltages on the driving control node, the driving output terminal, and the stage transmission output terminal under the action of a second noise reduction control signal output by the second noise reduction control end and the voltage on the driving control node; and is further configured to make the noise reduction transistor in the second noise reduction module in a reverse bias state under the action of a first noise reduction control signal output by the first noise reduction control end; wherein, the first noise reduction control signal and the second noise reduction control signal have opposite phases.

[0007] In a second aspect, an embodiment of the present application provides a gate driving circuit, which includes N cascaded gate driving modules. The nth gate driving module includes: a pull-up unit, the pull-up unit is respectively connected to the driving output terminal of the (n - i)th gate driving module and the stage transmission output terminal of the (n - i)th gate driving module; a pull-down unit, the pull-down unit is connected to the stage transmission output terminal of the (n + j)th gate driving module, and the pull-down unit is further connected to the pull-up unit through a driving control node; an output unit, the output unit is respectively connected to a clock signal terminal and the driving control node; a noise reduction circuit, the noise reduction circuit is respectively connected to the driving control node, the driving output terminal, and the stage transmission output terminal of the current stage gate driving module.

[0008] The technical solution provided by the embodiment of the present application has at least the following beneficial effects: When the noise reduction transistor in the first noise reduction module of this application performs noise reduction processing on important nodes, the noise reduction transistors in the non-operating second noise reduction module are in a reverse bias state, and when the noise reduction transistors in the second noise reduction module perform noise reduction processing on important nodes, the noise reduction transistors in the non-operating first noise reduction module are in a reverse bias state; therefore, in this application, the noise reduction transistors in the two groups of noise reduction modules are in a reverse bias state when not operating, so as to offset the forward bias state of the noise reduction transistors during alternating operation, improve the problem of the threshold voltage drift of the noise reduction transistors, and improve the noise reduction stability of the noise reduction circuit.

[0009] (2)The reverse correction of the noise reduction transistor in this application is carried out during the non-operating time period of the noise reduction transistor. The reverse correction time is long, which can effectively suppress the threshold voltage drift, and at the same time, it does not need to occupy the scanning time or the blanking time, and will not have any impact on the charging rate of the pixel. Brief Description of the Drawings

[0010] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 The following shows a schematic structural diagram of a gate driving module provided by an embodiment of this application.

[0012] Figure 2 The following shows a schematic circuit diagram of a noise reduction circuit in the related art.

[0013] Figure 3 The following shows a schematic structural diagram of a first noise reduction circuit provided by an embodiment of this application.

[0014] Figure 4 The following shows a schematic driving timing diagram provided by an embodiment of this application.

[0015] Figure 5 The following shows a schematic structural diagram of a second noise reduction circuit provided by an embodiment of this application.

[0016] Figure 6 The following shows a schematic circuit diagram of a first noise reduction circuit provided by an embodiment of this application.

[0017] Figure 7 The following shows a schematic circuit diagram of a second noise reduction circuit provided by an embodiment of this application.

[0018] Figure 8 The following shows a schematic circuit diagram of a third noise reduction circuit provided by an embodiment of this application.

[0019] Figure 9 The following is a schematic circuit diagram of the fourth noise reduction circuit provided by the embodiment of the present application.

[0020] Description of the reference numerals: 100, noise reduction circuit; 110, first noise reduction module; 111, first noise reduction control unit; 112, first noise reduction execution unit; 1121, first execution subunit; 1122, first correction subunit; 120, second noise reduction module; 121, second noise reduction control unit; 122, second noise reduction execution unit; 1221, second execution subunit; 1222, second correction subunit; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; Qn, drive control node; Fn, stage transmission output terminal; Gn, drive output terminal; LC1, first noise reduction control terminal; LC2, second noise reduction control terminal; VSS1, first low level terminal; VSS2, second low level terminal. Detailed implementation manners

[0021] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art.

[0022] In addition, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be used. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0023] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted here that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application and should not be construed as limiting the present application.

[0024] Through research by the inventors of the present application, it is found that the gate driving circuit includes N cascaded gate driving modules. As Figure 1 shown, the nth-stage gate driving module mainly includes a pull-up unit, a pull-down unit, an output unit, a reset unit, and a noise reduction circuit, etc. The pull-up unit and the pull-down unit generate the Q-point voltage. The pull-up unit and the pull-down unit need to obtain multiple stage transmission signals from the upper and lower gate driving modules. The Q-point voltage is the turn-on voltage of the output unit, which enables the output unit to output a gate driving signal to provide a turn-on voltage for the display area. The reset unit is used to avoid the influence between frames, and the noise reduction circuit performs noise reduction processing on the signals at each key node; where Qn represents the driving control node of the nth-stage gate driving module, Gn represents the driving output terminal of the nth-stage gate driving module, Fn represents the stage transmission output terminal of the nth-stage gate driving module, CKn represents the clock signal terminal of the nth-stage gate driving module, Reset represents the reset signal terminal, LC represents the noise reduction control terminal, Gn-3 represents the driving output terminal of the (n-3)th-stage gate driving module, Fn-3 represents the stage transmission output terminal of the (n-3)th-stage gate driving module, and Fn+4 represents the stage transmission output terminal of the (n+4)th-stage gate driving module.

[0025] The normal output of the gate driving module is a necessary condition to ensure the normal display of the picture. Therefore, the noise suppression effect of the noise reduction circuit on the signal is particularly important. Figure 2 The circuit schematic diagram of the noise reduction circuit in the related art is shown. The first transistor T1 and the second transistor T2 are control transistors, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all noise reduction transistors; when the driving control node (i.e., the Q point) in the nth-stage gate driving module is at a low level, the noise reduction control terminal LC continuously outputs a high level. At this time, the first transistor T1 is turned on, and the second transistor T2 is turned off, making the noise reduction control node Pn at a high level, and respectively turning on the third transistor T3, the fourth transistor T4, and the fifth transistor T5, so as to continuously pull down the signals on the driving output terminal Gn, the driving control node Qn, and the stage transmission output terminal Fn, achieving noise reduction processing on each important node in the gate driving module; since the driving output terminal, the driving control node, and the stage transmission output terminal in each stage of the gate driving module are only not noise-reduced during the scanning time of the current stage, and the other times are all noise reduction processing time periods; therefore, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 in the noise reduction circuit need to be in a forward gate-source voltage bias state for a long time, which is likely to cause the problem of threshold voltage (Vth) drift of the noise reduction transistors, and further cause abnormal output signals of the GOA circuit, affecting the display effect of the display panel.

[0026] In order to improve the problem of threshold voltage drift of the noise reduction transistors, the present application provides a noise reduction circuit, which specifically includes the following embodiments: Figure 3The following is a schematic structural diagram of a noise reduction circuit provided by an embodiment of the present application; the noise reduction circuit 100 of this embodiment is applied to a gate driving circuit, and the gate driving circuit includes N cascaded gate driving modules; as Figure 1 and Figure 3 shown, each stage of the gate driving module includes at least a driving control node Qn, a driving output terminal Gn, a stage transmission output terminal Fn, and a noise reduction circuit 100.

[0027] As Figure 3 shown, the noise reduction circuit 100 of this embodiment includes a first noise reduction module 110. The first input terminal of the first noise reduction module 110 is connected to a first noise reduction control terminal LC1, the second input terminal of the first noise reduction module 110 is connected to the driving control node Qn, the third input terminal of the first noise reduction module 110 is connected to a second noise reduction control terminal LC2, and the output terminal of the first noise reduction module 110 is respectively connected to the driving output terminal Gn, the stage transmission output terminal Fn, and the driving control node Qn, and is used to perform noise reduction processing on the voltages on the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn under the action of the first noise reduction control signal output by the first noise reduction control terminal LC1 and the voltage on the driving control node Qn; it is also used to make the noise reduction transistor in the first noise reduction module 110 in a reverse bias state under the action of the second noise reduction control signal output by the second noise reduction control terminal LC2.

[0028] The noise reduction circuit 100 of this embodiment further includes a second noise reduction module 120. The first input terminal of the second noise reduction module 120 is connected to the second noise reduction control terminal LC2, the second input terminal of the second noise reduction module 120 is connected to the driving control node Qn, the third input terminal of the second noise reduction module 120 is connected to the first noise reduction control terminal LC1, and the output terminal of the second noise reduction module 120 is respectively connected to the driving output terminal Gn, the stage transmission output terminal Fn, and the driving control node Qn, and is used to perform noise reduction processing on the voltages on the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn under the action of the second noise reduction control signal output by the second noise reduction control terminal LC2 and the voltage on the driving control node Qn; it is also used to make the noise reduction transistor in the second noise reduction module 120 in a reverse bias state under the action of the first noise reduction control signal output by the first noise reduction control terminal LC1.

[0029] Specifically, the phase of the first noise reduction control signal output by the first noise reduction control terminal LC1 and the phase of the second noise reduction control signal output by the second noise reduction control terminal LC2 are opposite, that is: as Figure 4As shown, during the working frame of the first noise reduction control signal (i.e., the LC1 working frame), the first noise reduction control signal output by the first noise reduction control terminal LC1 is at a high level, and the second noise reduction control signal output by the second noise reduction control terminal LC2 is at a low level; conversely, during the working frame of the second noise reduction control signal (i.e., the LC2 working frame), the first noise reduction control signal output by the first noise reduction control terminal LC1 is at a low level, and the second noise reduction control signal output by the second noise reduction control terminal LC2 is at a high level; wherein, the phase switching of the first noise reduction control signal and the second noise reduction control signal can be one frame or multiple frames.

[0030] Here, in combination with Figure 3 and Figure 4 the working principle of the noise reduction circuit 100 of this embodiment will be described in detail: (1) During the LC1 working frame, the first noise reduction control signal is at a high level, and the second noise reduction control signal is at a low level; since the voltage on the driving control node Qn is at a high level, it is the scanning time of the current-stage gate driving module, so the noise reduction of the important nodes of the gate driving module can only be carried out at the low level of the driving control node Qn; therefore, under the action of the first noise reduction control signal at a high level and the low-level voltage on the driving control node Qn, the first noise reduction module 110 performs noise reduction processing on the voltages on the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn. At the same time, the second noise reduction module 120 does not perform noise reduction processing under the action of the second noise reduction control signal at a low level, but the first noise reduction control signal at a high level makes the noise reduction transistor in the second noise reduction module 120 in a reverse bias state; that is to say, when the noise reduction transistor in the first noise reduction module 110 performs noise reduction processing on the important nodes, the noise reduction transistor in the second noise reduction module 120 is in a reverse bias state.

[0031] (2) During the LC2 working frame, the first noise reduction control signal is at a low level, and the second noise reduction control signal is at a high level; therefore, under the action of the second noise reduction control signal at a high level and the low-level voltage on the driving control node Qn, the second noise reduction module 120 performs noise reduction processing on the voltages on the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn. At the same time, the first noise reduction module 110 does not perform noise reduction processing under the action of the first noise reduction control signal at a low level, but the second noise reduction control signal at a high level makes the noise reduction transistor in the first noise reduction module 110 in a reverse bias state; that is to say, when the noise reduction transistor in the second noise reduction module 120 performs noise reduction processing on the important nodes, the noise reduction transistor in the first noise reduction module 110 is in a reverse bias state.

[0032] It can be seen from this that when the noise reduction transistor in the first noise reduction module 110 of the present application performs noise reduction processing on important nodes, the noise reduction transistors in the non-operating second noise reduction module 120 are in a reverse bias state, and when the noise reduction transistors in the second noise reduction module 120 perform noise reduction processing on important nodes, the noise reduction transistors in the non-operating first noise reduction module 110 are in a reverse bias state; therefore, in the present application, the noise reduction transistors in the two groups of noise reduction modules are in a reverse bias state when not in operation, so as to offset the forward bias state of the noise reduction transistors during alternating operation, improve the problem of the threshold voltage drift of the noise reduction transistors, and improve the noise reduction stability of the noise reduction circuit 100. Further, the reverse correction of the noise reduction transistors in the present application is performed during the non-operating time period of the noise reduction transistors. The reverse correction time is long, which can effectively suppress the threshold voltage drift, and at the same time, it does not need to occupy the scanning time or the blanking time, and has no impact on the charging rate of the pixels.

[0033] Continue as Figure 3 shown, the first noise reduction module 110 of this embodiment includes: a first noise reduction control unit 111 and a first noise reduction execution unit 112. The first control end of the first noise reduction control unit 111 is connected to the first noise reduction control end LC1, and the second control end of the first noise reduction control unit 111 is connected to the drive control node Qn, and is used to output a first noise reduction signal under the action of the first noise reduction control signal output by the first noise reduction control end LC1 and the voltage on the drive control node Qn; the first control end of the first noise reduction execution unit 112 is connected to the output end of the first noise reduction control unit 111, the second control end of the first noise reduction execution unit 112 is connected to the second noise reduction control end LC2, and the output end of the first noise reduction execution unit 112 is respectively connected to the drive control node Qn, the drive output end Gn, and the stage transmission output end Fn, and is used to perform noise reduction processing on the voltages on the drive control node Qn, the drive output end Gn, and the stage transmission output end Fn according to the first noise reduction signal; it is also used to make the noise reduction transistors in the first noise reduction execution unit 112 in a reverse bias state according to the second noise reduction control signal.

[0034] The second noise reduction module 120 of this embodiment includes: a second noise reduction control unit 121 and a second noise reduction execution unit 122. The first control end of the second noise reduction control unit 121 is connected to the second noise reduction control end LC2, and the second control end of the second noise reduction control unit 121 is connected to the drive control node Qn. It is used to output a second noise reduction signal under the action of the first noise reduction control signal output by the second noise reduction control end LC2 and the voltage on the drive control node Qn. The first control end of the second noise reduction execution unit 122 is connected to the output end of the second noise reduction control unit 121, the second control end of the second noise reduction execution unit 122 is connected to the first noise reduction control end LC1, and the output end of the second noise reduction execution unit 122 is respectively connected to the drive control node Qn, the drive output end Gn, and the stage transmission output end Fn. It is used to perform noise reduction processing on the voltages on the drive control node Qn, the drive output end Gn, and the stage transmission output end Fn according to the second noise reduction signal. It is also used to make the noise reduction transistor in the second noise reduction execution unit 122 in a reverse bias state according to the first noise reduction control signal.

[0035] It should be noted that the specific working principles of the first noise reduction control unit 111 and the second noise reduction control unit 121 are the same, and the working principles of the first noise reduction execution unit 112 and the second noise reduction execution unit 122 are the same. The only difference is that they are controlled by different noise reduction control signals. Next, only the working principles of one of the noise reduction control units and the noise reduction execution units will be described in detail.

[0036] In the driving technology of the display panel, the scan stage and the blanking stage are key points in timing control. The two jointly ensure the correct update of pixel data and the stability of display. The scan stage is the stage where the gate driving circuit activates pixels row by row and writes data. For example, in a display with progressive scanning, the gate driving signal will select each row of pixels from top to bottom in sequence and write the voltage signal into the pixel unit of that row through the data line. The blanking stage is the "interval period" between scans. At this time, the driving circuit stops writing data, which is used to switch rows or frames to prevent signal overlap from causing display disorders.

[0037] In this embodiment, taking the first noise reduction control unit 111 as an example, under the combined action of the first noise reduction control signal output by the first noise reduction control end LC1 and the voltage on the drive control node Qn, the first noise reduction control unit 111 in the nth - stage gate driving module outputs a first noise reduction signal during the non - scanning time period in the scan stage of the nth - stage gate driving module, and does not output the first noise reduction signal during the scanning time period of the nth - stage gate driving module.

[0038] Taking the first noise reduction execution unit 112 as an example, the voltages on the drive control node Qn, the drive output terminal Gn and the stage transmission output terminal Fn are subjected to noise reduction processing according to the first noise reduction signal output by the first noise reduction control unit 111. That is to say, the first noise reduction execution unit 112 continuously pulls down the signals on the drive output terminal Gn, the drive control node Qn and the stage transmission output terminal Fn in the gate drive module of this stage, so as to avoid leakage current in the circuit or other transistor abnormalities causing the voltages on the drive output terminal Gn, the drive control node Qn and / or the stage transmission output terminal Fn to be at a high level, thereby causing display abnormalities such as pixel mischarging.

[0039] Figure 5 FIG. 1 is a schematic diagram of the structure of a second noise reduction circuit provided in an embodiment of the present application; Figure 5 and Figure 4 The difference is: Figure 5 Will Figure 4 The first noise reduction execution unit 112 is subdivided into a first execution subunit 1121 and a first correction subunit 1122 , and the second noise reduction execution unit 122 is subdivided into a second execution subunit 1221 and a second correction subunit 1222 .

[0040] Specifically, the first noise reduction execution unit 112 includes a first execution subunit 1121 and a first correction subunit 1122. The control end of the first execution subunit 1121 is connected to the output end of the first noise reduction control unit 111, and the output end of the first execution subunit 1121 is respectively connected to the driving control node Qn, the driving output end Gn and the level transmission output end Fn, and is used to perform noise reduction processing on the voltages on the driving control node Qn, the driving output end Gn and the level transmission output end Fn according to the first noise reduction signal; the first control end of the first correction subunit 1122 is connected to the first noise reduction control end LC1, the second control end of the first correction subunit 1122 is connected to the second noise reduction control end LC2, and the output end of the first correction subunit 1122 is respectively connected to the first execution subunit 1121, and is used to output a low level when the first execution subunit 1121 performs noise reduction processing, and is also used to make the noise reduction transistor in the first execution subunit 1121 in a reverse bias state according to the second noise reduction control signal when the first execution subunit 1121 does not perform noise reduction processing; Optionally, the second noise reduction execution unit 122 includes a second execution subunit 1221 and a second correction subunit 1222. The control end of the second execution subunit 1221 is connected to the output end of the second noise reduction control unit 121. The output end of the second execution subunit 1221 is respectively connected to the drive control node Qn, the drive output end Gn, and the stage transmission output end Fn, and is configured to perform noise reduction processing on the voltages on the drive control node Qn, the drive output end Gn, and the stage transmission output end Fn according to the second noise reduction signal. The first control end of the second correction subunit 1222 is connected to the second noise reduction control end LC2, the second control end of the second correction subunit 1222 is connected to the first noise reduction control end LC1, and the output end of the second correction subunit 1222 is respectively connected to the second execution subunit 1221, and is configured to output a low level when the second execution subunit 1221 performs noise reduction processing, and is further configured to make the noise reduction transistors in the second execution subunit 1221 in a reverse bias state according to the first noise reduction control signal when the second execution subunit 1221 does not perform noise reduction processing.

[0041] It should be noted that taking the first noise reduction execution unit 112 as an example, the transistors in the first execution subunit 1121 are noise reduction transistors. When the first execution subunit 1121 works, the first correction subunit 1122 provides a low level for the first execution subunit 1121 under the action of the first noise reduction control signal, so that the noise reduction transistors in the first execution subunit 1121 perform noise reduction processing on the voltages on the drive control node Qn, the drive output end Gn, and the stage transmission output end Fn under the action of the first noise reduction signal and the low level, that is, the noise reduction transistors in the first execution subunit 1121 are in a forward bias state. In addition, when the first execution subunit 1121 is not working, the first correction subunit 1122 makes the noise reduction transistors in the first execution subunit 1121 in a reverse bias state under the action of the second noise reduction control signal, so as to cancel the forward bias state of the noise reduction transistors when they are working, and improve the problem that the threshold voltage of the noise reduction transistors drifts. The working principles of the second execution subunit 1221 and the second correction subunit 1222 are the same as the above, and will not be elaborated here.

[0042] Figure 6 The following shows a circuit schematic diagram of the first noise reduction circuit provided by the embodiment of the present application, as Figure 6As shown in the figure, the first noise reduction control unit 111 and the second noise reduction control unit 121 both include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. Among them, the control terminal of the first transistor T1 in the first noise reduction control unit 111 is connected to the first noise reduction control terminal LC1, and the control terminal of the first transistor in the second noise reduction control unit 121 is connected to the second noise reduction control terminal LC2. Optionally, the first end of the first transistor T1 is connected to the control terminal of the first transistor T1; the control terminal of the second transistor T2 is connected to the second end of the first transistor T1, and the first end of the second transistor T2 is connected to the first end of the first transistor T1; the control terminal of the third transistor T3 is connected to the drive control node Qn, the first end of the third transistor T3 is connected to the second end of the first transistor T1, and the second end of the third transistor T3 is connected to the first low level terminal VSS1; the control terminal of the fourth transistor T4 is connected to the control terminal of the third transistor T3, the first end of the fourth transistor T4 is connected to the second end of the second transistor T2, and the second end of the fourth transistor T4 is connected to the first low level terminal VSS1.

[0043] It should be noted that the main purpose of the first noise reduction control unit 111 and the second noise reduction control unit 121 in this embodiment is to invert the voltage on the drive control node Qn, that is: when the voltage on the drive control node Qn is high, the first noise reduction control unit 111 or the second noise reduction control unit 121 outputs a low level, and when the voltage on the drive control node Qn is low, the first noise reduction control unit 111 or the second noise reduction control unit 121 outputs a high level; the specific working principle of the first noise reduction control unit 111 is described as follows: (1) When the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all N-type MOS transistors, during the working stage of the first noise reduction control signal, the first noise reduction control terminal LC1 always outputs a high level, continuously turning on the first transistor T1.

[0044] (2) During the scanning time of the current stage gate drive module, the voltage on the drive control node Qn is high, and the third transistor T3 and the fourth transistor T4 are turned on simultaneously, so that the voltages on the node A1n and the first noise reduction control node P1n are both the first low level output by the first low level terminal VSS1, thereby turning off the second transistor T2, and the first noise reduction control unit 111 outputs the first low level.

[0045] (3) During the non-scanning time of the scanning stage of the current stage gate drive module, the voltage on the drive control node Qn is low, and the third transistor T3 and the fourth transistor T4 are turned off simultaneously, so that the voltage on the node A1n is high, thereby turning on the second transistor T2, and the first noise reduction control unit 111 outputs a high level, that is, the first noise reduction signal.

[0046] In addition, it should be noted that the above description of the working principle takes the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 as N-type MOS transistors as an example. When the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are P-type transistors, their working principles are the same but the phases are opposite, so it will not be elaborated here.

[0047] As Figure 6 shown, both the first noise reduction execution unit 112 and the second noise reduction execution unit 122 include a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7; specifically, in the first noise reduction execution unit 112, the control terminal of the fifth transistor T5 is connected to the output terminal of the first noise reduction control unit 111, the first terminal of the fifth transistor T5 is connected to the stage transmission output terminal Fn, and the second terminal of the fifth transistor T5 is connected to the second noise reduction control terminal LC2; the control terminal of the sixth transistor T6 is connected to the control terminal of the fifth transistor T5, the first terminal of the sixth transistor T6 is connected to the drive control node Qn, and the second terminal of the sixth transistor T6 is connected to the second noise reduction control terminal LC2; the control terminal of the seventh transistor T7 is connected to the control terminal of the fifth transistor T5, the first terminal of the seventh transistor T7 is connected to the drive output terminal Gn, and the second terminal of the seventh transistor T7 is connected to the second noise reduction control terminal LC2.

[0048] In the second noise reduction execution unit 122, the control terminal of the fifth transistor T5 is connected to the output terminal of the second noise reduction control unit 121, the first terminal of the fifth transistor T5 is connected to the stage transmission output terminal Fn, and the second terminal of the fifth transistor T5 is connected to the first noise reduction control terminal LC1; the control terminal of the sixth transistor T6 is connected to the control terminal of the fifth transistor T5, the first terminal of the sixth transistor T6 is connected to the drive control node Qn, and the second terminal of the sixth transistor T6 is connected to the first noise reduction control terminal LC1; the control terminal of the seventh transistor T7 is connected to the control terminal of the fifth transistor T5, the first terminal of the seventh transistor T7 is connected to the stage transmission output terminal FnGn, and the second terminal of the seventh transistor T7 is connected to the first noise reduction control terminal LC1.

[0049] It should be noted that taking the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 as N-type MOS transistors as an example, the working principle of the first noise reduction execution unit 112 will be described in detail: (1) When the first noise reduction control unit 111 outputs a first noise reduction signal, that is, the voltage on the first noise reduction control node P1n is at a high level, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned on simultaneously; at this time, the second noise reduction control signal output by the second noise reduction control terminal LC2 is at a low level, so that the voltage on the stage transmission output terminal Fn is pulled down through the turned-on fifth transistor T5, the voltage on the drive control node Qn is pulled down through the turned-on sixth transistor T6, and the voltage on the drive output terminal Gn is pulled down through the turned-on seventh transistor T7.

[0050] (2) When the first noise reduction control unit 111 does not output a first noise reduction signal, that is, the voltage on the first noise reduction control node P1n is at a low level, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off simultaneously, and the noise reduction process for the voltages on the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn is stopped.

[0051] In this embodiment, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the first noise reduction execution unit 112 are used as the noise reduction transistors of the first noise reduction module 110, and the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the second noise reduction execution unit 122 are used as the noise reduction transistors in the second noise reduction module 120. In this embodiment, the control terminal of the noise reduction transistor is connected to the output terminal of the noise reduction control unit, the first end of the noise reduction transistor is connected to the important node, and the second end of the noise reduction transistor is connected to the corresponding noise reduction control terminal of another module, so that the noise reduction transistor is in a forward bias state during noise reduction work and in a reverse bias state during non-noise reduction work, effectively improving the problem of threshold voltage drift of the noise reduction transistor.

[0052] Figure 7 The following shows the circuit schematic diagram of the second noise reduction circuit provided by the embodiment of the present application; Figure 7 In the shown noise reduction circuit 100, the first noise reduction control unit 111 and the second noise reduction control unit 121 are respectively connected to Figure 6 as shown above, and will not be elaborated here; Figure 7 Different from Figure 6 is that the specific circuit structures of the first noise reduction execution unit 112 and the second noise reduction execution unit 122 are different. Specifically, as shown in Figure 7 : The first execution subunit 1121 and the second execution subunit 1221 both include the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7; the first correction subunit 1122 and the second correction subunit 1222 both include the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11.

[0053] Specifically, in the first execution subunit 1121, the control terminal of the fifth transistor T5 is connected to the output terminal of the first noise reduction control unit 111. The first terminal of the fifth transistor T5 is connected to the stage transmission output terminal Fn. The second terminal of the fifth transistor T5 is connected to the first output terminal of the first correction subunit 1122. The control terminal of the sixth transistor T6 is connected to the control terminal of the fifth transistor T5. The first terminal of the sixth transistor T6 is connected to the drive control node Qn. The second terminal of the sixth transistor T6 is connected to the second output terminal of the first correction subunit 1122. The control terminal of the seventh transistor T7 is connected to the control terminal of the fifth transistor T5. The first terminal of the seventh transistor T7 is connected to the drive output terminal Gn. The second terminal of the seventh transistor T7 is connected to the third output terminal of the first correction subunit 1122. Among them, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are respectively used as the noise reduction transistors of the first noise reduction module 110.

[0054] In the second execution subunit 1221, the control terminal of the fifth transistor T5 is connected to the output terminal of the second noise reduction control unit 121. The first terminal of the fifth transistor T5 is connected to the stage transmission output terminal Fn. The second terminal of the fifth transistor T5 is connected to the first output terminal of the second correction subunit 1222. The control terminal of the sixth transistor T6 is connected to the control terminal of the fifth transistor T5. The first terminal of the sixth transistor T6 is connected to the drive control node Qn. The second terminal of the sixth transistor T6 is connected to the second output terminal of the second correction subunit 1222. The control terminal of the seventh transistor T7 is connected to the control terminal of the fifth transistor T5. The first terminal of the seventh transistor T7 is connected to the drive output terminal Gn. The second terminal of the seventh transistor T7 is connected to the third output terminal of the second correction subunit 1222. Among them, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are respectively used as the noise reduction transistors of the second noise reduction module 120.

[0055] It should be noted that the working principles of the first execution subunit 1121 and the second execution subunit 1221 in this embodiment are Figure 6 basically the same as those of the first noise reduction execution unit 112 and the second noise reduction execution unit 122 in Figure 6 , except that the second terminals of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in Figure 7 are connected to the noise reduction control terminal, while the second terminals of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in

[0056] are connected to the three output terminals of the execution subunit. Therefore, the working principles of the first execution subunit 1121 and the second execution subunit 1221 will not be elaborated here.In the first correction subunit 1122, the control terminal of the eighth transistor T8 is connected to the first noise reduction control terminal LC1, the first terminal of the eighth transistor T8 is connected to the second terminal of the fifth transistor T5, and the second terminal of the eighth transistor T8 is connected to the first low-level terminal VSS1; the control terminal of the ninth transistor T9 is connected to the control terminal of the eighth transistor T8, the first terminal of the ninth transistor T9 is connected to the second terminal of the sixth transistor T6, and the second terminal of the ninth transistor T9 is connected to the first low-level terminal VSS1; the control terminal of the tenth transistor T10 is connected to the control terminal of the eighth transistor T8, the first terminal of the tenth transistor T10 is connected to the second terminal of the seventh transistor T7, and the second terminal of the tenth transistor T10 is connected to the first low-level terminal VSS1; the control terminal of the eleventh transistor T11 is connected to the second noise reduction control terminal LC2, the first terminal of the eleventh transistor T11 is connected to the control terminal of the eleventh transistor T11, and the second terminal of the eleventh transistor T11 is respectively connected to the first terminal of the eighth transistor T8, the first terminal of the ninth transistor T9, and the second terminal of the tenth transistor T10.

[0057] In the second correction subunit 1222, the control terminal of the eighth transistor T8 is connected to the second noise reduction control terminal LC2, the first terminal of the eighth transistor T8 is connected to the second terminal of the fifth transistor T5, and the second terminal of the eighth transistor T8 is connected to the first low-level terminal VSS1; the control terminal of the ninth transistor T9 is connected to the control terminal of the eighth transistor T8, the first terminal of the ninth transistor T9 is connected to the second terminal of the sixth transistor T6, and the second terminal of the ninth transistor T9 is connected to the first low-level terminal VSS1; the control terminal of the tenth transistor T10 is connected to the control terminal of the eighth transistor T8, the first terminal of the tenth transistor T10 is connected to the second terminal of the seventh transistor T7, and the second terminal of the tenth transistor T10 is connected to the first low-level terminal VSS1; the control terminal of the eleventh transistor T11 is connected to the first noise reduction control terminal LC1, the first terminal of the eleventh transistor T11 is connected to the control terminal of the eleventh transistor T11, and the second terminal of the eleventh transistor T11 is respectively connected to the first terminal of the eighth transistor T8, the first terminal of the ninth transistor T9, and the second terminal of the tenth transistor T10.

[0058] It should be noted that taking the first correction subunit 1122 as an example, its specific working principle is as follows: (1) When the noise reduction transistor in the first execution subunit 1121 performs noise reduction work, the first noise reduction control signal is at a high level and the second noise reduction control signal is at a low level; at this time, the high-level first noise reduction control signal turns on the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10, so that the second terminal of the noise reduction transistor is respectively connected to the first low-level terminal VSS1, and the noise reduction process of the important node is realized through the noise reduction transistor in the forward bias state.

[0059] (2)When the noise reduction transistor in the first execution subunit 1121 does not perform noise reduction work, the first noise reduction control signal is at a low level, and the second noise reduction control signal is at a high level; at this time, the high-level second noise reduction control signal turns on the eleventh transistor T11, so that the second end of the noise reduction transistor is connected to the high level respectively, and the non-working noise reduction transistor is in a reverse bias state, effectively improving the problem of threshold voltage drift of the noise reduction transistor.

[0060] Figure 8 The following is a schematic structural diagram of the third noise reduction circuit provided by the embodiment of the present application; Figure 8 On the Figure 7 basis, a second low-level terminal VSS2 and a twelfth transistor T12 are added; specifically as Figure 8 shown: The first correction subunit 1122 and the second correction subunit 1222 include: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12; the control terminal of the eighth transistor T8 is connected to the first noise reduction control terminal LC1 or the second noise reduction control terminal LC2, the first end of the eighth transistor T8 is connected to the second end of the fifth transistor T5, and the second end of the eighth transistor T8 is connected to the first low-level terminal VSS1; the control terminal of the ninth transistor T9 is connected to the control terminal of the eighth transistor T8, the first end of the ninth transistor T9 is connected to the second end of the sixth transistor T6, and the second end of the ninth transistor T9 is connected to the first low-level terminal VSS1; the control terminal of the tenth transistor T10 is connected to the control terminal of the eighth transistor T8, the first end of the tenth transistor T10 is connected to the second end of the seventh transistor T7, and the second end of the tenth transistor T10 is connected to the second low-level terminal VSS2; the control terminal of the eleventh transistor T11 is connected to the second noise reduction control terminal LC2 or the first noise reduction control terminal LC1, the first end of the eleventh transistor T11 is connected to the control terminal of the eleventh transistor T11, and the second end of the eleventh transistor T11 is connected to the first end of the eighth transistor T8 and the first end of the ninth transistor T9 respectively; the control terminal of the twelfth transistor T12 is connected to the control terminal of the eleventh transistor T11, the first end of the twelfth transistor T12 is connected to the control terminal of the twelfth transistor T12, and the second end of the twelfth transistor T12 is connected to the first end of the tenth transistor T10.

[0061] It should be noted that in this embodiment, the eighth transistor T8 and the ninth transistor T9 are used to pull down the second ends of the fifth transistor T5 and the sixth transistor T6 (i.e., node Bn) to the first low level output by the first low level terminal VSS1, and the tenth transistor T10 is used to pull down the second end of the seventh transistor T7 (node Cn) to the second low level output by the second low level terminal VSS2; then, the second ends of the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are pulled up by the turned-on eleventh transistor T11 and twelfth transistor T12; by setting two low level terminals in this embodiment, the voltage values of the first low level and the second low level output by the two low level terminals can be adjusted respectively, the leakage currents of the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are reduced, and the stability of the voltage on the noise reduction control node is improved; in addition, by connecting the second end of the fifth transistor T5 and the second end of the seventh transistor T7 with the eleventh transistor T11 and the twelfth transistor T12 respectively, the short circuit of the two ends during the normal noise reduction stage can be avoided.

[0062] Figure 9 The figure shows a schematic structural diagram of a fourth noise reduction circuit provided by an embodiment of the present application; Figure 9 On the Figure 8 basis, a thirteenth transistor T13 is added; specifically as Figure 9 shown: the first correction subunit 1122 and the second correction subunit 1222 further include a thirteenth transistor T13, the control end of the thirteenth transistor T13 is connected to the control end of the eleventh transistor T11, the first end of the thirteenth transistor T13 is connected to the output end of the first noise reduction control unit 111 or the output end of the second noise reduction control unit 121, and the second end of the thirteenth transistor T13 is connected to the first low level terminal VSS1.

[0063] It should be noted that the addition of the thirteenth transistor makes the pull-down of the output ends of the first noise reduction control unit and the second noise reduction control unit ( Figure 9 the nodes P1n, P2n in) not limited to the second transistor, and in the reverse correction process, the thirteenth transistor can also complete the pull-down of the nodes P1n, P2n; so that without adopting the circuit structures of the first noise reduction control unit and the second noise reduction control unit shown in this embodiment Figures 6 - 9 the control end of the noise reduction transistor can be pulled down during non-noise reduction operation to realize the reverse correction of the noise reduction transistor.

[0064] In summary, the noise reduction circuit provided in this application, without affecting the pixel charging efficiency, realizes that the noise reduction transistor is in a reverse bias state when not working through the noise reduction execution units of multiple embodiments, so as to cancel the forward bias state of the noise reduction transistor during alternating operation, improves the problem of drift in the threshold voltage of the noise reduction transistor, and avoids abnormal driving of the gate driving circuit due to a decrease in the noise reduction ability.

[0065] In one embodiment, an embodiment of the present application provides a gate driving circuit, which includes N cascaded gate driving modules. The nth gate driving module includes: a pull-up unit, a pull-down unit, an output unit, and a noise reduction circuit. The pull-up unit is respectively connected to the driving output end and the stage transmission output end of the (n - i)th gate driving module; the pull-down unit is connected to the stage transmission output end of the (n + j)th gate driving module, and the pull-down unit is also connected to the pull-up unit through a driving control node; the output unit is respectively connected to the clock signal end and the driving control node; the noise reduction circuit is respectively connected to the driving control node, the driving output end, and the stage transmission output end of the current-stage gate driving module.

[0066] It should be noted that the specific structure of the gate driving module provided in this embodiment is as Figure 1 shown. The working principle of the gate driving module was described above by taking i = 3 and j = 4 as examples, and will not be elaborated here.

[0067] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", "third" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality" means two or more, unless otherwise specifically defined.

[0068] In the description of this specification, the description with reference to terms such as "some embodiments", "exemplarily", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0069] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and the description of the present application shall fall within the scope covered by the patent of the present application.

Claims

1. A noise reduction circuit, characterized in that, Applied to a gate driving circuit, the gate driving circuit includes N cascaded gate driving modules. The nth gate driving module includes at least a driving control node, a driving output terminal, a stage transmission output terminal, and a noise reduction circuit. The noise reduction circuit includes: A first noise reduction module. The first input terminal of the first noise reduction module is connected to a first noise reduction control terminal. The second input terminal of the first noise reduction module is connected to the driving control node. The third input terminal of the first noise reduction module is connected to a second noise reduction control terminal. The output terminal of the first noise reduction module is respectively connected to the driving output terminal, the stage transmission output terminal, and the driving control node, and is used to perform noise reduction processing on the voltages on the driving control node, the driving output terminal, and the stage transmission output terminal under the action of a first noise reduction control signal output by the first noise reduction control terminal and the voltage on the driving control node; and is further used to make the noise reduction transistor in the first noise reduction module in a reverse bias state under the action of a second noise reduction control signal output by the second noise reduction control terminal; A second noise reduction module. The first input terminal of the second noise reduction module is connected to the second noise reduction control terminal. The second input terminal of the second noise reduction module is connected to the driving control node. The third input terminal of the second noise reduction module is connected to the first noise reduction control terminal. The output terminal of the second noise reduction module is respectively connected to the driving output terminal, the stage transmission output terminal, and the driving control node, and is used to perform noise reduction processing on the voltages on the driving control node, the driving output terminal, and the stage transmission output terminal under the action of a second noise reduction control signal output by the second noise reduction control terminal and the voltage on the driving control node; and is further used to make the noise reduction transistor in the second noise reduction module in a reverse bias state under the action of a first noise reduction control signal output by the first noise reduction control terminal; Wherein, the phases of the first noise reduction control signal and the second noise reduction control signal are opposite.

2. The noise reduction circuit according to claim 1, wherein The first noise reduction module includes: A first noise reduction control unit. The first control terminal of the first noise reduction control unit is connected to the first noise reduction control terminal. The second control terminal of the first noise reduction control unit is connected to the driving control node, and is used to output a first noise reduction signal under the action of a first noise reduction control signal output by the first noise reduction control terminal and the voltage on the driving control node; A first noise reduction execution unit. The first control terminal of the first noise reduction execution unit is connected to the output terminal of the first noise reduction control unit. The second control terminal of the first noise reduction execution unit is connected to the second noise reduction control terminal. The output terminal of the first noise reduction execution unit is respectively connected to the driving control node, the driving output terminal, and the stage transmission output terminal, and is used to perform noise reduction processing on the voltages on the driving control node, the driving output terminal, and the stage transmission output terminal according to the first noise reduction signal; and is further used to make the noise reduction transistor in the first noise reduction execution unit in a reverse bias state according to the second noise reduction control signal; The second noise reduction module includes: A second noise reduction control unit, a first control end of the second noise reduction control unit is connected to the second noise reduction control end, a second control end of the second noise reduction control unit is connected to the drive control node, and is configured to output a second noise reduction signal under the action of a first noise reduction control signal output by the second noise reduction control end and a voltage on the drive control node; A second noise reduction execution unit, a first control end of the second noise reduction execution unit is connected to an output end of the second noise reduction control unit, a second control end of the second noise reduction execution unit is connected to the first noise reduction control end, and an output end of the second noise reduction execution unit is respectively connected to the drive control node, the drive output end and the stage transmission output end, and is configured to perform noise reduction processing on voltages on the drive control node, the drive output end and the stage transmission output end according to the second noise reduction signal; and is further configured to make a noise reduction transistor in the second noise reduction execution unit in a reverse bias state according to the first noise reduction control signal.

3. The noise reduction circuit according to claim 2, wherein The first noise reduction execution unit includes: A first execution subunit, a control end of the first execution subunit is connected to an output end of the first noise reduction control unit, and an output end of the first execution subunit is respectively connected to the drive control node, the drive output end and the stage transmission output end, and is configured to perform noise reduction processing on voltages on the drive control node, the drive output end and the stage transmission output end according to the first noise reduction signal; A first correction subunit, a first control end of the first correction subunit is connected to the first noise reduction control end, a second control end of the first correction subunit is connected to the second noise reduction control end, and an output end of the first correction subunit is respectively connected to the first execution subunit, and is configured to output a low level when the first execution subunit performs noise reduction processing, and is further configured to make a noise reduction transistor in the first execution subunit in a reverse bias state according to the second noise reduction control signal when the first execution subunit does not perform noise reduction processing; The second noise reduction execution unit includes: A second execution subunit, a control end of the second execution subunit is connected to an output end of the second noise reduction control unit, and an output end of the second execution subunit is respectively connected to the drive control node, the drive output end and the stage transmission output end, and is configured to perform noise reduction processing on voltages on the drive control node, the drive output end and the stage transmission output end according to the second noise reduction signal; A second correction subunit, a first control end of the second correction subunit is connected to the second noise reduction control end, a second control end of the second correction subunit is connected to the first noise reduction control end, and an output end of the second correction subunit is respectively connected to the second execution subunit, and is configured to output a low level when the second execution subunit performs noise reduction processing, and is further configured to make a noise reduction transistor in the second execution subunit in a reverse bias state according to the first noise reduction control signal when the second execution subunit does not perform noise reduction processing.

4. The noise reduction circuit according to claim 2 or 3, characterized in that The first noise reduction control unit and the second noise reduction control unit include: A first transistor, wherein a control terminal of the first transistor is connected to the first noise reduction control terminal or the second noise reduction control terminal, and a first terminal of the first transistor is connected to the control terminal of the first transistor; A second transistor, wherein a control terminal of the second transistor is connected to a second terminal of the first transistor, and a first terminal of the second transistor is connected to the first terminal of the first transistor; A third transistor, wherein a control terminal of the third transistor is connected to the drive control node, a first terminal of the third transistor is connected to the second terminal of the first transistor, and a second terminal of the third transistor is connected to a first low level terminal; A fourth transistor, wherein a control terminal of the fourth transistor is connected to the control terminal of the third transistor, a first terminal of the fourth transistor is connected to a second terminal of the second transistor, and a second terminal of the fourth transistor is connected to the first low level terminal.

5. The noise reduction circuit according to claim 2, wherein The first noise reduction execution unit and the second noise reduction execution unit include: A fifth transistor, wherein a control terminal of the fifth transistor is connected to an output terminal of the first noise reduction control unit or an output terminal of the second noise reduction control unit, a first terminal of the fifth transistor is connected to the stage transmission output terminal, and a second terminal of the fifth transistor is connected to the second noise reduction control terminal or the first noise reduction control terminal; A sixth transistor, wherein a control terminal of the sixth transistor is connected to the control terminal of the fifth transistor, a first terminal of the sixth transistor is connected to the drive control node, and a second terminal of the sixth transistor is connected to the second noise reduction control terminal or the first noise reduction control terminal; A seventh transistor, wherein a control terminal of the seventh transistor is connected to the control terminal of the fifth transistor, a first terminal of the seventh transistor is connected to the drive output terminal, and a second terminal of the seventh transistor is connected to the second noise reduction control terminal or the first noise reduction control terminal; Wherein, the fifth transistor, the sixth transistor and the seventh transistor are respectively used as noise reduction transistors in the first noise reduction module and the second noise reduction module.

6. The noise reduction circuit according to claim 3, wherein, The first execution sub-unit and the second execution sub-unit include: A fifth transistor, wherein a control terminal of the fifth transistor is connected to an output terminal of the first noise reduction control unit or an output terminal of the second noise reduction control unit, a first terminal of the fifth transistor is connected to the stage transmission output terminal, and a second terminal of the fifth transistor is connected to an output terminal of the first correction sub-unit or an output terminal of the second correction sub-unit; A sixth transistor, wherein a control terminal of the sixth transistor is connected to the control terminal of the fifth transistor, a first terminal of the sixth transistor is connected to the drive control node, and a second terminal of the sixth transistor is connected to an output terminal of the first correction sub-unit or an output terminal of the second correction sub-unit; A seventh transistor, wherein a control terminal of the seventh transistor is connected to the control terminal of the fifth transistor, a first terminal of the seventh transistor is connected to the drive output terminal, and a second terminal of the seventh transistor is connected to an output terminal of the first correction sub-unit or an output terminal of the second correction sub-unit; Among them, the fifth transistor, the sixth transistor, and the seventh transistor are respectively used as noise reduction transistors in the first noise reduction module and the second noise reduction module.

7. The noise reduction circuit according to claim 6, wherein The first correction subunit and the second correction subunit include: An eighth transistor, the control terminal of the eighth transistor is connected to the first noise reduction control terminal or the second noise reduction control terminal, the first terminal of the eighth transistor is connected to the second terminal of the fifth transistor, and the second terminal of the eighth transistor is connected to a first low level terminal; A ninth transistor, the control terminal of the ninth transistor is connected to the control terminal of the eighth transistor, the first terminal of the ninth transistor is connected to the second terminal of the sixth transistor, and the second terminal of the ninth transistor is connected to the first low level terminal; A tenth transistor, the control terminal of the tenth transistor is connected to the control terminal of the eighth transistor, the first terminal of the tenth transistor is connected to the second terminal of the seventh transistor, and the second terminal of the tenth transistor is connected to the first low level terminal; An eleventh transistor, the control terminal of the eleventh transistor is connected to the second noise reduction control terminal or the first noise reduction control terminal, the first terminal of the eleventh transistor is connected to the control terminal of the eleventh transistor, and the second terminal of the eleventh transistor is respectively connected to the first terminal of the eighth transistor, the first terminal of the ninth transistor, and the second terminal of the tenth transistor.

8. The noise reduction circuit according to claim 6, wherein The first correction subunit and the second correction subunit include: An eighth transistor, the control terminal of the eighth transistor is connected to the first noise reduction control terminal or the second noise reduction control terminal, the first terminal of the eighth transistor is connected to the second terminal of the fifth transistor, and the second terminal of the eighth transistor is connected to a first low level terminal; A ninth transistor, the control terminal of the ninth transistor is connected to the control terminal of the eighth transistor, the first terminal of the ninth transistor is connected to the second terminal of the sixth transistor, and the second terminal of the ninth transistor is connected to the first low level terminal; A tenth transistor, the control terminal of the tenth transistor is connected to the control terminal of the eighth transistor, the first terminal of the tenth transistor is connected to the second terminal of the seventh transistor, and the second terminal of the tenth transistor is connected to a second low level terminal; An eleventh transistor, the control terminal of the eleventh transistor is connected to the second noise reduction control terminal or the first noise reduction control terminal, the first terminal of the eleventh transistor is connected to the control terminal of the eleventh transistor, and the second terminal of the eleventh transistor is respectively connected to the first terminal of the eighth transistor and the first terminal of the ninth transistor; A twelfth transistor, the control terminal of the twelfth transistor is connected to the control terminal of the eleventh transistor, the first terminal of the twelfth transistor is connected to the control terminal of the twelfth transistor, and the second terminal of the twelfth transistor is connected to the first terminal of the tenth transistor.

9. The noise reduction circuit according to claim 7 or 8, characterized in that, The first correction subunit and the second correction subunit further include: The thirteenth transistor, the control terminal of the thirteenth transistor is connected to the control terminal of the eleventh transistor, the first terminal of the thirteenth transistor is connected to the output terminal of the first noise reduction control unit or the output terminal of the second noise reduction control unit, and the second terminal of the thirteenth transistor is connected to the first low level terminal.

10. A gate driving circuit includes N cascaded gate driving modules, characterized in that, The nth-stage gate driving module includes: A pull-up unit, the pull-up unit is respectively connected to the driving output terminal of the (n-i)th-stage gate driving module and the stage transmission output terminal of the (n-i)th-stage gate driving module; A pull-down unit, the pull-down unit is connected to the stage transmission output terminal of the (n+j)th-stage gate driving module, and the pull-down unit is further connected to the pull-up unit through a driving control node; An output unit, the output unit is respectively connected to the clock signal terminal and the driving control node; The noise reduction circuit according to any one of claims 1-9, the noise reduction circuit is respectively connected to the driving control node, the driving output terminal and the stage transmission output terminal of the current-stage gate driving module.

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