Shortest routing and deadlock avoiding method and device for double-layer polygon topology

By setting up anti-deadlock nodes and cache queues in the double-layer polygon topology, combining the XOR processing and routing type of the label sequence, the problem of reducing the number of shortest paths and deadlock risks is solved, and network transmission efficiency and reliability are improved.

CN120358187AActive Publication Date: 2025-07-22SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
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Patent Information

Application Number
CN202510847342.5
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-06-24
Publication Date
2025-07-22
Estimated Expiration
2045-06-24

AI Technical Summary

Technical Problem

In the prior art, the number of shortest paths in a computer network is reduced, resulting in a decrease in system transmission efficiency and a risk of loop deadlock, which may lead to network paralysis.

Method used

By setting up deadlock nodes in a double-layer polygon topology and using a cache queue, combining the XOR processing of the label sequence of the source node and the target node and determining the routing type, the candidate node of the shortest path generates a routing vector to avoid deadlocks and increase the path selection dimension.

Benefits of technology

The shortest number of paths between nodes in the computer network is improved, the system transmission efficiency and data throughput are enhanced, deadlocks are avoided, and the network reliability and load balancing capabilities are improved.

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Abstract

The invention relates to the technical field of computer networks, in particular to a shortest routing and deadlock avoiding method and device for a double-layer polygon topology, and the method comprises the steps: determining the routing type of the topology; xOR processing is carried out on the mark low bits of the source node and the target node, and a candidate node corresponding to the shortest path of the source node is determined; determining an available state of the anti-deadlock node, if the available state is idle, determining routing bypass information, and sending the routing bypass information to the source node; and determining an available state of the common node, and generating a route selection vector of the candidate node, so that the source node determines a next-hop node according to the route selection vector, sends the data packet to the next-hop node, and takes the next-hop node as a new source node. According to the method provided by the embodiment of the invention, the number of the shortest paths is expanded into all theoretical shortest paths, so that the number of the shortest paths among the nodes in the computer network topology structure is increased, the system transmission efficiency and the data throughput are improved, and meanwhile, deadlock is avoided.
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Citation Information

Patent Citations

  • Route selection method and device in wireless ad hoc network

    CN110300426A

  • Computer network communication method, computer equipment, storage medium and program product

    CN118890306A

  • Node coding method of double-loop topology and routing method based on double-loop topology

    CN119052100A

  • High Performance LFA Path Algorithms

    US20150103671A1

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