Single-cycle multi-data packet verification and retransmission method, electronic device, and medium

Abstract

The present invention relates to the field of communication technology, and in particular to a single-cycle multi-data packet verification and retransmission method, electronic device, and medium. The method can perform parallel verification of data packets to be transmitted, and the verification process of each data packet to be transmitted has no mutual constraints. The logical operation is simple, which greatly reduces the time overhead of the logical operation and reduces the delay of single-cycle multi-data packet verification and retransmission. In addition, compared with the traditional verification method, the data verification method of the present invention does not require additional storage space, and provides the possibility for high-frequency, high-bandwidth, low-power, and small-area data transmission operation circuits. Compared with the traditional operation method, the present invention has small structural changes and simple integration, can effectively improve the operation efficiency of the communication system, and reduce data transmission delay. The larger the data bandwidth and the more data packets are transmitted in a single clock cycle, the more obvious the performance improvement. The present invention reduces the power consumption and area of ​​the verification and retransmission circuit, and improves the performance of the communication system.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a single-cycle multi-data packet verification and retransmission method, electronic equipment, and medium. Background Art

[0002] In communication systems, signal distortion and non-isochronous delays occur during channel transmission, causing the actual received signal to differ from the originally transmitted signal, resulting in bit errors. To mitigate the impact of channel nonlinearities and minimize bit error rates, parity-and-retransmission technology is widely used. Existing technologies implement data parity and retransmission by checking packet header information and parity bits, significantly improving data transmission accuracy. However, with the development of technologies such as artificial intelligence, 5G, and blockchain, the demand for high bandwidth throughput is increasing, leading to significant adjustments in the operating mode of differential signal pairs (lanes) used for data transmission. The widespread adoption of high frequencies, multiple physical connections, and multi-lane operation has led to a proportional increase in the amount of data processed by communication systems per cycle, making the transmission of multiple data packets per cycle a common practice.

[0003] However, facing the explosive growth of data, traditional serial data verification methods are becoming unsustainable. Multi-packet serial verification not only increases signal transmission delay but also increases manufacturing complexity for complex circuit structures. The multi-packet verification and retransmission mechanism has become a significant constraint on system performance. Existing packet verification methods can quickly generate the expected sequence code for a single packet in a single cycle, verify the data in the receiving path, and respond to retransmissions. However, for multiple packets in a single cycle, the verification process for each subsequent packet is closely dependent on the verification result of the previous packet, increasing the logic operation time and depth. The greater the number of packets processed in a single cycle, the greater the data transmission delay. This makes the technical barriers to high-frequency applications difficult to overcome. The complex data verification structure also increases manufacturing complexity, hindering the development of low-power, high-frequency, and small-area communication systems. Therefore, reducing the delay of single-cycle multi-packet verification and retransmission, reducing the power consumption and area of ​​the verification and retransmission circuitry, and improving the performance of communication systems have become urgent technical challenges. Summary of the Invention

[0004] The purpose of the present invention is to provide a single-cycle multi-data packet verification and retransmission method, electronic equipment and medium, which reduces the delay of single-cycle multi-data packet verification and retransmission, reduces the power consumption and area of ​​the verification and retransmission circuit, and improves the performance of the communication system.

[0005] According to a first aspect of the present invention, a single-cycle multi-data packet verification and retransmission method is provided, comprising:

[0006] Step S1: The receiving path obtains the data packet information to be transmitted in the i-th clock cycle. i ,A2 i ,...,A n i ,...,A N i}, where A n i The information corresponding to the nth data packet to be transmitted in the i-th clock cycle, where n ranges from 1 to N, and N is the total number of data packets to be transmitted in one clock cycle, i=1,2,..., if the sending path receives the retransmission starting point sequence code R generated in the i-1th clock cycle i-1 , then A1 i The first expected sequence is coded as R i-1 +1 for the data packet to be transmitted, otherwise, A1 i A N i-1 The next data packet to be transmitted;

[0007] A n i ={P n i ,Q n i ,C n i ,D n i}, P n i A n i The corresponding expected order code, Q n i A n i The corresponding actual sequence code, C n i A n i Corresponding CRC check information, D n i A n i Corresponding load information;

[0008] Step S2, parallel based on each C n i Perform CRC check and generate each C n i Corresponding CRC check result CRC n i , if all CRC n i If both are passed, go to step S3; otherwise, go to step S4;

[0009] Step S3, compare each group P in parallel n i and Q n i Perform sequence code verification. If all are consistent, go to step S5. Otherwise, if the receiving path transmission mode is the full transmission mode, go to step S4.

[0010] Step S4: If the receiving path transmission mode is the full transmission mode, generate the retransmission starting point sequence code R i =P i-1 , R i Send a retransmission request to the sending end, discard all the data packets to be transmitted obtained in the current clock cycle, and execute step S6;

[0011] Step S5: D with a payload in the data packet to be transmitted received in the i-th clock cycle n i All are transmitted to the receiving end, and step S6 is executed;

[0012] Step S6: Set i=i+1 and return to step S1.

[0013] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0014] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0015] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above-described technical solution, the present invention provides a single-cycle multi-data packet check-and-retransmission method, electronic device, and medium that achieve considerable technological advancement and practicality, and possesses wide industrial application value, with at least the following beneficial effects:

[0016] The present invention can perform parallel verification of data packets to be transmitted. The verification process of each data packet to be transmitted has no mutual constraints, the logical operation is simple, the time overhead of the logical operation is greatly reduced, and the delay of single-cycle multi-data packet verification and retransmission is reduced. In addition, compared with the traditional verification method, the data verification method of the present invention does not require additional storage space, which provides the possibility for high-frequency, high-bandwidth, low-power, and small-area data transmission operation circuits. Compared with the traditional operation method, the present invention has a small structural change and is simple to integrate. It can effectively improve the operation efficiency of the communication system and reduce data transmission delay. The larger the data bandwidth and the more data packets are transmitted in a single clock cycle, the more obvious the performance improvement. The present invention reduces the power consumption and area of ​​the verification and retransmission circuit, and improves the performance of the communication system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 This is a flow chart of a single-cycle multi-data packet verification and retransmission method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0020] The embodiment of the present invention provides a single-cycle multi-data packet verification and retransmission method, such as Figure 1 As shown, including:

[0021] Step S1: The receiving path obtains the data packet information to be transmitted in the i-th clock cycle. i ,A2 i ,...,A n i ,...,A N i}, where A n i The information corresponding to the nth data packet to be transmitted in the i-th clock cycle, where n ranges from 1 to N, and N is the total number of data packets to be transmitted in one clock cycle, i=1,2,..., if the sending path receives the retransmission starting point sequence code R generated in the i-1th clock cyclei-1 , then A1 i The first expected sequence is coded as R i-1 +1 for the data packet to be transmitted, otherwise, A1 i A N i-1 The next data packet to be transmitted. n i ={P n i ,Q n i ,C n i ,D n i}, P n i A n i The corresponding expected order code, Q n i A n i The corresponding actual sequence code, C n i A n i Corresponding CRC check information, D n i A n i For the corresponding payload information, the expected sequence code is the expected sequence code of the data packets with effective payload to be transmitted, and the actual sequence code is the actual sequence code of the data packets with effective payload to be transmitted.

[0022] It should be noted that if the sending path receives the retransmission starting point sequence code R generated in the i-1th clock cycle i -1 , it means that in the i-th clock cycle, some or all of the data packets that were successfully transmitted in the i-1th clock cycle need to be retransmitted. i-1 It corresponds to the expected sequence encoding of the last successfully transmitted data packet in the i-1th clock cycle, so it is directly encoded from the first expected sequence to R i-1 +1 to be transmitted data packet information can be started. It should be noted that there may or may not be a payload in the transmission data packet. The expected sequence code is the expected sequence code of the data packet to be transmitted with a payload. It means that only when there is a payload in the data packet to be transmitted will the expected sequence code be updated according to the coding order. The expected sequence code is the standard sequence code. If the actual sequence code is consistent with the expected sequence code, there is no problem. If it is inconsistent, it means that there is a problem, resulting in verification failure.

[0023] If the sending path receives the retransmission starting point sequence code R generated in the i-1th clock cycle i-1 , then A1 i The first expected sequence is coded as R i-1 +1 data packet information to be transmitted refers to A1 i The expected sequence of the first occurrence in cycle i is coded as R i-1 +1 information about the data packets to be transmitted.

[0024] Step S2, parallel based on each C n i Perform CRC check and generate each C n i Corresponding CRC check result CRC n i , if all CRC n i If both are passed, go to step S3; otherwise, go to step S4.

[0025] It's important to note that the CRC check process for each data packet has no constraints on each other, resulting in simple logical operations and significantly reduced time overhead. Cyclic Redundancy Check (CRC) is a commonly used data verification technique that generates a check value (a CRC code) by performing polynomial operations on the data. This is used to detect errors (such as bit flips, loss, or tampering) during data transmission or storage. This section will not be further discussed.

[0026] Step S3, compare each group P in parallel n i and Q n i Perform sequence code verification. If all are consistent, execute step S5. Otherwise, if the receiving path transmission mode is the full transmission mode, execute step S4.

[0027] It should be noted that the sequential coding verification process of each data packet has no mutual constraints, the logical operation is simple, and the time overhead of the logical operation is greatly reduced.

[0028] Step S4: If the receiving path transmission mode is the full transmission mode, generate the retransmission starting point sequence code R i =P i-1 , R i Send a retransmission request to the sending end, discard all data packets to be transmitted obtained in the current clock cycle, and execute step S6.

[0029] It should be noted that the all - transmission mode means that the receiving path needs to receive all the data packets to be transmitted in the current clock cycle, and when all the data packets to be transmitted pass the verification, all the data packets to be transmitted in the current clock cycle are transmitted to the receiving end. However, it can be understood that only the data packets to be transmitted with valid payloads need to be transmitted. If there are data packets that fail the verification in the current clock cycle, all the data packets to be transmitted in the current clock cycle need to be re - transmitted. Therefore, when re - transmission is required, the receiving path needs to discard all the data packets to be transmitted obtained in the current clock cycle.

[0030] Step S5: Transmit all the D with valid payloads in the data packets to be transmitted received in the i - th clock cycle n i to the receiving end, and execute Step S6.

[0031] Step S6: Set i = i + 1, and return to Step S1.

[0032] As an embodiment, in Step S2, if there is a non - passing CRC n i , and the transmission mode of the receiving path is the partial - transmission mode, then execute Step S10.

[0033] It should be noted that the transmission mode being the partial - transmission mode means that some of the data packets to be transmitted in the current cycle can be transmitted to the receiving end.

[0034] Step S10: Set the CRC error code AE to the expected sequence code corresponding to the first data packet with a CRC verification error in the i - th clock cycle, and execute Step S3. AE is set to be empty in the initial state. [[ID=…]] [[ID=…]]

[0035] In Step S3, when each group of P n i and Q n i are not completely consistent, and the transmission mode of the receiving path is the partial - transmission mode, then execute Step S20.

[0036] Step S20: Set the encoding order error code BE to the expected sequence code corresponding to the first data packet where C n i and D n i are inconsistent, and execute Step S30. BE is set to be empty in the initial state.

[0037] Step S30: If AE is empty, or AE and BE are both not empty and AE≥BE, then execute Step S40. If BE is empty, or AE and BE are both not empty and AE < BE, then execute Step S50.

[0038] Step S40: Determine the data packet to be transmitted with inconsistent P n i and Q n i in the first occurrence in the i-th clock cycle as the target data packet. If the target data packet has a payload, set R i = BE - 1; otherwise, generate R i = BE, and send R i to the sender to request retransmission, set AE and BE to be empty, and execute Step S60.

[0039] It should be noted that when AE is empty, it means that only the sequential coding check fails. Determine the data packet to be transmitted with inconsistent P n i and Q n i in the first occurrence in the i-th clock cycle as the target data packet. If both AE and BE are not empty and AE ≥ BE, it means that the earliest check failure is the sequential coding check. If the target data packet has a payload, the expected sequential coding of the data packet finally transmitted to the receiver in the current cycle is BE - 1, so set R i = BE - 1. If the target data packet does not have a payload, the expected sequential coding of the data packet finally transmitted to the receiver in the current cycle is BE, so set R i = BE. The above setting method can ensure that R i is the expected sequential coding of the data packet finally transmitted to the receiver in the current cycle, and set AE and BE to be empty for use in the next clock cycle.

[0040] Step S50: Determine the data packet to be transmitted with CRC check error in the first occurrence in the i-th clock cycle as the target data packet. If the target data packet has a payload, set R i = AE - 1; otherwise, generate R i = AE, and send R i to the sender to request retransmission, set AE and BE to be empty, and execute Step S60.

[0041] It should be noted that when BE is empty, it means that only the CRC check fails. Determine the data packet to be transmitted with CRC check error in the first occurrence in the i-th clock cycle as the target data packet. If both AE and BE are not empty and AE < BE, it means that the earliest check failure is the CRC check. If the target data packet has a payload, the expected sequential coding of the data packet finally transmitted to the receiver in the current cycle is AE - 1, so set R i = AE - 1. If the target data packet does not have a payload, the expected sequential coding of the data packet finally transmitted to the receiver in the current cycle is AE, so set Ri =AEE, the above setting method can ensure R i Encode the expected sequence of the last data packet transmitted to the receiver in the current cycle, and set AE and BE to empty for use in the next clock cycle.

[0042] Step S60: transmit the data packet with payload to be transmitted before the target data packet in the i-th clock cycle to the receiving end, discard the target data packet in the i-th clock cycle and the data packet to be transmitted after the target data packet, and execute step S6.

[0043] As an embodiment, step S5 includes:

[0044] Step S51: record the expected sequence code P of the last data packet sent to the receiving end in the i-th clock cycle. i .

[0045] As an embodiment, step S60 includes:

[0046] Step S601: Record the expected sequence code P of the last data packet sent to the receiving end in the i-th clock cycle. i .

[0047] As an embodiment, step S1 includes:

[0048] Step S11: Obtain the statistical number U of the payload corresponding to the nth data packet to be transmitted in the i-th clock cycle n i , actual sequence code Q n i , CRC check information C n i and load information D n i , and the expected sequence code P of the last data packet sent to the receiver in the i-1th clock cycle i-1 , when i=1, P i-1 =0.

[0049] Assume N=5, and the payload information of the five packets to be transmitted in the i-th clock cycle are D1 i Empty, D2 i Is not empty, D3 i Is not empty, D4 i Empty, D5 i is non-empty, D n i Empty means there is no payload, D n i If it is not empty, it means there is a payload. Then the number of payload statistics corresponding to the 5 data packets to be transmitted in the i-th clock cycle is U1i 、U2 i 、U3 i 、U4 i 、U5 i They are 0, 1, 2, 2, and 3 respectively.

[0050] Step S12: Based on P i-1 and U n i Determine P n i :

[0051] P n i =P i-1 +U n i ;

[0052] Still with N=5, U1 i 、U2 i 、U3 i 、U4 i 、U5 i Assume that P is 0, 1, 2, 2, and 3 respectively. i-1 =10, then P1 i 、P2 i 、P3 i 、P4 i 、P5 i They are 10, 11, 12, 12, and 13 respectively.

[0053] Step S13: Based on the P corresponding to the nth data packet to be transmitted in the i-th clock cycle n i , Q n i 、C n i 、D n i Generate A n i , based on all A n i Generate i ,A2 i ,...,A n i ,...,A N i}.

[0054] As an embodiment, step S2 includes:

[0055] Step S21, parallel based on each C n i Perform CRC check, if the check passes, then C ni Corresponding CRC check result CRC n i Set to 0, if the check fails, the CRC n i Set to 1.

[0056] Step S22: All CRC n i If the result of the sum is 0, all CRC n i If both are passed, execute step S3; if the result of the sum is 1, execute step S4.

[0057] As an embodiment, step S3 includes:

[0058] Step S31: Parallel comparison of each group P n i and Q n i Perform sequential coding verification, if P n i and Q n i If they are consistent, set the corresponding sequence code verification result L n i If the check fails, L n i Set to 1.

[0059] Step S32: All L n i If the result of the AND operation is 0, all sequential coding checks are passed, and step S5 is executed. If the result of the AND operation is 1, and the receiving path transmission mode is the full transmission mode, step S4 is executed.

[0060] As an embodiment, the method further includes:

[0061] Step S100: If N×W≤B, the preset mode identification register is configured to a first value, indicating that the receiving path transmission mode is set to the full transmission mode, W is the bit width of a single data packet to be transmitted, and B is the data bit width of a single cycle receiving path.

[0062] Step S200: If N×W>B, the preset mode identification register is configured to a second value, indicating that the transmission mode of the receiving path is set to the partial transmission mode.

[0063] Specifically, the first value can be set to 0, and the second value can be set to 1. Through the settings of steps S100 to S200, in the above steps, when it is necessary to determine the transmission mode of the receiving path, the value in the preset mode identification register can be directly read. If the first value is read from the preset mode identification register, it indicates that the transmission mode of the receiving path is set to the full transmission mode. If the second value is read from the preset mode identification register, it indicates that the transmission mode of the receiving path is set to the partial transmission mode.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0065] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0066] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0067] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0068] The embodiment of the present invention can perform parallel verification of data packets to be transmitted. The verification process of each data packet to be transmitted has no mutual constraints, the logical operation is simple, the time overhead of the logical operation is greatly reduced, and the delay of single-cycle multi-data packet verification and retransmission is reduced. In addition, compared with the traditional verification method, the data verification method of the present invention does not require additional storage space, which provides the possibility for high-frequency, high-bandwidth, low-power, and small-area data transmission operation circuits. Compared with the traditional operation method, the present invention has small structural changes and simple integration, can effectively improve the operation efficiency of the communication system, and reduce data transmission delay. The larger the data bandwidth and the more data packets are transmitted in a single clock cycle, the more obvious the performance improvement. The present invention reduces the power consumption and area of ​​the verification and retransmission circuit, and improves the performance of the communication system. In addition, the parallel data packet verification method in the embodiment of the present invention is flexible and changeable, easy to connect with the traditional verification and retransmission communication module, and has strong applicability.

[0069] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A single-cycle multi-data packet verification and retransmission method, characterized in that: Including: Step S1: The receiving path obtains the data packet information to be transmitted in the i-th clock cycle. i ,A2 i ,...,A n i ,...,A N i }, where A n i The information corresponding to the nth data packet to be transmitted in the i-th clock cycle, where n ranges from 1 to N, and N is the total number of data packets to be transmitted in one clock cycle, i=1,2,..., if the sending path receives the retransmission starting point sequence code R generated in the i-1th clock cycle i-1 , then A1 i The first expected sequence is coded as R i-1 +1 for the data packet to be transmitted, otherwise, A1 i A N i-1 The next data packet to be transmitted; A n i ={P n i ,Q n i ,C n i ,D n i }, P n i A n i The corresponding expected order code, Q n i A n i The corresponding actual sequence code, C n i A n i Corresponding CRC check information, D n i A n i Corresponding load information; Step S2, parallel based on each C n i Perform CRC check and generate each C n i Corresponding CRC check result CRC n i , if all CRC n i If both are passed, go to step S3; otherwise, go to step S4; Step S3, compare each group P in parallel n i and Q n i Perform sequence code verification. If all are consistent, go to step S5. Otherwise, if the receiving path transmission mode is the full transmission mode, go to step S4. Step S4: If the receiving path transmission mode is the full transmission mode, generate the retransmission starting point sequence code R i =P i-1 , R i Send a retransmission request to the sending end, discard all the data packets to be transmitted obtained in the current clock cycle, and execute step S6; Step S5: D with a payload in the data packet to be transmitted received in the i-th clock cycle n i All are transmitted to the receiving end, and step S6 is executed; Step S6: Set i = i + 1, and return to Step S1.

2. The method according to claim 1, wherein: In step S2, if there is a CRC that does not pass n i , and the receiving path transmission mode is the partial transmission mode, then execute step S10; Step S10: Set the CRC error code AE to the expected sequence code corresponding to the data packet with the first CRC check error in the i-th clock cycle, and execute Step S3. AE is set to be empty in the initial state. In step S3, when each group P n i and Q n i If the transmission mode of the receiving path is not completely consistent and the receiving path transmission mode is a partial transmission mode, step S20 is executed; Step S20: Set the code BE with the wrong coding sequence to the first code P in the i-th clock cycle. n i and Q n i For the expected sequence codes corresponding to the inconsistent data packets, step S30 is executed, and the BE is initially set to be empty; Step S30: If AE is empty, or AE and BE are both not empty and AE ≥ BE, then execute Step S40. If BE is empty, or AE and BE are both not empty and AE < BE, then execute Step S50. Step S40: The first occurrence of P in the i-th clock cycle n i and Q n i The inconsistent data packet to be transmitted is determined as the target data packet. If the target data packet has a payload, R is set. i =BE-1, otherwise, generate R i =BE, R i Send to the sending end to request retransmission, set AE and BE to empty, and execute step S60; Step S50: The first data packet to be transmitted that has a CRC check error in the i-th clock cycle is determined as the target data packet. If the target data packet has a payload, set R i =AE-1, otherwise, generate R i =AE, R i Send to the sending end to request retransmission, set AE and BE to empty, and execute step S60; Step S60: Transmit the data packets to be transmitted with payloads before the target data packet in the i-th clock cycle to the receiving end, discard the target data packet and the data packets to be transmitted after the target data packet in the i-th clock cycle, and execute Step S6.

3. The method according to claim 1, wherein: The said Step S5 includes: Step S51: record the expected sequence code P of the last data packet sent to the receiving end in the i-th clock cycle. i .

4. The method according to claim 2, wherein: The said Step S60 includes: Step S601: Record the expected sequence code P of the last data packet sent to the receiving end in the i-th clock cycle. i .

5. The method according to claim 3 or 4, wherein: The said Step S1 includes: Step S11: Obtain the statistical number U of the payload corresponding to the nth data packet to be transmitted in the i-th clock cycle n i , actual sequence code Q n i , CRC check information C n i and load information D n i , and the expected sequence code P of the last data packet sent to the receiver in the i-1th clock cycle i-1 , when i=1, P i-1 =0; Step S12: Based on P i-1 and U n i Determine P n i : Q n i =P i-1 +U n i ; Step S13: Based on the P corresponding to the nth data packet to be transmitted in the i-th clock cycle n i , Q n i 、C n i 、D n i Generate A n i , based on all A n i Generate i ,A2 i ,...,A n i ,...,A N i }.

6. The method according to claim 1, wherein: The said Step S2 includes: Step S21, parallel based on each C n i Perform CRC check, if the check passes, then C n i Corresponding CRC check result CRC n i Set to 0, if the check fails, the CRC n i Set to 1; Step S22: All CRC n i If the result of the sum is 0, all CRC n i If both are passed, execute step S3; if the result of the sum is 1, execute step S4.

7. The method according to claim 1, wherein: The said Step S3 includes: Step S31: Parallel comparison of each group P n i and Q n i Perform sequential coding verification, if P n i and Q n i If they are consistent, set the corresponding sequence code verification result L n i If the check fails, L n i Set to 1; Step S32: All L n i If the result of the AND operation is 0, all sequential coding checks are passed, and step S5 is executed. If the result of the AND operation is 1, and the receiving path transmission mode is the full transmission mode, step S4 is executed.

8. The method according to claim 1, wherein: The said method further includes: Step S100: If N × W ≤ B, then configure the preset mode identification register to a first value, indicating that the receiving path transmission mode is set to the all-transmission mode, where W is the bit width of a single data packet to be transmitted, and B is the data bit width of the receiving path in a single cycle. Step S200: If N × W > B, then configure the preset mode identification register to a second value, indicating that the receiving path transmission mode is set to the partial-transmission mode.

9. An electronic device, characterized in that: Including: At least one processor; And a memory communicatively connected to the at least one processor; Wherein, the memory stores instructions executed by the at least one processor, and the instructions are set to execute the method according to any one of the foregoing claims 1-8.

10. A computer-readable storage medium, characterized in that Stores computer-executable instructions for executing the method according to any one of the foregoing claims 1-8.

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