Printed circuit board and intelligent robot domain brain with body

Abstract

The embodiment of the invention provides a printed circuit board and an intelligent robot brain with a body, and relates to the technical field of printed circuits. The printed circuit board is applied to the domain brain of the intelligent robot with the body, the printed circuit board comprises two independent printed circuit boards, namely a brain board and a cerebellum board, the brain board is used for bearing a graphics processing unit (GPU), the cerebellum board is used for bearing a central processing unit (CPU), and the brain board and the cerebellum board are electrically connected through a board-to-board connector in a plug-in mode. The printed circuit board has relatively high signal integrity, and can meet the requirements of a brain of an intelligent robot with a body.

Description

Technical Field

[0001] The present application relates to the field of printed circuit technology, and in particular to a printed circuit board and an embodied intelligent robot domain brain. Background Art

[0002] Embodied intelligent robots generally refer to intelligent robots with physical form and the ability to interact with their environment. These robots not only rely on computation and algorithms to process information but also interact with the external environment through sensors, enabling them to perform complex and dynamic tasks. The embodied intelligent robot domain brain can be understood as the domain controller of the embodied intelligent robot, responsible for managing and controlling the embodied intelligent robot's actions.

[0003] The domain brain of an embodied intelligent robot typically consists of hardware and software. The hardware serves as the material foundation for the software, which is used to implement pre-defined calculations and algorithms. The hardware typically includes multiple electronic components and the printed circuit board (PCB) that supports them.

[0004] Because embodied intelligent robots need to process large amounts of multi-source information from their environment, their domain brains must be able to process data at high speeds. This requires the printed circuit boards (PCBs) of these robots to have high signal integrity to support this high-speed processing. However, existing PCBs for embodied intelligent robots' domain brains have structural flaws and low signal integrity, failing to meet the requirements of embodied intelligent robots. Summary of the Invention

[0005] The embodiments of the present application provide a printed circuit board and an embodied intelligent robot domain brain. The printed circuit board has high signal integrity and can meet the needs of the embodied intelligent robot.

[0006] In the first aspect, an embodiment of the present application provides a printed circuit board, which is applied to the domain brain of an embodied intelligent robot. The printed circuit board includes two independent printed circuit boards, namely a brain board and a cerebellum board. The brain board is used to carry a graphics processing unit GPU, and the cerebellum board is used to carry a central processing unit CPU. The brain board and the cerebellum board are electrically connected by plugging a board-to-board connector.

[0007] In one possible embodiment, the brain board includes multiple conductive layers, which include at least one low-speed signal layer, at least one high-speed signal layer, at least one power supply layer and at least one ground layer. The high-speed signal layer is a signal layer whose signal transmission rate is greater than the signal transmission rate of the low-speed signal layer. The multiple conductive layers are stacked to form a large brain board stack; at least one power supply layer is stacked on the inner core of the large brain board stack and ground layers are stacked on both sides thereof to form the first inner core layer of the large brain board stack; first transmission layers are stacked on both sides of the first inner core layer, and any first transmission layer includes at least one high-speed signal layer and at least one ground layer stacked at intervals; the low-speed signal layer is stacked on the outside of the first transmission layer to form the first outer layer of the large brain board stack.

[0008] In one possible embodiment, the brain board includes twelve conductive layers, and the two first outer layers of the brain board stack are the first top layer and the first bottom layer respectively; the conductive layers from the first top layer to the first bottom layer are the 1st layer to the 12th layer of the brain board stack, including: the 1st layer low-speed signal layer, the 2nd layer ground layer, the 3rd layer high-speed signal layer, the 4th layer ground layer, the 5th layer high-speed signal layer, the 6th layer ground layer, the 7th layer power layer, the 8th layer power layer, the 9th layer ground layer, the 10th layer high-speed signal layer, the 11th layer ground layer and the 12th layer low-speed signal layer.

[0009] In one possible embodiment, the cerebellum board includes multiple conductive layers, which are stacked to form a cerebellum board stack; at least one power supply layer is stacked on the inner core of the cerebellum board stack and ground layers are stacked on both sides to form the second inner core layer of the cerebellum board stack; second transmission layers are stacked on both sides of the second inner core layer, and any second transmission layer includes at least one high-speed signal layer and at least one ground layer stacked at intervals; a low-speed signal layer is stacked on the outside of the second transmission layer to form the second outer layer of the cerebellum board stack.

[0010] In one possible embodiment, the cerebellum board includes twelve conductive layers, and the two second outer layers of the cerebellum board stack are the second top layer and the second bottom layer respectively; the conductive layers from the second top layer to the second bottom layer are the 1st layer to the 12th layer of the cerebral board stack respectively, including: the 1st layer low-speed signal layer, the 2nd layer ground layer, the 3rd layer high-speed signal layer, the 4th layer ground layer, the 5th layer high-speed signal layer, the 6th layer ground layer, the 7th layer power supply layer, the 8th layer power supply layer, the 9th layer ground layer, the 10th layer high-speed signal layer, the 11th layer ground layer and the 12th layer low-speed signal layer.

[0011] In a possible implementation, for at least one high-speed signal layer in the cerebral board stack and / or the cerebellum board stack, vias are formed in the at least one high-speed signal layer using a skip hole method.

[0012] In one possible embodiment, at least one conductive layer uses reverse-processed copper foil; and / or at least one of the first outer layer and the second outer layer is covered with a solder resist layer formed by R500 Z28DF solder resist ink.

[0013] In a possible implementation, at least one insulating layer is stacked between any two conductive layers. The insulating layer is used to support and insulate the conductive layers stacked therewith. The material of the at least one insulating layer is NPG-171.

[0014] In a possible implementation, the insulating layer between the high-speed signal layer and the ground layer, and / or the insulating layer between the low-speed signal layer and the ground layer, is made of a flat semi-cured epoxy resin sheet or core board.

[0015] In the second aspect, an embodiment of the present application provides an embodied intelligent robot domain brain, which includes: at least one processor and a printed circuit board as described in the first aspect and / or various possible implementations of the first aspect above, the processor is arranged on the printed circuit board, and the processor is used to execute computer execution instructions to realize the actions of the embodied intelligent robot.

[0016] The printed circuit board and embodied intelligent robot domain brain provided by the embodiment of the present application are applied to the embodied intelligent robot domain brain. The printed circuit board places the graphics processing unit GPU and the central processing unit CPU on two independent printed circuit boards, namely the brain board carrying the graphics processing unit GPU and the cerebellum board carrying the central processing unit CPU. In this way, after the printed circuit board is broken down into parts, the brain board and the cerebellum board can be independently wired, which is conducive to reducing the overall wiring difficulty and complexity of the printed circuit board; and the brain board and the cerebellum board are electrically connected by means of board-to-board connectors, and then a suitable channel can be selected from the multiple high-quality signal channels provided by the connector for communication. Based on this, while the wiring complexity is reduced, the communication between electronic components can also select a suitable communication channel for connection, which can shorten the signal transmission path between the CPU and the GPU, reduce the energy loss during signal transmission, and improve the signal transmission quality. Therefore, the printed circuit board has high signal integrity and is suitable for the needs of the embodied intelligent robot domain brain. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of an embodied intelligent robot domain brain provided in an embodiment of the present application;

[0019] Figure 2A schematic diagram of a printed circuit board provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of a brain plate stack provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of a cerebellum plate stack provided in an embodiment of the present application;

[0022] Figure 5 Schematic diagram of various via methods provided in the embodiments of the present application;

[0023] Figure 6 A schematic diagram of a single-ended four-port network provided in an embodiment of the present application;

[0024] Figure 7 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 1 ;

[0025] Figure 8 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 2 ;

[0026] Figure 9 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 3 .

[0027] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0028] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0029] In the technical solutions of the embodiments of this application, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0030] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0031] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0032] In the embodiments of this application, if words such as "first" and "second" are used, they are intended to distinguish between identical or similar items with substantially the same functions and effects. For example, the first electronic device and the second electronic device are merely used to distinguish between different electronic devices and do not limit the order of precedence. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity or execution order, and words such as "first" and "second" do not necessarily mean that they are different.

[0033] In the embodiments of this application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0034] With the development of artificial intelligence technology, embodied intelligent robots are also rapidly iterating and updating. For example, some embodied intelligent robots have humanoid bodies and can perform movements such as walking, running, and dancing. The behavior of embodied intelligent robots is mainly controlled by the embodied intelligent robot's domain brain.

[0035] The domain brain of an embodied intelligent robot, also referred to as the domain brain or domain controller, operates similarly to the human brain and serves as the decision-making and control center for the embodied intelligent robot. Embodied intelligent robots may also include cameras, lidar, temperature sensors, and tactile sensors. The domain brain receives data collected by the embodied intelligent robot's sensors, processes it, and then makes decisions based on pre-set decision-making algorithms and data, thereby controlling the robot's body to perform corresponding actions. Of course, embodied intelligent robots are not limited to humanoid robots; they also include cleaning robots, agricultural robots, rescue robots, and other intelligent robots with physical forms.

[0036] The domain brain of the embodied intelligent robot includes a printed circuit board, namely a PCB board, which is mainly used to carry electronic components such as the system on chip (SOC), central processing unit (CPU), graphics processing unit (GPU) and / or data processing unit (DPU).

[0037] Embodied intelligent robots need to continuously perceive the environment and respond according to the environment or instructions. Therefore, the embodied intelligent robot's domain brain needs to process data from sensors in real time. This data may be multi-source data and the data volume may be large. Therefore, the embodied intelligent robot's domain brain usually needs to have high-performance data processing capabilities, which also places high signal integrity requirements on the PCB board of the embodied intelligent robot's domain brain.

[0038] The existing PCB boards of the domain brain of embodied intelligent robots have low signal integrity due to structural defects and cannot meet the needs of embodied intelligent robots.

[0039] For example, some existing embodied intelligent robot domain brains place the CPU and GPU on a single PCB. This requires integrated routing of the CPU, GPU, and other electronic components, increasing the complexity of wiring. This complexity leads to a longer signal transmission path between the CPU and GPU, resulting in significant energy loss and reduced signal transmission quality. Consequently, existing embodied intelligent robot domain brain PCBs suffer from low signal integrity.

[0040] In view of this, an embodiment of the present application provides a printed circuit board, which is applied to the domain brain of an embodied intelligent robot. The printed circuit board places a graphics processing unit (GPU) and a central processing unit (CPU) on two separate printed circuit boards, namely a brain board carrying the graphics processing unit (GPU) and a cerebellum board carrying the central processing unit (CPU). In this way, after the printed circuit board is broken down into parts, the brain board and the cerebellum board can be independently wired, which is conducive to reducing the overall wiring difficulty and complexity of the printed circuit board; and, the brain board and the cerebellum board are electrically connected by means of a board-to-board connector, and a suitable channel can be selected from the multiple high-quality signal channels provided by the connector for communication. Based on this, while the wiring complexity is reduced, the communication between electronic components can also select a suitable communication channel for connection, which can shorten the signal transmission path between the CPU and the GPU, reduce the energy loss during signal transmission, and improve the signal transmission quality. Therefore, the printed circuit board has high signal integrity and is suitable for the needs of the domain brain of an embodied intelligent robot.

[0041] The technical solutions of the present application are described in detail below with reference to specific embodiments. The specific embodiments below may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0042] Figure 1 This is a schematic diagram of an embodied intelligent robot domain brain provided in an embodiment of the present application. The embodied intelligent robot domain brain provided in an embodiment of the present application includes two PCB boards: a brain board that carries a GPU and a brain board that carries a CPU. Both the CPU and GPU can be understood as processors.

[0043] like Figure 1 As shown, the cerebellum board is provided with a CPU module (COME Module), which includes a CPU. The CPU module can be used to calculate and process information such as data and instructions. The cerebellum board is also provided with a power module (Power) and a board-to-board connector (Board to Board Connector, B2B CON). The power module can be used to supply power to the CPU module, for example, it can provide power at voltage levels such as P12V (12 volts) or P5V (5 volts); the power module can also supply power to other modules or electronic components. The B2B CON can provide a high-quality signal transmission channel for the cerebellum board and can be used for the electrical connection between the cerebellum board and the brain board.

[0044] The brain board is provided with two GPU modules, namely GPU1 module and GPU2 module, each of which includes a GPU. GPU1 module and GPU2 module can be connected to external devices via interface 1 and interface 2, respectively. For example, they can be connected to camera 1 (Camera1) and camera 2 (Camera2), respectively. Camera 1 (Camera1) and camera 2 (Camera2) can respectively acquire image data, providing data for the embodied intelligent robot to perceive the environment. Interface 1 and interface 2 can be, for example, Gigabit Multimedia Serial Links (GMSL) interfaces, which can achieve high-speed image data transmission.

[0045] like Figure 1 As shown, the brain board is also provided with a B2B CON, which can be used for the electrical connection between the brain board and the cerebellum board. Specifically, the CPU module in the cerebellum board is connected to the B2B CON of the cerebellum board, and can communicate based on a high-speed interface standard (Peripheral Component Interconnect Express 4.0, PCIE4.0); the GPU1 module and the GPU2 module in the brain board are respectively connected to the B2B CON of the brain board, and can communicate based on PCIE4.0. By plugging the B2BCON of the brain board with the B2B CON of the cerebellum board, communication and power supply between the brain board and the cerebellum board can be achieved, thereby achieving communication and power supply of the entire embodied intelligent robot domain brain.

[0046] The embodied intelligent robot domain brain provided in the embodiment of the present application includes a brain board and a cerebellum board. By plugging the board-to-board connectors on the two PCB boards, a carrier is provided for the brain board and the cerebellum board to communicate with each other and for the cerebellum board to supply power to the brain board, thereby obtaining data communication guarantees with higher reliability and stability.

[0047] It is understandable that the above embodiment is only an example, and more CPU modules or GPU modules can also be set on the brain board and the cerebellum board, and other modules or electronic components can also be set. The communication between electronic components such as modules, interfaces and board-to-board connectors is not limited to PCIE4.0 and GMSL, but can also be 10 Gigabit Ethernet interface standards (10Gigabit Attachment Unit Interface, XFI) or high-speed universal serial bus (UniversalSerialBus, USB), etc. The above-mentioned external devices can be other electronic devices, such as storage devices such as solid-state drives (SolidState Disk, SSD), or acquisition devices such as infrared sensors or millimeter wave radars, and these external devices can be connected to the domain brain via a cable. The embodiment of the present application does not limit the electronic components provided in the domain brain, the external devices of the domain brain, and the connection mode and communication protocol between each device, and will not be repeated here for example.

[0048] Figure 2 A schematic diagram of a printed circuit board provided in an embodiment of the present application, wherein the printed circuit board is applied to an embodied intelligent robot domain brain, such as Figure 2 As shown, the printed circuit board includes two independent printed circuit boards, namely the brain board and the cerebellum board. The brain board is used to carry the graphics processing unit GPU, and the cerebellum board is used to carry the central processing unit CPU. The brain board and the cerebellum board are electrically connected by plugging in a board-to-board connector.

[0049] For example, the brain board is a PCB for carrying a graphics processing unit (GPU), and the cerebellum board is a PCB for carrying a central processing unit (CPU). When constructing the stack of the brain and cerebellum boards, independent wiring designs can be performed based on the GPU and CPU layout requirements, respectively. The stack of the brain and cerebellum boards can have the same or different numbers of layers.

[0050] The brain board's B2B CON board-to-board connector and the cerebellum board's B2B CON board-to-board connector are connectors that provide high-quality signal paths and can be plugged in. By plugging the two B2B CONs together, high-speed signal transmission can be achieved between the brain and cerebellum boards using the high-quality signal paths provided by the B2B CONs. Furthermore, if the B2B CONs include anti-interference devices such as shielding layers, plugging the B2B CONs together can reduce electromagnetic interference (EMI) and signal noise introduced by electronic components during operation, helping to improve signal transmission quality and enhance the overall signal integrity of the printed circuit board.

[0051] Exemplarily, the board-to-board connector can be a high-quality board-to-board connector such as a coaxial connector or a high-speed board-to-board connector. These connectors are suitable for high-frequency signal transmission, have high density and high bandwidth characteristics, and can support high-quality signal transmission.

[0052] It should be understood that according to the performance requirements of the embodied intelligent robot in the actual application scenario, the graphics processor GPU and central processing unit CPU in the embodied intelligent robot domain brain can be set according to demand, and the embodiments of the present application do not limit this.

[0053] The printed circuit board provided in the embodiment of the present application is applied to the domain brain of an embodied intelligent robot. The printed circuit board places the graphics processing unit GPU and the central processing unit CPU on two independent printed circuit boards, namely the brain board carrying the graphics processing unit GPU and the cerebellum board carrying the central processing unit CPU. In this way, after the printed circuit board is broken down into parts, the brain board and the cerebellum board can be independently wired, which is conducive to reducing the wiring difficulty and complexity of the printed circuit board as a whole; and, the brain board and the cerebellum board are electrically connected by means of a board-to-board connector, and a suitable channel can be selected from the multiple high-quality signal channels provided by the connector for communication. Based on this, while the wiring complexity is reduced, the communication between electronic components can also select a suitable communication channel for connection, which can shorten the signal transmission path between the CPU and the GPU, reduce the energy loss during signal transmission, and improve the signal transmission quality. Therefore, the printed circuit board has high signal integrity and is suitable for the needs of the domain brain of an embodied intelligent robot.

[0054] In one possible implementation, the brain board includes multiple conductive layers, which include at least one low-speed signal layer, at least one high-speed signal layer, at least one power supply layer and at least one ground layer. The high-speed signal layer is a signal layer whose signal transmission rate is greater than the signal transmission rate of the low-speed signal layer. The multiple conductive layers are stacked to form a large brain board stack; at least one power supply layer is stacked on the inner core of the large brain board stack and ground layers are stacked on both sides thereof to form the first inner core layer of the large brain board stack; first transmission layers are stacked on both sides of the first inner core layer, and any first transmission layer includes at least one high-speed signal layer and at least one ground layer stacked at intervals; the low-speed signal layer is stacked on the outside of the first transmission layer to form the first outer layer of the large brain board stack.

[0055] For example, the conductive layer can be understood as a copper foil layer used for conduction. The conductive layer can be a power layer for transmitting electrical energy, a signal layer for transmitting electrical signals, or a ground layer for grounding. A circuit path can be formed through the conductive layer to achieve electrical connection between the various electronic components arranged on the PCB board.

[0056] The power plane distributes the voltage and current of the power supply. It can be a large copper layer, providing a stable power supply and minimizing voltage drop. The ground plane is a conductive layer that provides a common ground point for the circuit. A ground plane can be a relatively unbroken copper surface, providing a low-impedance ground path, thereby reducing electromagnetic interference and signal noise between electronic components.

[0057] The signal layer can be understood as a conductive layer for arranging signal lines, which can help transmit electrical signals between electronic components. In the embodiment of the present application, the signal layer can be divided into a low-speed signal layer and a high-speed signal layer according to the size of the signal transmission rate, wherein the signal transmission rate of the high-speed signal layer is greater than the signal transmission rate of the low-speed signal layer. For example, if the signal transmission rate of the high-speed signal layer is above 10 Mbps (megabits per second), the signal transmission rate of the low-speed signal layer is below 10 Mbps; if the signal transmission rate of the high-speed signal layer is above 100 Mbps, the signal transmission rate of the low-speed signal layer is below 100 Mbps.

[0058] When obtaining the cerebral and / or cerebellar boards in the printed circuit boards provided in the embodiments of the present application, multiple conductive layers may be stacked together to form a multi-conductive layer stack. It should be understood that when stacking the conductive layers, at least one insulating layer may be stacked between any two conductive layers to provide mechanical support and electrical insulation between the two adjacent stacked conductive layers via the insulating layer.

[0059] The brain plate stack, formed by stacking multiple conductive layers, includes a first inner core layer, a first transmission layer, and a first outer layer. All power layers are stacked within the inner core of the brain plate stack. These layers function as a single unit, with ground layers stacked on both sides. This structure effectively wraps around all the power layers, forming the first inner core layer of the brain plate stack.

[0060] First transmission layers are stacked on both sides of the formed first core layer. It is worth noting that the first transmission layers on both sides can have the same number of conductive layers or different numbers of conductive layers. For example, the first transmission layer on one side may include more high-speed signal layers and ground layers than the first transmission layer on the other side.

[0061] In the first transmission layer, the high-speed signal layer and the ground layer are stacked in an alternating pattern. This means that the only conductive layer adjacent to the high-speed signal layer is the ground layer. This separation allows the ground layer to wrap around both sides of the high-speed signal layer, reducing the high-frequency noise generated by the signal during transmission. The stacking of the high-speed signal layer and the ground layer in the first transmission layer also helps to more accurately control the characteristic impedance of the signal line, reducing signal reflections and distortion, and improving signal quality. The overall structure of the first transmission layer and the first core layer, with the first transmission layer on both sides wrapping around the first core layer, facilitates the routing of differential signal pairs and provides better common-mode noise suppression and signal integrity.

[0062] In the first core layer, ground planes are stacked on both sides of each power layer. This effectively wraps around all power layers, creating a capacitive effect between the ground planes. This helps filter out high-frequency noise generated by the power layers, suppressing their impact on signal transmission. Furthermore, this first core layer forms a good reference plane, reducing the area of ​​the signal loop and helping to mitigate electromagnetic interference and radiation generated by electronic components during operation.

[0063] Furthermore, placing each power layer in the center of the brain board allows for a more even distribution of current paths for the electronic components on both sides of the board, reducing voltage drops and current congestion in the power distribution network, and thus improving the board's power integrity. Furthermore, stacking the two first transmission layers on either side of the first core layer reduces power impedance by shortening the power paths and increasing the area of ​​the power layers, thus providing a more stable power supply for the entire board.

[0064] The low-speed signal layer is stacked on the outside of the first transmission layer to form the first outer surface layer of the brain plate stack. The first outer surface layer can transmit low-speed signals away from the power layer, thereby obtaining relatively stable low-speed signal transmission quality.

[0065] In the embodiments of the present application, all power layers are stacked within the inner core of the main board stack, which allows for more even current distribution to components, reduces voltage drop and current congestion in the power distribution network, and improves power integrity. The first core layer, formed by the ground layers on both sides, is equivalent to wrapping around each power layer. This creates a capacitive effect between the ground layers, filtering out high-frequency noise from the power layers and suppressing their impact on signal transmission. The entire first core layer is placed within the main board stack, with the first transmission layers stacked on both sides. This creates a good reference plane, reducing signal loop area, helping to reduce electromagnetic interference and electromagnetic radiation, and improving the signal integrity of high-speed signal transmission within the first transmission layer. The reference plane formed by the first core layer also improves the characteristic impedance control of the signal transmission path, reducing signal reflections and crosstalk. Furthermore, by embedding all power layers within the inner core and stacking two first transmission layers on either side of the first core layer, the power impedance is reduced by shortening the power path length and increasing the area of ​​the power layers, resulting in more stable power supply and reducing power supply noise and voltage fluctuations. The stacking of high-speed signal layers and ground layers in the first transmission layer helps control the characteristic impedance of signal lines in the high-speed signal layer, reducing signal reflections and distortion. The two first transmission layers stacked on either side of the first core layer also facilitate the routing of differential signal pairs, providing better common-mode noise suppression and signal integrity. The low-speed signal layer stacked on the outside to form the first outer layer allows for the transmission of low-speed signals within the first outer layer, achieving relatively stable low-speed signal transmission quality. Therefore, the stacked structure of the brain board helps the board achieve higher signal integrity and power integrity, meeting the requirements of the embodied intelligent robot domain brain for the brain board.

[0066] When building the stackup for the cerebellum board, a similar structure to the brain board can be used to ensure high signal integrity and power integrity for the cerebellum board.

[0067] In one possible implementation, the cerebellum board includes multiple conductive layers, which are stacked to form a cerebellum board stack; at least one power supply layer is stacked on the inner core of the cerebellum board stack and ground layers are stacked on both sides to form the second inner core layer of the cerebellum board stack; second transmission layers are stacked on both sides of the second inner core layer, and any second transmission layer includes at least one high-speed signal layer and at least one ground layer stacked at intervals; a low-speed signal layer is stacked on the outside of the second transmission layer to form the second outer layer of the cerebellum board stack.

[0068] For example, the cerebellum board also includes multiple conductive layers, which can also be power layers, high-speed signal layers, low-speed signal layers, or ground layers. The conductive layers of the cerebellum board are stacked to form a cerebellum board stack, and the structure of the cerebellum board stack can be similar to that of the cerebral board stack.

[0069] The cerebellar plate stack includes a second inner core layer, a second transmission layer, and a second outer surface layer. The structure of the second inner core layer is similar to that of the first inner core layer, the structure of the second transmission layer is similar to that of the first transmission layer, and the structure of the second outer surface layer is similar to that of the first outer surface layer.

[0070] Because the cerebellar and cerebral board stacks share a similar laminate structure, the cerebellar board stack achieves similar technical benefits as the cerebral board stack: all power planes are stacked within the inner core of the cerebellar board stack, distributing current more evenly to components, reducing voltage drops and current congestion in the power distribution network, and improving power integrity. The resulting second core layer, which is equivalent to the ground planes on both sides enveloping the power planes, creates a capacitive effect between the ground planes, filtering out high-frequency noise from the power planes and suppressing their impact on signal transmission. The second core layer, positioned entirely within the cerebellar board stack and stacked with second transmission layers on both sides, forms a good reference plane, reducing signal loop area, helping to mitigate electromagnetic interference and radiation, and improving signal integrity for high-speed signal transmission within the second transmission layer. The reference plane formed by the second core layer also improves the characteristic impedance control of the signal transmission path, reducing signal reflections and crosstalk. Furthermore, by integrating all power planes within the inner core and stacking two second transmission layers on either side of the second core layer, the power supply impedance is reduced by shortening the power path length and increasing the power layer area, ensuring more stable power supply. This also reduces power supply noise and voltage fluctuations. The high-speed signal layer and ground layer are stacked alternately within the second transmission layer, helping to control the characteristic impedance of signal lines within the high-speed signal layer and reducing signal reflections and distortion. The two second transmission layers stacked on either side of the second core layer also facilitate the routing of differential signal pairs, providing improved common-mode noise suppression and signal integrity. The low-speed signal layer is stacked on the outside to form the second outer layer, enabling low-speed signal transmission within the second outer layer and achieving relatively stable low-speed signal transmission quality. Therefore, the stacked structure of the cerebellum board ensures high signal and power integrity, meeting the requirements of the embodied intelligent robot domain brain.

[0071] In one possible implementation, the first core layer includes two stacked power layers and two ground layers stacked outside the two power layers. Thus, by providing two power layers in the first core layer, the two power layers are respectively close to the front and back sides of the PCB board. Electronic components arranged on either side of the PCB board can be conveniently connected to the power layers to obtain power, thereby reducing the length of the power path supplied by the power layers, lowering the power impedance and improving the power integrity of the PVB board. Furthermore, this structure can also optimize the signal path, reduce unnecessary vias, reduce signal delay and distortion, and improve the speed and quality of signal transmission. Similar to the first core layer, the second core layer can also include two stacked power layers and two ground layers stacked outside the two power layers. The technical effects achieved are similar to those of the first core layer and will not be elaborated on.

[0072] In one possible implementation, the first transmission layer includes two high-speed signal layers and two ground layers, and one of the high-speed signal layers is stacked close to the first core layer. In this way, the first transmission layer can provide two high-speed signal layers for high-speed signal transmission, and one of the high-speed signal layers is stacked close to the first core layer. The ground layer of the first core layer can be used to wrap both high-speed signal layers of the first transmission layer with the ground layer, thereby reducing the electromagnetic interference and electromagnetic radiation when the high-speed signal layer transmits high-speed signals through the ground layer, further improving the signal integrity of the PCB board. Similar to the first transmission layer, the second transmission layer can also include two high-speed signal layers and two ground layers, and one of the high-speed signal layers is stacked close to the second core layer. The technical effect achieved is similar to that of the first transmission layer and will not be repeated here.

[0073] In one possible implementation, the brain board includes twelve conductive layers, and the two first outer layers of the brain board stack are the first top layer and the first bottom layer respectively; the conductive layers from the first top layer to the first bottom layer are the 1st layer to the 12th layer of the brain board stack, including: the 1st layer low-speed signal layer, the 2nd layer ground layer, the 3rd layer high-speed signal layer, the 4th layer ground layer, the 5th layer high-speed signal layer, the 6th layer ground layer, the 7th layer power layer, the 8th layer power layer, the 9th layer ground layer, the 10th layer high-speed signal layer, the 11th layer ground layer and the 12th layer low-speed signal layer.

[0074] Figure 3 A schematic diagram of the brain plate stack provided in the embodiment of the present application is shown in FIG. Figure 3As shown in the figure, the brain board stack composed of 12 conductive layers can be represented as follows: the first layer is the low-speed signal layer, which is also the first top layer, namely Layer 1; the second layer is the ground layer, namely Layer 2; the third layer is the high-speed signal layer, namely Layer 3; the fourth layer is the ground layer, namely Layer 4; the fifth layer is the high-speed signal layer, namely Layer 5; the sixth layer is the ground layer, namely Layer 6; the seventh layer is the power layer, namely Layer 7; the eighth layer is the power layer, namely Layer 8; the ninth layer is the ground layer, namely Layer 9; the tenth layer is the high-speed signal layer, namely Layer 10; the eleventh layer is the ground layer, namely Layer 11; the twelfth layer is the low-speed signal layer, which is also the first bottom layer, namely Layer 12.

[0075] In one possible implementation, Figure 3 The brain plate stack shown, layers 1 to 12, meet the parameters shown in Table 1 below.

[0076] Table 1 is a parameter table of a brain plate laminate

[0077]

[0078]

[0079]

[0080] As shown in Table 1, Layer 1 is a low-speed signal layer, Layer 1, which is also the top layer of the brain board stack and is used to transmit low-speed signals (for example, less than 10Mbps). The thickness of Layer 1 is 1.40 mil (one thousandth of an inch). Layer 12 is also a low-speed signal layer, which is the bottom layer of the brain board stack and can be used to transmit low-speed signals. The thickness of Layer 12 is also 1.40 mil. All conductive layers use 1oz (ounce) thick copper foil, of which Layer 1 and Layer 12 are both plated with 1 / 3oz. The board thickness of the brain board is 62.8 mil, and the board thickness is 1.60 mm.

[0081] For example, as shown in Table 1, Layer 7 and Layer 8 are both power layers. Layer 2, Layer 4, Layer 6, Layer 9, and Layer 11 are all ground layers. All high-speed signals go through Layer 3, Layer 5, and Layer 10. This structure allows the ground layer to be wrapped on both sides of the two power layers, shielding the interference of the power layer on signal transmission through the ground layer, suppressing the crosstalk generated by EMI and power supply noise. In addition, ground layers are stacked on both sides of each high-speed signal layer, and the ground layer can shield the radiation of the high-speed signal of the high-speed signal layer. When the differential mode is converted to common mode, the signal can be returned through the ground layer, making the common mode as small as possible. The energy field of the signal can be shielded by the ground layer, thereby reducing the signal propagation path and preventing crosstalk.

[0082] In one possible implementation, the cerebellum board includes twelve conductive layers, and the two second outer layers of the cerebellum board stack are the second top layer and the second bottom layer respectively; the conductive layers from the second top layer to the second bottom layer are the 1st layer to the 12th layer of the cerebellum board stack, including: the 1st layer low-speed signal layer, the 2nd layer ground layer, the 3rd layer high-speed signal layer, the 4th layer ground layer, the 5th layer high-speed signal layer, the 6th layer ground layer, the 7th layer power supply layer, the 8th layer power supply layer, the 9th layer ground layer, the 10th layer high-speed signal layer, the 11th layer ground layer and the 12th layer low-speed signal layer.

[0083] Figure 4 A schematic diagram of the cerebellum plate stack provided in an embodiment of the present application is shown in FIG. Figure 4 As shown in the figure, the cerebellum board stack composed of 12 conductive layers can be represented as follows: the first layer is the low-speed signal layer, which is also the second top layer, namely Layer 1; the second layer is the ground layer, namely Layer 2; the third layer is the high-speed signal layer, namely Layer 3; the fourth layer is the ground layer, namely Layer 4; the fifth layer is the high-speed signal layer, namely Layer 5; the sixth layer is the ground layer, namely Layer 6; the seventh layer is the power layer, namely Layer 7; the eighth layer is the power layer, namely Layer 8; the ninth layer is the ground layer, namely Layer 9; the tenth layer is the high-speed signal layer, namely Layer 10; the eleventh layer is the ground layer, namely Layer 11; the twelfth layer is the low-speed signal layer, which is also the second bottom layer, namely Layer 12.

[0084] In one possible implementation, Figure 4 The cerebellum plate stack shown, layers 1 to 12 meet the parameters shown in Table 2 below.

[0085] Table 2 is a parameter table of a cerebellum plate stack

[0086]

[0087]

[0088]

[0089] As shown in Table 2, Layer 1 is the low-speed signal layer, also the second top layer of the cerebellar board stack. It is used to transmit low-speed signals (e.g., less than 10 Mbps). Layer 1 has a thickness of 1.40 mils. Layer 12 is also a low-speed signal layer, the second bottom layer of the cerebellar board stack. It can transmit low-speed signals. Layer 12 is also 1.40 mils thick.

[0090] Layers 1, 2, 4, 5, 8, 9, 11, and 12 all use 1oz copper foil, while Layers 6 and 7 use 2oz copper foil. Layers 3 and 10 use 0.5oz copper foil. Layers 1 and 12 are plated with a 1 / 3oz starting thickness, resulting in a final copper thickness of 1oz. The cerebellum board has a board thickness of 64.0 mils and a board thickness of 1.63 mm.

[0091] For example, as shown in Table 2, Layer 7 and Layer 8 are both power layers. Layer 2, Layer 4, Layer 6, Layer 9, and Layer 11 are all ground layers. All high-speed signals go through Layer 3, Layer 5, and Layer 10. This structure allows the ground layer to be wrapped on both sides of the two power layers, shielding the interference of the power layer on signal transmission through the ground layer, suppressing the crosstalk generated by EMI and power supply noise. In addition, ground layers are stacked on both sides of each high-speed signal layer, and the ground layer can shield the radiation of the high-speed signal of the high-speed signal layer. When the differential mode is converted to common mode, the signal can be returned through the ground layer, making the common mode as small as possible. The energy field of the signal can be shielded by the ground layer, thereby reducing the signal propagation path and preventing crosstalk.

[0092] In a possible implementation, at least one insulating layer is stacked between any two conductive layers. The insulating layer is used to support and insulate the conductive layers stacked therewith. The material of the at least one insulating layer is NPG-171.

[0093] For example, the insulating layer is a material layer in the PCB board used to support and insulate the conductive layer stacked therewith. The insulating layer can also be called a base material layer, a dielectric layer or a substrate layer. Figure 3 and Figure 4 As shown, an insulating layer is stacked between any two conductive layers.

[0094] For example, as shown in Table 1, the insulating layer between Layer 1 and Layer 2 uses a semi-cured epoxy resin sheet (PrePreg) 1078x1 with a thickness of 2.7 mil; the insulating layer between Layer 2 and Layer 3 uses a core board (Core) 1078x1 with a thickness of 3.00 mil; the insulating layer between Layer 3 and Layer 4 uses a PrePreg 2113x1 with a thickness of 4.0 mil; the insulating layer between Layer 4 and Layer 5 uses a Core 1078x1 with a thickness of 3.0 mil; the insulating layer between Layer 5 and Layer 6 uses a PrePreg 2113x2 with a thickness of 9.0 mil; the insulating layer between Layer 6 and Layer 7 uses a Core 1078x1 with a thickness of 3.0 mil; the insulating layer between Layer 7 and Layer 8 uses a PrePreg 2113x2 with a thickness of 9.0 mil; the insulating layer between Layer 8 and Layer 9 uses a Core 1078x1 with a thickness of 3.0 mil. 1078x1; the insulation layer between Layer 9 and Layer 10 uses PrePreg 2113x1 with a thickness of 4.0 mil; the insulation layer between Layer 10 and Layer 11 uses Core 1078x1 with a thickness of 3.0 mil; the insulation layer between Layer 11 and Layer 12 uses PrePreg 1078x1 with a thickness of 2.7 mil.

[0095] For example, as shown in Table 2, the insulation layer between Layer 1 and Layer 2 uses PrePreg 1078x1 with a thickness of 2.7 mil; the insulation layer between Layer 2 and Layer 3 uses Core 1078x1 with a thickness of 3.00 mil; the insulation layer between Layer 3 and Layer 4 uses PrePreg 2113x1 with a thickness of 4.0 mil; the insulation layer between Layer 4 and Layer 5 uses Core 1078x1 with a thickness of 3.0 mil; the insulation layer between Layer 5 and Layer 6 uses PrePreg 2113x2 with a thickness of 9.0 mil; the insulation layer between Layer 6 and Layer 7 uses Core 1078x1 with a thickness of 3.0 mil; the insulation layer between Layer 7 and Layer 8 uses PrePreg 2113x2 with a thickness of 9.0 mil; the insulation layer between Layer 8 and Layer 9 uses Core 2113x2 with a thickness of 3.0 mil. 1078x1; the insulation layer between Layer 9 and Layer 10 uses PrePreg2113x1 with a thickness of 4.0 mil; the insulation layer between Layer 10 and Layer 11 uses Core 1078x1 with a thickness of 3.0 mil; the insulation layer between Layer 11 and Layer 12 uses PrePreg1078x1 with a thickness of 2.7 mil.

[0096] The semi-cured epoxy resin sheet (PrePreg) refers to a pre-impregnated material, usually glass fiber cloth impregnated in resin and then partially cured to facilitate handling as an insulation layer. The core board is usually a glass fiber reinforced epoxy resin laminate.

[0097] Both the PrePreg and Core insulation layers can be made of NPG-171. NPG-171 is an excellent epoxy resin material with high stability, high temperature resistance, and a low thermal expansion coefficient, making it suitable for use as an insulation layer on PCBs. Insulation layers made with NPG-171 provide excellent mechanical support and electrical insulation.

[0098] Compared to FR-4 or polyimide insulation layers, NPG-171's higher glass transition temperature (Tg) allows it to maintain excellent mechanical and electrical properties even in high-temperature environments. NPG-171 also exhibits good dielectric loss and dielectric constant, making it suitable for high-speed signal transmission applications. Its high mechanical strength and dimensional stability provide stable mechanical support for the conductive layers of the PCB, enhancing the overall stability and reliability of the cerebral and / or cerebellum boards.

[0099] Based on this, at least one insulating layer of NPG-171 material is used in the brain board and / or cerebellum board. Due to the high stability, high temperature resistance and low thermal expansion coefficient of NPG-171, it can provide good mechanical support and electrical insulation for the conductive layer, meeting the physical property requirements of the embodied intelligent robot domain brain for the PCB board.

[0100] In a possible implementation, the insulating layer between the high-speed signal layer and the ground layer, and / or the insulating layer between the low-speed signal layer and the ground layer, is formed of a flat semi-cured epoxy resin sheet or core board.

[0101] For example, a flat semi-cured epoxy resin sheet is PrePreg 1078x1 shown in Tables 1 and 2, and a flat core board is Core 1078x1 shown in Tables 1 and 2. Compared to 1078x1, 1080 semi-cured epoxy resin sheet or core board is a non-flat insulation layer.

[0102] For example, as shown in Table 1, the insulation layer between Layer 2 and Layer 3 uses Core 1078x1, a flat core board. Another example, as shown in Table 2, the insulation layer between Layer 10 and Layer 11 uses Core 1078x1, also a flat core board. Because Core 1078 is flatter, its internal gaps are relatively fewer, resulting in a more uniform dielectric distribution. Therefore, when transmitting signals in high-speed or low-speed signal layers, skew is reduced, resulting in higher signal transmission quality.

[0103] In an embodiment of the present application, when a flat semi-cured epoxy resin sheet or core board is used as the insulating layer between the high-speed signal layer and the ground layer, and / or the insulating layer between the low-speed signal layer and the ground layer, since the flat semi-cured epoxy resin sheet or core board is thinner and has fewer gaps in the material than the non-flat insulating layer material, the medium distribution is more uniform, and the difference in the path length of the signal propagating in the medium can be reduced. Therefore, when transmitting differential signals and other signals, the signal skew can be reduced, and the signal transmission quality can be improved.

[0104] For example, when using vias in high-speed signal layers, mismatched via impedance can cause high-speed signal reflection and attenuation, impacting circuit performance. Controlling via impedance is crucial in high-speed digital and RF circuits because it can affect signal integrity and circuit reliability.

[0105] In a possible implementation, for at least one high-speed signal layer in the cerebral board stack and / or the cerebellum board stack, a skip via is used to provide a via to the at least one high-speed signal layer.

[0106] Via impedance mainly includes series impedance and parallel impedance. Series impedance is caused by the conductor resistance and inductance of the via, while parallel impedance is caused by the capacitance effect between the via and the surrounding medium. Via impedance can be calculated using the following formula:

[0107]

[0108] Where Z represents the via impedance; R represents the via resistance; j represents the imaginary unit; ω represents the angular frequency; L represents the parasitic inductance; and C represents the parasitic capacitance.

[0109] The via resistance R can be calculated using the following formula:

[0110] R=ρ×l / A

[0111] Where ρ represents the resistivity of the material; l represents the length of the via; and A represents the cross-sectional area of ​​the via.

[0112] The parasitic inductance L of the via can be calculated using the following formula:

[0113] L=(μ0×μ r × D) / [2×ln(D / d)+0.4]

[0114] Where μ0 represents the magnetic permeability of vacuum; μ r Represents the relative magnetic permeability of the PCB material; D represents the diameter of the via; d represents the aperture of the via.

[0115] The parasitic capacitance C of the via can be calculated using the following formula:

[0116] C=(ε0×ε r ×D) / [ln(D / 2d)+0.8]

[0117] Where ε0 represents the permittivity of vacuum; ε r Represents the relative permittivity of the PCB material; D represents the diameter of the via; and d represents the aperture of the via.

[0118] The formula for calculating via impedance above shows that the via impedance, Z, is related to parasitic inductance, L, and parasitic capacitance, C. Because high-speed signals transmit at high frequencies and experience fluctuations, these fluctuations generate parasitic inductance, L, and capacitance, C, which in turn increase the via impedance, Z. If the vias in the high-speed signal layer exhibit layer deviation, this increases the signal fluctuations during high-speed signal transmission, further increasing the via impedance, Z.

[0119] Figure 5 Schematic diagram of various via hole methods provided in the embodiment of the present application, such as Figure 5As shown in the figure, vias can be used to connect two or more conductive layers between conductive layers of a PCB board. Vias typically include through-hole vias, staggered microvias, stacked microvias, and buried vias.

[0120] A through-hole (Via) is a hole that runs through the entire PCB, from the top layer to the bottom layer, and is typically used to connect signals between all conductive layers. In a through-hole, unnecessary sections can be removed through back drilling to improve signal integrity.

[0121] Misaligned microvias and stacked microvias are two different forms of microvias. Microvias are small-diameter vias. Misaligned microvias are designed so that the microvias between different layers are not aligned vertically, but staggered. Misaligned microvias can improve the mechanical strength of PCBs. Stacked microvias are designed so that the microvias between different layers are vertically aligned, forming a continuous channel. Stacked microvias enable more direct interlayer connections and are suitable for PCBs requiring complex interconnections and higher density.

[0122] Buried vias are vias located inside the PCB and not connected to the outer layers. Buried vias can be used in multi-layer boards to achieve connections between internal layers without affecting the wiring of the outer layers. Buried vias can also be filled with epoxy resin to enhance the mechanical strength of the PCB and improve signal integrity. Figure 5 As shown, the stacked microvia is located above the buried via. The stacked microvia can also be understood as stacked microvias on buried via.

[0123] exist Figure 5 The figure also shows a skip via method. A skip via is a via that directly connects non-adjacent conductive layers. Skip vias can bypass intermediate conductive layers and directly connect non-adjacent conductive layers, allowing signals to be transmitted to more distant layers. Compared to the other via methods mentioned above, which connect layer by layer, skip vias can skip certain layers and directly connect to more distant layers.

[0124] Because skip vias provide direct connections, they exhibit smaller layer offset errors compared to buried vias or second-order blind buried vias. Furthermore, compared to the multiple backdrilling steps of stacked microvias, skip vias also produce less residual copper. Smaller layer offset errors and less residual copper can reduce fluctuations in high-frequency signal transmission, thereby reducing parasitic inductance L and parasitic capacitance C, thereby lowering via impedance.

[0125] In an embodiment of the present application, to reduce via impedance and thereby improve signal integrity, a skip-via method may be used to connect at least one high-speed signal layer in the brain board stack and / or the cerebellum board stack. For example, a two-level skip-via method (Skip Via 2 levels) may be used to directly connect the Layer 1 low-speed signal layer and the Layer 3 high-speed signal layer in the brain board stack and / or the cerebellum board stack. This can reduce the via impedance during signal transmission between the two signal layers, thereby improving the signal integrity of the brain board and / or the cerebellum board.

[0126] In the embodiments of the present application, skip-hole vias are used for the high-speed signal layer, directly connecting the high-speed signal layer to the conductive layer to be connected. This results in a relatively smaller layer offset error and a relatively smaller amount of residual copper between the two connected layers, thereby reducing signal fluctuations and reflections during high-speed signal transmission and lowering signal transmission losses. Furthermore, the use of skip-hole vias can reduce parasitic capacitance and inductance, thereby reducing via impedance and improving high-speed signal transmission quality. This improves the overall signal integrity of the printed circuit board.

[0127] For example, for vias between two low-speed signal layers, such as between Layer 1 low-speed signal layer and Layer 12 low-speed signal layer, through holes can be used to reduce the difficulty of vias.

[0128] In a possible implementation, at least one conductive layer uses reverse treated copper foil (RTF).

[0129] For example, RTF copper foil is an electrolytic copper foil with different degrees of roughening treatment on both sides. It reverses the rough surface and smooth surface functions of traditional electrolytic copper foil and enhances the smooth surface to optimize the adhesion and etching performance in circuit board manufacturing.

[0130] The use of RTF copper foil for the conductive layers reduces the surface roughness of the copper foil. This low-roughness surface helps reduce the skin effect and signal transmission loss during high-frequency signal transmission, thereby improving the signal integrity of the PCB. As shown in Tables 1 and 2, RTF copper foil is used in multiple conductive layers of the cerebral and cerebellum boards.

[0131] For example, the skin effect is caused by the change of the electromagnetic field inside the conductor. The skin depth is a parameter that can quantify the skin effect and reflect the extent of the skin effect. The skin depth can be calculated using the following formula:

[0132]

[0133] Where δ represents skin depth, ω represents angular frequency, μ represents magnetic permeability, σ represents electrical conductivity, and f represents frequency. Magnetic permeability μ = μ0 × μ r ; μ0 represents the magnetic permeability of vacuum; μ r Represents relative magnetic permeability, for non-ferromagnetic metals, μ r =1. μ0=4π×10 -7 H·m -1 .

[0134] RTF copper foil is classified into different grades based on surface roughness, such as RTF1 (Rz ≤ 3.5μm), RTF2 (Rz ≤ 2.3μm), and RTF3 (Rz ≤ 2.1μm). RTF copper foil with an RTF1 roughness grade, such as RTF1, can be used for the conductive layer to minimize the skin effect and signal transmission loss during high-frequency signal transmission, thereby improving the signal integrity of the PCB board.

[0135] Based on this, at least one conductive layer uses reverse-processed copper foil, which can reduce the skin effect of the conductive layer, improve the rate and signal quality of high-speed signal transmission, and further improve the signal integrity and power integrity of the printed circuit board.

[0136] In a possible implementation, at least one of the first outer layer and the second outer layer is covered with a solder mask (SM) formed by R500Z28DF solder mask ink.

[0137] like Figure 3 and Figure 4 As shown in the figure, a solder mask layer is stacked on the surface of the first and second outer layers, and the thickness of each solder mask layer can be 0.8 mil. The solder mask layer is a layer of polymer material covering the surface of the PCB board. This solder mask can prevent solder bridging short circuits during soldering, reduce solder loss in non-soldering areas, and provide electrical environmental and chemical resistance protection.

[0138] Solder mask ink is the main material of the solder mask layer. Compared with standard solder mask inks such as epoxy resin solder mask ink or polyimide solder mask ink, the solder mask ink of the R500 Z28DF model has optimized dielectric properties, which can reduce the loss in signal transmission and facilitate high-speed signal transmission.

[0139] The R500 Z28DF also offers excellent high-temperature resistance, capable of withstanding temperatures of at least 260°C during reflow soldering. Its solder mask layer has a low coefficient of thermal expansion, which helps reduce material expansion and contraction during thermal cycling, thereby improving the overall reliability and stability of the brain and / or cerebellum boards and meeting the physical property requirements of PCBs for embodied intelligent robot domain brains.

[0140] Figure 6 A schematic diagram of a single-ended four-port network provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, port 1 (PORT1), port 2 (PORT2), port 3 (PORT3) and port 4 (PORT4) are four different ports, each of which can correspond to the input / output end of the electronic components set on the embodied intelligent robot domain brain. For example, PORT1, PORT2, PORT3 and PORT4 can correspond to multiple input / output ends of GPU1 respectively.

[0141] After the cerebral plate stack and / or cerebellum plate stack are constructed, the insertion loss and return loss can be calculated for different ports using calculation formulas for insertion loss SDD21 and return loss SDD11 of differential signals.

[0142] The calculation formula for differential insertion loss is: SDD21 = 1 / 2 (S21 + S23 - S41 - S43);

[0143] The calculation formula for differential return loss is: SDD11 = 1 / 2 (S11-S13-S31+S33);

[0144] Among them, S21, S23 and S41 all represent corresponding elements in the S parameter matrix.

[0145] The dielectric loss of a PCB is related to the dielectric constant DK and the dielectric loss factor DF. The dielectric loss represents the attenuation of signal propagation and can be calculated using the following formula:

[0146]

[0147] Where a represents dielectric loss, which also represents signal propagation attenuation, and its unit is dB / inch (decibel / inch); f represents frequency; tanδ represents the dielectric loss factor DF of the substrate; ε r Indicates the dielectric constant DK of the substrate.

[0148] Based on the above dielectric loss formula, the dielectric loss of the PCB board can be calculated. It can then be calculated that the insertion loss of the interconnection between the brain board and the cerebellum board of the embodied intelligent robot domain brain needs to meet the requirement that the dielectric loss is less than or equal to 1dB / inch at a frequency of 8GHz (gigahertz), and the return loss needs to meet the requirement of less than or equal to -10dB (decibel).

[0149] In addition, for the brain board and cerebellum board, you can also determine whether the power integrity of the two boards meets the requirements. When determining the power integrity, you can calculate the ripple and noise using the following formula:

[0150]

[0151] Where i represents the current, R represents the DC resistance, L1 represents the AC inductance, di / dt represents the instantaneous current change in the power supply system, V drop Represents ripple and noise.

[0152] against Figure 3 and Figure 4 For the brain board stack and the cerebellum board stack in the corresponding embodiment, the brain board needs to meet the current requirement of greater than 30A (amperes) at a voltage of 12V; the cerebellum board needs to meet the current requirement of greater than 50A at a voltage of 12V. Therefore, based on the above-mentioned ripple and noise calculation formulas and other formulas for constructing PCB boards, it can be calculated that the two power supply layers of the brain board stack are both 1oz thick copper foil; the two power supply layers of the cerebellum board stack, one of which is 1oz thick copper foil and the other is 2oz thick copper foil. From the parameters of the brain board stack and the cerebellum board stack shown in Tables 1 and 2, it can be seen that the power supply layer in the cerebellum board is relatively thicker, which can meet the larger current requirements when running the CPU.

[0153] After building the brain and cerebellum board stacks, simulation tests can be used to verify that the boards meet the signal integrity and power integrity requirements of the embodied intelligent robot domain brain. The two boards are connected via a board-to-board connector and must be interconnected using the PCIE 4.0 bus. The specification requires a differential insertion loss (SDD21) greater than -28dB and a differential return loss (SDD11) less than -10dB.

[0154] Figure 7 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 1 After the brain plate stack shown in Table 1 and the cerebellum plate stack shown in Table 2 are connected, an excitation signal with a frequency (freq) of 8 GHz is applied to one of the ports to perform simulation detection. Figure 7 As shown, the SDD21 corresponding to 8GHz is -27.489dB, which is greater than -28dB and meets the specification requirements.

[0155] Figure 8 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 2 After the brain board stack shown in Table 1 and the cerebellum board stack shown in Table 2 are connected, an excitation signal with a frequency of 8 GHz is applied to one of the ports to perform simulation detection. Figure 8 As shown, the SDD11 corresponding to 8GHz is -22.384dB, which is less than -10dB and meets the specification requirements.

[0156] Figure 9 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 3 After the brain plate stack shown in Table 1 and the cerebellum plate stack shown in Table 2 are connected, Figure 9 As shown in the figure, the current of the simulated input P10V voltage is detected at the power supply end (Source), and a current greater than 50A is detected at the measurement point (SINK), indicating that the ripple and noise of the printed circuit board at the P10V voltage meet the power integrity requirements.

[0157] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules is merely a logical function division. In actual implementation, other division methods may be used. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not implemented.

[0158] The above-mentioned integrated module implemented in the form of a software functional module can be stored in a computer-readable storage medium. The above-mentioned software functional module is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) or a processor to perform some steps of the method described in each embodiment of the present application.

[0159] It should be understood that the above-mentioned processor may be a CPU, or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The steps of the method disclosed in the application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor. The memory may include random access memory (RAM), and may also include non-volatile memory (NVM), such as at least one disk storage, and may also be a USB flash drive, a mobile hard disk, a read-only memory, a disk or an optical disk, etc.

[0160] The above-mentioned storage device or storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random-access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0161] An exemplary storage medium is coupled to a processor, such that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an application-specific integrated circuit. Of course, the processor and storage medium can also exist as discrete components in an electronic device or a host control device.

[0162] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0163] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0164] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0165] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

[0166] Those skilled in the art will readily conceive of other implementations of the embodiments of the present application after considering the specification and practicing the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the embodiments of the present application, which follow the general principles of the embodiments of the present application and include common knowledge or customary technical means in the art that are not disclosed in the embodiments of the present application.

[0167] It should be understood that the embodiments of the present application are not limited to the precise structures described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the embodiments of the present application is limited only by the appended claims.

Claims

1. A printed circuit board, characterized in that: The printed circuit board is applied to the domain brain of an embodied intelligent robot. The printed circuit board includes two independent printed circuit boards, namely a brain board and a cerebellum board. The brain board is used to carry a graphics processing unit GPU, and the cerebellum board is used to carry a central processing unit CPU. The brain board and the cerebellum board are electrically connected by plugging a board-to-board connector.

2. The printed circuit board according to claim 1, wherein: The brain board includes multiple conductive layers, including at least one low-speed signal layer, at least one high-speed signal layer, at least one power layer, and at least one ground layer. The high-speed signal layer is a signal layer with a signal transmission rate greater than that of the low-speed signal layer. The multiple conductive layers are stacked to form a brain board stack. The at least one power supply layer is stacked in the inner core of the brain plate stack and the ground layers are stacked on both sides thereof to form a first inner core layer of the brain plate stack; A first transmission layer is stacked on both sides of the first core layer, and any of the first transmission layers includes at least one high-speed signal layer and at least one ground layer stacked alternately; The low-speed signal layer is stacked on the outer side of the first transmission layer to form a first outer surface layer of the brain plate stack.

3. The printed circuit board according to claim 2, wherein: The brain plate includes twelve conductive layers, wherein the two first outer layers of the brain plate laminate are respectively a first top layer and a first bottom layer; the conductive layers between the first top layer and the first bottom layer are respectively the first layer to the twelfth layer of the brain plate laminate, including: The first layer is the low-speed signal layer, the second layer is the ground layer, the third layer is the high-speed signal layer, the fourth layer is the ground layer, the fifth layer is the high-speed signal layer, the sixth layer is the ground layer, the seventh layer is the power layer, the eighth layer is the power layer, the ninth layer is the ground layer, the tenth layer is the high-speed signal layer, the eleventh layer is the ground layer, and the twelfth layer is the low-speed signal layer.

4. The printed circuit board according to claim 2, wherein: The cerebellum plate comprises the plurality of conductive layers, and the plurality of conductive layers are stacked to form a cerebellum plate stack; The at least one power supply layer is stacked in the inner core of the cerebellar plate stack, and the ground layers are stacked on both sides thereof to form a second inner core layer of the cerebellar plate stack; A second transmission layer is stacked on both sides of the second core layer, and any of the second transmission layers includes at least one high-speed signal layer and at least one ground layer stacked alternately; The low-speed signal layer is stacked on the outer side of the second transmission layer to form a second outer surface layer of the cerebellar plate stack.

5. The printed circuit board according to claim 4, wherein: The cerebellum plate comprises twelve conductive layers, wherein the two second outer layers of the cerebellum plate stack are respectively a second top layer and a second bottom layer; the conductive layers between the second top layer and the second bottom layer are respectively the first layer to the twelfth layer of the cerebral plate stack, including: The first layer is the low-speed signal layer, the second layer is the ground layer, the third layer is the high-speed signal layer, the fourth layer is the ground layer, the fifth layer is the high-speed signal layer, the sixth layer is the ground layer, the seventh layer is the power layer, the eighth layer is the power layer, the ninth layer is the ground layer, the tenth layer is the high-speed signal layer, the eleventh layer is the ground layer, and the twelfth layer is the low-speed signal layer.

6. The printed circuit board according to claim 5, wherein: For at least one high-speed signal layer in the cerebral plate stack and / or the cerebellum plate stack, a skip hole method is used to make vias in the at least one high-speed signal layer.

7. The printed circuit board according to any one of claims 2 to 6, characterized in that: At least one of the conductive layers is made of reverse-processed copper foil; and / or at least one of the first outer layer and the second outer layer is covered with a solder resist layer formed by R500Z28DF solder resist ink.

8. The printed circuit board according to any one of claims 2 to 6, characterized in that: At least one insulating layer is stacked between any two of the conductive layers. The insulating layer is used to support and insulate the conductive layers stacked therewith. The material of at least one of the insulating layers is NPG-171.

9. The printed circuit board according to claim 8, wherein: The insulating layer between the high-speed signal layer and the ground layer, and / or the insulating layer between the low-speed signal layer and the ground layer, is made of a flat semi-cured epoxy resin sheet or core board.

10. An embodied intelligent robot domain brain, characterized in that: The domain brain of the embodied intelligent robot includes: at least one processor and a printed circuit board as described in any one of claims 1-9, wherein the processor is arranged on the printed circuit board, and the processor is used to execute computer execution instructions to realize the actions of the embodied intelligent robot.

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