Hierarchical circuit repairing method based on netlist learning

By analyzing the hierarchical circuit structure based on a netlist learning method, the problem of the scan unit clock pin is accurately located and optimally repaired, which solves the problem of low efficiency in traditional methods and achieves efficient circuit repair and resource optimization.

CN120654624APending Publication Date: 2025-09-16INST OF COMPUTING TECH CHINESE ACAD OF SCI
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Patent Information

Application Number
CN202510688307.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-05-27
Publication Date
2025-09-16

AI Technical Summary

Technical Problem

Traditional design rule checking and repair methods are inefficient in hierarchical circuits and have difficulty quickly locating faulty nodes. Repair strategies that simply insert MUX logic lead to increased chip area, increased latency, and increased power consumption.

Method used

A netlist learning-based method is used to analyze the hierarchical structure and connection relationship of the hierarchical circuit, accurately locate the connection problem of the scan unit clock pin, and repair it through optimal repair point selection and minimized MUX module insertion strategy combined with hierarchical analysis.

Benefits of technology

It improves the repair efficiency of hierarchical circuits, reduces logic resource consumption and circuit performance impact, ensures the integrity of the circuit hierarchy, and solves the technical bottlenecks of traditional methods in logic resource consumption and delay power consumption control.

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Abstract

The invention provides a method for repairing a Hierarchical circuit based on netlist learning, and aims to solve the technical problems that in a traditional repairing scheme, logic resource consumption is high, a circuit hierarchical structure is prone to being damaged, and time delay power consumption is increased. The method comprises the steps that information of the Hierarchical circuit is obtained in a netlist learning mode, the connection state of a clock pin of a scanning unit is recognized according to the information, and therefore the Hierarchical circuit is repaired. According to the method, an optimal repair point is positioned by combining hierarchical structure analysis, a clock signal repair strategy based on minimum MUX module insertion is provided for a multi-clock scene, time delay accumulation and power consumption rise caused by excessive deployment of logic units in a deep module are avoided, and experimental results show that the method can significantly improve the test coverage rate and improve the test efficiency. And the occupation of logic resources for repairing the violation points is reduced, so that the technical bottleneck of repairing the multi-clock Hierarchical circuit is effectively broken through, and an efficient solution is provided for the testability design of a super-large-scale integrated circuit.
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