SPD burning method and system based on serial port instruction and embedded controller

Abstract

The invention discloses an SPD burning method and system based on a serial port instruction and an embedded controller, and relates to the embedded field, and the method comprises the following steps: connecting a serial port cable with a host and a slave, and configuring serial port parameters; monitoring a serial port data buffer area in a timed polling mode by utilizing an embedded controller, extracting an instruction data packet and performing comparison verification on the instruction data packet and a pre-stored instruction feature library after a data arrival event is obtained; after the instruction verification is passed, receiving an SPD data packet input by a user through a serial port, and performing data format analysis and verification processing; writing the SPD data passing the verification into a target chip page by page by utilizing an I2C bus, and executing read-back verification after writing operation on each page by adopting a paging writing mode; in view of low SPD burning efficiency and low data reliability in the prior art, according to the application, the embedded controller SPD burning based on serial port instruction control is constructed, multiple data verification mechanisms are integrated and the like, and the reliability of data burning is improved.

Description

Technical Field

[0001] The present application relates to the embedded field, and in particular to an SPD burning method and system based on serial port instructions and an embedded controller. Background Art

[0002] With the rapid development of computer memory technology, Serial Presence Detect (SPD) chips, as key components of memory modules, store important configuration information such as memory timing parameters, capacity information, and manufacturer data. The accuracy of SPD data directly impacts system memory initialization, performance optimization, and compatibility, making SPD programming technology a crucial component of the memory industry chain. The widespread adoption of next-generation memory standards like DDR4 and DDR5, along with the continued increase in memory frequency and capacity, has placed higher demands on the reliability, efficiency, and flexibility of SPD programming technology.

[0003] Currently, the industry mainly adopts three SPD burning technology solutions: Existing solution 1: Offline independent burning technology This solution uses a dedicated EEPROM programmer (such as the RT809F or CH341A) for direct programming via a DIP socket. This requires physically disassembling the SPD chip on the memory module for off-device programming. However, this solution has significant drawbacks: Disassembly and assembly are extremely risky, requiring physical removal of the memory heat sink or SPD chip, which can easily cause irreversible damage such as PCB deformation and pad loss. Programming efficiency is low, with programming a single chip taking approximately 30-45 seconds, only 1 / 40 the efficiency of an automated production line. Labor costs account for over 60% of total costs. Compatibility is limited, requiring programmer firmware to be continuously updated to support new SPD chips, resulting in high maintenance costs.

[0004] Existing Solution 2: In-System Programming (ISP) Technology This solution utilizes the memory slot's SMBus interface (an I2C derivative) to achieve live programming via a motherboard PCH bridge, requiring precise control of bus arbitration timing. However, this solution faces hardware compatibility limitations: Relying on motherboard IC interfaces, some OEMs lock bus access permissions, resulting in a programming failure rate as high as 30%. DDR5 memory requires synchronous configuration of its PMIC (power management chip), which traditional ISP tools cannot fully support and requires additional hardware adaptation. Motherboard manufacturers also need to consider programming compatibility during the design phase, increasing hardware design complexity.

[0005] Existing solution three: automated production line burning system This solution, integrated into the memory module production line, utilizes a fully automated programming solution, employing precision robotic arms for multi-channel parallel operation. Combined with AOI (Automated Optical Inspection) to ensure contact reliability, SPD programming is completed during the memory module production phase. However, this solution lacks flexibility later on: after the memory manufacturer programs the SPD, motherboard manufacturers face significant inconvenience in modifying the SPD configuration based on their own designs. Initial investment costs are high, with equipment procurement typically exceeding several million yuan. Furthermore, the solution requires an MES management system, making it suitable only for large-scale production and prohibitive for small and medium-sized enterprises. System maintenance costs are also high, with the annual replacement of consumable parts such as probes and pneumatic modules exorbitant.

[0006] In summary, existing SPD programming technologies suffer from low efficiency, insufficient reliability, high costs, complex operations, and limited flexibility, making them unable to meet the current memory industry's demand for efficient, reliable, and flexible SPD programming. The limitations of existing solutions are particularly prominent in application scenarios such as batch SPD configuration modification, small- to medium-scale production, or on-site debugging. A new technical solution is urgently needed to address these issues. Summary of the Invention

[0007] In view of the low SPD burning efficiency and low data reliability in the existing technology, the present application provides an SPD burning method and system based on serial port instructions and an embedded controller. By constructing an embedded controller SPD burning based on serial port instruction control and integrating multiple data verification mechanisms, the reliability of the burned data is improved.

[0008] One aspect of the present application provides an SPD programming method based on serial port instructions and an embedded controller, comprising: connecting a serial port cable to a host and a slave, configuring serial port parameters, including baud rate, data bits, stop bits, and parity bits; utilizing the embedded controller to monitor a serial port data buffer through a periodic polling method, and upon obtaining a data arrival event, extracting a command data packet and performing a comparison and verification with a pre-stored command signature library; upon successful command verification, receiving an SPD data packet input by a user through the serial port, performing data format parsing and verification processing; and writing the verified SPD data into a target chip page by page using an I2C bus, employing a paged write mode and performing a readback verification after each page write operation. Among them, SPD (Serial Presence Detect) is a tiny EEPROM chip on the memory module that uses the I2C interface to communicate and stores key parameter information of the memory. The SPD chip records core data such as memory type, capacity, timing parameters, and operating voltage. When the computer is turned on, the BIOS will automatically read the SPD information to configure the memory controller to achieve plug-and-play. Modern SPD also includes XMP overclocking configuration, which supports one-click improvement of memory performance. The SPD capacity of DDR4 memory is usually 512 bytes, using a standard 100kHzI2C interface, and the address is fixed in the range of 0x50-0x57. It not only ensures the stable operation of the memory, but also provides the system with the ability to automatically identify and optimize memory configuration.

[0009] Embedded Controller (EC): In this solution, this refers to a microcontroller chip integrated into the motherboard or a standalone hardware module, equipped with a serial communication interface and I2C bus control capabilities. This controller runs dedicated firmware responsible for receiving and parsing serial port commands, processing SPD data, controlling I2C bus timing, and managing the state machine for the entire programming process. The EC includes built-in non-volatile memory for storing command signatures and configuration parameters.

[0010] Data Arrival Event: This flag is triggered when the embedded controller detects new data arriving in the serial port data buffer through a periodic polling mechanism. When the data counter in the serial port receive FIFO buffer changes or the receive interrupt flag is set, the EC recognizes it as a data arrival event and initiates data extraction and processing.

[0011] Command Data Packet: refers to the structured command information transmitted through the serial port, including the command header, function code, parameter field, and check bit. In SPD burning applications, the command data packet is used to control the start, stop, and parameter configuration of the burning process. It has a fixed format specification and a specific identifier to facilitate EC parsing and verification.

[0012] Command Feature Library: A database of predefined command templates stored in the embedded controller's non-volatile memory. It contains characteristic information for all legal commands, such as command codes, parameter ranges, format specifications, and functional descriptions. The EC verifies the legitimacy and integrity of commands by comparing received command packets against the templates in the Command Feature Library, ensuring that only authorized SPD programming commands can be executed.

[0013] I2C bus (Inter-Integrated Circuit Bus): A bidirectional, two-wire serial bus protocol developed by Philips that uses a serial data line (SDA) and a serial clock line (SCL) for communication. In this solution, the I2C bus serves as the data transmission channel between the embedded controller and the SPD chip, supporting master-slave communication. The EC acts as the master device to control bus timing, and the SPD chip acts as the slave device to respond to read and write operations.

[0014] PageWriteMode: An optimized data writing strategy that divides large-capacity SPD data into multiple data pages of fixed size (16 bytes in this solution) and writes them page by page. This mode fully utilizes the page buffering feature of the EEPROM chip, improving write efficiency by writing a complete page of data at once. It also facilitates accurate error location and recovery mechanisms. After each page is written, a readback check is performed immediately to ensure data integrity.

[0015] In particular, this application achieves full compatibility with the full range of SPD specifications from DDR3 to DDR5 by adopting the standard I2C protocol and a standardized SPD register mapping mechanism. Based on the unified I2C interface definition and register address mapping specification in the SPD standard, the embedded controller's adaptive protocol stack can automatically identify different types of SPD chips and adopt the corresponding timing parameters and register operation sequences. This design ensures forward compatibility and technical continuity of the solution, eliminating the need for major hardware or firmware modifications for different memory standards.

[0016] Furthermore, a state machine-controlled approach selectively activates debugging modules based on serial port commands, enabling and disabling functions such as matrix keyboard scanning and serial port printout. This mechanism avoids the resource waste associated with traditional solutions where functional modules are permanently resident in memory and constantly running. By leveraging dynamic resource allocation strategies, it effectively reduces the embedded controller's CPU utilization and power consumption, improving overall system efficiency and responsiveness.

[0017] Furthermore, data format parsing includes: receiving standardized input data, the standardized input data adopts the format of register offset address + data value, the register offset address and data value are both in hexadecimal number and separated by preset delimiter; using a preset regular expression pattern to perform format parsing on the standardized input data, extracting the register offset address and the corresponding data value, and converting the hexadecimal string into a hexadecimal value and storing it in a data buffer sorted by address; when a single line of data extraction is completed, the pointer is incremented to point to the next line of data, and when the data end mark is detected or the preset number of lines is reached, the data extraction is determined to be completed, and the subsequent verification process is started.

[0018] The "Register Offset Address + Data Value Format" format is the standardized data representation format used when users enter SPD data. The "Register Offset Address" refers to the address offset of the SPD chip's internal storage unit, expressed as a 1-byte hexadecimal number (e.g., 00, 01, FF), and is used to specify the specific register location to be operated on. The "Data Value" refers to the specific data to be written to that register address, also expressed as a 1-byte hexadecimal number. The entire format uses the "address + delimiter + value" structure. For example, "00A0" indicates writing data 0xA0 at offset address 0x00, while "1A,FF" indicates writing data 0xFF at offset address 0x1A. This format is easy for users to understand and input, and it also facilitates program parsing and verification.

[0019] Address-Sorted Arrangement: This refers to the storage organization of the extracted address-data pairs in the data buffer, sorted in ascending order by the numerical value of the register offset address. In specific implementations, the embedded controller parses the multiple lines of "address + data" input by the user and sorts and stores them according to the hexadecimal numerical value of the offset address (e.g., 0x00 < 0x01 < 0x02 ... < 0xFF), ensuring that data at address 0x00 is placed first and data at address 0xFF is placed last. The technical advantages of this sorting method include: facilitating subsequent sequential writes to the SPD chip, improving I2C bus write efficiency; facilitating data management and error location; and conforming to the physical order of the SPD chip registers, avoiding timing issues caused by random access.

[0020] Furthermore, the preset regular expression pattern includes a first capturing group and a second capturing group, wherein: the first capturing group is used to match a combination of 1 to 2 hexadecimal characters to extract the register offset address; the second capturing group is used to match a combination of 1 to 2 hexadecimal characters to extract the corresponding data value; the regular expression pattern is ^([0-9A-Fa-f]{1,2})[ / s,]+([0-9A-Fa-f]{1,2}), wherein the first capturing group and the second capturing group are separated by a space character or a comma separator.

[0021] The ^ (start-of-line anchor) indicates that the match must begin at the beginning of the string, ensuring strict formatting of the entire line of data. In the SPD programming solution, this anchor prevents invalid characters or spaces from appearing at the beginning of the user-entered data line, ensuring that each line of data is parsed starting from a valid register address, improving the accuracy of data format verification.

[0022] ([0-9A-Fa-f]{1,2}) (first capturing group): Parentheses (): define the first capturing group, which is used to extract the matched register offset address; [0-9A-Fa-f]: character class, matching a single hexadecimal character, including the numbers 0-9 and the letters AF (case insensitive); {1,2}: quantifier, indicating that the preceding character class must appear 1 to 2 times, allowing the input of single-byte (such as A, F) or double-byte (such as 0A, FF) hexadecimal addresses; in this solution, this capturing group is specifically used to extract the register offset address of the SPD chip, supporting all valid address values ​​in the range of 0x00 to 0xFF.

[0023] [ / s,]+ (delimiter pattern): [ / s,]: character class, matching whitespace characters (including spaces and tabs) or commas; +: quantifier, indicating that the preceding character class must appear one or more times; this pattern is designed to identify the delimiter between addresses and data and supports multiple common delimiter methods (such as "00A0", "00,A0", and "00A0"), improving user input flexibility and error tolerance.

[0024] ([0-9A-Fa-f]{1,2}) (Second Capture Group): This capture group has the same structure as the first capture group and is used to extract the data value to be written to the SPD chip. This capture group supports 1 to 2 hexadecimal characters, allowing the user to enter any data value in the range of 0x00 to 0xFF, which meets the writing requirements of the SPD chip's 8-bit data register.

[0025] In particular, this regular expression implements the automatic recognition and parsing of standardized data formats in the SPD burning solution, simultaneously extracts address and data information through a double capture group mechanism, and ensures the validity of input data through strict character class restrictions, providing a reliable data source for subsequent hexadecimal conversion and SPD writing operations.

[0026] When format parsing of standardized input data fails using a preset regular expression pattern, an embedded controller generates an error report and provides feedback through the serial port to ensure the integrity and correctness of the data input.

[0027] Furthermore, the verification process includes: initializing a 16-bit CRC check code, reading the SPD data to be verified byte by byte; performing a left shift XOR operation on each data byte, shifting the byte data left by N bits and then performing an XOR operation with the current CRC value; preferably, N is set to 8. Performing multiple bit shift operations on the XOR result, shifting 1 bit left each time and detecting the state of the highest bit, if the highest bit is 1, performing an XOR operation with a preset polynomial, otherwise only performing the left shift operation; after completing each byte processing, intercepting the lowest 16 bits of the operation result as the updated CRC value, repeating the process until the verification calculation of all data is completed; comparing the final CRC check result with the CRC reference value stored in the SPD to verify data integrity.

[0028] Among them, the most significant bit (MSB): in the CRC check calculation process, refers to the leftmost bit (bit 15, bit

[15] ) of the binary data of the current calculation result. In the CRC-16 algorithm implementation of this scheme, the state of the most significant bit of the calculation result needs to be checked after each left shift operation: if the most significant bit is 1, it indicates that the data overflow requires polynomial correction. At this time, an exclusive OR operation with the preset CRC generator polynomial (such as 0x1021) is performed to eliminate the overflow effect; if the most significant bit is 0, only a simple left shift operation is performed. This mechanism is a key component of the core logic of the CRC algorithm, ensuring the mathematical correctness and error detection capability of the check calculation.

[0029] Least Significant 16 Bits: Refers to the lower 16 bits (bits [15:0]) of the CRC calculation result during the CRC checksum calculation. Higher-order bits are discarded. In this SPD programming solution, due to the use of the CRC-16 checksum algorithm, the final checksum length is fixed at 16 bits. After completing the CRC calculation for each byte, regardless of the number of bits in the intermediate result, only the lowest 16 bits are retained as the valid CRC checksum value. This ensures consistency in checksum length and standardization of the algorithm.

[0030] CRC Reference Value: refers to the 16-bit cyclic redundancy check code pre-stored in a specific register of the SPD chip, which serves as a standard reference value for data integrity verification. This reference value is usually calculated and generated when the SPD chip leaves the factory or is correctly burned for the first time, and is written to the dedicated CRC register of the SPD chip (such as the 0x7E-0x7F address). In the data verification process of this burning solution, the real-time CRC verification result calculated by the embedded controller needs to be compared bit by bit with this reference value: if the two are completely consistent, it indicates that no errors occurred during the SPD data transmission and storage process, and the data integrity is verified; if there is a difference, it indicates that the data may have been damaged during transmission or storage, and the burning operation needs to be performed again.

[0031] Furthermore, the verified SPD data is written to the target chip page by page using the I2C bus, including: reading 16 bytes of data to be written from the starting address of the data buffer, selecting the target I2C physical channel through the data selector and generating an I2C start signal; sending a 7-bit slave address byte, wherein the read / write bit of the address byte is set to 0 to indicate the write operation mode, and waiting for the slave to return an ACK signal to confirm that the address recognition is successful; when the slave returns an ACK signal, starting the data sending sequence, transmitting 16 bytes of data byte by byte in the order of the most significant bit first, and waiting for the slave to return an ACK signal after each byte is transmitted before continuing to transmit the next byte; after completing the 16-byte data page write operation, starting the data readback verification process, reading the written data from the SPD chip through the I2C read operation, and performing row-by-row bit verification with the original written data.

[0032] The I2C physical channel (I2CPhysicalChannel) refers to the specific hardware path for data transmission between the embedded controller and the SPD chip. In this programming solution, the I2C physical channel consists of a two-wire bus consisting of a serial data line (SDA) and a serial clock line (SCL). A data selector (such as a multiplexer) can be used to select a specific target channel from multiple I2C channels, enabling independent access to different SPD chips. This physical channel supports master-slave communication. The embedded controller acts as the master device to control bus timing and data transmission rhythm, while the SPD chip acts as the slave device to respond to read and write operations. The channel's electrical characteristics conform to the I2C standard.

[0033] I2C Start Signal (I2CStartSignal): This is a specific timing signal used in the I2C communication protocol to signal the start of data transmission. In this SPD programming solution, the start signal is generated by transitioning the serial data line (SDA) from a high to a low level while the serial clock line (SCL) remains high. This signal announces to all devices on the bus that a new data transaction is about to begin, and all slave devices enter the listening state to receive address information. The start signal is a key component of the I2C bus arbitration mechanism, ensuring communication order and data integrity in a multi-master environment.

[0034] Slave Address Byte: This refers to the 8-bit address information used to identify the target slave device in I2C communication. In this SPD programming solution, this address byte consists of a 7-bit device address and a 1-bit read / write control bit. The 7-bit device address is determined by the configuration of the SPD chip's A0, A1, and A2 pins and is used to uniquely identify a specific SPD chip on the I2C bus. The least significant bit (LSB) is the read / write control bit; setting it to 0 indicates write mode and 1 indicates read mode. After the master controller sends this address byte, the SPD chip on the bus with a matching address will respond and participate in subsequent data transmissions. Other devices remain silent.

[0035] Acknowledge Signal (ACK): This is the feedback signal used by the slave device in the I2C protocol to confirm successful data reception. In this SPD programming solution, the ACK signal timing is as follows: After the master device transmits 8 bits of data (address byte or data byte), it releases control of the SDA line during the ninth clock cycle. If the slave device successfully receives and recognizes the data, it pulls the SDA line low during this clock cycle to generate an ACK signal (logic 0). If the slave device fails to receive the data correctly or the address does not match, it holds the SDA line high to generate a NACK signal (logic 1). The embedded controller determines the success of communication by monitoring the ACK signal status, providing a basis for subsequent data transmission decisions and error handling.

[0036] Furthermore, initiating the data readback verification process also includes: when the readback verification fails, querying the current retry counter status, and if the number of retries does not exceed a preset threshold, re-initiating the readback operation for secondary verification; preferably, the threshold is set to 3, i.e., 3 retries. If the threshold is exceeded, it is determined to be a data error, and a page erase instruction is sent to the SPD chip, the corresponding page data is retransmitted, and the verification state machine is reset; the buffer register data pointer offset is continuously monitored, and the write progress is determined by comparing it with the total data length register. When the pointer offset reaches the total data length, an I2C stop signal is sent and bus control is released.

[0037] The Retry Counter (RetryCounter) refers to a counter register maintained within the embedded controller that records the number of readback verification failures for the current data page. In this SPD programming solution, when a readback verification failure occurs, the Retry Counter automatically increments by 1. The system compares the current value of this counter with a preset threshold (3 times) to determine whether to continue the retry operation. This counter automatically resets to 0 at the beginning of each new data page, ensuring that each page of data has an independent retry opportunity. The Retry Counter mechanism effectively distinguishes temporary errors caused by transient signal interference from persistent errors caused by hardware failures, improving the system's fault tolerance and data reliability.

[0038] Pointer Offset: This refers to the byte offset of the current processing position in the data buffer relative to the starting address. In this SPD programming solution, the embedded controller maintains a data pointer to track the amount of data written. The pointer offset represents the cumulative number of bytes from the buffer starting address 0x00 to the current processing position. After each 16-byte page of data is successfully written, the pointer offset automatically increments by 16. By comparing it with the total data length register in real time, the system can accurately determine the entire programming progress. When the pointer offset equals the total data length, all data is written.

[0039] Furthermore, the SPD chip is connected to the embedded controller through the I2C interface. The SCL and SDA pins of the SPD chip are directly connected to the corresponding I2C interface pins of the embedded controller. The A0, A1 and A2 pins of the SPD chip are respectively configured to high or low levels for setting the I2C device address to achieve addressing of different SPD chips.

[0040] The SCL and SDA pins (Serial Clock Line and Serial Data Line Pins) refer to the physical connection pins corresponding to the two core signal lines in the I2C bus protocol. The SCL (Serial Clock Line) pin transmits a synchronous clock signal, controlled by the master device (embedded controller), and provides a timing reference for data transmission. The SDA (Serial Data Line) pin is used for bidirectional data transmission, sending and receiving address, data, and control information under the control of the clock signal. In this programming solution, the SPD chip's SCL and SDA pins are directly connected to the corresponding pins on the embedded controller, forming a standard I2C bus communication link that supports open-drain output and bus arbitration.

[0041] I2C interface pins (I2CInterfacePins): These are hardware interface pins on the embedded controller chip specifically used for I2C communication, including the SCL output pin and the bidirectional SDA pin. These pins typically have built-in pull-up resistors and open-drain output characteristics, complying with I2C electrical standards. In this SPD programming solution, the embedded controller establishes a direct hardware connection with the SPD chip through these dedicated I2C interface pins, eliminating the need for additional level conversion or signal conditioning circuitry. This simplifies hardware design and ensures reliable signal transmission and timing accuracy.

[0042] Pins A0, A1, and A2 (Address Selection Pins): These are the three address selection pins on the SPD chip used to configure the I2C device address. In this programming solution, these three pins are connected to either a high voltage (VCC) or a low voltage (GND), respectively. Eight different high and low voltage combinations (000, 001, 010, 011, 100, 101, 110, and 111) are used to set the SPD chip's unique device address on the I2C bus. This address configuration, combined with the SPD chip's base address, forms a complete 7-bit I2C slave address, enabling embedded controllers to precisely address and access different SPD chips on the same I2C bus, enabling multi-chip parallel connection and selective programming.

[0043] Furthermore, a start signal is generated by transitioning the SDA line of the I2C bus from high to low while the SCL line is high, ensuring the execution of the I2C communication protocol. The I2C communication protocol refers to the standardized serial bus protocol used in this SPD programming solution for data communication between the embedded controller and the SPD chip. Developed by Philips (now NXP), this protocol utilizes a two-wire design, requiring only two signal lines: the serial data line (SDA) and the serial clock line (SCL) for full-duplex communication.

[0044] Specifically, in this application, the embedded controller acts as the master device (Master), controlling bus timing and communication rhythm. The SPD chip acts as the slave device (Slave), responding to the master's read and write requests, implementing a unidirectional data transmission mechanism. The protocol specifies strict timing requirements, including standardized operation sequences such as the start signal (SDA transitions from high to low when SCL is high), the stop signal (SDA transitions from low to high when SCL is high), and data transmission timing (SDA changes state when SCL is low and remains stable when SCL is high). A 7-bit or 10-bit device address mechanism is supported. In this solution, multi-device addressing is achieved through the SPD chip's A0, A1, and A2 pins, allowing multiple SPD chips to be connected on the same bus and selectively accessed. An acknowledgement bit (ACK / NACK) is inserted after every 8 bits of data transmission. The slave device generates an ACK signal by pulling the SDA line low to confirm successful data reception. The master device uses this ACK signal to determine the communication status and decide on subsequent operations. This protocol provides a standardized SPD chip access method for embedded controllers, supports efficient data transmission in page write mode, and ensures the reliability of data burning through error detection and retransmission mechanisms at the protocol level. At the same time, its openness and standardization ensure the compatibility and scalability of the solution.

[0045] Another aspect of the present application also provides an SPD burning system based on serial port instructions and an embedded controller, comprising: a serial port communication module, which establishes a serial port connection between a host and a slave, and configures baud rate, data bits, stop bits, and check bit parameters; an embedded controller, which monitors the serial port data buffer by periodic polling, extracts the instruction data packet when a data arrival event is detected, and compares and verifies it with a pre-stored instruction feature library; a data processing module, which receives the SPD data packet input by the user through the serial port, performs data format parsing and multiple verification processing, wherein the multiple verification processing includes regular expression format verification and CRC cyclic redundancy check; an I2C bus interface module, which converts the SPD data after verification into a buffered state. The target chip is written page by page, using a paged write mode, writing 16 bytes of data per page, and controlling the data sending sequence; the readback verification module performs data readback verification after each page data write operation, and compares the readback data with the original written data bit by bit; the error handling module executes a retry mechanism and error recovery process when the readback verification fails. The error recovery process includes re-initiating the readback operation, sending a page erase instruction, and resetting the verification state machine; the SPD chip is connected to the embedded controller through the I2C interface, and the SCL and SDA pins of the SPD chip are directly connected to the corresponding I2C interface pins of the embedded controller, and the A0, A1, and A2 pins are respectively configured to set the I2C device address.

[0046] Compared with the existing technology, the advantages of this application are: (1) The standard I2C bus protocol is used to directly connect the SPD chip and the embedded controller. By directly connecting the SCL and SDA pins of the SPD chip to the corresponding I2C interface pins of the embedded controller, the need for complex level conversion circuits, signal conditioning modules, and dedicated programmers in traditional solutions is eliminated. This design is based on the open-drain output characteristics of the I2C protocol and the built-in pull-up resistor mechanism to ensure that the electrical characteristics of signal transmission meet the specification requirements, reduce hardware implementation costs by more than 60%, and improve the system integration and reliability.

[0047] (2) The real-time dynamic modification capability of SPD configuration parameters is achieved through the serial port command control mechanism. Based on the embedded controller's command parsing engine and the real-time read and write characteristics of the I2C bus, users can send configuration commands through the standardized serial port protocol. The embedded controller parses the commands in real time and converts them into corresponding I2C read and write timings, directly manipulating the register contents of the SPD chip. This mechanism does not require any changes to the hardware architecture of the target system. SPD content updates can be completed only through command interaction at the software level, improving configuration modification efficiency by more than 90%, significantly improving the system's adaptability and ease of maintenance.

[0048] (3) Establish a triple verification architecture, including serial port frame format verification, page write and readback comparison verification, and I2C physical layer ACK / NACK status monitoring, to ensure the end-to-end integrity of data transmission through multi-level verification; implement an intelligent retransmission mechanism, automatically perform up to 3 retry operations when a data error is detected, and dynamically adjust the I2C timing parameters to adapt to different electrical environments, significantly improving the reliability of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The present application will be further described in the form of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting, and in these embodiments, the same numbers represent the same structures, wherein: Figure 1 This is an exemplary flow chart of an SPD programming method based on serial port instructions and an embedded controller according to some embodiments of the present application; Figure 2 This is a flowchart of exemplary sub-steps of data format parsing and verification processing according to some embodiments of the present application. DETAILED DESCRIPTION

[0050] The method and system provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0051] A SPD burning method based on serial port instructions and EC. This debugging method is suitable for computer memory SPD burning and has been put into mass use. The overall process of the method is as follows Figure 1 As shown, the following steps are included: First, you need to physically connect the serial port from the host to the slave. Make sure the required serial cable is ready. Plug one end of the serial cable into the host's serial port and the other end into the slave's serial port. Ensure that the serial port's transmit and receive ports are correctly connected. Connect the host's transmit port to the slave's receive port, and vice versa, to ensure data transmission and reception. After the connection is complete, carefully inspect the serial cable for any bends, damage, or looseness to ensure communication stability.

[0052] Start the communication program on the master and slave devices and configure the corresponding serial port parameters, such as the baud rate, data bits, stop bits, and parity bit. For example, set the baud rate to 112000, the data bits to 8, and the stop bit to 1. These parameters must be consistent on both the master and slave devices. Perform a preliminary communication test to confirm the serial port connection and communication are working properly. Send simple commands and observe the slave device's response to ensure that data is being transmitted correctly.

[0053] When a slave device inputs an SPD programming instruction via the serial port, the embedded controller (EC) implements a multi-level instruction verification mechanism to ensure the legitimacy of the instruction. In practice, the EC monitors the serial port data buffer through periodic polling. Upon detecting a data arrival event, it immediately extracts the most recently received instruction packet. This packet is then fed into the instruction parsing engine for line-by-line verification against the instruction signature library pre-stored in the EC's non-volatile memory. If the instruction fully matches the instruction signature for the SPD programming function, the EC immediately initiates the SPD programming process. The detailed implementation process is described in Step 4. If a match fails, the EC logs an error and returns a command invalid response via the serial port. The EC then continues to poll the serial port data buffer for instructions.

[0054] If the instruction completely matches the instruction signature of the SPD burning function, the SPD burning process will begin. The user burns the SPD chip data in a specific format through the serial port, and the embedded controller (EC) performs intelligent data processing and verification. In specific implementation, after the EC receives the SPD data packet input by the user, it first parses the data format and extracts the valid data fields; then it activates multiple verification mechanisms, including data length verification, regular expression matching, and CRC cyclic redundancy check, such as Figure 2 shown.

[0055] Specifically, this step includes the following sub-steps: When entering SPD byte data in a standardized format through the serial port, each line of user-entered data uses a fixed format of "register offset address + data value". The register offset address is a 1-byte hexadecimal number, and the data value is a 1-byte hexadecimal number, separated by a preset delimiter (such as a space or comma).

[0056] Upon receiving data, the EC first performs a format compliance check, verifying that each line of data contains complete and valid address-value pairs. Specifically, the EC pre-sets the regular expression pattern ^([0-9A-Fa-f]{1,2})[ / s,]+([0-9A-Fa-f]{1,2}). This pattern matches standard SPD data lines. The first capture group extracts the register offset address, and the second capture group extracts the corresponding data value. When receiving SPD data input by the user, the EC applies this regular expression line by line for pattern matching. Upon a successful match, the EC automatically converts the hexadecimal string into a hexadecimal value and stores it in an address-sorted data buffer. For abnormal data lines that fail to match, the EC immediately generates an error report and provides feedback via the serial port.

[0057] When a single row of data is extracted successfully, the pointer automatically increments to point to the next row of data to continue processing. If the data end mark is detected or the preset number of rows is reached, the data extraction is determined to be complete and the CRC check process is immediately started. If not completed, the pointer maintains its current position and continues to process subsequent data rows.

[0058] After the data is extracted, the CRC check process begins. Specifically, the EC performs the following check process: first, the 16-bit CRC check value is initialized to 0x0000, and then the data to be checked is read byte by byte. Each byte is shifted left by 8 bits and then XORed with the current CRC value; then, 8 bit operations are performed on the XOR result, each time shifting left by 1 bit and detecting the state of the highest bit. If the highest bit is 1, XOR is performed with the preset polynomial 0x1021, otherwise only the shift operation is performed; after each byte is processed, the lower 16 bits of the CRC value are retained; the above process is repeated until all data are processed, and finally a 16-bit CRC check result is obtained.

[0059] If the obtained CRC check result is consistent with the result in the corresponding CRC register in the SPD, the CRC check passes.

[0060] When the CRC check passes, the EC writes the parsed and verified SPD data to the target chip page by page through the IC bus interface. The page write mode is adopted, and 16 bytes of data are written per page. A readback check is performed immediately after each page write operation.

[0061] Specifically, this step includes the following sub-steps: The EC reads 16 bits of data starting from the starting address of the buffer register. After selecting the target I2C physical channel through the data selector, the master controller generates a start signal (START). The specific implementation includes: first, the SDA line of the I2C bus is transitioned from high to low during the SCL high level period to generate a start signal, followed by a 7-bit slave address byte, in which the most significant bit (MSB) of the address byte is fixed to 0, indicating write operation mode. The address byte is followed by a 1-bit waiting acknowledgement bit (ACK).

[0062] When the EC detects that the slave returns a valid ACK signal, it immediately starts the data transmission sequence and transmits the 16-bit data in the buffer register in the order of the high bit first (MSB first). After each data byte is transmitted, a 1-clock cycle ACK detection window is automatically inserted. If no valid ACK signal is detected within the preset timeout period, the EC automatically triggers the retransmission mechanism, which includes: regenerating the start signal, sending the slave address byte again (the lowest bit remains 0 to indicate a write operation), and reinitializing the data transmission process.

[0063] After completing the write operation of the 16-bit data page, the EC immediately starts the data readback verification process, and reads the 16-bit data just written from the SPD chip by re-initiating the I2C read operation; the data verification engine inside the EC compares the readback data with the original written data bit by bit. If all bits match successfully, the data pointer is automatically incremented by 16 bits to prepare for processing the next data page.

[0064] When it detects that the readback data fails to compare with the original written data, the EC first queries the current retry counter status. If the number of retries does not exceed the preset threshold (3 times), it immediately re-initiates the readback operation for secondary verification. This mechanism can effectively eliminate misjudgments caused by transient signal interference; If the verification fails three times in a row, it is determined to be a substantial data error, and the EC automatically executes the error recovery process: first, it sends a page erase instruction to the SPD chip, then retransmits the 16-bit data of the page, and resets the verification state machine.

[0065] The EC continuously monitors the data pointer offset of the buffer register and determines the current writing progress by comparing it with the preset total data length register in real time. When it detects that the data pointer offset is less than the total data length, the EC automatically keeps the I2C bus active and continues to read the next data block from the buffer register to perform the write operation. When the pointer offset reaches the total data length, the EC executes the termination sequence: first sending an I2C stop signal (STOP condition), then releasing bus control and updating the completion flag of the status register.

[0066] The invention of the present application and its implementation methods are described schematically above. This description is not restrictive. Without departing from the spirit or basic features of the present application, the present application can be implemented in other specific forms. What is shown in the accompanying drawings is only one of the implementation methods of the invention of the present application, and the actual structure is not limited to this. Therefore, if a person of ordinary skill in the art is inspired by it, without departing from the purpose of the invention, a structural method and embodiment similar to the technical solution are designed without creativity, which should all fall within the scope of protection of the present application. In addition, the word "including" does not exclude other elements or steps, and the word "one" before an element does not exclude the inclusion of "multiple" elements. Words such as first and second are used to indicate names and do not indicate any specific order.

Claims

1. A SPD burning method based on serial port instructions and embedded controller, characterized in that: include: Connect the serial cable between the host and the slave, and configure the serial port parameters, including baud rate, data bits, stop bits, and parity bit; The embedded controller monitors the serial port data buffer through periodic polling. When the data arrival event is obtained, the command data packet is extracted and compared with the pre-stored command feature library for verification. When the command verification is passed, the SPD data packet input by the user through the serial port is received and the data format is parsed and verified; The verified SPD data is written to the target chip page by page using the I2C bus, using the page write mode and performing a readback verification after each page write operation.

2. The SPD programming method based on serial port instructions and embedded controller according to claim 1, wherein: Data format parsing, including: Receive standardized input data, wherein the standardized input data is in a register offset address + data value format, wherein the register offset address and the data value are both in hexadecimal and separated by a preset delimiter; Use a preset regular expression pattern to parse the format of the standardized input data, extract the register offset address and the corresponding data value, and convert the hexadecimal string into a hexadecimal value and store it in a data buffer sorted by address; When a single row of data is extracted, the pointer is incremented to point to the next row of data. When the data end mark is detected or the preset number of rows is reached, the data extraction is determined to be complete and the subsequent verification process is started.

3. The SPD programming method based on serial port instructions and embedded controller according to claim 2, wherein: The preset regular expression pattern contains the first capturing group and the second capturing group, where: The first capture group is used to match a combination of 1 to 2 hexadecimal characters and extract the register offset address; The second capture group is used to match 1 to 2 hexadecimal character combinations and extract the corresponding data values; The regular expression pattern is ^([0-9A-Fa-f]{1,2})[\s,]+([0-9A-Fa-f]{1,2}), where the first capturing group and the second capturing group are separated by whitespace or commas.

4. The SPD programming method based on serial port instructions and embedded controller according to claim 3, wherein: When format parsing of standardized input data fails using a preset regular expression pattern, an embedded controller generates an error report and provides feedback through the serial port to ensure the integrity and correctness of the data input.

5. The SPD programming method based on serial port instructions and embedded controller according to claim 2, wherein: Verification processing, including: Initialize the 16-bit CRC check code and read the SPD data to be checked byte by byte; Perform a left shift XOR operation on each data byte, shift the byte data left by N bits and then perform an XOR operation with the current CRC value; Perform multiple shift operations on the XOR result, shifting left by 1 bit each time and checking the state of the highest bit. If the highest bit is 1, perform XOR with the preset polynomial, otherwise only perform the left shift operation; After each byte is processed, the lowest 16 bits of the calculation result are intercepted as the updated CRC value, and the process is repeated until the check calculation of all data is completed; The final CRC check result is compared with the CRC reference value pre-stored in the SPD to verify data integrity.

6. The SPD programming method based on serial port instructions and embedded controller according to claim 1, wherein: The verified SPD data is written to the target chip page by page using the I2C bus, including: Read 16 bytes of data to be written from the starting address of the data buffer, select the target I2C physical channel through the data selector and generate an I2C start signal; Send a 7-bit slave address byte, where the read / write bit of the address byte is set to 0 to indicate write operation mode, and wait for the slave to return an ACK signal to confirm successful address recognition; When the slave returns an acknowledgment signal, the data transmission sequence is started, and 16 bytes of data are transmitted byte by byte in the order of the most significant bit first. After each byte is transmitted, the slave returns an acknowledgment signal before continuing to transmit the next byte. After completing the 16-byte data page write operation, the data readback verification process is started. The written data is read out from the SPD chip through the I2C read operation and verified row by row bit with the original written data.

7. The SPD programming method based on serial port instructions and embedded controller according to claim 6, wherein: Start the data readback verification process, which also includes: When the read-back verification fails, the current retry counter status is queried. If the number of retries does not exceed the preset threshold, the read-back operation is re-initiated for secondary verification; If the threshold is exceeded, it is determined to be a data error, and a page erase instruction is sent to the SPD chip to retransmit the corresponding page data and reset the verification state machine; Continuously monitor the buffer register data pointer offset and determine the writing progress by comparing it with the total data length register. When the pointer offset reaches the total data length, an I2C stop signal is sent and bus control is released.

8. The SPD programming method based on serial port instructions and embedded controller according to claim 1, wherein: The SPD chip is connected to the embedded controller through the I2C interface. The SCL and SDA pins of the SPD chip are directly connected to the corresponding I2C interface pins of the embedded controller. The A0, A1 and A2 pins of the SPD chip are configured as high or low levels respectively to set the I2C device address to achieve addressing of different SPD chips.

9. The SPD programming method based on serial port instructions and embedded controller according to claim 8, characterized in that: A start signal is generated by switching the SDA line of the I2C bus from high to low during the SCL high level period to ensure the execution of the I2C communication protocol.

10. An SPD burning system based on serial port instructions and embedded controller, characterized in that: include: Serial communication module, establishes a serial port connection between the host and the slave, and configures the baud rate, data bits, stop bits and parity bit parameters; The embedded controller monitors the serial port data buffer through periodic polling. When a data arrival event is detected, the controller extracts the instruction data packet and compares it with the pre-stored instruction signature library for verification. The data processing module receives the SPD data packet input by the user through the serial port and performs data format analysis and multiple verification processing, wherein the multiple verification processing includes regular expression format verification and CRC cyclic redundancy check; The I2C bus interface module writes the verified SPD data into the target chip page by page, using a page write mode, writing 16 bytes of data per page, and controls the data transmission sequence; The readback verification module performs data readback verification after each page data write operation, and compares the readback data with the original written data bit by bit; an error handling module that executes a retry mechanism and an error recovery process when readback verification fails, the error recovery process including re-initiating a readback operation, sending a page erase instruction, and resetting a verification state machine; The SPD chip is connected to the embedded controller through the I2C interface. The SCL and SDA pins of the SPD chip are directly connected to the corresponding I2C interface pins of the embedded controller. The A0, A1 and A2 pins are respectively configured to set the I2C device address.

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