Multi-dimensional test case generation method and device

Abstract

The invention discloses a multi-dimensional test case generation method and device, and relates to the technical field of test case generation, and the method comprises the steps: building a unified causal diagram model through analyzing a schematic circuit diagram, designing a constraint document, simulating data and other multi-source inputs according to the verification demands of a complex electronic system, and automatically generating a multi-dimensional test case, the technical problems that in related technologies, model type dependency is high, natural language constraint analysis operation is lacked, schematic diagrams, design specifications, signal integrity simulation and other data generated in the design stage exist in an isolated mode, overrun scenes are ignored, and the scene coverage local limit is high are solved, and the purpose that multi-source design data are fused, so that the design efficiency is improved is achieved. The unified causal graph model is constructed, and the complete expression of the design intention and the dominance of the implicit knowledge are realized, so that the technical effects of remarkably improving the coverage range of the test scene and the utilization efficiency of the test resources are achieved.

Description

Technical Field

[0001] The present application relates to the technical field of test case generation, and in particular to a method and device for generating multi-dimensional test cases. Background Art

[0002] Currently, electronic design automation (EDA) and hardware verification technologies lack natural language constraint processing, making it difficult to integrate physical laws. Furthermore, boundary testing has significant limitations, significantly impacting the efficiency and reliability of test case generation.

[0003] To solve the above problems, relevant technologies can first streamline the original system model (such as the Simulink design model) and generate an intermediate representation model by extracting the core functional subgraphs related to the test requirements; secondly, establish a mapping relationship between the test target and the model calculation path, and use path tracing technology to ensure that the test cases accurately cover the key functional interfaces and core behavioral logic; finally, automatically construct a test case table based on path constraints and test targets, and systematically generate a complete test plan including input variable combinations, expected outputs and coverage criteria.

[0004] However, the relevant technologies are highly dependent on model types and lack natural language constraint parsing operations. Moreover, the schematics, design specifications, signal integrity simulations and other data generated during the design phase exist in isolation. In addition, the relevant technologies only verify the scope of design requirements and ignore the over-limit scenarios. The scenario coverage is highly limited and needs to be addressed urgently. Summary of the Invention

[0005] The present application provides a multi-dimensional test case generation method and device to at least solve the technical problems in related technologies, such as strong model type dependence, lack of natural language constraint parsing operations, isolated existence of schematic diagrams, design specifications, signal integrity simulation and other data generated in the design stage, ignoring over-limit scenarios, and high limitation of scenario coverage.

[0006] The present application provides a multi-dimensional test case generation method, comprising the following steps: obtaining original multi-source data corresponding to a target electronic system, and converting the original multi-source data into corresponding standardized data, wherein the standardized data includes at least one of a topological map, constraint rules, causal relationships, a boundary condition dictionary, and a fault path list; constructing a topological skeleton corresponding to the target electronic system based on the topological map, converting the constraint rules into virtual constraint nodes, and constructing causal edges and node attributes corresponding to the topological skeleton based on the causal relationships and the boundary condition dictionary, and calculating edge weights corresponding to the causal edges, so as to establish a unified causal graph model corresponding to the target electronic system based on the topological skeleton, the virtual constraint nodes, the causal edges, the node attributes, and the edge weights; performing multi-dimensional testing using the unified causal graph model to generate multiple test case sets, determining resource consumption data and at least one sorting metric corresponding to the multiple test case sets, sorting the multiple test case sets according to the at least one sorting metric, and grouping the sorted multiple test case sets into test cases using the resource consumption data to generate a final test sequence for the target electronic system.

[0007] The present application also provides a multi-dimensional test case generation device, comprising: a data standardization module, configured to obtain original multi-source data corresponding to a target electronic system and convert the original multi-source data into corresponding standardized data, wherein the standardized data includes at least one of a topology map, constraint rules, causal relationships, a boundary condition dictionary, and a fault path list; a causal graph construction module, configured to construct a topology skeleton corresponding to the target electronic system based on the topology map, convert the constraint rules into virtual constraint nodes, and construct causal edges and node attributes corresponding to the topology skeleton based on the causal relationships and the boundary condition dictionary, and calculate edge weights corresponding to the causal edges, so as to establish a unified causal graph model corresponding to the target electronic system based on the topology skeleton, the virtual constraint nodes, the causal edges, the node attributes, and the edge weights; and a test sequence generation module, configured to perform multi-dimensional testing using the unified causal graph model to generate multiple test case sets, determine resource consumption data and at least one sorting metric corresponding to the multiple test case sets, sort the multiple test case sets according to the at least one sorting metric, and group the sorted multiple test case sets into test cases using the resource consumption data to generate a final test sequence for the target electronic system.

[0008] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned multi-dimensional test case generation methods when executing the computer program.

[0009] The present application also provides a non-volatile computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned multi-dimensional test case generation methods are implemented.

[0010] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned multi-dimensional test case generation methods when executed by a processor.

[0011] Through the present application, the original multi-source data corresponding to the target electronic system can be obtained, and the original multi-source data can be converted into corresponding standardized data, wherein the standardized data includes at least one of a topological map, constraint rules, causal relationships, a boundary condition dictionary, and a fault path list; a topological skeleton corresponding to the target electronic system is constructed based on the topological map, and the constraint rules are converted into virtual constraint nodes, and the causal edges and node attributes corresponding to the topological skeleton are constructed according to the causal relationships and the boundary condition dictionary, and the edge weights corresponding to the causal edges are calculated, so as to establish a unified causal graph model corresponding to the target electronic system according to the topological skeleton, virtual constraint nodes, causal edges, node attributes, and edge weights; multi-dimensional testing is performed using the unified causal graph model to generate multiple categories of test case sets, and determine the corresponding test case sets of multiple categories. Resource consumption data and at least one sorting indicator are used to sort multiple test case sets according to at least one sorting indicator, and the resource consumption data is used to group the sorted multiple test case sets into test cases to generate the final test sequence of the target electronic system. Therefore, it can solve the technical problems in related technologies, such as strong model type dependence, lack of natural language constraint parsing operations, isolated existence of schematic diagrams, design specifications, signal integrity simulation and other data generated in the design stage, and ignoring over-limit scenarios, and high scenario coverage limitations. It achieves the technical effect of integrating multi-source design data, constructing a unified causal graph model, realizing the complete expression of design intent and the explicitness of implicit knowledge, thereby significantly improving the coverage of test scenarios and the utilization efficiency of test resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A flowchart of a multi-dimensional test case generation method provided according to an embodiment of the present application; Figure 2 A schematic diagram of the structure of a topology resolver provided in one embodiment of the present application; Figure 3 A schematic diagram of a constraint extractor provided for one embodiment of the present application; Figure 4 A schematic diagram of the principle of a feature analyzer provided in one embodiment of the present application; Figure 5 A schematic diagram of execution logic of data source alignment provided for one embodiment of the present application; Figure 6 A schematic diagram of a construction process of a unified causal graph model provided for one embodiment of the present application; Figure 7 A schematic diagram of the execution flow of a counterfactual test provided for one embodiment of the present application; Figure 8 A schematic diagram of the logical architecture of a multi-dimensional test case generation method provided in one embodiment of the present application; Figure 9 A schematic diagram of the logical architecture of a data preprocessing engine provided for one embodiment of the present application; Figure 10 A schematic diagram of a logical architecture of multi-dimensional data mounting provided for one embodiment of the present application; Figure 11 A schematic diagram of the execution logic of a multi-dimensional test generation algorithm provided in one embodiment of the present application; Figure 12 A schematic diagram of the cause-effect relationship of charge and discharge control of a lithium battery BBU (Battery Backup Unit) provided in one embodiment of the present application; Figure 13 A schematic diagram of cause-effect relationships in a fan array coordinated speed regulation verification process provided by one embodiment of the present application; Figure 14 A schematic diagram of cause-effect relationships in a fan speed regulation verification process in a high-temperature environment provided by one embodiment of the present application; Figure 15 This is an example diagram of a multi-dimensional test case generation device according to an embodiment of the present application.

[0014] Among them, 10-multi-dimensional test case generation device, 100-data standardization module, 200-causal graph construction module, 300-test sequence generation module. DETAILED DESCRIPTION

[0015] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0016] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0017] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0018] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the multi-dimensional test case generation method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0019] An embodiment of the present application provides a multi-dimensional test case generation method.

[0020] like Figure 1 FIG. 1 is a flowchart of a multi-dimensional test case generation method according to an embodiment of the present application, wherein the multi-dimensional test case generation method includes the following steps: In step S101 , original multi-source data corresponding to a target electronic system is acquired and converted into corresponding standardized data, wherein the standardized data includes at least one of a topology map, constraint rules, causal relationships, a boundary condition dictionary, and a fault path list.

[0021] Those skilled in the art should understand that the current electronic design automation and hardware verification fields mainly have the following problems: 1. Data silo problem: Schematics, design specifications, signal integrity simulations, and other data generated during the design phase exist in isolation and lack unified modeling. This results in test case generation relying on local data sources and insufficient coverage.

[0022] 2. Lack of natural language constraint processing: Text constraints in design documents (such as "temperature range -40°C to 85°C") need to be manually encoded into machine rules, which is costly to maintain and prone to errors.

[0023] 3. Difficulty in integrating physical laws: Traditional methods cannot automatically convert physical laws (such as thermal derating effects and Ohm's law) into test constraints, resulting in the lack of verification of multi-physics field coupling scenarios (such as voltage tolerance reduction at high temperatures).

[0024] 4. Limitations of boundary testing: Traditional methods only verify the design requirement range (such as voltage 18-36V) and lack the ability to test out-of-limit scenarios (such as sudden changes to 40V) and counterfactual tests.

[0025] In order to solve the above problems, the embodiments of the present application can build a unified causal graph model based on the verification requirements of complex electronic systems (such as server power modules, high-speed interface circuits, etc.) by parsing multi-source inputs such as circuit schematics, design constraint documents, simulation data, etc., and automatically generate multi-dimensional test cases.

[0026] Therefore, the embodiments of the present application can first obtain the original multi-source data corresponding to the electronic system, which covers five dimensions: circuit topology, design intent, physical characteristics, failure cases and device limits; secondly, the embodiments of the present application can perform data preprocessing operations on the original multi-source data through a topology parser, a constraint extractor, a feature analyzer, a boundary extractor and a fault extractor to obtain corresponding unified structured data such as topology maps, constraint rules, causal relationships, boundary condition dictionaries or fault path lists, and perform naming standardization processing on the unified structured data to obtain corresponding standardized data.

[0027] Therefore, the embodiment of the present application obtains the original multi-source data corresponding to the electronic system and performs data preprocessing and naming standardization operations on it to obtain standardized data, thereby providing reliable data guidance and basis for the subsequent generation of multi-dimensional test cases.

[0028] Optionally, in one embodiment of the present application, original multi-source data corresponding to the target electronic system is obtained, and the original multi-source data is converted into corresponding standardized data, including: obtaining the original multi-source data corresponding to the target electronic system, and performing data preprocessing operations on the original multi-source data to obtain corresponding preprocessed data, and performing data fusion operations on the preprocessed data to generate unified structured data, wherein the unified structured data includes a topological map, constraint rules, causal relationships, boundary condition dictionaries or fault path lists; performing data alignment on the unified structured data to convert the original multi-source data into a unified namespace to generate corresponding standardized data.

[0029] It should be noted that the original multi-source data of the electronic system obtained by the embodiment of the present application includes multiple types of heterogeneous data such as circuit schematics, design documents, simulation reports, and fault records. During the preprocessing of the above-mentioned original data, the embodiment of the present application can convert unstructured data (such as natural language design instructions) into structured tables through a format conversion tool, and perform field extraction and completion on semi-structured data (such as simulation logs in XML (eXtensible Markup Language) format); secondly, through data cleaning, duplicate records are eliminated and outliers (such as parameters that exceed the physical reasonable range) are corrected to obtain unified structured data including topology diagrams (component connection relationships), constraint rules (such as voltage and current limits), causal relationships (such as signal transmission logic), boundary condition dictionaries (such as environmental parameter ranges), and fault path lists (such as historical failure links).

[0030] Afterwards, the embodiments of the present application can use a fuzzy matching algorithm based on a preset domain vocabulary to resolve naming differences in data from different sources, and establish a mapping relationship table across data sources to achieve unique identification association of the same component in the topology map and fault record; process parameter contradictions through a conflict resolution mechanism, and ultimately convert all data into a unified namespace to generate standardized data with consistent format and unified semantics.

[0031] Therefore, the embodiment of the present application converts heterogeneous multi-source data into standardized data through preprocessing and data alignment, thereby eliminating naming and format differences, ensuring data consistency, and providing a high-quality data foundation for the subsequent construction of a causal graph model.

[0032] Optionally, in one embodiment of the present application, original multi-source data corresponding to the target electronic system is obtained, and data preprocessing operations are performed on the original multi-source data to obtain corresponding preprocessed data, and data fusion operations are performed on the preprocessed data to generate unified structured data, including: obtaining original multi-source data corresponding to the target electronic system, wherein the original multi-source data includes circuit schematics, design documents, simulation data, historical fault libraries, and device manuals; parsing the netlist data in the electronic design exchange format in the circuit schematics to extract corresponding component identifications, and based on the component identifications, performing signal flow analysis on the circuit schematics to calculate the path weights of the circuit schematics, and marking the corresponding critical paths according to the path weights to generate a topology diagram through the critical paths; performing text preprocessing on the design documents, and performing regular expression matching operations on the text-preprocessed design documents based on a preset rule template library to obtain corresponding matching results, and converting the matching results into constraint rules.

[0033] It should be noted that the embodiments of the present application can first obtain the original data of five dimensions corresponding to the electronic system in the input layer, including the circuit schematic diagram (EDIF (‌Electronic Design Interchange Format, Electronic Design Interchange Format) / Schematic format), design documents (PDF (Portable Document Format, Portable Document Format) / DOC / natural language), simulation data (SPICE (‌Simulation Program with Integrated Circuit Emphasis, simulation program for integrated circuit simulation‌) / CSV (Comma-Separated Values, comma-separated values) / text report), historical fault library (SQL (Structured Query Language, Structured Query Language)) / XML database) and device manual (PDF / Datasheet).

[0034] Secondly, if Figure 2 As shown, in an embodiment of the present application, a topology parser can be used to parse and process the netlist data in the electronic design exchange format in the circuit schematic diagram to convert the circuit schematic diagram into a topology network that can be processed by a computer. The specific process is as follows: 1. Netlist analysis: By parsing circuit schematics in formats such as EDIF / Schematic, the component entities and their connection relationships in the circuit are extracted; each component is converted into a node in the topology diagram, containing metadata such as component type (resistor / capacitor / MOSFET, etc.) and device parameters (resistance / capacitance / model); the connection relationship is converted into a directed edge between nodes, recording the connection network name (such as VCC (Voltage To Current Converter, circuit voltage), GND (Ground, ground terminal), etc.).

[0035] As an achievable method, an embodiment of the present application can use a recursive descent parser to decompose the netlist hierarchy and identify key grammatical elements, for example, identifying R1 N001 N002 10K as a resistor node and identifying NET N001U1.PIN5 as a connection edge; thereafter, an embodiment of the present application can expand the sub-circuit corresponding to the circuit schematic diagram into a planar network.

[0036] 2. Critical path marking: Based on a user-defined list of critical paths (such as power input and clock source), the system automatically marks component nodes along these paths. For example, in a power module, the path from "input filtering" to "PWM controller" to "MOSFET driver" is marked as a critical path and assigned a higher weight (1.0). This ensures that critical functional paths are prioritized during subsequent test generation.

[0037] In an embodiment of the present application, signal flow analysis may be performed based on forward propagation and backward tracing strategies to calculate path weights, as shown in the following formula:

[0038] In the embodiment of the present application, the power element coefficient can be set to 1.0, the clock element coefficient can be set to 0.8, and the logic element coefficient can be set to 0.5.

[0039] Afterwards, the embodiment of the present application also needs to perform user-defined coverage to support user annotation of critical paths, and merge the automatic analysis results with the user annotations through a hybrid mode.

[0040] 3. Topology map generation: The embodiments of the present application can determine the node attributes corresponding to each component based on the component type, electrical parameters, and critical path markings to convert each component into a corresponding node, and determine the edge attributes between each component based on the connection type (power / signal / ground), network name, and signal direction to convert the connection relationship between the nodes into the corresponding edge, thereby generating a corresponding topological diagram.

[0041] Therefore, the topology diagram constructed in the embodiment of the present application can completely preserve the physical connection relationship of the circuit, providing a skeleton support for subsequent constraint injection and feature association.

[0042] Afterwards, if Figure 3 As shown, the embodiment of the present application further needs to process the design document through a constraint extractor to convert the design specifications described in natural language into structured machine rules to obtain corresponding constraint rules, as described below: 1. Text preprocessing: The PDF / DOC parsing engine extracts the original text, performs segmentation processing, standardizes terminology (for example, "voltage" is described as "Voltage"), and unifies units ("volt" is described as "V"). It also identifies key paragraphs, such as those containing keywords such as "constraint," "range," and "limit."

[0043] 2. Rule template matching: (1) Regular expression matching based on a predefined rule template library: 1) Voltage range: r'(\w+) Voltage range: (\d+)V to (\d+)V' to capture target components and limits; 2) Frequency tolerance: r'(\w+) frequency must be maintained at (\d+)kHz±(\d+)%' to capture the nominal value and deviation; 3) Temperature range: r'Operating temperature: (-?\d+)℃ to (-?\d+)℃' to capture the temperature boundaries.

[0044] Therefore, the embodiments of the present application can support user-defined template extensions and can adapt to different design specification formats.

[0045] 3. Constraint rule generation: The matching results are converted into structured JSON (JavaScript Object Notation) rules (i.e., constraint rules), as described below: { "type": "VOLTAGE_RANGE", "target": "Input level", "min": 18, "max": 36, "unit": "V" } It should be noted that, in the embodiment of the present application, each of the above constraint rules includes a target element, a constraint type, a numerical boundary, and a measurement unit, thereby providing design intent input for subsequent cause-and-effect diagram construction.

[0046] Afterwards, the embodiments of the present application can use a semantic similarity algorithm based on cosine similarity and word embedding strategy to perform fuzzy matching processing, and perform priority sorting according to preset priorities, such as the priority of the schematic diagram annotation is higher than the priority of the design document, and the priority of the design document is higher than the priority of the simulation report, to resolve conflicts.

[0047] Therefore, the embodiments of the present application realize intelligent parsing and rule extraction of electronic design data through multi-source data fusion and structured conversion, significantly improving the design verification efficiency; in addition, the embodiments of the present application accurately restore the circuit connection relationship through the topology parser, and use the constraint extractor to convert natural language specifications into executable rules, combined with the priority mechanism to ensure the reliability of conflict resolution, and provide a complete and accurate input basis for subsequent automated testing.

[0048] Optionally, in one embodiment of the present application, original multi-source data corresponding to the target electronic system is obtained, and data preprocessing operations are performed on the original multi-source data to obtain corresponding preprocessed data, and data fusion operations are performed on the preprocessed data to generate unified structured data, and also includes: data cleaning of the simulation data to obtain corresponding standard data, and calculating the correlation coefficient matrix corresponding to the standard data, and performing thermal effect modeling based on the standard data to construct a corresponding temperature-parameter response model; calculating the corresponding timing margin based on the standard data to determine the corresponding timing relationship through the timing margin, and mapping the correlation coefficient matrix, temperature-parameter response model and timing relationship into a causal relationship; performing a causal chain extraction operation on the historical fault library to obtain a fault path list, and performing a boundary extraction operation on the device manual to obtain a boundary condition dictionary.

[0049] In the actual implementation process, Figure 4 As shown, the embodiment of the present application also needs to mine implicit causal relationships from simulation data through a feature analyzer to extract corresponding physical characteristics and obtain corresponding causal relationships, as described below: 1. Data cleaning: Preprocessing operations such as filling missing values, smoothing noisy data, and normalization are performed on simulation data in SPICE / CSV format to ensure that the data quality meets the analysis requirements.

[0050] 2. Feature extraction: Use corresponding algorithms to extract features for data of different simulation types: (1) Parameter sensitivity: The correlation coefficient matrix is ​​calculated by the following formula to identify strongly correlated parameters:

[0051] in, represents an input variable or parameter. In the embodiment of the present application, X represents a causal factor or independent variable (i.e., input variable change) extracted from simulation data, such as ambient temperature, input voltage, signal frequency, etc.; represents another input variable or parameter. In the embodiment of the present application, Y may represent a result factor or dependent variable (i.e., an output response change) affected by X, such as the on-resistance of a MOSFET, the delay of an output signal, the efficiency of a power module, etc.; Represents the covariance of variables X and Y to measure the trend of changes in the two variables; Represents the standard deviation of variable X, which characterizes the degree of dispersion of X; Represents the standard deviation of variable Y, which characterizes the degree of dispersion of Y; It represents the Pearson correlation coefficient between variables X and Y, indicating the degree of linear correlation between the two variables. Its value ranges from [-1, 1]. =1, indicating a perfect positive correlation. =-1, indicating a completely negative correlation. =0, indicating no linear correlation.

[0052] (2) Thermal coupling effect: Establish a temperature-parameter response model, such as the MOSFET on-resistance temperature rise model, whose mathematical expression is as follows:

[0053] in, represents the on-resistance of MOSFET at temperature T; Indicates the temperature change, i.e. T-25°C, in °C; Indicates the on-resistance at 25°C (i.e., the reference value); It represents the temperature coefficient, which indicates the ratio of resistance change with temperature. The parameter value can be obtained from the device manual.

[0054] (3) Timing relationship: Analyze the signal setup time and hold time to calculate the corresponding timing margin, thereby obtaining the corresponding characteristic relationship.

[0055] 3. Cause and effect mapping: (1) Map feature relationships into edges in a causal graph: 1) Source node: influencing factors (such as temperature); 2) Target node: affected component (e.g. MOSFET); 3) Edge attributes: relationship type (thermal_impact), sensitivity coefficient, and confidence level.

[0056] (2) Calculate the corresponding sensitivity coefficient using the following sensitivity coefficient calculation formula:

[0057] Where X is the change in input variable and Y is the change in output response.

[0058] It should be noted that the cause-effect mapping rules in the embodiment of the present application are shown in Table 1: Table 1

[0059] 4. Model construction: Furthermore, the embodiment of the present application can generate a mathematical expression for the causal relationship, such as a thermal effect equation, and inject the equation into the causal graph as domain knowledge: Rds_on = 0.02*(1+0.0038*(T-25)) in, Indicates the on-resistance of the MOSFET at the current temperature T; T is the current temperature in °C.

[0060] In addition, the embodiments of the present application also need to process the device manual and historical fault library through a boundary extractor and a fault extractor to output a boundary condition dictionary (such as {"MOSFET": {"V_max": 40V}}) and a fault path list.

[0061] Therefore, the embodiments of the present application achieve in-depth mining and modeling of electronic system characteristics through multi-source data fusion and causal analysis; in addition, the embodiments of the present application extract physical characteristics and causal relationships from simulation data through a feature analyzer, and combine boundary and fault information to construct a high-confidence causal graph, thereby providing accurate domain knowledge support for design verification and fault prediction, significantly improving system reliability and analysis efficiency.

[0062] Optionally, in one embodiment of the present application, data alignment is performed on the unified structured data to convert the original multi-source data into a unified namespace to generate corresponding standardized data, including: standardizing the original name of each data in the original multi-source data to obtain the corresponding standard name, and constructing a mapping relationship table between the original name and the standard name; judging whether there is a name conflict among all the standard names according to the mapping relationship table, wherein, in the case that there is a name conflict among all the standard names, different weights are set for the data with name conflicts based on a preset confidence voting strategy to obtain standardized data.

[0063] In the actual implementation process, Figure 5 As shown, the embodiment of the present application performs name standardization on circuit topology nodes, design constraint targets, simulation feature elements, and device manual bodies to convert them into a unified namespace for unified naming. The specific process is as follows: 1. Naming standardization: The embodiments of the present application may use a fuzzy matching algorithm based on Levenshtein distance (i.e., Levenshtein distance or edit distance) to resolve naming differences between different data sources. For example, "Q1" in the schematic diagram is the "main MOSFET" in the design document and the "IRF3205" in the manual.

[0064] 2. Create a mapping dictionary: Generate a mapping relationship table of <original name, standard name>.

[0065] 3. Conflict resolution mechanism: When multiple standard names conflict, a confidence voting strategy is used to set different weights for the data with name conflicts (e.g., design document weight 0.7, schematic weight 0.9).

[0066] Therefore, the embodiments of the present application effectively resolve the naming differences and conflicts of different data sources through naming standardization, establishment of mapping dictionaries and conflict resolution mechanisms, achieve data alignment, generate standardized data, and provide a unified and reliable data foundation for subsequent system modeling.

[0067] Optionally, in one embodiment of the present application, the original name of each data in the original multi-source data is standardized to obtain a corresponding standard name, including: extracting component naming features from the original multi-source data, and constructing a corresponding structured feature vector based on the component naming features; associating the symbol identification and function description in the original multi-source data through a preset domain knowledge graph to construct a corresponding semantic mapping rule; based on the structured feature vector and the semantic mapping rule, adaptively adjusting the editing operation weights corresponding to multiple editing operations corresponding to the fuzzy matching algorithm based on the edit distance, and selecting the target editing operation weights corresponding to the multiple editing operations that meet the preset editing requirements to determine the corresponding standard name according to the target editing operation weight.

[0068] It should be noted that the process of standardizing the original names of the original multi-source data using the fuzzy matching algorithm in the embodiment of the present application is as follows: 1. Extract component naming features from raw multi-source data (such as schematics, design documents, and component manuals), including naming prefixes (such as "R" for resistors), serial numbers (such as "123"), and function suffixes (such as "_power"). Through part-of-speech tagging and feature encoding, a structured feature vector is constructed to accurately represent the naming logic. 2. Relying on a preset domain knowledge graph (covering relationships such as component types, functional attributes, and model parameters), semantically associate symbolic identifiers (such as "Q1") in the original data with functional descriptions (such as "high-voltage switch tube") to generate semantic mapping rules containing synonyms and hyponyms. For example, "MOS tube" and "field-effect transistor" can be mapped to the same functional category. 3. Based on the similarity of the structured feature vectors and the matching degree of the semantic mapping rules, the weights of the insertion, deletion, and replacement operations in the edit distance algorithm are adaptively adjusted. That is, the editing operations of functional feature words (such as "power") are given higher weights, and the editing operations of serial number characters (such as "123") are given lower weights. The matching result corresponding to the maximum editing operation weight is selected as the standard name to ensure that the naming standardization takes into account both structural consistency and semantic accuracy.

[0069] Therefore, the embodiments of the present application optimize fuzzy matching through structural features and semantic associations, thereby achieving accurate standardization of multi-source data naming, effectively eliminating naming differences, and improving data consistency and subsequent processing reliability.

[0070] In step S102, a topological skeleton corresponding to the target electronic system is constructed based on the topological graph, and the constraint rules are converted into virtual constraint nodes. The causal edges and node attributes corresponding to the topological skeleton are constructed according to the causal relationship and boundary condition dictionary, and the edge weights corresponding to the causal edges are calculated to establish a unified causal graph model corresponding to the target electronic system based on the topological skeleton, virtual constraint nodes, causal edges, node attributes and edge weights.

[0071] Furthermore, the embodiments of the present application also need to integrate multiple structured data and complete data alignment to generate standardized data; construct a topological skeleton of the electronic system based on the topological graph, and convert the constraint rules into virtual constraint nodes; then add causal edges and node attributes to the topological skeleton based on the causal relationship and boundary condition dictionary in the data, calculate the weight of the causal edge, and finally construct a unified causal graph model of the electronic system.

[0072] It can be understood that the embodiments of the present application solve the problem of data fragmentation in related technologies by integrating multi-source design data (schematics, constraint documents, simulation reports, historical fault libraries, device manuals) to construct a unified causal graph model, and achieve the complete expression of design intent and the explicitness of implicit knowledge (such as physical effects, historical failure modes), thereby significantly improving the coverage of test scenarios such as multi-physical field coupling and over-limit.

[0073] Therefore, the embodiment of the present application generates a weighted causal graph (the causal graph model is mainly composed of nodes, edges and corresponding node attributes) based on the above-mentioned preprocessed structured data through data integration and structured modeling, thereby realizing a unified representation of the electronic system topology, constraints and causal relationships, improving the integrity and relevance of the model, and providing a reliable basis for subsequent analysis.

[0074] Optionally, in one embodiment of the present application, a topological skeleton corresponding to the target electronic system is constructed based on the topological graph, including: parsing the electronic components in the netlist data of the circuit schematic to obtain corresponding parsed data, and determining the physical nodes corresponding to the electronic components based on the parsed data; extracting the electrical connection relationships in the netlist data, and converting the electrical connection relationships into corresponding causal edges; constructing an initial directed graph based on the causal edges and the physical nodes corresponding to the electronic components, and determining the topological skeleton through the initial directed graph.

[0075] Specifically, when parsing circuit schematic netlist data, the embodiments of the present application can first identify electronic components such as resistors, capacitors, and ICs, extract their models, parameters, and other information, and map each component to a unique physical node to ensure that the node attributes are consistent with the physical characteristics of the component; at the same time, extract the electrical connection relationship in the netlist (such as pin connection, signal transmission path), and convert it into directed causal edges (for example, "output pin of component A-drive signal-input pin of component B") according to the current flow direction and signal driving logic. Secondly, the embodiments of the present application can adopt the netlist-graph structure automatic mapping technology when constructing the initial directed graph based on entity nodes and causal edges, and ensure that the connection relationship is not missed through pin number matching, signal naming association, etc.; for complex modules (such as integrated circuits), sub-nodes are split according to internal functional units, and the hierarchical connection between modules is retained, and finally a topological skeleton is formed that fully reflects the circuit signal flow and connection relationship, thereby ensuring the structural integrity of the circuit topology.

[0076] Therefore, the embodiments of the present application construct a complete topological skeleton through precise mapping of components-nodes, connection relationships-causal edges, clearly presenting the circuit structure and signal flow, and providing a reliable foundation for subsequent circuit analysis.

[0077] Optionally, in one embodiment of the present application, the constraint rules are converted into virtual constraint nodes, and the causal edges and node attributes corresponding to the topological skeleton are constructed according to the causal relationship and boundary condition dictionary, and the edge weights corresponding to the causal edges are calculated, so as to establish a unified causal graph model corresponding to the target electronic system according to the topological skeleton, virtual constraint nodes, causal edges, node attributes and edge weights, including: extracting the number of failures of the target element and the total number of uses of the target element from a preset enterprise fault database, and calculating the corresponding risk coefficient based on the number of failures, the total number of uses and the preset failure severity level; determining the number of Monte Carlo simulations corresponding to the target electronic system, and determining the corresponding confidence level through the number of Monte Carlo simulations, so as to calculate the edge weight based on the risk coefficient and the confidence level.

[0078] It should be noted that if Figure 6 The specific process of establishing a causal graph (i.e., a unified causal graph model) in the embodiment of the present application through operations such as multi-source data input, constraint node embedding, physical rule injection, dynamic weight assignment, and causal graph output is as follows: 1. Multi-source data input: Input the standardized data after data preprocessing and data alignment of the original multi-source data.

[0079] 2. Constraint node embedding (design intent fusion): (1) Input data: natural language constraints in design documents; (2) Processing: 1) Identify key parameter boundaries (e.g., “voltage is not greater than 36V”) through NLP (Natural Language Processing); 2) Create a virtual constraint node (CONST_ type); 3) Establish constraint relationships between virtual constraint nodes: constraint node-constraint relationship-target component, for example, CONST_Voltage - "constrains" - MOSFET_Gate.

[0080] 3. Physical rule injection (domain knowledge enhancement): (1) Input data: physical law library and simulation data; (2) Processing: 1) Load predefined physical rules (Ohm's law, thermal derating curve, etc.); 2) Instantiate the physical rules into super nodes; 3) Establishing governing relationships: physical rules - "governs" - related component groups; 4) Supernodes have global influence and can propagate effects across levels. The scope of control of supernodes is determined by the scope of physical laws. In the embodiments of this application, circuit-level laws (such as Kirchhoff's laws) govern the entire graph; component-level laws (such as MOSFET temperature rise model) govern the associated component group.

[0081] 4. Dynamic weight assignment (quantifying the strength of causal relationships): The embodiment of the present application can first determine the number of Monte Carlo simulations corresponding to the electronic system, and determine the corresponding simulation data confidence through the number of Monte Carlo simulations, and obtain historical failure statistics based on the component failure probability, so as to determine the corresponding risk coefficient through the historical failure statistics. Secondly, the embodiment of the present application can calculate the corresponding edge weight based on the risk coefficient and the simulation data confidence, in combination with the following: W edge = k 1• + k 2•

[0082] in, represents the simulation confidence; Represents the risk coefficient; from the above formula, we can see that the higher the edge weight, the more significant the corresponding causal relationship.

[0083] It should be noted that the calculation expression of the simulation confidence in the embodiment of the present application is: in, is the number of Monte Carlo simulations.

[0084] The calculation expression of risk coefficient is:

[0085] in, Indicates the number of failures of the target component in the historical fault database (i.e., failure statistics under specific conditions). This can generally be obtained from the enterprise fault database or SQL record data (such as the number of MOSFET failures in overvoltage scenarios); Indicates the total number of times the target component has been used (including normal and failure conditions), which can generally be obtained from production batch record data or device manuals (total number of times a certain model of MOSFET has been used); Indicates the severity level of the failure (according to the quantification of the consequences of failure, industry standards (such as JEDEC JESD94), the severity level can be divided into: catastrophic = 1.0, severe = 0.7, moderate = 0.4).

[0086] 5. Cause and effect diagram output: Output is a unified causal graph model consisting of nodes, edges and attributes.

[0087] It can be understood that the embodiment of the present application realizes the automatic embedding of domain knowledge by introducing super nodes representing physical laws and establishing a dominant relationship between them and related component groups, so that the generated test cases can more accurately reflect the behavior of actual physical systems.

[0088] Therefore, the embodiments of the present application construct comprehensive and accurate constraints and causal relationships through operations such as embedding constraint nodes to integrate design intent, injecting physical rules to enhance domain knowledge, and dynamically assigning weights to quantify causal strength, thereby improving the reliability and analysis depth of the electronic system model.

[0089] In step S103, multi-dimensional testing is performed using a unified causal graph model to generate a multi-category test case set, and resource consumption data and at least one sorting indicator corresponding to the multi-category test case set are determined to sort the multi-category test case set according to the at least one sorting indicator, and the resource consumption data is used to group the test cases of the sorted multi-category test case set to generate a final test sequence for the target electronic system.

[0090] Afterwards, the embodiments of the present application can use the unified causal graph model to perform multi-dimensional testing to generate multiple test case sets, and perform sorting optimization and resource grouping operations on the multiple test case sets to obtain an optimized executable test sequence, that is, the final test sequence.

[0091] Therefore, the embodiments of the present application prioritize coverage of critical paths and high-risk components through a test sequence generation strategy based on weight optimization, thereby improving the utilization efficiency of test resources and the targetedness of test execution.

[0092] Optionally, in one embodiment of the present application, a unified causal graph model is used for multi-dimensional testing to generate multiple types of test case sets, including: identifying critical signal paths in the unified causal graph model, and generating input and output verification data under standard working conditions based on the critical signal paths, so as to perform design verification testing through the input and output verification data, and output a design verification test case set that meets preset verification function requirements; extracting limit values ​​of virtual constraint nodes in the unified causal graph model, and performing boundary test operations based on the limit values ​​to obtain a boundary test case set; injecting defect information into the unified causal graph model through a historical fault library to perform fault injection testing on the unified causal graph model to generate a fault injection test case set.

[0093] It should be noted that the embodiments of the present application can use a unified causal graph model to perform multi-dimensional testing to generate a corresponding test case set, as described below: 1. Design verification test: (1) Generation principle: Generate corresponding test cases along the main path of the causal graph; (2) Test steps: Step 1: Identify high-weight critical paths (e.g., clock-logic-output); Step 2: Generate standard input combinations and expected outputs to obtain a design verification test case set that meets the preset verification function requirements (i.e., a design verification test case set with correct output verification function).

[0094] 2. Boundary testing: (1) Generation principle: exploring parameter boundary combinations; (2) Test steps: Step 1: Extract the constraint node limit values ​​(e.g., Vmin=18V, Vmax=36V); Step 2: Cartesian product combination parameters (such as voltage, temperature, and frequency combination parameters: 36V@85℃, maximum clock frequency) to obtain a boundary test case set.

[0095] 3. Fault injection testing: (1) Generation principle: simulate component failure; (2) Test steps: Step 1: Map the fault library to causal nodes (e.g. resistor open circuit); Step 2: Activate the vulnerable path to generate abnormal scenarios to generate a set of fault injection test cases.

[0096] Therefore, the embodiments of the present application generate a multi-dimensional test case set of design verification, boundaries, and fault injection based on a unified causal graph model, thereby covering critical paths, parameter boundaries and failure scenarios, comprehensively verifying system performance, and improving test integrity and effectiveness.

[0097] Optionally, in one embodiment of the present application, a critical signal path in a unified causal graph model is identified, and input and output verification data under standard working conditions is generated based on the critical signal path, so as to perform design verification testing through the input and output verification data, and output a set of design verification test cases that meet the preset verification function requirements, including: constructing a digital twin dynamic mapping model based on the main path of the unified causal graph model, and synchronizing the physical parameters and virtual simulation parameters of the critical signal path in real time through the digital twin dynamic mapping model, wherein the physical parameters include signal transmission delay and logic unit temperature drift coefficient, and the virtual simulation parameters include path node state variables and signal attenuation model; based on a preset reinforcement learning algorithm, training the digital twin dynamic mapping model, using the input and output verification results under standard working conditions as the reward function, and generating a test sequence generation strategy for adaptive critical signal path parameter drift; injecting multi-dimensional disturbance factors into the identified critical signal path according to the test sequence generation strategy to generate an extended test sequence including disturbance response verification; performing virtual-real comparison analysis on the extended test sequence through the digital twin dynamic mapping model to output a set of design verification test cases that meet the preset verification function requirements.

[0098] In the specific implementation process, during the design verification test, the embodiment of the present application can first combine the main path of the unified causal graph model with the high-weight critical path (such as the clock-logic-output path) to accurately identify the core signal transmission link; based on this, a digital twin dynamic mapping model is constructed to synchronize the physical parameters of the critical path (signal transmission delay, logic unit temperature drift coefficient, etc.) and virtual simulation parameters (path node state variables, signal attenuation model, etc.) in real time to achieve linkage between virtual and real parameters. Secondly, the embodiments of the present application can use a preset reinforcement learning algorithm to train the model, and use the matching degree of input and output verification results under standard working conditions as the reward function to generate a test sequence generation strategy that can adaptively adapt to critical path parameter drift (such as signal delay caused by temperature drift); subsequently, the embodiments of the present application can inject multi-dimensional disturbance factors (such as voltage fluctuations and frequency deviations) along the identified critical path to generate an extended test sequence including disturbance response verification, covering parameter drift scenarios. Finally, the embodiment of the present application can use the digital twin model to perform virtual-to-real comparison analysis on the extended test sequence (cross-checking the physical measured data with the virtual simulation results) to screen out the correct functional verification sequence and form a design verification test case set. Therefore, the embodiments of the present application integrate digital twins and reinforcement learning to accurately cover critical paths and parameter drift scenarios, improve test adaptability and verification depth, and ensure the comprehensiveness and accuracy of design verification.

[0099] Optionally, in one embodiment of the present application, the limit values ​​of the virtual constraint nodes in the unified causal graph model are extracted, and based on the limit values, boundary testing operations are performed to obtain a boundary test case set, including: semantically annotating the limit values ​​of the virtual constraint nodes based on a pre-built parameter association knowledge graph to obtain multiple parameters with semantic information, and obtaining implicit constraint relationships between multiple parameters through a preset graph neural network; based on the parameter association knowledge graph and the implicit constraint relationship, an adaptive particle swarm optimization algorithm is used to generate boundary combination samples, and the boundary combination samples are extended and verified through a preset Monte Carlo simulation strategy to obtain a boundary test case set.

[0100] It should be noted that during boundary testing, the embodiments of the present application can first extract limit values ​​from the virtual constraint nodes of the unified causal graph model, semantically annotate these limit values ​​in combination with the parameter association knowledge graph, and clarify the physical meaning of the parameters (such as the voltage upper limit and the temperature critical value); secondly, the implicit constraint relationship between parameters (such as the coupling effect of voltage and temperature) is mined through the graph neural network. Afterwards, the embodiment of the present application can generate boundary combination samples based on the knowledge graph and implicit constraint relationships, and adopt an adaptive particle swarm optimization algorithm to replace the traditional Cartesian product combination and reduce redundant samples; at the same time, a Monte Carlo simulation strategy is introduced to perform random perturbation expansion on the samples (such as fluctuations within the limit value ±5%) to verify the impact of slight changes in parameters on the system, and finally form a boundary test case set covering explicit and implicit constraint relationships. Therefore, the embodiment of the present application optimizes parameter combinations through semantic annotation and implicit relationship mining, and improves boundary scenario coverage through simulation expansion, thereby enhancing test accuracy and efficiency and comprehensively verifying the adaptability of system boundaries.

[0101] Optionally, in one embodiment of the present application, defect information is injected into the unified causal graph model through a historical fault library to perform a fault injection test on the unified causal graph model to generate a fault injection test case set, including: based on the historical fault library, extracting at least one typical fault mode that meets the fault occurrence frequency, so as to establish a multidimensional fault model library based on at least one typical fault mode; determining at least one vulnerable node in the unified causal graph model that meets the preset vulnerability requirements, and establishing a dynamic mapping relationship between the multidimensional fault model library and at least one vulnerable node, so as to construct a fault path set based on the dynamic mapping relationship; determining the test requirements corresponding to the target server, and selecting multiple target nodes from the fault path set according to the test requirements, and determining the target fault mode corresponding to the multiple target nodes in the multidimensional fault model library; injecting the target fault mode into the unified causal graph model to generate a fault injection test case set.

[0102] Specifically, during the fault injection test, the embodiment of the present application can first extract high-frequency typical fault modes (such as open resistors and short capacitors) from the historical fault library to build a multi-dimensional fault model library covering electrical failures and logical errors; secondly, the embodiment of the present application can be combined with a unified causal graph model to identify vulnerable nodes (such as high-power components and signal bottleneck nodes) through node load rates and connection edge weights, and establish a dynamic mapping between fault models and vulnerable nodes (such as mapping "overvoltage breakdown" to power tube nodes). Again, the embodiments of the present application can screen key target nodes from the fault path set according to the server testing requirements (such as reliability verification and fault tolerance testing), and match the corresponding target failure mode (such as injecting a "voltage drop" failure into the power module); thereafter, the embodiments of the present application can inject the failure mode into the model, trace the propagation path of the failure in the causal graph (such as the chain effect from the power node to the logic unit), activate the vulnerable path to generate abnormal scenarios, and finally form a set of fault injection test cases covering typical failures and critical paths. Therefore, the embodiments of the present application fully activate abnormal scenarios by accurately mapping typical fault modeling and vulnerable nodes, and combining demand screening with target faults, thereby improving the pertinence and coverage of fault testing and ensuring the system reliability verification effect.

[0103] Optionally, in one embodiment of the present application, multi-dimensional testing is performed using a unified causal graph model to generate a multi-category test case set, which also includes: determining the target constraint node in the unified causal graph model, and extracting all thermally related input edges of the target constraint node; determining the edge weights and direct sensitivity of all thermally related input edges, and calculating the thermal sensitivity of all thermally related input edges based on the edge weights and direct sensitivity; fitting historical fault data in a historical fault library to obtain corresponding sensitivity attenuation coefficients, and calculating the safety margins of all thermally related input edges based on a preset material maximum tolerance coefficient and basic safety offset, and combining the sensitivity attenuation coefficient and thermal sensitivity; calculating the breakthrough values ​​corresponding to all thermally related input edges based on the safety margins, and constructing a counterfactual test case set based on the breakthrough values.

[0104] It should be noted that if Figure 7 As shown, the embodiment of the present application can be based on the exploratory testing principle of breaking through design constraints, by executing steps such as locating constraint nodes, calculating safety margins, deriving breakthrough values, and constructing test scenarios to construct a set of counterfactual test cases. Among them, the mathematical expression of the safety margin calculation model is as follows:

[0105] in, Represents thermal sensitivity (which can be calculated through causal graph transfer); k Represents the attenuation coefficient, the default value can be set to 0.5, α andβ are all material calibration parameters obtained by fitting historical failure data, among which, α is the maximum tolerance coefficient of the material, β As the basic safety offset.

[0106] In the embodiments of the present application, the thermal sensitivity The calculation process is as follows: 1. Extract all heat-related incoming edges of the target constraint node from the causal graph and calculate the weighted sensitivity as shown in the following formula:

[0107] in, represents edge weight (0.0~1.0); Represents the direct sensitivity determined through simulation calculations.

[0108] For example, a MOSFET node has three incoming edges: 1) Ambient temperature - junction temperature: =0.8, S =0.5; 2) Power consumption-junction temperature: =0.9, S =0.7; Therefore, the corresponding thermal sensitivity of the MOSFET node is: .

[0109] Furthermore, the embodiment of the present application can also determine the sensitivity attenuation coefficient by fitting historical fault data using the least squares method. k The specific process is as follows: 1. Collect fault data: S (Thermal Sensitivity) and Critical Margin ; 2. Optimization k Minimize the error: ,in, Indicates the margin value calculated according to the above safety margin calculation model.

[0110] In the embodiment of the present application, the material calibration parameter α 、 β and sensitivity attenuation coefficient k The physical meaning and determination method of are shown in Table 2: Table 2

[0111] In addition, the embodiment of the present application can also calculate the corresponding edge weight through the confidence Confidence, risk factor Risk and corresponding weight coefficient. The calculation expression of the edge weight is as follows:

[0112] in, and is the weight coefficient, and its default configuration is =0.7, =0.3.

[0113] In addition, the optimization results based on 200 sets of historical verification cases are When >0.8, the confidence level is too high, resulting in a 15% increase in the missed rate of boundary tests; when When it is >0.5, the risk weight is too high, causing the false alarm rate of the counterfactual test to increase by 22%.

[0114] Therefore, in the embodiments of the present application, (default ), the embodiment of the present application can be used for and The coefficient is dynamically configured, such as in high-risk applications it can be increased .

[0115] After obtaining the safety margin, the embodiment of the present application can calculate the corresponding breakthrough value (i.e., test value) based on the safety margin to quantitatively evaluate the critical point close to failure but not documented. The calculation expression of the test value is shown as follows: Test value = constraint value × (1 + margin) Test value = constraint value × (1 + margin) It is understandable that the essential difference between counterfactual testing and boundary testing is that boundary testing verifies the combination within the design constraint boundary; counterfactual testing actively and computationally breaks through the constraint boundary (based on the margin model) to explore the consequences of violating the constraint and the location of the critical point.

[0116] Therefore, the embodiments of the present application automatically generate counterfactual test cases based on the causal graph model and the safety margin calculation model, thereby being able to break through design constraints to explore boundaries, actively discover potential critical points of failure, and improve the ability to detect potential defects.

[0117] Optionally, in one embodiment of the present application, resource consumption data and at least one sorting indicator corresponding to multiple categories of test case sets are determined to sort the multiple categories of test case sets according to at least one sorting indicator, and the resource consumption data is used to group the sorted multiple categories of test case sets to generate a final test sequence for the target electronic system, including: determining the edge weights and component failure rates of each category of test case sets in the multiple categories of test case sets, and sorting the multiple categories of test case sets according to the edge weights and component failure rates respectively to generate corresponding executable test sequences; determining the resource consumption data of each category of test case sets, and grouping the executable test sequences according to the resource consumption data to obtain the final test sequence.

[0118] Specifically, when optimizing the test sequence, the embodiment of the present application can first extract the edge weights (reflecting the criticality of the path) and the failure rates of the components involved (reflecting the failure risk) of multiple types of test case sets, and use a weighted summation method to calculate the comprehensive priority (the critical path weight accounts for 60%, and the failure rate accounts for 40%), and generate executable test sequences in descending order of priority to ensure that the use cases corresponding to high-weight paths and high-risk components are executed first. Secondly, the embodiment of the present application can analyze the resource consumption data of each type of use case (such as power load, test interface occupancy, and execution time), identify parallel use cases (such as shared power modules and tests of non-conflicting interfaces) through a resource dependency graph, and perform clustering and grouping; thereafter, the embodiment of the present application can sort resource-conflicting use cases (such as exclusive core test instruments) in a ladder of execution time, and ultimately form a final test sequence that takes into account both priority and resource efficiency.

[0119] Therefore, the embodiments of the present application prioritize coverage of critical and high-risk scenarios through comprehensive sorting, and achieve parallel execution through resource grouping, thereby improving testing efficiency and timeliness of problem discovery, and optimizing resource utilization.

[0120] In addition, in one embodiment of the present application, resource consumption data for each type of test case set is determined, and executable test sequences are grouped according to the resource consumption data to obtain a final test sequence, including: collecting resource consumption data and historical execution parameters of various test cases to construct a dynamic resource dependency graph; based on the dynamic resource dependency graph, in combination with the shared resource load threshold, identifying use cases that can be executed in parallel, grouping them through an adaptive clustering algorithm to form a dynamic parallel test group; for test cases with resource conflicts, after sorting them by execution time, introducing a priority weight coefficient for secondary sorting; real-time monitoring of resource occupancy status, dynamically adjusting the test sequence, and optimizing the execution order in combination with a machine learning prediction model to generate a final test sequence.

[0121] Specifically, the process of generating a test sequence based on priority and resource efficiency in the embodiment of the present application is as follows: 1. Dynamic resource data collection and graph construction: In addition to collecting hardware and software resource consumption data, it also adds parameters such as historical execution success rate and resource fluctuation coefficient. It builds dynamic graphs through time-series correlation analysis and updates resource dependencies in real time.

[0122] 2. Adaptive clustering grouping: After identifying independent use cases based on the dynamic graph, the system automatically adjusts the clustering granularity using a density clustering algorithm based on load thresholds for shared resources like power supplies (e.g., 80% of the maximum power). When the shared resource load exceeds the threshold, some use cases are split into new groups.

[0123] 3. Weighted conflict sorting: Resource conflict use cases are first sorted by duration, and then a priority weight coefficient (1-10) is introduced. Secondary sorting is performed using the formula "adjustment value = duration × (1 / weight)" to ensure that high-priority use cases are executed first in the same duration interval.

[0124] 4. Intelligent dynamic optimization: By monitoring resource utilization in real time, we trigger parallel group splitting when the idle rate of a resource exceeds 30%. We also use the LSTM (Long Short-Term Memory) model to predict deviations in use case execution times and dynamically adjust the sorting sequence.

[0125] Therefore, the embodiments of the present application, based on the introduction of dynamic adjustment and intelligent prediction, further improve resource utilization, shorten the test cycle, and achieve a precise balance between priority and efficiency through adaptive clustering and weighted sorting.

[0126] The following describes the execution logic of the multi-dimensional test case generation method of the present application in conjunction with the accompanying drawings.

[0127] Figure 8 This is a diagram of the logical architecture of the multi-dimensional test case generation method of this application. Figure 8 As shown, the present application can first obtain circuit schematics, design documents, simulation data, historical fault libraries and device manuals at the input layer, and preprocess the circuit schematics, design documents, simulation data, historical fault libraries and device manuals through a data preprocessing engine to obtain corresponding unified structured data, and construct a unified causal graph model based on the unified structured data; based on the unified causal graph model, a four-dimensional test generation operation including design verification testing, boundary testing, fault injection testing and counterfactual testing is performed to construct a test case library based on the obtained test cases.

[0128] Figure 9 This is a diagram of the logical architecture of the data preprocessing engine. Figure 9 As shown, the embodiment of the present application can parse the circuit schematic diagram through a topology parser to obtain a corresponding topology diagram; perform constraint extraction on the design document through a constraint extractor to obtain corresponding constraint rules; perform feature analysis on the simulation data through a feature analyzer to obtain corresponding causal features; perform causal chain extraction on the historical fault library through a fault extractor to obtain the corresponding fault causal chain; perform boundary extraction operation on the device manual through a boundary extractor to obtain corresponding operating limits; furthermore, the present application can perform multi-source data fusion on the topology diagram, constraint rules, causal features, fault causal chains and operating limits to obtain a corresponding unified data structure.

[0129] In the process of multi-source data processing, the input data types and processing methods are shown in Table 3: Table 3

[0130] It is understandable that unified structured data is the final product of multi-source data fusion. Its essence is to build a cross-domain knowledge graph. The design of this data follows the following principles: 1. Topological skeleton principle: The circuit topology diagram is used as the basic framework, and other data are used as attribute annotations; 2. Causal relationship principle: Establish a causal relationship chain between design constraints, physical characteristics and failure modes; 3. Dynamic evolution principle: support incremental updates based on subsequent test feedback.

[0131] After obtaining the unified structured data, the embodiment of the present application can align the data sources of the unified structured data to unify the namespace and obtain the corresponding standardized data; further, Figure 10 As shown, the embodiment of the present application can perform a multi-dimensional data mounting operation on the standardized data to mount the design constraints, simulation features, boundary conditions and failure modes in the standardized data to the corresponding topological nodes. The specific process is as follows: 1. Constrained mounting: (1) Locate the nodes of the constraint target in the topology graph; (2) Create a "design constraint" attribute group to store the constraint type and value range; (3) Establish a "constraint relationship" edge from the constraint node to the target element.

[0132] 2. Feature Fusion (1) Convert simulation features into causal edges: for example, temperature node-thermal effect-MOSFET node; (2) Quantitative attributes: sensitivity coefficient (0.0~1.0), confidence level (0.0~1.0).

[0133] 3. Boundary injection: (1) Extract the operating limit values ​​from the device manual; (2) Create a "Boundary Conditions" property group containing electrical / thermal / mechanical limits.

[0134] 4. Failure Path Integration: (1) Convert the causal chain of historical faults (overvoltage-insulation failure-short circuit) into a path sequence; (2) Add the "Failure Risk" label to the corresponding node.

[0135] Therefore, the embodiment of the present application constructs a causal graph model through the above process, and based on the multidimensional test generation algorithm, performs multidimensional testing and test sequence optimization on the causal graph model to establish a corresponding test case library.

[0136] Among them, the execution logic of the multidimensional test generation algorithm is as follows Figure 11 As shown by Figure 11 It can be seen that the embodiments of the present application can perform design verification testing, boundary testing, fault injection testing and counterfactual testing through causal graph traversal, and perform test sequence optimization to build a test case library.

[0137] The following describes the execution process of the multi-dimensional test case generation method of the present application through specific embodiments and in conjunction with the accompanying drawings.

[0138] Specific Example 1: BBU charging and discharging strategy verification: Test object: Lithium battery BBU charge and discharge control.

[0139] 1. Data fusion process: (1) Topology parser: 1) Input BBU schematic (EDIF format); 2) Parsing the netlist (recursive descent method); 3) Extract key paths (e.g., "charging IC-MOSFET-battery cell") and generate a topological skeleton. Nodes include physical components (MOSFET, voltage sensor), and edges record connection relationships (drive signal, power network).

[0140] (2) Constraint Extractor: 1) Input design document (PDF); 2) Matching rule template (e.g. "Charging voltage range: 18V-36V"); 3) Generate structured rules: { "type": "VOLTAGE_RANGE", "target": "Charging IC", "min": 18, "max": 36,"unit": "V"}.

[0141] (3) Feature Analyzer: 1) Input cell aging simulation data (CSV); 2) Extract the capacity decay model (capacity after 500 cycles = initial value × 0.8); 3) Generate sensitivity coefficient: the effect of temperature on internal resistance ( S =0.7).

[0142] (4) Boundary extraction: 1) Input device manual; 2) Extract the operating limit of the battery cell (pulse discharge rate is not greater than 20C).

[0143] 2. Causal Modeling Figure 12 Figure 1 is a cause-effect relationship diagram for the charge and discharge control of lithium battery BBU. Figure 12 As described above, during the charging process, when the temperature drops, the internal resistance increases, resulting in a decrease in charging efficiency; during the discharging process, when the load suddenly increases, the discharge depth becomes abnormal, resulting in damage to the battery cell.

[0144] It should be noted that the key nodes, important edges, weights, and weight calculation process of the causal modeling process are as follows: (1) Key nodes: 1) Physical nodes: MOSFET_Q1, Cell_Cell1 (including parameters: internal resistance = 5mΩ); 2) Constraint node: CONST_Voltage (min=18V, max=36V); 3) Supernode: Thermal_Derating (thermal derating law, governing changes in cell internal resistance).

[0145] (2) Important edges and weights: 1) Causal edge: ambient temperature - [thermal_impact, W=0.8] - cell internal resistance (weight based on simulation confidence); 2) Constraint edge: CONST_Voltage-[constrains, W=1.0]-MOSFET_Gate; 3) Physical governing edge: Thermal_Derating -[governs]-cell group (global propagation effect).

[0146] (3) Weight calculation: .

[0147] 3. Test generation: (1) Design verification test: Generate standard scenario use cases (25°C environment, 20A constant current charging); (2) Boundary test: combined limit parameters (-10℃ environment + 20C pulse discharge); (3) Fault injection: simulate BMS (Battery Management System) voltage detection ±5% deviation; (4) Counterfactual test generation: 1) Target constraint: The sudden load increase is no more than 100% of the rated value; 2) Margin calculation: Sensitivity (temperature - internal resistance) + 0.9 × 0.7 (load - damage) = 1.03; Margin = ≈ 0.21 (α=0.15 for silicon-based materials, k=2.0 fitting parameter); 3) Breakthrough value: test load = 100% × (1 + 0.21) = 121%; 4) Test significance: Verify the failure mechanism (such as voltage sag) of 80% aged cells at the critical overload point, revealing undocumented safety margins; 5) Priority rule: select constraint nodes in descending order of risk factor .

[0148] 4. Verification indicators: (1) Charging efficiency is not less than 92% (reference design specifications): by covering the "charging IC-battery cell" causal path; (2) Over-discharge protection response is no more than 10ms: The "voltage detection-shutdown logic" path (weight 0.95) in the causal diagram verifies the signal transmission delay.

[0149] Specific Example 2: Verification of fan array coordinated speed regulation: Test object: Multi-fan wind speed coordination controlled by a PID (Proportion Integration Differentiation) controller.

[0150] 1. Data Fusion (1) Topology parser: 1) Input fan drive schematic; 2) Extract PWM (Pulse Width Modulation Controller) and temperature sensor nodes.

[0151] (2) Constraint Extractor: 1) Parsing design documents; 2) Capture the "speed fluctuation ≤ 3%" text constraint.

[0152] (3) Feature Analyzer: 1) Input CFD (Computational Fluid Dynamics) airflow simulation; 2) Generate dead zone distribution and resonant frequency characteristics (800-1200Hz).

[0153] 2. Causal Modeling Figure 13The diagram below is a cause-effect relationship diagram during the verification process of fan array coordinated speed regulation. Figure 13 As shown in Figure 1, the causal relationship in the fan array coordinated speed regulation verification process is as follows: First, when a single fan fails, the vibration intensifies, resulting in airflow imbalance, causing temperature false alarms, and then PID overcompensation, and finally leading to bearing wear.

[0154] The key edges and supernodes involved in this causal modeling are as follows: (1) Critical side: Single fan failure - - bearing wear (weighting based on failure statistics); (2) Supernode: (Dominates controller temperature drift effects).

[0155] 3. Counterfactual testing: (1) Constraint: The temperature sensor error is no more than 1°C; (2) Margin calculation: S = 0.85 (temperature drift sensitivity), margin = 0.18, so the breakthrough value = 1℃×1.18≈1.2℃; (3) Test scenario: simulate sensor failure and master control communication delay to verify PID anti-interference capability.

[0156] 4. Verification indicators: (1) Temperature control accuracy ±0.8°C: achieved through injection sensor deviation test; (2) Speed ​​fluctuation is no more than 3% (reference JEDEC JESD94 standard): the cause-effect diagram covers the vibration transmission path to ensure.

[0157] Example 3: Verification of fan speed regulation in high temperature environment: Test object: Temperature-speed curve adaptive adjustment circuit.

[0158] 1. Data Fusion (1) Importing the material thermal expansion coefficient (fan gap change), integrating the high-temperature bearing lubrication characteristics, and combining the PID parameter temperature drift model; (2) Feature Analyzer: Input the bearing high-temperature lubrication data and construct a thermal expansion model (the clearance change rate is 0.05 μm / °C); (3) Boundary extraction: The upper limit of bearing temperature in the device manual is 120°C.

[0159] 2. Causal Modeling Figure 14 The diagram below is a cause-effect relationship diagram during the verification process of fan speed control in a high temperature environment. Figure 14As shown in the figure, the cause-effect relationship during the fan speed control verification process in a high-temperature environment is as follows: when the ambient temperature rises, the bearing resistance increases. At the same time, the controller temperature drifts, causing PID imbalance. Due to the increase in bearing resistance and PID imbalance, the speed decreases, ultimately leading to insufficient cooling.

[0160] 3. Test generation: (1) Boundary test: full load operation at 65°C; (2) Counterfactual test: 1) Target constraint: Bearing temperature is no more than 120°C (upper limit in the device manual); 2) Margin calculation: S=0.85, the margin is calculated by the formula ≈0.15; 3) Derivation of breakthrough value: test temperature = constraint value × (1 + margin) = 120℃ × (1 + 0.15) = 138℃; 4) Constraint value: The temperature is 120°C, the margin can be calculated as 0.15, and the breakthrough value is obtained as 138°C, which ultimately verifies the critical failure point of the bearing material.

[0161] (3) Fault injection: Inject ±20% deviation into the speed feedback line.

[0162] 4. Verification indicators: (1) The high-temperature speed maintenance rate is not less than 98%, and the boundary test coverage of the path from "temperature drift model" to "PID output" in the causal diagram is promoted.

[0163] (2) Control accuracy: ±50RPM at 65℃.

[0164] In summary, the embodiment of the present application parses the circuit schematic netlist to construct a topological skeleton including component nodes and the connecting edges between them; parses the natural language description in the design constraint document, extracts the design constraint rules through rule template matching and converts them into structured machine executable rules, creates virtual constraint nodes and associates them with target component nodes; analyzes simulation report data, extracts causal characteristic relationships between parameters (such as sensitivity, thermal coupling, timing), and maps the characteristic relationships into causal edges and attributes between source nodes and target nodes in the topological skeleton; extracts operating limit parameters in the device manual and mounts them as boundary condition attributes to corresponding component nodes; and aligns component identifiers from different data sources based on preset naming standardization rules to construct a unified causal graph model including topological skeletons, virtual constraint nodes, causal edges and attributes, and boundary condition attributes.

[0165] It can be understood that the core of causal driving in the embodiments of the present application is to construct an explicit causal graph model that integrates physical connections, design intent, physical laws and failure knowledge, and use this model as the only or main basis and engine to drive the automatic generation, optimization and interpretation of subsequent multi-dimensional test cases. This technical means is different from traditional testing methods based on coverage criteria (such as code coverage, functional coverage) or random input generation, and is also different from simple analysis that relies only on a single data source (such as a pure netlist or pure simulation data). It can more deeply understand the inherent mechanism of system behavior, thereby generating a more comprehensive (covering explicit and implicit relationships), more efficient (focusing on key causal chains), and more insightful (especially counterfactual testing) verification scheme.

[0166] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0167] The embodiments of the present application also provide a multi-dimensional test case generation device.

[0168] like Figure 15 As shown, the multi-dimensional test case generation device 10 includes: a data standardization module 100 , a cause-effect graph construction module 200 and a test sequence generation module 300 .

[0169] Among them, the data standardization module 100 is used to obtain the original multi-source data corresponding to the target electronic system and convert the original multi-source data into corresponding standardized data, wherein the standardized data includes at least one of a topological map, constraint rules, causal relationships, boundary condition dictionaries and fault path lists.

[0170] The causal graph construction module 200 is used to construct a topological skeleton corresponding to the target electronic system based on the topological graph, convert the constraint rules into virtual constraint nodes, and construct the causal edges and node attributes corresponding to the topological skeleton according to the causal relationship and boundary condition dictionary, and calculate the edge weights corresponding to the causal edges, so as to establish a unified causal graph model corresponding to the target electronic system based on the topological skeleton, virtual constraint nodes, causal edges, node attributes and edge weights.

[0171] The test sequence generation module 300 is used to perform multi-dimensional testing using a unified causal graph model to generate multiple test case sets, and determine resource consumption data and at least one sorting indicator corresponding to the multiple test case sets, so as to sort the multiple test case sets according to the at least one sorting indicator, and use the resource consumption data to group the test cases of the sorted multiple test case sets to generate a final test sequence for the target electronic system.

[0172] Optionally, in one embodiment of the present application, the data standardization module 100 includes: a preprocessing unit and a data alignment unit.

[0173] Among them, the preprocessing unit is used to obtain the original multi-source data corresponding to the target electronic system, and perform data preprocessing operations on the original multi-source data to obtain corresponding preprocessed data, and perform data fusion operations on the preprocessed data to generate unified structured data.

[0174] The data alignment unit is used to align the unified structured data to convert the original multi-source data into a unified namespace and generate corresponding standardized data.

[0175] Optionally, in one embodiment of the present application, the preprocessing unit includes: an acquisition subunit, a parsing subunit, and a matching subunit.

[0176] The acquisition subunit is used to acquire original multi-source data corresponding to the target electronic system, wherein the original multi-source data includes circuit schematics, design documents, simulation data, historical fault libraries and device manuals.

[0177] The parsing subunit is used to parse the netlist data in the electronic design exchange format in the circuit schematic to extract the corresponding component identification, and based on the component identification, perform signal flow analysis on the circuit schematic to calculate the path weight of the circuit schematic, and mark the corresponding critical path according to the path weight to generate a topology diagram through the critical path.

[0178] The matching subunit is used to perform text preprocessing on the design document, and based on the preset rule template library, perform regular expression matching operations on the design document after text preprocessing to obtain corresponding matching results, and convert the matching results into constraint rules.

[0179] Optionally, in one embodiment of the present application, the pre-processing unit further includes: a data cleaning sub-unit, a mapping sub-unit and an extraction sub-unit.

[0180] Among them, the data cleaning subunit is used to clean the simulation data to obtain the corresponding standard data, calculate the correlation coefficient matrix corresponding to the standard data, and perform thermal effect modeling based on the standard data to construct the corresponding temperature-parameter response model.

[0181] The mapping subunit is used to calculate the corresponding timing margin according to the standard data, determine the corresponding timing relationship through the timing margin, and map the correlation coefficient matrix, the temperature-parameter response model and the timing relationship into a causal relationship.

[0182] The extraction subunit is used to perform causal chain extraction operations on the historical fault library to obtain a fault path list, and to perform boundary extraction operations on the device manual to obtain a boundary condition dictionary.

[0183] Optionally, in one embodiment of the present application, the data alignment unit includes: a construction subunit and a judgment subunit.

[0184] The construction subunit is used to standardize the original name of each data in the original multi-source data to obtain the corresponding standard name, and to construct a mapping relationship table between the original name and the standard name.

[0185] The judgment subunit is used to judge whether there is a name conflict among all standard names according to the mapping relationship table. In the case that there is a name conflict among all standard names, different weights are set for the data with name conflicts based on the preset confidence voting strategy to obtain standardized data.

[0186] Optionally, in one embodiment of the present application, the causal graph construction module 200 includes: a node determination unit, a conversion unit, and a skeleton determination unit.

[0187] The node determination unit is used to parse the electronic components in the netlist data of the circuit schematic to obtain corresponding parsing data, and determine the physical nodes corresponding to the electronic components according to the parsing data.

[0188] The conversion unit is used to extract the electrical connection relationship in the netlist data and convert the electrical connection relationship into corresponding causal edges.

[0189] The skeleton determination unit is used to construct an initial directed graph based on the causal edges and the entity nodes corresponding to the electronic components, and determine the topological skeleton through the initial directed graph.

[0190] Optionally, in one embodiment of the present application, the causal graph construction module 200 further includes: a first computing unit and a second computing unit.

[0191] Among them, the first calculation unit is used to extract the number of failures of the target component and the total number of uses of the target component from a preset enterprise fault database, and calculate the corresponding risk coefficient based on the number of failures, the total number of uses and the preset failure severity level.

[0192] The second calculation unit is used to determine the number of Monte Carlo simulations corresponding to the target electronic system, and determine the corresponding confidence level through the number of Monte Carlo simulations, so as to calculate the edge weight based on the risk coefficient and the confidence level.

[0193] Optionally, in one embodiment of the present application, the test sequence generation module 300 includes: an identification unit, a boundary test unit, and a fault injection test unit.

[0194] Among them, the identification unit is used to identify the key signal path in the unified causal graph model, and generate input and output verification data under standard working conditions based on the key signal path, so as to perform design verification testing through the input and output verification data to output a set of design verification test cases that meet the preset verification function requirements.

[0195] The boundary test unit is used to extract the limit values ​​of the virtual constraint nodes in the unified causal graph model, and perform boundary test operations based on the limit values ​​to obtain a boundary test case set.

[0196] The fault injection test unit is used to inject defect information into the unified causal graph model through the historical fault library to perform fault injection testing on the unified causal graph model to generate a set of fault injection test cases.

[0197] Optionally, in one embodiment of the present application, the recognition unit includes: a modeling subunit, a training subunit, an injection subunit and a comparison and analysis subunit.

[0198] Among them, the modeling subunit is used to build a digital twin dynamic mapping model based on the main path of the unified causal graph model, and synchronize the physical parameters and virtual simulation parameters of the key signal path in real time through the digital twin dynamic mapping model. Among them, the physical parameters include signal transmission delay and logic unit temperature drift coefficient, and the virtual simulation parameters include path node state variables and signal attenuation model.

[0199] The training subunit is used to train the digital twin dynamic mapping model based on a preset reinforcement learning algorithm, using the input-output verification results under standard working conditions as the reward function to generate a test sequence generation strategy that is adaptive to the drift of key signal path parameters.

[0200] The injection subunit is used to inject multi-dimensional disturbance factors on the identified key signal paths according to the test sequence generation strategy to generate an extended test sequence including disturbance response verification.

[0201] The comparison and analysis subunit is used to perform virtual-to-real comparison analysis on the extended test sequence through the digital twin dynamic mapping model to output a set of design verification test cases that meet the preset verification function requirements.

[0202] Optionally, in one embodiment of the present application, the boundary testing unit includes: a semantic annotation subunit and an extended verification subunit.

[0203] Among them, the semantic annotation sub-unit is used to semantically annotate the limit values ​​of virtual constraint nodes based on a pre-built parameter association knowledge graph to obtain multiple parameters with semantic information, and obtain the implicit constraint relationship between multiple parameters through a preset graph neural network. The extended verification subunit is used to generate boundary combination samples based on the parameter association knowledge graph and implicit constraint relationships, and adopt an adaptive particle swarm optimization algorithm to perform extended verification on the boundary combination samples to obtain a boundary test case set.

[0204] Optionally, in one embodiment of the present application, the test sequence generation module 300 further includes: an input edge extraction unit, a third calculation unit, a fitting unit, and a breakthrough value calculation unit.

[0205] The incoming edge extraction unit is used to determine the target constraint node in the unified causal graph model and extract all heat-related incoming edges of the target constraint node.

[0206] The third calculation unit is configured to determine the edge weights and direct sensitivities of all heat-related incoming edges, and calculate the thermal sensitivities of all heat-related incoming edges according to the edge weights and direct sensitivities.

[0207] The fitting unit is used to fit the historical fault data in the historical fault library to obtain the corresponding sensitivity attenuation coefficient, and calculate the safety margin of all heat-related input edges based on the preset material maximum tolerance coefficient and basic safety offset, and in combination with the sensitivity attenuation coefficient and thermal sensitivity; The breakthrough value calculation unit is used to calculate the breakthrough values ​​corresponding to all thermal-related input edges according to the safety margin, so as to construct a counterfactual test case set based on the breakthrough values.

[0208] Optionally, in one embodiment of the present application, the test sequence generation module 300 further includes: a sorting unit and a grouping unit.

[0209] Among them, the sorting unit is used to determine the edge weight and component failure rate of each type of test case set in the multiple types of test case sets, and sort the multiple types of test case sets according to the edge weight and component failure rate to generate corresponding executable test sequences.

[0210] The grouping unit is used to determine the resource consumption data of each type of test case set and group the executable test sequences into resource groups according to the resource consumption data to obtain the final test sequence.

[0211] For the description of the features in the embodiment corresponding to the multi-dimensional test case generation device, reference can be made to the relevant description of the embodiment corresponding to the multi-dimensional test case generation method, which will not be repeated here.

[0212] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned multi-dimensional test case generation method embodiments.

[0213] An embodiment of the present application further provides a non-volatile computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned multi-dimensional test case generation method embodiments when running.

[0214] In an exemplary embodiment, the non-volatile computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0215] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned multi-dimensional test case generation method embodiments are implemented.

[0216] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned multi-dimensional test case generation method embodiments.

[0217] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0218] The above is a detailed introduction to the multi-dimensional test case generation method, device, equipment and medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be noted that for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A multi-dimensional test case generation method, characterized in that: The following steps are involved: Acquiring original multi-source data corresponding to a target electronic system and converting the original multi-source data into corresponding standardized data, wherein the standardized data includes at least one of a topology map, constraint rules, causal relationships, a boundary condition dictionary, and a fault path list; Constructing a topological skeleton corresponding to the target electronic system based on the topological graph, converting the constraint rules into virtual constraint nodes, constructing causal edges and node attributes corresponding to the topological skeleton according to the causal relationships and the boundary condition dictionary, and calculating edge weights corresponding to the causal edges, so as to establish a unified causal graph model corresponding to the target electronic system according to the topological skeleton, the virtual constraint nodes, the causal edges, the node attributes, and the edge weights; Multi-dimensional testing is performed using the unified causal graph model to generate multiple test case sets, and resource consumption data and at least one sorting indicator corresponding to the multiple test case sets are determined to sort the multiple test case sets according to the at least one sorting indicator, and the resource consumption data is used to group the test cases of the sorted multiple test case sets to generate a final test sequence for the target electronic system.

2. The multi-dimensional test case generation method according to claim 1, characterized in that: The acquiring of original multi-source data corresponding to the target electronic system and converting the original multi-source data into corresponding standardized data includes: Acquiring original multi-source data corresponding to the target electronic system, performing a data preprocessing operation on the original multi-source data to obtain corresponding preprocessed data, and performing a data fusion operation on the preprocessed data to generate unified structured data; Data alignment is performed on the unified structured data to convert the original multi-source data into a unified namespace and generate corresponding standardized data.

3. The multi-dimensional test case generation method according to claim 2, characterized in that: The acquiring of original multi-source data corresponding to the target electronic system, performing a data preprocessing operation on the original multi-source data to obtain corresponding preprocessed data, and performing a data fusion operation on the preprocessed data to generate unified structured data includes: Acquiring original multi-source data corresponding to the target electronic system, wherein the original multi-source data includes circuit schematics, design documents, simulation data, historical fault libraries, and device manuals; parsing netlist data in an electronic design exchange format in the circuit schematic to extract corresponding component identifiers, performing signal flow analysis on the circuit schematic based on the component identifiers to calculate path weights of the circuit schematic, and marking corresponding critical paths according to the path weights to generate the topology diagram through the critical paths; The design document is subjected to text preprocessing, and based on a preset rule template library, a regular expression matching operation is performed on the text preprocessed design document to obtain a corresponding matching result, and the matching result is converted into the constraint rule.

4. The multi-dimensional test case generation method according to claim 3, characterized in that: The acquiring of original multi-source data corresponding to the target electronic system, performing a data preprocessing operation on the original multi-source data to obtain corresponding preprocessed data, and performing a data fusion operation on the preprocessed data to generate unified structured data further includes: Performing data cleaning on the simulation data to obtain corresponding standard data, calculating a correlation coefficient matrix corresponding to the standard data, and performing thermal effect modeling based on the standard data to construct a corresponding temperature-parameter response model; Calculating a corresponding timing margin according to the standard data to determine a corresponding timing relationship through the timing margin, and mapping the correlation coefficient matrix, the temperature-parameter response model, and the timing relationship into the causal relationship; A causal chain extraction operation is performed on the historical fault library to obtain the fault path list, and a boundary extraction operation is performed on the device manual to obtain the boundary condition dictionary.

5. The multi-dimensional test case generation method according to claim 2, characterized in that: The step of aligning the unified structured data to convert the original multi-source data into a unified namespace and generating corresponding standardized data includes: Standardizing the original name of each type of data in the original multi-source data to obtain a corresponding standard name, and constructing a mapping relationship table between the original name and the standard name; According to the mapping relationship table, it is determined whether there is a name conflict among all the standard names. In the case that there is a name conflict among all the standard names, different weights are set for the data with name conflicts based on a preset confidence voting strategy to obtain the standardized data.

6. The multi-dimensional test case generation method according to claim 1, characterized in that: The constructing a topological skeleton corresponding to the target electronic system based on the topological graph includes: parsing electronic components in the netlist data of the circuit schematic to obtain corresponding parsed data, and determining physical nodes corresponding to the electronic components based on the parsed data; Extracting electrical connection relationships in the netlist data and converting the electrical connection relationships into corresponding causal edges; An initial directed graph is constructed based on the causal edges and the entity nodes corresponding to the electronic components, and the topological skeleton is determined through the initial directed graph.

7. The multi-dimensional test case generation method according to claim 1, characterized in that: The step of converting the constraint rules into virtual constraint nodes, constructing causal edges and node attributes corresponding to the topological skeleton based on the causal relationships and the boundary condition dictionary, and calculating edge weights corresponding to the causal edges, so as to establish a unified causal graph model corresponding to the target electronic system based on the topological skeleton, the virtual constraint nodes, the causal edges, the node attributes, and the edge weights, includes: Extracting the number of failures of a target component and the total number of uses of the target component from a preset enterprise fault database, and calculating a corresponding risk factor based on the number of failures, the total number of uses, and a preset failure severity level; The number of Monte Carlo simulations corresponding to the target electronic system is determined, and a corresponding confidence level is determined by the number of Monte Carlo simulations, so as to calculate the edge weight based on the risk coefficient and the confidence level.

8. The multi-dimensional test case generation method according to claim 1, characterized in that: The method of using the unified causal graph model to perform multi-dimensional testing to generate a multi-category test case set includes: Identifying a critical signal path in the unified causal graph model, and generating input and output verification data under standard working conditions based on the critical signal path, so as to perform a design verification test using the input and output verification data, and output a design verification test case set that meets preset verification function requirements; Extracting the limit values ​​of the virtual constraint nodes in the unified causal graph model, and performing boundary testing operations based on the limit values ​​to obtain a boundary test case set; Defect information is injected into the unified causal graph model through a historical fault library to perform a fault injection test on the unified causal graph model, so as to generate a fault injection test case set.

9. The multi-dimensional test case generation method according to claim 8, characterized in that: The identifying of a key signal path in the unified causal graph model and generating input and output verification data under standard working conditions according to the key signal path, performing a design verification test using the input and output verification data, and outputting a design verification test case set that meets preset verification function requirements, includes: Based on the main path of the unified causal graph model, a digital twin dynamic mapping model is constructed, and the physical parameters and virtual simulation parameters of the key signal path are synchronized in real time through the digital twin dynamic mapping model, wherein the physical parameters include signal transmission delay and logic unit temperature drift coefficient, and the virtual simulation parameters include path node state variables and signal attenuation model; Based on a preset reinforcement learning algorithm, the digital twin dynamic mapping model is trained, and the input and output verification results under the standard working conditions are used as a reward function to generate a test sequence generation strategy that is adaptive to the drift of key signal path parameters; Injecting multi-dimensional disturbance factors on the identified critical signal paths according to the test sequence generation strategy to generate an extended test sequence including disturbance response verification; The extended test sequence is subjected to virtual-real comparison analysis through the digital twin dynamic mapping model to output a set of design verification test cases that meet the preset verification function requirements.

10. The multi-dimensional test case generation method according to claim 8, characterized in that: The step of extracting the limit values ​​of the virtual constraint nodes in the unified causal graph model and performing boundary testing operations based on the limit values ​​to obtain a boundary test case set includes: Based on a pre-built parameter association knowledge graph, semantic annotation is performed on the limit values ​​of the virtual constraint nodes to obtain multiple parameters with semantic information, and the implicit constraint relationship between the multiple parameters is obtained through a preset graph neural network; Based on the parameter association knowledge graph and the implicit constraint relationship, an adaptive particle swarm optimization algorithm is used to generate boundary combination samples, and the boundary combination samples are extended and verified to obtain the boundary test case set.

11. The multi-dimensional test case generation method according to claim 8, characterized in that: The method of performing multi-dimensional testing using the unified causal graph model to generate a multi-category test case set further includes: Determine a target constraint node in the unified causal graph model, and extract all heat-related incoming edges of the target constraint node; Determining edge weights and direct sensitivities of all the heat-related incoming edges, and calculating thermal sensitivities of all the heat-related incoming edges based on the edge weights and the direct sensitivities; Fitting historical fault data in the historical fault library to obtain corresponding sensitivity attenuation coefficients, and calculating safety margins of all heat-related input edges based on a preset material maximum tolerance coefficient and a basic safety offset, and in combination with the sensitivity attenuation coefficients and the thermal sensitivity; The breakthrough values ​​corresponding to all the heat-related input edges are calculated according to the safety margin, so as to construct a counterfactual test case set based on the breakthrough values.

12. The multi-dimensional test case generation method according to claim 1, characterized in that: The determining resource consumption data and at least one sorting indicator corresponding to the multiple test case sets, sorting the multiple test case sets according to the at least one sorting indicator, and grouping the sorted multiple test case sets into test cases using the resource consumption data to generate a final test sequence for the target electronic system includes: Determining edge weights and component failure rates of each type of test case set in the multiple types of test case sets, and sorting the multiple types of test case sets according to the edge weights and the component failure rates, respectively, to generate corresponding executable test sequences; Resource consumption data of each type of test case set is determined, and resource grouping of the executable test sequences is performed according to the resource consumption data to obtain the final test sequence.

13. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the multi-dimensional test case generation method according to any one of claims 1 to 12 when executing the computer program.

14. A non-volatile computer-readable storage medium, characterized in that: The non-volatile computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the multi-dimensional test case generation method according to any one of claims 1 to 12 are implemented.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the multi-dimensional test case generation method according to any one of claims 1 to 12 are implemented.

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