Matrix calculation adaptive optimization method and system based on ARM architecture

Abstract

The invention discloses a matrix calculation adaptive optimization method and system based on an ARM architecture. The method comprises the following steps: preprocessing to-be-processed matrix data; performing local activeness calculation and hot spot region identification on the preprocessed matrix data, and determining long-tail distribution characteristics of the matrix; calculating the optimal block size range of the matrix based on the long tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the processor information, and generating an asymmetric block scheme; based on an asymmetric partitioning scheme, establishing a mapping relation between matrix features and optimal partitioning parameters; calculating the calculation density and the memory access mode of each block based on the asymmetric block scheme and the mapping relation, and generating a task scheduling scheme; based on the task scheduling scheme, matrix calculation is executed on the processor, and a final calculation result is output. According to the method, self-adaptive blocking and heterogeneous core scheduling are realized by identifying the long tail distribution characteristics of the matrix, and the performance and energy efficiency of matrix calculation on ARM are improved.

Description

Technical Field

[0001] The present invention relates to the field of computer science and technology, and in particular to a matrix calculation adaptive optimization method and system based on ARM architecture. Background Art

[0002] With the rapid development of artificial intelligence (AI), deep learning algorithms are widely used in various smart devices. Matrix calculations, as the core operations of these algorithms, directly impact the overall performance and energy efficiency of the system. Efficiently executing matrix operations on resource-constrained ARM architecture devices has become a key technical challenge.

[0003] Common matrix computation optimization methods currently used in the industry primarily include general-purpose matrix multiplication libraries (such as OpenBLAS) and hardware-accelerated libraries (such as the ARM Compute Library). These methods typically employ a static blocking strategy, decomposing large matrices into fixed-size sub-matrices to improve cache utilization and parallelism. For example, OpenBLAS uses the Strassen algorithm and blocking techniques to decompose matrix multiplication into multiple sub-matrix operations, while the ARM Compute Library utilizes the NEON SIMD instruction set for vectorized computation.

[0004] More advanced matrix computation optimization techniques incorporate automatic tuning mechanisms to predetermine optimal block parameters based on matrix size and hardware characteristics. This approach uses offline analysis to build a performance model, selects predefined compute kernels for matrix computation tasks of varying sizes, and utilizes the ARM NEON instruction set for underlying optimization. However, this technique assumes uniform matrix element distribution and uses a uniform block size, ignoring the uneven distribution of matrix element activity in real applications.

[0005] Existing technologies suffer from two major flaws: First, the fixed partitioning strategy cannot adapt to the long-tail distribution of matrix elements, resulting in uneven distribution of computing resources, excessive computational pressure in high-activity areas and wasted resources in low-activity areas; second, it fails to fully utilize the characteristics of the ARM big.LITTLE heterogeneous multi-core architecture and fails to dynamically schedule to the most appropriate processing core based on the partitioning characteristics, resulting in performance bottlenecks and low energy efficiency. These issues are particularly prominent in computationally intensive scenarios such as large model inference, severely limiting the ability of ARM devices to handle complex matrix calculations. Summary of the Invention

[0006] The purpose of the present invention is to provide a matrix calculation adaptive optimization method and system based on the ARM architecture. The method implements an asymmetric block strategy by identifying the long-tail distribution characteristics of matrix elements, and combines the characteristics of the ARM big.LITTLE heterogeneous architecture to allocate computing tasks with different characteristics to the most appropriate processing core, significantly improving the performance and energy efficiency of matrix calculations.

[0007] To achieve the above object, the present invention provides a matrix calculation adaptive optimization method based on ARM architecture, comprising the following steps: Obtaining matrix data to be processed and ARM processor information, preprocessing the matrix data to be processed to obtain preprocessed matrix data; Performing local activity calculation and hotspot area identification on the preprocessed matrix data to determine the long-tail distribution characteristics of the matrix; Based on the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the ARM processor information, the optimal block size range of the matrix is ​​calculated to generate an asymmetric block scheme; Based on the asymmetric block scheme, the execution time and cache hit rate of each block are collected to establish a mapping relationship between matrix characteristics and optimal block parameters, wherein the block is a basic sub-block divided by the preprocessed matrix data; Based on the asymmetric block scheme and the mapping relationship between the matrix characteristics and the optimal block parameters, the computational density and memory access pattern of each block are calculated to generate a task scheduling scheme; Based on the task scheduling scheme, matrix calculations are performed on an ARM big.LITTLE architecture processor to output the final calculation results.

[0008] Preferably, the performing local activity calculation on the pre-processed matrix data includes: Dividing the preprocessed matrix data into basic sub-blocks of a reference size, and calculating the proportion of non-zero elements and the variance of the value distribution for each basic sub-block; Calculate the relative importance score of each basic sub-block according to the non-zero element ratio and value distribution variance of each basic sub-block to obtain the sub-block calculation contribution; Calculating the contribution of the sub-blocks, calculating the statistical distribution data of the local activity of the basic sub-blocks using NEON SIMD instructions, and obtaining a local activity distribution map of the matrix; Normalizing the local activity distribution map to obtain a normalized local activity distribution map; Based on the standardized local activity distribution graph, a sparse data structure is used to store basic sub-block information whose activity exceeds a first preset threshold.

[0009] Preferably, the hotspot area identification includes: Based on the preprocessed matrix data, calculating statistical distribution data of global activity and constructing a global activity distribution graph, wherein the statistical distribution data of global activity includes a mean value and a standard deviation; Based on the statistical distribution data of the global activity, the OTSU algorithm is used to optimize the activity threshold segmentation point to obtain an optimized activity threshold; Obtaining the optimized activity threshold, and converting the global activity distribution map into a hotspot distribution binary map; Receive the hotspot distribution binary map, execute the connected region marking algorithm, cluster and merge adjacent hotspot regions, and obtain a cluster merging result; Obtaining cluster merging results, applying morphological operations to trim the hotspot area, removing isolated hotspots whose areas are smaller than a second preset threshold, and obtaining trimmed hotspot areas; The trimmed hotspot areas are received, and the location information, shape features, and activity features of each hotspot area are obtained.

[0010] Preferably, the calculating of the optimal block size range of the matrix based on the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the ARM processor information and the generating of the asymmetric block scheme include: Obtaining statistical distribution data of the global activity and the local activity, designing blocks adapted to the L1 cache for regions where the activity exceeds a third preset threshold, and designing blocks adapted to the L2 / L3 cache for regions where the activity is below a fourth preset threshold, to obtain an initial block scheme; Based on the initial block scheme, identify cross-block hotspot areas, ensure that the hotspot elements are completely contained in a single block through overlapping cutting, and output block boundary data; Obtaining the block boundary data, performing memory alignment optimization, and ensuring that the block boundary is aligned to the cache line; Obtain historical execution data and fine-tune the chunk size and shape based on execution efficiency metrics.

[0011] Preferably, establishing a mapping relationship between matrix features and optimal block parameters includes: Obtain block execution data, collecting the execution time, cache hit rate and instruction throughput of each block; Obtaining performance indicators, and analyzing the correlation between the block execution data and the performance indicators; Obtaining correlation data between the block execution data and the performance indicators, and establishing a mapping relationship model between matrix features and optimal block parameters; Deploy the mapping relationship model into the ARM TrustZone environment and update the block strategy history library; Obtain historical database data and record the optimal block parameters under different matrix characteristics.

[0012] Preferably, the task scheduling scheme includes: Obtaining block characteristic data, allocating blocks having a computational density exceeding a fifth preset threshold to a first core for processing, and allocating blocks having a computational density below a sixth preset threshold to a second core for processing, wherein the number of the first cores is greater than the number of the second cores; Receive block priority data, set task execution order and preemption strategy; Get the core characteristics of the ARM processor, configure core affinity, get the core affinity configuration, and specify the execution core of a specific type of task; Receive the dependencies of the executed tasks, implement task group scheduling and synchronization checkpoint setting; Obtain cache characteristic data, optimize shared cache and memory access strategies, and reduce inter-core data transmission.

[0013] Preferably, performing matrix calculations on an ARM big.LITTLE architecture processor includes: Obtaining the block characteristic data and selecting corresponding NEON instruction set optimization kernels for different types of blocks; Obtain block activity characteristics and configure mixed precision calculation matrix parameters; Obtain the memory access mode, configure ARM cache prefetch instructions, and optimize memory access order; According to the core affinity configuration, the calculation of each block is executed in parallel to obtain the calculation results of each block; Obtain the calculation results of each block, perform result merging and correctness verification.

[0014] Preferably, the method further comprises: Obtain the matrix operation process and the characteristics of the ARM processor, use a formal language to define the operation axiom system, and obtain a formal specification; Analyze and process the formal specification, generate system verification assertions, and output executable verification rules; According to the executable verification rules, the correctness of the asymmetric block scheme is verified using a theorem proving tool, and a verification report is generated; Based on the verification report and mixed precision calculation data, perform error propagation analysis and establish an accuracy error model; Based on the accuracy error model and actual execution data, formal verification is performed and a formal proof result is output.

[0015] Preferably, the method further includes execution-time verification and recovery, including: Obtain matrix calculation execution status information, perform verification checks, and generate verification results; Based on the verification results and the preset error level standards, perform hierarchical error classification and determine the error handling strategy; According to the error handling strategy and the accuracy problem data, the accuracy path is adjusted and the corrected calculation path is output; Based on the modified calculation path and the numerical distribution characteristics of the matrix, performing numerical stability adjustment to obtain optimized calculation parameters; According to the optimized calculation parameters and the current ARM processor state, task scheduling is reorganized and a new execution plan is output.

[0016] Preferably, the method comprises: Obtaining the preprocessed matrix data and state space model parameters, performing dynamic characteristic analysis, and obtaining a characteristic sequence; Construct a complete computational operation graph, combine the feature sequence, identify fusionable operation combinations, and output a fusion solution; Obtaining optimized execution code according to the fusion solution and the characteristics of the ARM processor; Collecting multi-source runtime information and outputting a dynamic switching strategy using the optimized execution code; Based on the dynamic switching strategy and execution feedback data, an optimization feedback model is constructed to obtain a continuous optimization solution.

[0017] Preferably, the method further comprises mixed precision optimization, comprising: Obtaining the numerical distribution characteristics and precision requirements of the matrix, performing block floating-point representation design, and outputting a bidirectional block floating-point solution; Based on the bidirectional block floating point scheme and matrix region features, performing ternary region identification to determine quantization regions, wherein the matrix region features are a set of parameters describing geometric features, numerical features, and computational features of different spatial regions of a matrix; Performing ternary quantization with a scaling factor on the quantization region and the precision parameter to obtain compressed representation data, wherein the precision parameter is a set of configuration parameters that control numerical representation precision and calculation precision; Performing a pre-filling operation on the compressed representation data and the memory characteristics of the ARM processor, and outputting a memory access optimization solution; Based on the memory access optimization scheme and the ARM processor instruction set, bit operation acceleration processing is performed to obtain the final optimization result.

[0018] Preferably, the method further includes energy efficiency optimization and monitoring, including: Obtain ARM processor status data and energy efficiency targets, execute execution controller design, and output energy efficiency control strategy; Based on the energy efficiency control strategy and ARM processor parameters, dynamically adjust the configuration to obtain optimized operating parameters, wherein the ARM processor parameters are a set of parameters that describe the hardware characteristics and operating status of the ARM architecture processor; Performing error tracking analysis on the optimized operating parameters and precision representation data, and outputting a cumulative error report, wherein the precision representation data is detailed information recording different numerical precision representation methods; Performing accuracy improvement configuration based on the cumulative error report and computational task characteristics to obtain a balanced accuracy solution, wherein the computational task characteristics are characteristic parameters that describe the attributes and requirements of the matrix computation task; Based on the balanced accuracy scheme and system operation data, an accuracy energy efficiency model is constructed and a final optimization strategy is output.

[0019] The present invention also provides a matrix calculation adaptive optimization system based on ARM architecture, comprising: An acquisition module is used to obtain matrix data to be processed and ARM processor information, preprocess the matrix data to be processed, and obtain preprocessed matrix data; An identification module is used to calculate local activity and identify hot spots on the pre-processed matrix data to determine the long-tail distribution characteristics of the matrix; A calculation module is used to receive the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters of the ARM processor, calculate the optimal block size range, and generate an asymmetric block solution; Establish a module for obtaining the asymmetric block solution, collecting the execution time and cache hit rate of each block, and establishing a mapping relationship between matrix characteristics and optimal block parameters; A generation module is used to obtain the asymmetric block scheme and mapping relationship, calculate the computing density and memory access mode of each block, and generate a task scheduling plan; The output module is used to obtain the task scheduling plan, perform matrix calculations on an ARM big.LITTLE architecture processor, and output final calculation results.

[0020] The beneficial effects of the present invention are: (1) By accurately identifying the long-tail distribution characteristics of matrix elements and implementing an asymmetric blocking strategy, computing resource allocation is precisely matched to matrix characteristics, significantly improving cache utilization and computing efficiency; (2) Combining the characteristics of ARM big.LITTLE heterogeneous multi-core architecture, computing-intensive tasks are assigned to large cores and memory-intensive tasks are assigned to small cores, achieving the optimal match between task characteristics and processing core characteristics, improving overall computing performance and reducing energy consumption; (3) Through precise online detection of matrix hotspots and boundary optimization technology, we ensure that highly active elements are completely contained in a single block, reducing cross-block communication overhead and optimizing execution efficiency; (4) Using the ARM TrustZone secure environment to maintain an execution history database, establish a mapping relationship between matrix characteristics and optimal block parameters, and achieve experience-driven continuous optimization to adapt to different types of matrix computing tasks; (5) Through the mixed precision computing strategy, differentiated precision configuration is applied to different activity areas, which improves processing efficiency and reduces energy consumption while maintaining computing accuracy. It is particularly suitable for resource-constrained ARM devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. The drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without inventive effort.

[0022] Figure 1 This is a flow chart of a matrix calculation adaptive optimization method based on ARM architecture of the present invention; Figure 2 It is a flow chart of the method for generating an adaptive block strategy according to the present invention; Figure 3 It is a flow chart of the historical execution data feedback and optimization method of the present invention; Figure 4 This is a flow chart of the heterogeneous core task weight prediction and scheduling method of the present invention; Figure 5 This is a flow chart of the NEON instruction set optimization execution method of the present invention; Figure 6 This is a structural diagram of a matrix computing adaptive optimization system based on ARM architecture in the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0024] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0025] The term "and / or" herein simply describes an association relationship, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, and the existence of B alone. In addition, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0027] Example 1 like Figure 1 As shown, the present invention provides a matrix calculation adaptive optimization method based on ARM architecture, which mainly includes the following steps: Step 101: Obtain matrix data to be processed and ARM processor information, pre-process the matrix data to be processed, and obtain pre-processed matrix data; The preprocessing in step 101 specifically involves loading the matrix data into main memory via DMA and obtaining the ARM processor's multi-level cache capacity and core configuration parameters. The system supports multiple input formats for matrix data, including dense matrix format and compressed sparse row format. Processor parameter information includes L1 / L2 / L3 cache capacity, core configuration, and NEON vector unit parameters.

[0028] This step first receives two key inputs: the matrix data to be processed and information about the target ARM processor. The system supports matrix data input in a variety of formats, including dense and compressed sparse row formats (CSR), which is crucial for processing matrix data in diverse scenarios. The system then efficiently loads the matrix data into main memory using direct memory access (DMA). This mechanism significantly reduces CPU-involved data transfer overhead and improves data loading efficiency. Simultaneously, the system automatically detects and retrieves detailed parameter information for the target ARM processor, focusing on multi-level cache capacity (including the L1 instruction cache, L1 data cache, L2 unified cache, and the L3 shared cache on some high-end ARM chips), core configuration (including the number, frequency, and power consumption of large and small cores in the big.LITTLE architecture), and NEON vector unit parameters (including register width and supported instruction set extensions). The system organizes these processor parameters into structured configuration sets for easy reference in subsequent optimization algorithms.

[0029] Step 102 : performing local activity calculation and hotspot area identification on the pre-processed matrix data to determine the long-tail distribution characteristics of the matrix.

[0030] In this step, the system first divides the matrix into fixed-size basic analysis units (basic sub-blocks), typically 8×8 or 16×16. This size selection takes two factors into consideration: small enough to capture local feature variations and large enough to reduce analysis overhead. For each basic sub-block, the system calculates activity metrics such as the proportion of nonzero elements, numerical distribution variance, and computational contribution. These calculations are accelerated using NEON SIMD instructions, such as VABD.F32, VCGT.F32, and VPADD.F32. The system then uses an adaptive threshold algorithm to identify high-activity regions, converts the activity distribution map into a binary hotspot distribution map, and uses a connected component labeling algorithm to cluster and merge adjacent hotspot regions. Finally, the system extracts the long-tail distribution characteristics of the matrix, including key parameters such as overall sparsity, proportion of hotspot regions, hotspot distribution divergence, and long-tail index, providing important information for subsequent block partitioning strategy development.

[0031] Step 103 : Based on the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the ARM processor information, the optimal block size range of the matrix is ​​calculated to generate an asymmetric block solution.

[0032] In this step, the system first builds a cache optimization model based on the multi-level cache characteristics of ARM processors. This model takes into account parameters such as cache capacity at each level, cache line size, cache associativity, and access latency to calculate the theoretically optimal tile size range. The system then applies differentiated tile strategies to different activity regions based on the long-tail distribution of the matrix. Small tiles (such as 4×4, 8×8, or 16×16) are designed for high-activity regions (hotspots) to ensure full L1 cache fit, maximizing cache utilization and NEON vectorization efficiency. Large tiles (such as 32×32, 64×64, or larger) are designed for low-activity regions (the long tail) to match L2 / L3 cache capacity and reduce task scheduling overhead. The system also uses overlapping slicing techniques to address cross-tile hotspots, ensuring that highly active elements are fully contained within a single tile. Memory alignment optimization is then performed to ensure tile boundaries align with cache lines, avoiding the overhead of cross-cache line accesses.

[0033] Step 104 : Based on the asymmetric block scheme, the execution time and cache hit rate of each block are collected to establish a mapping relationship between matrix characteristics and optimal block parameters, wherein the blocks are basic sub-blocks of the pre-processed matrix data.

[0034] In this step, the system collects detailed performance data of each block execution through the ARM Performance Monitoring Unit (PMU), including indicators such as execution time, cache hit rate, instruction throughput and memory access latency. The system preprocesses these raw performance data, including outlier detection, missing value interpolation and data standardization, and then associates the performance data with the block characteristics to construct an analysis matrix. Through multi-dimensional correlation analysis, the system identifies key factors affecting performance, including the functional relationship between block size and cache hit rate, the relationship between matrix activity pattern and computational efficiency, and ARM architecture-specific performance factors. Based on these analyses, the system establishes a mapping relationship model between matrix characteristics and optimal block parameters, uses a lightweight machine learning algorithm to predict the optimal block parameters under different matrix characteristics, and deploys the model in the ARM TrustZone security environment to continuously update the block strategy history library.

[0035] Step 105 : Based on the asymmetric block scheme and the mapping relationship between the matrix characteristics and the optimal block parameters, the computation density and memory access pattern of each block are calculated to generate a task scheduling scheme.

[0036] The system analyzes the computational characteristics of each block, including its compute density ratio (CDR), memory access patterns, parallelism, and dependencies. Based on these characteristics, the system applies a pre-trained lightweight task weight prediction model to assess the execution efficiency and energy consumption of each block on different processing cores. The system employs a "compute-intensive priority allocation strategy," assigning blocks with high compute density ratios (typically small, highly active blocks) to large cores and blocks with low compute density ratios (typically large, less active blocks) to small cores. The system designs a core load balancing algorithm to ensure a balanced workload distribution between large and small cores, and implements work-stealing mechanisms, energy-aware scheduling, and temperature balancing strategies. Ultimately, the system generates a complete task scheduling plan, including task priority, core affinity, and execution timing, to guide subsequent matrix calculations.

[0037] Step 106 : Based on the task scheduling solution, perform matrix calculation on the ARM big.LITTLE architecture processor and output the final calculation result.

[0038] Specifically, the system selects the most suitable NEON instruction set-optimized kernel for each type of block based on block characteristics and task scheduling. For small, high-activity blocks, the system selects instruction templates optimized for intensive computation, such as VLDM, VMLA, and VSTM. For large, low-activity blocks, the system selects memory-optimized instruction templates, focusing on optimizing cache utilization and memory access patterns. The system also configures mixed-precision computing parameters based on block activity, using FP32 for high-activity areas, FP16 for moderately active areas, and INT8 or lower precision for low-activity areas. The system also configures ARM cache prefetch instructions (PLDs) to preload upcoming data into the cache and optimize memory access order to reduce cache misses. Based on core affinity configurations, the system executes block computations in parallel across heterogeneous multicores, achieving dynamic load balancing. Finally, the system collects all block computation results, reorganizes them into a complete matrix, and performs multi-level validation checks to ensure the correctness and reliability of the results before outputting the final optimized output.

[0039] Example 2 The detailed steps of calculating local activity and identifying hotspot areas on pre-processed matrix data include: Step 201: Divide the pre-processed matrix data into basic sub-blocks of a reference size, and calculate the proportion of non-zero elements and the variance of the value distribution for each basic sub-block; In step 201, the system divides the matrix into 8×8 or 16×16 basis blocks. This size is chosen based on two factors: small enough to capture local feature variations and large enough to reduce analysis overhead. For the ARM architecture, an 8×8 block size takes up exactly 256 bytes, fitting into an L1 cache line.

[0040] Specifically, the system first determines a basic sub-block size suitable for the ARM architecture, typically choosing 8×8 or 16×16. This choice carefully balances computational efficiency and analysis accuracy: a size that is too small results in excessive analysis overhead, while a size that is too large loses local feature variations. For the ARM architecture, an 8×8 sub-block size (assuming float data types) occupies exactly 256 bytes, which fits within an L1 cache line (typically 64-128 bytes), enabling efficient local liveness analysis. The system then traverses the entire matrix and performs quantitative analysis on each basic sub-block. It first calculates the non-zero element ratio (NZR), which is the number of non-zero elements in the sub-block divided by the total number of elements in the sub-block. For floating-point matrices, the system sets a small threshold (typically 1e-6) and treats elements with absolute values ​​below this threshold as zero. It then calculates the value distribution variance (VDS), which reflects the statistical variance of the absolute values ​​of the elements within the sub-block. This metric captures the dispersion of the value distribution within the sub-block and is particularly important for identifying hot spots in the matrix.

[0041] In step 202, the relative importance score of each basic sub-block is calculated based on the non-zero element percentage and value distribution variance of each basic sub-block, resulting in a sub-block computational contribution. In this step, the system further calculates the computational contribution (CC) of each sub-block based on the basic features obtained in step 201, estimating the relative importance of the sub-block in the matrix calculation. For common operations such as matrix multiplication, the system uses a weighted combination formula that comprehensively considers the non-zero element percentage, value distribution variance, and the sum of the absolute values ​​of the elements to generate an importance score for each sub-block. This scoring mechanism effectively identifies critical sub-blocks that, despite having a small number of elements, have significant values ​​and contribute significantly to the computational results. For example, in the attention matrix of a deep learning model, a small number of highly active regions often determine the final computational accuracy. The system uses normalization to map the computational contribution to the [0, 1] range for ease of subsequent processing and comparison. This refined importance assessment forms the foundation of the subsequent asymmetric block partitioning strategy, ensuring that computing resources are allocated to the areas most in need.

[0042] In step 203, based on the calculated contributions of the sub-blocks, the system uses NEON SIMD instructions to calculate the statistical distribution of local activity for the basic sub-blocks, thereby obtaining a local activity distribution map for the matrix. In this step, the system fully utilizes the NEON SIMD (Single Instruction, Multiple Data) instruction set of the ARM architecture to perform efficient local activity calculations on the basic sub-blocks. The system uses the VABD.F32 (Absolute Value Difference) instruction to quickly calculate element absolute values, the VCGT.F32 (Greater Than Compare) instruction to efficiently identify non-zero elements exceeding a threshold, and the VPADD.F32 (Parallel Add) instruction to accelerate accumulation operations. For large matrices, the system employs a multi-threaded parallel processing strategy, dividing the matrix into multiple regions. Each thread is responsible for calculating the activity of a region, significantly improving processing speed. These calculation results are ultimately integrated into the local activity distribution map of the matrix, a reduced-dimensional representation in which each cell corresponds to a basic sub-block of the original matrix, and the cell value represents the activity index of that sub-block. Through this local activity analysis, the system can accurately capture the differences in computing density and importance of different regions in the matrix, providing key basis for subsequent hotspot identification and blocking strategies.

[0043] In step 204, the local activity distribution map is normalized to obtain a standardized local activity distribution map. In this step, the system normalizes the local activity distribution map to ensure comparability between matrices of different sizes and types, and to facilitate the subsequent setting of common thresholds. The normalization process first calculates global statistical features, including the minimum, maximum, mean, and standard deviation of activity. The system then uses appropriate normalization methods, such as min-max normalization or Z-score normalization, to map the activity values ​​of each sub-block to a unified range (typically the interval [0, 1]). This process ensures that matrices of different scales use a consistent activity metric, avoiding comparison bias caused by varying absolute values ​​of matrix elements. For matrices with extreme values, the system also applies robust normalization methods, such as percentile-based scaling, to reduce the impact of outliers on the overall distribution. The standardized activity distribution map more clearly displays the relative activity patterns of the matrix, facilitating the accurate identification of hotspots and long-tail distribution characteristics.

[0044] Step 205 : Based on the standardized local activity distribution graph, a sparse data structure is used to store basic sub-block information whose activity exceeds a first preset threshold.

[0045] In this step, the system uses an efficient sparse data structure to store information about sub-blocks with significant activity, rather than storing a complete activity distribution map. The system sets a first preset threshold (typically 0.3-0.5, depending on the matrix type) and only stores information about sub-blocks with activity exceeding this threshold, including the sub-block's location coordinates and corresponding activity values. This sparse representation significantly saves storage space, which is particularly important for large matrices. In implementation, the system can use efficient data structures such as coordinate lists (COOs), compressed sparse rows (CSRs), or quadtrees, selecting the most appropriate representation based on the matrix's sparsity pattern. For example, for matrices with block-like activity distribution, a quadtree representation provides good spatial locality; for matrices with dispersed activity, a coordinate list may be more suitable. This sparse representation not only reduces storage overhead but also accelerates subsequent hotspot identification and processing, as the system only needs to focus on sub-blocks with significant activity, eliminating the need to process large areas of low activity.

[0046] Step 206 : Calculate statistical distribution data of global activity based on the pre-processed matrix data and construct a global activity distribution graph. The statistical distribution data of global activity includes a mean value and a standard deviation.

[0047] In this step, the system analyzes the matrix's activity distribution characteristics from a holistic perspective and calculates key statistical indicators. First, the system calculates the mean activity value (μ) for the entire matrix, reflecting the overall activity level. It then calculates the standard deviation (σ), which characterizes the dispersion of the activity distribution. A larger standard deviation typically indicates the presence of distinct hotspots in the matrix. The system also calculates higher-order statistics such as skewness (reflecting the asymmetry of the distribution) and kurtosis (reflecting the peakedness of the distribution). These metrics help identify characteristics of long-tailed distributions. Furthermore, the system calculates quantile information for activity, such as the 25th, 50th (median), 75th, and 90th percentiles, which provide a more comprehensive description of the shape of the activity distribution. Based on these statistics, the system constructs a global activity distribution map, visualizing the overall distribution characteristics of activity, such as a histogram or cumulative distribution function (CDF). These global statistical features provide a mathematical basis for identifying hotspots, enabling the system to adaptively set hotspot identification criteria based on the overall characteristics of the matrix.

[0048] Step 207 : Based on the statistical distribution data of the global activity, the OTSU algorithm is used to optimize the activity threshold segmentation point to obtain an optimized activity threshold.

[0049] In this step, the system uses the OTSU algorithm (Otsu algorithm) to automatically determine the optimal activity threshold and classify the matrix into hotspot and non-hotspot regions. The OTSU algorithm is a classic image segmentation method whose core principle is to maximize the between-class variance and find the optimal binary classification threshold. The system treats the activity distribution as a grayscale histogram and, by traversing possible thresholds, calculates the average activity and weights of hotspot and non-hotspot regions. The threshold that maximizes the variance between the two regions is selected as the optimal segmentation point. The advantage of this adaptive thresholding method is that it does not require manual setting of a fixed threshold, but rather automatically adjusts the segmentation criteria based on the activity distribution characteristics of different matrices. For matrices with highly uneven activity distributions, the system can also extend the multi-threshold OTSU algorithm to divide the matrix regions into multiple activity levels, achieving more refined hotspot classification. The thresholds determined by the OTSU algorithm have a strong theoretical basis and can more objectively identify hotspot regions in the matrix, providing a reliable foundation for subsequent segmentation strategies.

[0050] Step 208: Obtain the optimized activity threshold, and convert the global activity distribution map into a hotspot distribution binary map.

[0051] In this step, the system binarizes the global activity distribution map based on the optimal threshold determined by the OTSU algorithm to generate a binary map of hotspot distribution. For each basic sub-block, if its activity value exceeds the optimized threshold, it is marked as 1 in the binary map (indicating a hotspot region); otherwise, it is marked as 0 (indicating a non-hotspot region). The binarization process can be vectorized using ARM NEON instructions, such as VCGT (Vector Compare Greater Than) and VBSL (Vector Bit Select), to efficiently implement large-scale binarization operations. The resulting binary map clearly illustrates the spatial distribution of hotspot regions within the matrix, simplifying subsequent processing. For special cases, such as extremely sparse matrices or matrices with highly uneven activity distribution, the system applies additional optimization strategies, such as combining a fixed percentage approach (e.g., selecting the top 10% most active sub-blocks as hotspots) with the results of the OTSU algorithm to ensure the rationality and stability of hotspot identification.

[0052] Step 209: Receive the hotspot distribution binary map, execute a connected component labeling algorithm, cluster and merge adjacent hotspot areas, and obtain a cluster merging result.

[0053] In this step, the system applies a connected component labeling algorithm to merge spatially adjacent hotspot sub-blocks into larger connected components. The system first scans the binary hotspot distribution graph and assigns a temporary label to each cell with a value of 1 (hotspot sub-block). Then, in a second scan, the system merges adjacent cells with the same label, establishing equivalence classes. Ultimately, all sub-blocks belonging to the same connected component are labeled with the same unique identifier. The system implements two neighbor definition strategies: 4-adjacency (considering only adjacency in the four directions of up, down, left, and right) and 8-adjacency (considering four additional diagonal directions). For large matrices, the system uses parallelized connected component labeling algorithms, such as a parallel two-pass scan or a parallel algorithm based on the Union-Find data structure, to accelerate processing. After connected component labeling, the system obtains a series of hotspot clusters, each consisting of multiple adjacent high-activity sub-blocks. This cluster merging not only reduces the complexity of subsequent processing but also better reflects the physical characteristics of hotspot regions in real-world matrix calculations, as high-activity elements often cluster in space.

[0054] Step 210 , obtaining cluster merging results, applying morphological operations to trim the hotspot area, removing isolated hotspots whose areas are smaller than a second preset threshold, and obtaining trimmed hotspot areas.

[0055] In this step, the system further optimizes the connected component labeling results, applying mathematical morphological operations to improve the shape and connectivity of hotspot regions. The system first applies a morphological opening operation (erosion followed by dilation) to remove small protrusions and noise. It then applies a morphological closing operation (dilation followed by erosion) to fill small holes within the hotspot regions and smooth the region boundaries. These operations are performed using structuring elements (typically 3×3 or 5×5 square or cross convolution kernels), which can be efficiently implemented using ARM NEON instructions. The system then sets a second preset threshold (typically 5-10 basis blocks) to remove isolated hotspot regions with an area smaller than the threshold. These small regions are often noise or unimportant active points, and processing them increases the complexity of partitioning and scheduling with limited benefit. For some specialized applications, the system also retains small hotspots of special significance, such as matrix diagonal elements or known key points. This trimming process significantly improves the quality of the hotspot regions and provides a more reasonable region division for subsequent partitioning strategies.

[0056] Step 211: Receive the trimmed hotspot areas and obtain the location information, shape features, and activity features of each hotspot area.

[0057] In this step, the system extracts detailed features from each trimmed hotspot region to construct a complete description of the hotspot region. Positional information includes the region's boundary coordinates (upper left and lower right corner coordinates) and center of mass position, which are directly used for subsequent block positioning. Shape features include the region's area (number of basic sub-blocks), perimeter (boundary length), rectangularity (the ratio of the region's area to the area of ​​its minimum enclosing rectangle), aspect ratio (height-to-width ratio), and directionality (major axis direction). These features help design a block strategy tailored to the specific hotspot shape. Activity features include the region's average activity, maximum activity, activity standard deviation, and activity distribution pattern. These metrics reflect the computational density and importance of the hotspot region. The system integrates this information into a structured hotspot region description, which contains a complete set of features for each hotspot region. For a typical deep learning matrix, this step typically identifies 5-20 key hotspot regions, greatly simplifying the complexity of subsequent processing while preserving the most important computational features in the matrix.

[0058] Step 212 , calculate key feature parameters of the matrix, such as the overall sparsity, the proportion of hotspot areas, and the hotspot distribution divergence, and output a description of the long-tail distribution characteristics of the matrix.

[0059] In this step, based on the hotspot information obtained in the previous step, the system further extracts and quantifies the long-tail distribution characteristics of the matrix. The system first calculates the matrix's overall sparsity index (GS), which is the proportion of nonzero elements in the entire matrix. It then calculates the hotspot ratio (HR), which is the ratio of the number of elements covered by all hotspot regions to the total number of elements in the matrix, and the hotspot activity concentration (HAC), which is the ratio of nonzero elements in hotspot regions to the total number of nonzero elements in the matrix. The system also calculates the hotspot distribution divergence (HDD), which uses the average distance or standard deviation of the hotspot region's centroid to characterize the dispersion of the hotspot distribution. Higher divergence values ​​indicate a more dispersed hotspot distribution, which may require a more complex blocking strategy. Furthermore, the system calculates the long-tail index (α) by fitting the power-law distribution P(x) ∝ x^(-α). This index reflects the extent of the long-tail distribution; larger α values ​​indicate a more concentrated distribution. The system also calculates the Gini coefficient (G) and entropy (H), which quantify the characteristics of the activity distribution from the perspectives of unevenness and information theory, respectively. Finally, based on these characteristics, the system classifies the matrix as "strong long tail," "moderate long tail," "weak long tail," or "uniformly distributed," providing guidance for subsequent optimization strategy selection. These long-tail distribution features collectively constitute the matrix's characteristic fingerprint, a key input for generating adaptive blocking strategies.

[0060] Example 3 like Figure 2 As shown, the detailed steps of generating the adaptive block strategy of the present invention include: Step 301: Obtain statistical distribution data of the global activity and statistical distribution data of the local activity, design blocks adapted to the L1 cache for areas whose activity exceeds a third preset threshold, and design blocks adapted to the L2 / L3 cache for areas whose activity is lower than a fourth preset threshold, to obtain an initial block solution.

[0061] In this step, the system first comprehensively analyzes the global activity distribution and local activity characteristics of the matrix to identify areas of high computational density. The system then sets a third preset threshold (typically 0.7-0.8, which can be dynamically adjusted based on the application scenario) and marks areas with activity exceeding this threshold as high-priority processing targets. For these high-activity areas, the system designs a small-size block strategy to ensure that the blocks fully fit within the ARM processor's L1 cache. The system analyzes the L1 cache characteristics in detail, including capacity (typically 16-64KB), row size (typically 64 bytes), and associativity (typically 4-way or 8-way set associative), and then calculates the optimal block size. For typical ARM architectures, the system typically selects block sizes of 4×4, 8×8, or 16×16. These sizes ensure that block data and intermediate computational results remain entirely within the L1 cache, maximizing cache hit rates. The system also takes into account the characteristics of NEON vector instructions and optimizes the block size to meet SIMD processing requirements. For example, for 32-bit floating-point numbers, the dimension length of the inner loop should be a multiple of the 4 elements that can be processed by the 128-bit NEON register. This small-size block strategy significantly improves computational efficiency in highly active areas and reduces cache misses and memory access latency.

[0062] In this step, the system identifies regions in the matrix where activity falls below a fourth preset threshold (typically 0.3-0.4). These regions typically have low computational density and contribute relatively little to the final result. For these low-activity regions, the system designs a large-size block strategy to match the L2 or L3 cache characteristics of the ARM processor. The system analyzes the capacity and access characteristics of the L2 cache (typically 256KB-2MB) and L3 cache (typically 2-4MB) to determine an appropriate block size, typically 32×32, 64×64, or larger. This large block size offers several key advantages: first, it reduces overall task scheduling overhead, as larger blocks mean fewer tasks; second, it reduces the complexity of block boundary processing; and third, it facilitates the use of ARM's cache prefetching mechanism, improving memory access efficiency. For regions with extremely low activity, the system can also employ special optimization strategies, such as using compressed sparse formats (CSR or CSC) for storage or applying low-precision representations (such as FP16 or INT8), to further reduce memory usage and improve processing efficiency. This activity-based differentiated partitioning strategy ensures a precise match between computing resource allocation and matrix characteristics, significantly improving overall computing efficiency.

[0063] Step 302: Based on the initial block scheme, identify cross-block hotspot areas, ensure that the hotspot elements are completely contained in a single block through overlapping cutting, and output block boundary data.

[0064] In step 302, the system uses overlapping cutting techniques to process hotspots across tiles. For hotspots shared by adjacent tiles, the system creates a new tile containing the overlapping area. The size of the overlapping area is dynamically adjusted based on the activity and shape of the hotspot, typically 10%-30% of the original tile size.

[0065] In this step, the system addresses the issue of the initial segmentation scheme potentially splitting hotspots into multiple segments. This segmentation significantly impacts computational efficiency because cross-segment hotspots require frequent inter-segment communication and data synchronization. The system first identifies cross-segment hotspots. These regions meet the following criteria: they contain elements from the hotspot identified in step 211, and these elements are segmented into two or more segments by the initial segmentation scheme. For identified cross-segment hotspots, the system employs an overlapping segmentation strategy. In cases where adjacent segments share a hotspot, a new segment containing the overlapping region is created to ensure the hotspot is fully contained. The size of the overlapping region is dynamically adjusted based on the hotspot activity and shape, typically ranging from 10% to 30% of the original segment size. The system also implements a hotspot merging strategy. When multiple small hotspots are located in close proximity, they are merged into a larger segment. The merging criteria are based on the ratio of hotspot distance to hotspot size, using an adaptive threshold. Furthermore, the system can adjust segment shape to better accommodate irregular hotspots. For example, for strip-shaped hotspots, segments can be adjusted from square to rectangular. These boundary optimization techniques significantly improve the locality and efficiency of hotspot area processing, reduce cross-block communication overhead, and are key steps to improving overall performance.

[0066] Step 303: Obtain block boundary data and perform memory alignment optimization to ensure that the block boundary is aligned to the cache line.

[0067] In step 303, the system ensures that the block boundaries are aligned with cache line boundaries, usually multiples of 64 bytes, to avoid extra overhead caused by cross-cache line access. At the same time, the system adjusts the block start position to meet the memory alignment requirements required for NEON vector instruction operations.

[0068] In this step, the system optimizes the memory alignment of block boundaries based on the cache characteristics of ARM processors. The system first obtains the block boundary data output in step 302, including the start and end coordinates of each block. The system then performs memory alignment optimization, adjusting the block boundary positions to ensure that the block start address aligns with a cache line boundary, which is typically a multiple of 64 bytes. This alignment optimization has several important advantages: First, it avoids the overhead of splitting cache line accesses, improving memory access efficiency; second, it reduces cache conflicts and false sharing, especially in multi-core parallel computing environments; and third, it optimizes NEON vector instruction access, as many NEON operations require memory address alignment. The system implements an intelligent alignment algorithm to minimize redundant data caused by alignment adjustments while maintaining the logical integrity of the blocks. For example, when possible, the system will align the block start address upward and the end address downward to avoid unnecessary expansion. For hotspots that must cross cache line boundaries, the system designs special access patterns to reduce the frequency of cross-line accesses. This memory alignment optimization fully utilizes the characteristics of the ARM cache architecture to significantly improve memory access efficiency, which is particularly important for computations with limited memory bandwidth.

[0069] Step 304: Obtain historical execution data and fine-tune the block size and shape based on the execution efficiency index. In this step, the system further optimizes the block parameters based on the historical execution data through the feedback optimization mechanism.

[0070] The system first checks for available historical execution data, derived from the feedback mechanism in step 4 or a pre-set optimization experience library. If historical data is available, the system calculates the similarity between the current matrix features and those recorded in the historical data using a multi-dimensional feature vector distance metric, which includes matrix dimensions, sparsity patterns, and hotspot distribution characteristics. The system selects the historical data with the highest similarity as a reference, extracts block parameters from it, including block size, shape, and overlap strategy, and applies these parameters to adjust the current block scheme. The system also incrementally fine-tunes the current block parameters based on performance trends in the historical data. For example, if historical data indicates that increasing the size of a specific block type improves performance, similar adjustments are attempted in the current scheme, keeping the change within a safe range (typically ±20% of the baseline value). For first-time executions (without historical data), the system uses a safe default strategy, such as setting the block size to 85%-95% of the theoretical optimal value, to mitigate potential cache capacity estimation errors. The system also performs block balancing, adjusting the sizes of blocks with similar activity levels to minimize scheduling complexity. Through this experience-based fine-tuning, the system can continuously learn and improve the blocking strategy, adapt to the characteristics of different matrix calculations, and provide optimized execution performance.

[0071] Example 4 like Figure 3 As shown, the detailed steps of historical execution data feedback and optimization of the present invention include: Step 401: Obtain block execution data, and collect the execution time, cache hit rate, and instruction throughput of each block.

[0072] In step 401, the system collects detailed execution data through the ARM Performance Monitoring Unit (PMU), including execution time metrics, cache-related metrics, instruction execution metrics, and memory access metrics. This data provides empirical evidence for subsequent optimization.

[0073] The system performs matrix calculations based on the block-based solution output in step 3, while simultaneously activating the ARM processor's Performance Monitoring Unit (PMU) to collect detailed execution performance data. The ARM PMU is a hardware counter system integrated into the processor that records various performance events with minimal overhead. The system focuses on monitoring the following performance metrics: First, execution time metrics, including the absolute execution time (in microseconds) of each block, normalized execution time (per-element computation time), and execution time variance across blocks. These metrics directly reflect computational efficiency and load balancing. Second, cache-related metrics, such as the L1D_CACHE_REFILL and L2D_CACHE_REFILL PMU event counters, are used to obtain L1 / L2 / L3 cache hit rates, cache line replacement frequency, and TLB miss rates. These metrics reflect memory system efficiency. Third, instruction execution metrics, including instruction throughput (IPC), branch prediction failure rate, NEON instruction share, and instruction stall cycles, reflect processor core utilization efficiency. Finally, memory access metrics, including memory bandwidth utilization, memory access latency, and cross-node memory access ratio (for multi-chip systems), are monitored. The system collects this data using a low-intrusion design, employing the PMU's sampling mode rather than full counting mode, and batching data to minimize impact on the main computing process. This detailed performance data provides a solid empirical foundation for subsequent optimization and serves as a key input for data-driven optimization.

[0074] Step 402: Acquire performance indicators and analyze the correlation between the block execution data and the performance indicators.

[0075] In step 402, the system performs multi-dimensional correlation analysis, including single-factor performance sensitivity analysis, multi-factor interaction effect analysis, and hotspot bottleneck location. Through these analyses, the system can identify key factors affecting performance.

[0076] In this step, the system conducts an in-depth analysis of the raw performance data collected in step 401 to identify key factors affecting performance. The system first preprocesses the raw data, including outlier detection and processing, missing value interpolation, data normalization, and time series smoothing to ensure the reliability of the analysis. The system then correlates the performance data with the block features to construct a multidimensional analysis matrix, including feature dimensions (block size, location, activity, etc.), performance dimensions (execution time, cache hit rate, etc.), and environmental dimensions (CPU frequency, temperature, etc.). The system performs multi-level correlation analysis: First, single-factor performance sensitivity analysis calculates the Pearson correlation coefficient between each feature and key performance indicators (such as execution time). Scatter plots are then drawn to identify linear and nonlinear relationships. For categorical features, ANOVA analysis of variance is used to assess the significance of performance differences. Second, multi-factor interaction analysis identifies the impact of interactions between features on performance, such as the interaction between block size and cache capacity on cache hit rate. Methods such as partial least squares regression are used to address multicollinearity between features. Finally, hotspot bottleneck identification is performed, with in-depth analysis of blocks experiencing performance anomalies to identify bottleneck causes and categorize common performance problem patterns, such as cache thrashing and misprediction. The system specifically focuses on several key correlation patterns: the functional relationship between block size and cache hit rate, the relationship between matrix activity patterns and computational efficiency, the impact of non-zero element distribution on NEON vectorization efficiency, and the varying adaptability of ARM big.LITTLE cores to different block characteristics. These analytical results directly guide the development of subsequent optimization strategies, ensuring that optimization decisions are based on a solid data foundation.

[0077] Step 403: Obtain correlation data between the block execution data and the performance indicators, and establish a mapping relationship model between matrix features and optimal block parameters.

[0078] In step 403, the system uses a lightweight machine learning algorithm to build a mapping relationship model. The model is divided into a classification layer (using a decision tree or a simplified random forest), a regression layer (using a piecewise linear regression or a simplified multi-layer perceptron), and a fine-tuning layer (using a local search algorithm such as Hill Climbing or simulated annealing).

[0079] In this step, the system builds a machine learning model that predicts the optimal block parameters based on the correlation analysis results of step 402. The system first defines the optimization objective function, which usually takes minimizing the total execution time as the main goal while balancing energy consumption, memory usage, and computational accuracy. These goals are combined into a weighted objective function F = w1T + w2E + w3M, where T is time, E is energy consumption, M is memory usage, and w is the corresponding weight. The system constructs a training data set, where the feature vector X contains features such as matrix dimension, sparsity, and hotspot distribution pattern, the label vector Y contains parameters such as the corresponding optimal block size, shape, and overlap strategy, and the weight vector W assigns different weights based on sample reliability and importance. Considering the resource constraints of the ARM embedded environment, the system employs a lightweight model architecture and implements a hierarchical prediction framework. The first layer predicts the partitioning strategy type (uniform / asymmetric / hybrid) using decision trees or simplified random forests. The second layer predicts key partitioning parameters (size range, ratio) using piecewise linear regression or a simplified multilayer perceptron. The third layer fine-tunes specific parameters (precise size, overlap) using local search algorithms such as Hill Climbing or simulated annealing. The system trains the model using incremental learning, continuously updating the model as new performance data accumulates. NEON instructions are used to accelerate the model training process. To improve generalization, the system implements feature engineering (constructing combined features to capture interaction effects), regularization (applying L1 / L2 regularization to reduce overfitting), and cross-validation (using k-fold cross-validation to assess model stability). To address the cold start problem (where no historical data is available for a new matrix), the system employs transfer learning, transferring initial parameters from models of similar matrix types and generating prior knowledge based on theoretical models. The resulting mapping model accurately predicts optimal partitioning parameters from matrix features, providing decision support for adaptive optimization.

[0080] Step 404: deploy the mapping relationship model into the ARM TrustZone environment and update the block strategy history library.

[0081] In step 404, the system deploys and updates the partitioning policy history library in the ARM TrustZone secure environment to ensure the reliability of optimization decisions and data integrity. TrustZone provides a hardware isolation mechanism to prevent malicious modification of policy data.

[0082] The system securely deploys the mapping relationship model constructed in step 403 into the ARM TrustZone environment and updates the block policy history library. TrustZone is a security technology provided by the ARM architecture that creates a hardware-isolated trusted execution environment that can prevent policy data from being maliciously modified and ensure the reliability of optimization decisions. The system designs the data structure of the block policy history library and uses technologies such as LSH (locally sensitive hashing) to build efficient indexes to support fast similarity queries. The record format contains complete block scheme parameters, execution environment information, and performance results. Lossless compression is applied to data that has not been used for a long time to save storage space. The system executes a policy library update process: First, new data is integrated. The matrix features and optimal block parameters of the current execution are added to the history library. If similar records exist, a weighted average is calculated to update the parameters, while also recording the execution context, such as CPU load, temperature, and other environmental factors. Next, policy generalization and induction are performed. Based on the model, rules covering a wider parameter space are generated. Common rules are summarized for similar matrix types to reduce redundant storage, extract parameter change trends, and construct dynamic adjustment guidelines. Finally, redundancy optimization and pruning are performed. Highly similar historical records are identified and merged, outdated records that have been replaced by new data are deleted, and records of special cases are retained as guidance for handling extreme cases. Finally, version management and consistency maintenance are performed. This involves implementing an incremental update mechanism to ensure the atomicity of library updates, maintaining policy version history, supporting rollbacks to stable versions, and synchronizing the policy library across distributed environments to ensure consistency across nodes. The system specifically focuses on extracting and updating several types of specialized policies: matrix type-specific policies (such as specialized optimizations for the Toeplitz matrix of convolutional networks and the attention matrix of the Transformer), hardware adaptability policies (parameter differences between different ARM processor models), and dynamic environment response policies (adjustment policies for system load changes). Through the policy library management of the TrustZone security environment, the system achieves the safe accumulation and effective utilization of optimization experience.

[0083] Step 405: Obtain historical database data and record the optimal block parameters under different matrix characteristics.

[0084] In this step, the system builds a comprehensive database of relationships between matrix features and optimal partitioning parameters, forming a knowledge base to support subsequent optimization decisions. The system first retrieves historical data from the TrustZone environment, obtaining the recorded optimal partitioning parameters for various matrix features. The system then systematically organizes this data, categorizing it by matrix type (e.g., dense, sparse, structured), application scenario (e.g., deep learning inference, scientific computing, image processing), and hardware configuration (e.g., different ARM processor models and core configurations), creating a multidimensional index structure. For each matrix feature combination, the system records the optimal partitioning parameter set, including the partition size for high-activity regions, the partition size for low-activity regions, the overlapping region processing strategy, the core affinity configuration, and the accuracy strategy. The system also records the performance metrics of these parameters under different execution environments, such as execution time, energy consumption, and cache utilization, as well as parameter sensitivity analysis results, indicating which parameter changes have the greatest impact on performance. The system implements an efficient knowledge base query mechanism that supports similarity retrieval based on matrix features, enabling rapid identification of reference configurations for new matrix computation tasks. Furthermore, the system maintains parameter evolution histories, tracking how optimization parameters for specific matrix types change over time and with data accumulation. This helps understand long-term optimization trends and potential areas for improvement. Through this systematic recording and management of historical data, the system transforms scattered execution experience into structured knowledge, significantly improving the quality and efficiency of optimization decisions. This enables experience-driven continuous optimization and provides powerful support for handling various types of matrix computation tasks.

[0085] Example 5 like Figure 4 As shown, the detailed steps of heterogeneous core task weight prediction and scheduling of the present invention include: Step 501, obtain block characteristic data, assign blocks with a computing density exceeding a fifth preset threshold to the first core for processing, and assign blocks with a computing density lower than a sixth preset threshold to the second core for processing, and the number of the first cores is higher than the number of the second cores.

[0086] In step 501, the system analyzes the compute density ratio (CDR) of each block and allocates high-density blocks with a CDR greater than 10 to large cores (such as the Cortex-A7x series, the first core) for processing, while low-density blocks with a CDR less than 5 are allocated to small cores (such as the Cortex-A5x series, the second core). This allocation strategy fully utilizes the heterogeneous nature of the ARM big.LITTLE architecture.

[0087] In this step, the system first analyzes the computational characteristics of each block, focusing on the compute density ratio (CDR), which is the ratio of the number of computational operations to the number of memory accesses per block. For matrix multiplication blocks, the calculation formula is CDR = (2mn-1)k / (mk + kn + m*n), where m, n, and k represent the block dimensions. The system sets a fifth preset threshold (typically 10) and a sixth preset threshold (typically 5) to classify blocks as compute-intensive, memory-intensive, or mixed. The system employs a "compute-intensive priority allocation strategy," prioritizing high-compute-density blocks with a CDR greater than 10 (typically small, high-activity blocks) for processing on large cores (such as the Cortex-A7x series). These blocks typically have high instruction-level parallelism, fully utilizing the deep pipelines and complex execution units of large cores, and their data sets typically fit entirely in the L1 cache. Conversely, the system allocates low-compute-density blocks with a CDR less than 5 (typically large, low-activity blocks) to small cores (such as the Cortex-A5x series). These blocks frequently access memory, causing processor waits. This prevents the large cores from fully utilizing their high computing power. Memory access is highly random, resulting in low cache hit rates. Therefore, processing is more efficient on smaller cores with lower power consumption. For blocks with mixed characteristics between these two extremes, the system dynamically allocates them based on the current core load. The system also analyzes each block's memory access patterns (spatial locality, temporal locality, access regularity, and bandwidth pressure), parallelism characteristics (instruction-level parallelism, data-level parallelism, and task-level parallelism), and dependencies. These characteristics provide a basis for subsequent refined scheduling.

[0088] Step 502: Receive block priority data and set task execution order and preemption strategy.

[0089] In step 502, the system assigns execution priorities based on the location and criticality of the blocks in the dependency graph, determines which high-priority tasks can preempt low-priority tasks, and sets a maximum execution time to prevent a single task from occupying resources for a long time.

[0090] In this step, the system assigns execution priority to each block task based on the position and criticality of the block in the matrix calculation dependency graph. The system first builds a dependency graph (DAG) between blocks and analyzes the critical path and task dependency depth. Blocks that are on the critical path and have longer dependency chains are given higher execution priority because their execution delays directly affect the overall calculation completion time. The system assigns a priority level to each block task, which is usually divided into three levels: high, medium, and low, and configures corresponding scheduling strategies. For critical tasks with the highest priority, the system allows them to preempt low-priority tasks to ensure that the critical calculation path is not blocked. The system also sets a maximum execution time threshold to prevent a single task from occupying processing resources for a long time, leading to priority inversion problems. For block groups with dependencies, the system calculates the overall priority to ensure that dependencies are handled correctly and avoid deadlocks or resource starvation. The system also implements a dynamic priority adjustment mechanism, adjusting task priorities based on real-time execution. When it detects that certain tasks are taking significantly longer than expected, the system increases the priority of their successors, accelerating the critical path. When the system load is light, it reduces the difference in priority between tasks, improving resource utilization. When it detects excessively high temperatures, it adjusts the priority strategy to avoid sustained high loads in hot spots. This fine-grained priority management and preemption strategy ensures that computing resources are allocated appropriately, critical tasks are processed promptly, and overall execution efficiency is significantly improved.

[0091] Step 503: Obtain the core characteristics of the ARM processor, configure core affinity, obtain core affinity configuration, and specify the execution core of a specific type of task.

[0092] In step 503, the system configures core affinity, including hard affinity (tasks must be executed on a specific core type) and soft affinity (tasks are prioritized for execution on a specific core type, but can be migrated during load balancing). This configuration ensures that tasks are assigned to the most suitable processing core.

[0093] In this step, the system configures a precise core affinity policy based on the detailed characteristics of the ARM processor and the computational requirements of the task block, ensuring that tasks are assigned to the most appropriate processing core. The system first obtains the ARM processor's core configuration information, including the specific model, frequency range, pipeline depth, cache configuration, and instruction set extensions of both the large core (e.g., the Cortex-A7x series) and the small core (e.g., the Cortex-A5x series). The system implements two types of core affinity configuration: hard affinity and soft affinity. Hard affinity specifies that tasks must execute on a specific core type and is typically applied to critical blocks with strict computational requirements. For example, a compute-intensive block that relies heavily on NEON instructions must execute on a large core supporting advanced NEON extensions. Soft affinity prioritizes execution on a specific core type but allows tasks to be migrated during load balancing, providing greater scheduling flexibility. The system also evaluates task portability—the cost-benefit ratio of migrating tasks between cores—which influences dynamic load balancing decisions. The system implements refined affinity strategies to address specific computing characteristics: for example, for blocks that rely on advanced vector instructions, cores with the latest ARM architecture are assigned; for memory-intensive blocks, cores with low memory access latency are selected, taking into account the memory controller topology; and for groups of blocks with data dependencies, cores with shared caches are assigned as much as possible to reduce synchronization overhead. The system also maintains a core capability database that records the efficiency characteristics of different ARM cores for specific computing modes and guides affinity decisions. This fine-grained core affinity configuration fully leverages the characteristics of ARM's heterogeneous multi-core architecture, ensuring the optimal match between tasks and processing cores, significantly improving computing efficiency and energy utilization.

[0094] Step 504: Receive the dependency relationship of the executed tasks, implement task group scheduling and synchronous checkpoint setting.

[0095] In step 504, the system groups the dependent blocks into scheduling units, determines the ideal execution order of each task group, and sets necessary synchronization checkpoints to ensure that data dependencies are met.

[0096] In this step, the system handles complex task dependencies and designs efficient task group scheduling strategies and synchronization mechanisms. The system first receives the task dependency graph (DAG) generated in step 502 and analyzes the types of dependencies between tasks: data dependencies (the output of one task is the input of another), resource dependencies (tasks competing for shared resources), and control dependencies (constraints on the order in which tasks execute). The system adopts a batch scheduling strategy, grouping closely dependent blocks into scheduling units to reduce scheduling overhead and task switching frequency. For a typical matrix multiplication calculation, the system analyzes the multiplication path, identifies groups of blocks that can be executed in parallel, and constructs balanced execution batches. The system sets key synchronization checkpoints to ensure the correct execution order of dependent tasks. These checkpoints are typically set between major computational phases, such as the row block completion point or column block processing switch point in matrix multiplication. The system implements lightweight synchronization primitives, including barriers, semaphores, and condition variables, using the ARM architecture's atomic operation instructions for efficient implementation to minimize synchronization overhead. For tasks on the critical path, the system uses an advance notification mechanism. When the preceding task is nearing completion, it triggers the preparation of subsequent tasks in advance, reducing task switching delays. The system also implements adaptive batch size adjustment, dynamically adjusting the batch size according to the execution progress and resource availability: in the early stages of the calculation, when all tasks are available, larger batches are used to improve parallelism; in the later stages of the calculation, when the number of tasks decreases, the batch size is reduced to improve flexibility. In addition, the system also handles task cancellation and error recovery scenarios to ensure that the remaining tasks can be safely rolled back or continued when some tasks fail. This efficient task group scheduling and synchronization mechanism maximizes parallel execution opportunities while ensuring computational correctness, significantly improving overall execution efficiency.

[0097] Step 505: Obtain cache characteristic data, optimize shared cache and memory access strategies, and reduce inter-core data transfer. In this step, the system deeply optimizes cache usage and memory access patterns in ARM processor multi-core environments, focusing on addressing inter-core data sharing and transfer issues. The system first obtains detailed information about the ARM processor's cache hierarchy, including the capacity, associativity, sharing relationships, and the MESI (Modify, Exclusive, Shared, Invalid) cache coherence protocol characteristics of each cache level. Targeting the heterogeneous multi-core environment of the ARM big.LITTLE architecture, the system optimizes inter-core data sharing: First, shared cache-aware scheduling prioritizes data-dependent blocks to cores sharing the L2 / L3 cache, maximizing cache sharing benefits. Second, a data migration minimization strategy replaces data migration with task migration, prioritizing computing tasks to the core where the data resides rather than moving data to the execution core. Third, NUMA-aware optimization (applicable to multi-chip ARM servers) considers the physical topology of the memory controller and processing cores to minimize memory accesses across NUMA nodes. The system also implements cache segmentation and partitioning technologies, allocating independent cache regions to different types of block tasks, reducing cache contamination and conflicts. For data that needs to be shared frequently, the system uses cache pinning technology to prevent critical data from being replaced out of the cache. The system optimizes memory consistency management, accurately uses memory barrier instructions (such as DMB and DSB), and inserts barriers only at necessary synchronization points to reduce consistency maintenance overhead. For independent blocks that can be executed in parallel, the system implements a data replication strategy, allowing data to exist redundantly in multiple core caches, eliminating sharing conflicts at the cost of slightly increasing memory usage. The system also uses a pre-fetch shared data strategy to load the data to be shared into the cache of the consumer core in advance before the producer task is completed, masking memory access latency. These cache and memory optimization strategies significantly reduce inter-core data transmission overhead and improve computing efficiency and scalability in multi-core environments.

[0098] Example 6 like Figure 5 As shown, the detailed steps of the NEON instruction set optimization execution of the present invention include: Step 601: Obtain the block characteristic data and select corresponding NEON instruction set optimization kernels for different types of blocks.

[0099] In step 601, the system selects the most suitable NEON instruction set optimized kernel based on the block characteristics. For small, highly active blocks, the system selects instruction templates optimized for intensive computation, such as VLDM (Vector Load Multiple Registers), VMLA (Vector Multiply Add Accumulate), and VSTM (Vector Store Multiple Registers). For large, less active blocks, the system selects memory-optimized instruction templates, focusing on optimizing cache utilization and memory access patterns.

[0100] In this step, the system selects and configures the most appropriate NEON instruction set-optimized kernel for each type of block based on the block characteristic data obtained in step 501. The system first carefully classifies the blocks, considering not only computational density but also data type (e.g., FP32, FP16, INT8), matrix structure characteristics (e.g., dense, sparse, structured), and computational mode (e.g., general matrix multiplication, matrix transposition, element-wise operations). For highly active, small blocks, the system selects instruction templates optimized for dense computation. These templates fully leverage NEON's SIMD parallelism, processing multiple data elements simultaneously through vectorized operations. Typical instruction sequences include VLDM (vector load multiple registers), VMLA (vector multiply-add accumulate), and VSTM (vector store multiple registers). The system carefully adjusts loop parameters based on the block dimensions to achieve optimal loop unrolling and register allocation. For example, for an FP32 matrix multiplication in a 4×4 block, four VMLA.F32 instructions are used to complete 16 scalar multiplications, achieving a 4x speedup. The system automatically adjusts inner loop bounds to multiples of 4 for 128-bit NEON registers (which can accommodate four 32-bit floating-point numbers) to ensure full utilization of vector instructions. For large, low-activity blocks, the system selects memory-optimized instruction templates, focusing on optimizing cache utilization and memory access patterns. PLD (preload) instructions are used to preload data into the cache, reducing memory access latency. For blocks with significant sparsity, the system uses conditional execution instructions, such as VCVT (conditional transform) combined with masking, to skip calculations on zero or very small values. For blocks with boundary regions or irregular shapes, the system selects specialized templates for boundary processing, which include boundary condition checking logic and leverage ARM's conditional execution feature to achieve branchless computations. The system also considers the microarchitecture of ARM processors. For processors supporting FMA (fused multiply-add) instructions (such as the Cortex-A73 and later architectures), VFMA instructions are preferred over VMLA instructions to improve accuracy and performance. This precise matching of block characteristics with NEON instruction templates significantly improves instruction-level parallelism and vectorization efficiency for matrix computations.

[0101] Step 602: Obtain block activity characteristics and configure mixed precision calculation matrix parameters.

[0102] In step 602, the system configures mixed-precision computation parameters based on the block activity characteristics. For high-activity areas, the system configures FP32 (32-bit single-precision floating point) computation; for moderate-activity areas, the system configures FP16 (16-bit half-precision floating point) computation; for low-activity areas, the system can configure INT8 (8-bit integer) or even lower precision representation. This mixed-precision strategy significantly improves processing efficiency and reduces energy consumption while maintaining critical computational accuracy.

[0103] In this step, the system implements a mixed-precision computing strategy that balances accuracy and performance based on the block activity characteristics. The system first evaluates the precision sensitivity of each block, primarily considering factors such as numerical activity, computational stability, and result impact. For high-activity regions (corresponding to "hot spots" in the matrix), where the absolute values ​​of elements are large and contribute significantly to the final result, the system uses FP32 (32-bit single-precision floating point) computing to ensure numerical accuracy. This high-precision configuration is particularly suitable for high-information regions near the matrix diagonal or corresponding to eigenvectors, ensuring that critical calculations are not affected by insufficient precision. For moderately active regions, the system uses FP16 (16-bit half-precision floating point) computing. FP16 offers significant advantages on ARM processors: it reduces memory usage by half, improving cache efficiency; NEON instructions can process twice the number of elements simultaneously, increasing computational throughput; and it significantly reduces power consumption, making it particularly suitable for mobile devices. In ARMv8.2 and higher, the system uses specialized half-precision instructions (such as VCVT.F16.F32) for precision conversion and instructions such as VFMUL.F16 to perform half-precision calculations. For low-activity regions (the long tail), the system implements a more aggressive precision degradation strategy, potentially using INT8 (8-bit integer) or even lower precision representations. The system uses quantization techniques to map floating-point values ​​to the integer range, maintaining relative accuracy using scaling factors and offsets. ARM NEON provides a rich set of integer vector instructions (such as VMULL.S8), enabling each 128-bit register to process 16 INT8 elements simultaneously, achieving higher parallelism. The system pays special attention to precision conversion boundaries, inserting necessary type conversion instructions at the intersection of different precision regions to ensure data type compatibility. To reduce the overhead of frequent conversions, the system implements a precision conversion buffer to batch type conversion operations. The system also tracks accumulated errors and dynamically increases the accuracy of critical paths when potential precision issues (such as overflow risks) are detected. This intelligent mixed-precision strategy significantly improves processing efficiency while maintaining computational accuracy, making it particularly suitable for resource-constrained ARM devices.

[0104] Step 603: Obtain memory access mode, configure ARM cache prefetch instructions, and optimize memory access sequence.

[0105] In step 603, the system configures the ARM cache prefetch instructions (PLD - Preload Data) to preload the data to be used into the cache. The system selects the appropriate prefetch target level based on data reuse characteristics and dynamically adjusts the prefetch distance, typically 16-64 cache lines (approximately 1-4KB of data).

[0106] In this step, the system configures an optimized cache prefetch strategy and memory access pattern based on the memory access characteristics of each block. The system first analyzes the block's memory access pattern, including spatial locality (proportion of contiguous memory accesses), temporal locality (frequency of data reuse), access regularity (predictability of access patterns), and bandwidth pressure (number of memory accesses per unit time). For access patterns exhibiting high regularity (such as row and column scans in matrix multiplication), the system configures hardware prefetch instructions (PLD - Preload Data) to preload upcoming data into the cache. The ARM architecture supports different prefetch strategies, and the system selects the appropriate prefetch target level based on data reuse characteristics: highly reused data is prefetched into the L1 cache; moderately reused data is prefetched into the L2 cache; and streaming data that is only accessed once is retained in the L1 cache using the PLDL1KEEP instruction. The prefetch distance (how far ahead of computation time the data is prefetched) is a key parameter, dynamically adjusted by the system based on processor characteristics and memory latency, typically ranging from 16 to 64 cache lines (approximately 1 to 4KB of data). The system also avoids excessive prefetching, preventing useful cache content from being replaced by unnecessary prefetched data. For large blocks, the system implements a segmented prefetch strategy, prefetching only the portion to be processed, reducing the risk of cache contamination. The system also optimizes memory access order and rearranges computations to maximize memory access continuity. For small blocks with intensive computations, the system optimizes data alignment and padding to ensure that memory accesses are aligned to cache line boundaries (typically 64 bytes). For operations with unfriendly access patterns, such as matrix transposition, the system implements matrix rearrangement and buffering techniques to convert column accesses into more efficient row accesses. For large blocks with sparse computations, the system applies compressed storage format optimization, selecting an appropriate storage format based on the sparsity pattern, such as row compression (CSR), column compression (CSC), or coordinate format (COO). The system specifically optimizes the use of the ARM architecture's TLB (Translation Lookaside Buffer), prioritizing large page mappings (typically 2MB rather than 4KB) to reduce TLB miss rates. These cache prefetching and memory optimization strategies directly improve data access efficiency and significantly reduce the impact of memory latency on computational performance.

[0107] Step 604: Execute calculations of each block in parallel according to the core affinity configuration to obtain calculation results of each block.

[0108] In step 604, the system executes the computations for each block in parallel across the heterogeneous multicores according to the task scheduling scheme. The system employs a dynamic scheduling model, assigning compute-intensive blocks to large cores and memory-intensive tasks to smaller cores. The system also implements a work-stealing mechanism, allowing idle cores to acquire tasks from other queues, improving resource utilization.

[0109] In this step, the system coordinates the execution of each block of computation on the ARM heterogeneous multi-core architecture based on the core affinity configured in step 503 and the task scheduling policy generated in step 504. The system first initializes the parallel execution environment, establishes a thread pool and task queue, and creates independent task queues for big and small cores. For the typical ARM big.LITTLE architecture, the system identifies the processor core type (e.g., Cortex-A7x for big cores and Cortex-A5x for small cores) and configures execution parameters based on its characteristics. The system uses lightweight synchronization primitives (such as spinlocks and atomic operations) to enable inter-thread communication, minimizing synchronization overhead. The system applies the optimization parameters configured in steps 601 to 603 to each block, including the NEON instruction sequence, precision configuration, and memory access policy. The parallel execution phase utilizes a dynamic scheduling model, implementing the core strategy of assigning compute-intensive blocks to big cores and memory-intensive tasks to small cores. When a core completes its current task, it retrieves a new task from the corresponding queue. If a queue is empty, the system activates a work-stealing mechanism, allowing idle cores to acquire tasks from other queues to improve resource utilization. The system implements fine-grained load monitoring and dynamic balancing, detecting load imbalances by tracking the task completion rate and queue length of each core in real time. When an imbalance is detected (e.g., a large core's queue is backlogged while smaller cores are idle), the system triggers task redistribution, migrating some tasks from the busy queue to the idle queue. Migration decisions take into account task characteristics and migration costs, prioritizing "floating" tasks with moderate computational characteristics. The system also integrates frequency-aware scheduling and thermal management, monitoring the operating frequency of each core (which may fluctuate dynamically due to temperature and power consumption constraints) and allocating high-intensity computations to cores with the highest current frequency. Furthermore, the system implements a temperature balancing strategy to prevent overheating and frequency drops caused by sustained high load on some cores. For blocks with data dependencies, the system implements precise dependency tracking and synchronization mechanisms, ensuring that a block is scheduled for execution only after all prerequisites have completed. This efficient parallel execution strategy fully leverages the advantages of ARM's heterogeneous multi-core architecture to achieve optimal computational load distribution.

[0110] Step 605: Obtain the calculation results of each block, perform result merging and correctness verification.

[0111] In step 605, the system collects all the block calculation results and reconstructs them into a complete matrix based on the mapping relationship of the original block solution. For overlapping regions, the system applies a merging strategy to ensure the consistency of the results. The system performs multiple levels of verification, including numerical stability checks, accuracy verification, and feature verification, to ensure the correctness and reliability of the calculation results.

[0112] In this step, the system collects and integrates the computational results of all blocks, performing result merging and comprehensive correctness verification. The system first collects the computational results of each block executed in parallel in step 604 and reorganizes them into a complete matrix based on the mapping relationship of the original block scheme. For overlapping areas, the system applies a merging strategy: for addition operations, any copy can be directly taken; for accumulation operations (such as matrix multiplication), the impact of duplicate calculations needs to be eliminated, usually by weighting the overlapping areas. The system uses atomic operations to ensure data consistency during concurrent writes, avoiding race conditions caused by multiple threads updating the same memory location at the same time. After the results are merged, the system performs multi-level verification checks: first, a numerical stability check is performed, calculating key statistical indicators such as maximum, minimum, average, and standard deviation to ensure that the results are within a reasonable range; second, accuracy verification is performed, sampling and comparing the differences between the mixed precision calculation results and the standard precision calculation results (usually FP64) to ensure that the accuracy loss is within an acceptable range; third, property verification is performed, for matrix operations with theoretically known properties (such as the unit of orthogonal matrix products), checking whether the results meet mathematical expectations. The system pays special attention to potential numerical issues, such as underflow (values ​​that are too small to be rounded to zero), overflow (values ​​that exceed the representation range), and outliers (NaN or infinity), implementing automatic detection and reporting mechanisms. For iterative algorithms (such as matrix inversion and eigenvalue calculation), the system verifies convergence conditions to ensure that the results meet predetermined error thresholds. As a quality assurance measure, the system also performs self-consistency checks, recalculating some calculation results using different algorithm paths and comparing the consistency of multiple results. For detected issues, the system implements a graded response strategy: minor precision issues generate warnings but do not affect the output; moderate issues trigger automatic correction processes, such as recalculating the problem area; and severe issues (such as numerical instability) trigger error handling, which may fall back to a conservative algorithm or report an error condition to the application. After verification, the system performs final data post-processing, including format conversion, memory reordering, and result optimization, to output final results that meet application requirements. This rigorous result merging and verification mechanism ensures the correctness and reliability of block-by-block parallel computing, providing quality assurance for optimized calculations.

[0113] Example 7 like Figure 6 As shown, the present invention also provides a matrix calculation adaptive optimization system based on ARM architecture, comprising: An acquisition module 701 is configured to acquire matrix data to be processed and ARM processor information, and preprocess the matrix data to be processed to obtain preprocessed matrix data. Identification module 702, configured to perform local activity calculation and hotspot area identification on the pre-processed matrix data to determine the long-tail distribution characteristics of the matrix; A calculation module 703 is configured to receive the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters of the ARM processor, calculate the optimal block size range, and generate an asymmetric block solution; Establishing module 704, for obtaining the asymmetric block solution, collecting the execution time and cache hit rate of each block, and establishing a mapping relationship between matrix features and optimal block parameters; A generation module 705 is used to obtain the asymmetric block scheme and mapping relationship, calculate the computing density and memory access mode of each block, and generate a task scheduling scheme; The output module 706 is configured to obtain the task scheduling solution, perform matrix calculations on an ARM big.LITTLE architecture processor, and output final calculation results.

[0114] Example 8 The method of the present invention also includes ARM matrix calculation optimization and verification based on formal specifications, specifically comprising the following steps: The system obtains the matrix operation flow and the characteristics of the ARM processor and defines an axiom system of operations using a formal language to obtain a formal specification. In this step, the system first establishes a rigorous formal specification that precisely describes the mathematical properties and expected behavior of matrix operations. The system uses a formal language (such as Z notation, TLA+, or Coq) to define the axiom system of matrix operations, including the mathematical properties of basic operations such as addition, multiplication, and transposition, such as associativity, distributiveness, and various boundary conditions. For long-tailed distributed matrices, the system specifically defines their activity characteristics, formally describing the characteristics and processing requirements of hot and low-activity regions. The formal specification also includes numerical accuracy requirements, clearly defining acceptable error ranges and rounding behavior. For ARM architectural features, the system incorporates hardware characteristics (such as NEON instruction semantics, cache coherence model, and heterogeneous core characteristics) into the formal specification, establishing a formal framework for hardware-software collaboration. The system also defines the composability properties of operations to ensure that complex matrix operations can be implemented through the correct combination of basic operations. This precise formal definition ensures clear correctness standards for subsequent optimization processes, preventing unintended behavior from being introduced. In this way, the system establishes a "golden reference model" for matrix calculations, which serves as a benchmark for subsequent verification. This formal method is particularly suitable for scenarios with high reliability requirements, such as scientific computing, financial analysis, or safety-critical systems.

[0115] The formal specification is analyzed and processed to generate system verification assertions and output executable verification rules. In this step, the system automatically generates system verification assertions (SVAs) based on the formal specification to verify the correctness of the optimization implementation. The system first converts the formal specification into two types of assertions: static assertions and dynamic assertions. Static assertions are derived directly from the specification using formal methods and verify the structural properties of the optimization algorithm, such as deadlock freedom, correct resource release, and boundary condition handling. These assertions can be verified at compile time using static analysis tools. Dynamic assertions focus on runtime behavior, verifying that the computation results satisfy mathematical properties, such as the associative and distributive properties of matrix multiplication or the inherent properties of special matrices (such as orthogonal matrices). To improve the coverage and accuracy of SVA, the system incorporates Large Language Model (LLM) technology to convert optimization intent and potential edge cases described in natural language into formal assertions. LLM analyzes existing code and specifications to automatically generate test scenarios and assertion expressions, focusing on corner cases that are difficult to identify manually, such as matrices with special shapes and extreme numerical distributions. The system also generates verification rules for ARM-specific features, such as the correct use of NEON instructions, memory alignment requirements, and cache coherence maintenance. Generated assertions are converted into executable verification rules, including preconditions, postconditions, and invariants. These rules are expressed as assertion macros, runtime check functions, or input formats for formal verification tools. They can be embedded in actual code or used as input to external verification tools. The system optimizes verification rules, removing redundant checks, merging related assertions, and classifying them according to execution cost to ensure that the verification process itself does not become a performance bottleneck.

[0116] Based on the executable verification rules, the asymmetric partitioning scheme is verified for correctness using a theorem proving tool, generating a verification report. In this step, the system rigorously and formally proves the correctness of the asymmetric partitioning strategy in step 2, ensuring its mathematical equivalence. The system uses theorem proving tools (such as Coq, Isabelle / HOL, or Lean) to construct a proof model for matrix partitioning computation, demonstrating the consistency of computational results under different partitioning strategies. The proof begins by formally defining the semantics of standard matrix operations (as a reference implementation), then defining the operational semantics of the asymmetric partitioning version. Subsequently, through mathematical induction or other proof techniques, it is demonstrated that the two implementations produce equivalent results under all possible input conditions. The system specifically focuses on the merging logic of overlapping partitions, using formal methods to prove that the final results satisfy mathematical equivalence regardless of the merging strategy used (such as weighted averaging, preferential selection, or specific rule merging). For precision-sensitive operations, the system establishes precise error bound models, proving that the cumulative error does not exceed a preset threshold under a given precision configuration. The system also verifies the correct handling of boundary conditions, such as when matrix dimensions are not integer multiples of the block size or when hotspots straddle block boundaries. For performance-critical paths, the system verifies the safety of parallel execution through model checking, proving the absence of data races or deadlock risks. The verification process generates a detailed proof tree and intermediate steps, ultimately outputting a formal verification report containing all verification results. This report details the verification scope, methods, results, and possible boundary conditions, providing a solid theoretical basis for optimization decisions and ensuring computational correctness even in extreme cases.

[0117] Based on the validation report and mixed-precision computation data, an error propagation analysis is performed to establish a precision error model. In this step, the system deeply analyzes the errors introduced by mixed-precision computations and their propagation characteristics, constructing an accurate error model. The system first determines the error bounds and behavioral characteristics for each precision representation (e.g., FP32, FP16, and INT8) based on the formal definitions in the validation report. The system then analyzes the error propagation paths in matrix computations, focusing specifically on the error amplification effects of accumulation operations (e.g., dot products). The system establishes a hierarchical error model: an element-level error model captures rounding errors within individual operations; a block-level error model analyzes error accumulation within blocks; and a global error model assesses error propagation across the entire computation. For mixed-precision computations, the system specifically analyzes the error introduced at precision transition points (e.g., from FP32 to FP16 or from FP16 to FP32) and the impact of boundary processing between different precision regions. The system uses techniques such as interval arithmetic, error polynomials, or probabilistic error models to quantify the error characteristics for different matrix regions and operation types. For iterative algorithms (e.g., matrix inversion or eigenvalue computation), the system establishes an error accumulation model to predict error growth over multiple iterations. The system also considers ARM processor-specific error sources, such as the precision characteristics of NEON instructions and the rounding behavior of fused multiply-add operations. Based on these analyses, the system constructs a complete precision error model that can predict the error distribution and limits under a given computational graph and precision configuration. This model supports an adaptive precision strategy: high precision is maintained in error-sensitive hotspots; precision can be safely reduced in error-insensitive areas. The system parameterizes the model to support dynamic adjustment of precision configuration under different matrix characteristics and computational requirements, achieving an optimal balance between accuracy and performance. This precise error modeling significantly improves the reliability of mixed-precision calculations, ensuring that optimization does not sacrifice necessary computational accuracy.

[0118] Based on the precision error model and actual execution data, formal verification is performed and formal proof results are output. In this step, the system combines the theoretical error model with actual execution data for final formal verification, ensuring the correctness and stability of the entire optimization system. The system first collects key data points during the actual execution process, including intermediate results, error samples, and boundary condition behavior. The system then compares this data with the predictions of the precision error model to verify the model's accuracy and completeness. If significant deviations are found, the system refines the error model parameters to improve its prediction accuracy. After model verification, the system uses formal verification tools to perform a comprehensive correctness proof. This process includes several key aspects: first, functional correctness verification, proving that the optimization implementation is consistent with the mathematical specification; second, numerical stability verification, proving that the algorithm does not produce numerical overflow, underflow, or unstable behavior under all possible input ranges; and third, resource safety verification, proving that the implementation correctly manages memory, cache, and parallel resources and does not suffer from leaks or race conditions. The system uses a hybrid verification approach, combining static formal proof and dynamic symbolic execution, to comprehensively cover possible execution paths. For key optimization techniques such as asymmetric blocking, mixed-precision computing, and heterogeneous core scheduling, the system specifically constructs formal models to prove their correct behavior under various conditions. The verification process pays special attention to edge cases of long-tail distribution matrices, such as highly unbalanced activity distributions, extreme sparsity patterns, or special numerical distributions. The system ultimately outputs detailed formal proof results, including proof coverage, key property verification status, boundary condition handling, and verified performance guarantees. This rigorous formal verification provides the highest level of quality assurance for optimization implementations and is particularly suitable for critical application areas such as scientific computing, financial analysis, or safety-critical systems. Through a combination of theoretical proof and practical verification, the system ensures the reliability and correctness of optimization while maintaining high performance.

[0119] Acquire matrix calculation execution status information, perform verification checks, and generate verification results. In this step, the system implements a real-time verification mechanism during matrix calculation execution, monitoring the calculation status and promptly identifying potential issues. The system first defines collection points for key execution status information, including calculation phase boundaries, important intermediate results, resource usage, and system environment parameters. At these collection points, the system collects multiple types of status information: numerical status (such as the range, distribution characteristics, and outliers of intermediate results), calculation status (such as progress, number of completed blocks, and pending tasks), resource status (such as memory usage, cache hit rate, and core utilization), and system status (such as processor temperature, frequency, and power consumption). The system uses lightweight monitoring mechanisms to collect data, ensuring that monitoring itself does not significantly impact calculation performance. For example, this uses sampling techniques rather than full monitoring, or directly captures key metrics using ARM hardware performance counters. Based on the collected status information, the system performs multiple levels of validation checks: numerical correctness checks verify that intermediate results conform to theoretical expectations and promptly identify numerical instabilities or precision issues; resource integrity checks ensure that memory allocation, cache usage, and core scheduling conform to design specifications; schedule consistency checks monitor the execution progress of different blocks to identify potential load imbalances or scheduling anomalies; and boundary condition checks focus on system behavior under extreme conditions, such as performance degradation near full load. The system performs these checks using the validation rules generated in step 2 and records the results and relevant context of each check. For any anomalies discovered, the system records detailed information, including the anomaly type, severity, location, and relevant status data. The system ultimately generates structured validation results, including the status of all checkpoints, identified issues and their details, resource usage statistics, and performance metrics. These validation results provide critical support for subsequent error handling and recovery, enabling real-time quality control of the computational process.

[0120] Based on the verification results and pre-set error severity standards, a hierarchical error classification is performed to determine an error handling strategy. In this step, the system systematically categorizes issues discovered during the verification process and determines appropriate handling strategies based on their severity. The system first loads a pre-set error severity standard, which categorizes potential anomalies into multiple levels: critical (serious issues that lead to completely incorrect calculation results or system instability), severe (significant issues that significantly impact calculation accuracy or performance), warning (minor issues that may affect result quality but are not fatal), and informational (anomalies that do not affect results but are noteworthy). The system analyzes various anomalies in the verification results and classifies them based on multi-dimensional criteria: error type (e.g., numerical anomaly, resource issue, scheduling conflict), scope of impact (local block, specific region, or global calculation), potential consequences (data corruption, performance degradation, or reduced accuracy), and difficulty of repair (immediate fix, parameter adjustment, or recalculation). The system determines the final severity level for each issue based on the characteristics of the issue and the current execution context. Based on this classification, the system develops a corresponding handling strategy for each type of problem. For critical-level problems, the current calculation may need to be aborted, reverting to a safe state, and restarting with an alternative algorithm. For severe-level problems, the system may recalculate the problem area without interrupting the overall calculation, or adjust key parameters before continuing. For warning-level problems, the system records the problem details and may adjust relevant parameters, but continues the current calculation path. For information-level problems, the system only records the information for subsequent optimization and does not interfere with the current execution. The system also considers the combined effects of problems. When multiple lower-level problems occur simultaneously and potentially affect each other, their combined severity may increase. The handling strategy also includes action timing (immediate action or deferral until a specific checkpoint) and resource allocation decisions (such as allocating additional resources to fix the problem). The system outputs the final error classification and handling strategy in a structured format to guide subsequent recovery and adjustment processes. This sophisticated error classification and handling mechanism ensures that the system can gracefully handle various abnormal situations, maximizing the accuracy of calculation results and system stability.

[0121] Based on the error handling strategy and precision problem data, the system performs precision path adjustments and outputs the corrected computational path. In this step, the system implements precise computational path adjustments for detected precision-related issues to ensure that the computational results meet the precision requirements. The system first analyzes the precision issues in the error handling strategy, including numerical instability (such as asymptotic divergence, oscillation, or outliers), insufficient precision (such as loss of significant digits or excessive relative error), and inconsistent precision (such as error accumulation at the mixed precision boundary). The system also collects detailed context for the precision issues, including the matrix characteristics of the problem area, the currently used precision configuration, and computational path information. Based on this data, the system implements a multi-level precision path adjustment strategy. First, precision upgrade adjustment: For matrix regions detected to have insufficient precision (typically hotspots or critical computation paths), the system increases their computational precision, such as from FP16 to FP32 or from INT8 to FP16, to ensure sufficient numerical accuracy for critical computations. Second, algorithm path switching: For numerically unstable operations (such as computations on ill-conditioned matrices), the system switches to more stable algorithmic implementations, such as switching from a fast but potentially unstable algorithm to a more conservative but stable algorithm, or switching from a direct method to an iterative method for matrix inversion. Third, precision hybrid optimization: the system reevaluates the overall precision allocation scheme, potentially adjusting precision boundaries in different regions or inserting precision improvement points on critical paths to balance accuracy and performance. For precision-sensitive computations (such as scientific computing or financial analysis), the system may implement strict precision safeguards, such as using the Kahan summation algorithm to reduce roundoff error or employing interval arithmetic to track error bounds. The system also optimizes precision conversion operations, minimizing frequent precision conversions and merging adjacent same-precision operations to reduce conversion overhead. After adjustments, the system revalidates the expected accuracy of the corrected paths to ensure they meet application requirements. The system outputs a complete revised calculation path, including precision configuration, algorithm selection, and key checkpoints, providing clear guidance for subsequent execution. This precise precision path adjustment maximizes performance while ensuring computational quality, and is a key guarantee for high-quality matrix calculations.

[0122] Based on the modified calculation path and the numerical distribution characteristics of the matrix, numerical stability adjustment is performed to obtain optimized calculation parameters. In this step, the system further optimizes the calculation parameters related to numerical stability for the modified calculation path to ensure that reliable numerical behavior is maintained while improving performance. The system first analyzes the numerical distribution characteristics of the matrix, focusing on factors that may affect stability, such as the numerical range (the ratio of the maximum value to the minimum value), the condition number (indicating the sensitivity of the matrix to input perturbations), and special structures (such as diagonal dominance or sparsity patterns). The system also identifies key numerical sensitive points in the calculation, such as division operations, square root calculations, or iterative convergence judgments. Based on these characteristics, the system implements various numerical stability techniques. First, scaling transformation: For matrices with excessively large numerical ranges, the system applies row / column scaling or global scaling transformations to compress the values ​​to an appropriate range, reducing accuracy issues caused by dynamic range. Second, conditioning improvement: For matrices nearing singularity or pathological conditions, the system adds regularization terms or preprocessing steps to improve the matrix's condition number and numerical stability. Third, alternative formula selection: the system may replace the original formula with a numerically stable equivalent, such as using the logarithm of the sum of squares instead of a direct sum of squares calculation, to avoid overflow or precision loss. For iterative calculations, the system optimizes convergence conditions and step size parameters to balance convergence speed and stability. The system configures safety thresholds for critical calculations, such as minimum divisor values, rounding thresholds, and outlier criteria, to prevent computational errors caused by extreme values. For identified stability risk points, the system may also insert runtime checking code to monitor key values ​​and adjust parameters or paths promptly when potential issues are detected. The system pays particular attention to stability issues in mixed-precision environments, potentially performing precision enhancement at key points or using compensation techniques (such as the double backoff algorithm) to maintain accuracy. Through these techniques, the system comprehensively optimizes computational parameters, improving numerical stability while maintaining high performance. Ultimately, the system outputs a complete set of optimized parameters, including scaling factors, regularization parameters, algorithm control parameters, and safety thresholds. These parameters are directly applied during actual execution to ensure the stability and reliability of matrix calculations.

[0123] Based on the optimized computation parameters and the current ARM processor state, the system reorganizes task scheduling and outputs a new execution plan. In this step, the system reorganizes task allocation and execution order based on the optimized computation parameters and the current ARM processor state, generating an optimized execution plan. The system first obtains the latest processor state information, including the load level, operating frequency, temperature status, and available resources of each core. The system also considers overall system status, such as memory pressure, I / O wait times, and resource usage by other applications. Based on these real-time states and the optimized computation parameters, the system performs a multi-level scheduling reorganization: First, task repartitioning. Based on the revised precision path and numerical stability parameters, the system reassesses the computational complexity and resource requirements of each block. This may involve adjusting block boundaries or merging or splitting specific blocks to optimize task granularity for the current processor state. Second, priority reallocation. The system adjusts task execution priorities based on numerical dependencies and stability considerations, ensuring that stability-sensitive computations on the critical path receive priority. Third, resource allocation optimization. The system allocates the most appropriate processing resources to tasks with different characteristics, such as cores with advanced NEON capabilities for precision-sensitive tasks and cores with large cache capacities for memory-intensive tasks. The system also optimizes core affinity strategies, potentially adjusting the mapping between tasks and cores based on the current temperature distribution to prevent hot cores from continuing to operate at high loads. For detected performance bottlenecks, the system implements targeted optimizations. For example, in the case of memory bottlenecks, the system reorders task execution to maximize data locality and cache utilization. For uneven core loads, the system adjusts work stealing parameters and task migration thresholds to improve load balancing. The system also considers energy efficiency objectives. While meeting performance requirements, it may reduce the execution frequency of some non-critical paths or allocate floating tasks to the cores with the highest energy efficiency. The system ultimately generates a complete execution plan, including a detailed task allocation table, execution order, core affinity settings, synchronization point configuration, resource allocation guidelines, and performance monitoring points. This dynamic scheduling and reorganization capability enables the system to maintain optimal performance under various execution conditions while ensuring computational accuracy and stability, achieving true adaptive optimization.

[0124] Example 9 The method of the present invention also includes fine-grained fusion ARM matrix calculation optimization, which specifically includes the following steps: The system obtains the preprocessed matrix data and state-space model parameters, performs dynamic characteristic analysis, and obtains a feature sequence. In this step, the system first establishes a dynamic characteristic analysis framework for matrix computation, deeply exploring the changing characteristics of matrix data during execution. The system obtains preprocessed matrix data, including basic characteristics (dimensionality, sparsity, and numerical distribution) and long-tail distribution characteristics (hotspot location and activity distribution). Simultaneously, the system loads state-space model parameters, including the state transition matrix, observation matrix, and noise covariance matrix. These parameters describe the mathematical model of the system's dynamic behavior and the observation process. Based on these inputs, the system performs multi-dimensional dynamic characteristic analysis: temporal analysis tracks changes in matrix characteristics over execution phases, such as the evolution of sparsity patterns in iterative algorithms; spatial analysis examines differences in computational characteristics across different matrix regions, such as the migration patterns of hotspots; and computational analysis assesses changes in computational intensity and memory access patterns. The system uses state-space models (such as Kalman filters or particle filters) to predict the dynamic changes in these characteristics, enabling proactive optimization. The analysis process employs an adaptive sampling strategy, increasing the sampling frequency in key regions or phases to reduce system overhead. The system also performs feature extraction and dimensionality reduction, using techniques such as principal component analysis (PCA) or autoencoders to compress raw observation data and extract key features. Ultimately, the system generates structured feature sequences that contain temporal patterns, spatial distribution characteristics, and computational load characteristics. These feature sequences are represented compactly, such as feature vector sequences or state transition diagrams, providing a data foundation for subsequent fusion optimization. This dynamic feature analysis breaks through the limitations of traditional static optimization, can capture the complex dynamic behavior in matrix calculations, and provides an accurate feature description for fine-grained operation fusion.

[0125] A complete computational operation graph is constructed, and based on the feature sequence, combinations of operations that can be fused are identified and a fusion solution is output. In this step, the system deeply analyzes the operational dependencies of matrix computations to identify combinations of operations that can be optimized for fusion. The system first constructs a complete computational operation graph, representing matrix computations as a directed graph of operation nodes and data flow edges. This graph includes not only primary operations (such as matrix multiplication, addition, and transposition) but also auxiliary operations (such as data movement, format conversion, and synchronization points). Based on the feature sequence obtained in step 1, the system identifies multiple types of fusionable patterns: temporal fusion merges operations that are adjacent in time and have close data dependencies, reducing the storage and loading of intermediate results; spatial fusion merges operations computed in the same matrix region to improve data locality; and algorithmic fusion reorganizes multiple independent operations into equivalent composite operations, such as fusing matrix multiplication and addition into a GEMM operation. The system employs a multi-stage identification strategy: first, pattern matching is used to identify common fusion patterns, such as matrix multiplication chains, transpose-multiplication combinations, or scale-add sequences. Next, data flow analysis is used to identify data reuse opportunities and optimize memory access patterns. Finally, algebraic optimization techniques are employed to apply mathematical equivalent transformations of matrix operations, such as associativity and distributive properties, to identify implicit fusion opportunities. The system then evaluates the benefits of each fusion candidate and constructs a performance model to predict the execution efficiency before and after fusion, taking into account changes in computational intensity, memory access pattern improvements, and the impact of parallelism. The system also assesses the feasibility of fusions, taking into account ARM architecture constraints (such as the number of registers and cache levels) and accuracy requirements. For conflicting fusion options, the system applies priority rules or global optimization algorithms to find the optimal fusion combination. Finally, the system outputs a structured fusion solution, including the type, bounds, execution order, and data dependencies of the fused operations, as well as an analysis of the expected performance benefits. This fine-grained operation fusion strategy significantly reduces memory access and control overhead, improves computational density and hardware utilization, and is a key technology for optimizing matrix computation performance.

[0126] Based on the fusion scheme and the characteristics of the ARM processor, optimized execution code is generated. In this step, the system converts the high-level fusion scheme into highly optimized execution code for the ARM architecture. The system first loads detailed ARM processor feature information, including instruction set architecture version (e.g., ARMv7, ARMv8), microarchitectural features (e.g., pipeline depth, instruction issue width, out-of-order execution capability), NEON vector unit specifications, and cache parameters. For each fused operation group, the system performs multi-level code generation and optimization: first, operation conversion, mapping the fused operation to an ARM-supported instruction mode, such as mapping a matrix multiply-add operation to NEON's VMLA or VFMA instructions; second, memory access optimization, generating efficient data load / store sequences, leveraging ARM's multi-register load / store instructions (e.g., VLDM / VSTM) and alignment hints to maximize memory bandwidth utilization; third, instruction scheduling optimization, reordering instructions to reduce pipeline stalls caused by data dependencies and increase instruction-level parallelism. The system implements ARM-specific loop optimization techniques, including loop unrolling (automatically determining the unrolling factor based on the number of registers), loop blocking (adjusting the block size to the cache hierarchy), and loop vectorization (converting scalar operations to NEON vector operations). For complex fused operations, the system employs the following strategies: It automatically generates specialized kernels for the fused pattern, such as matrix multiply-add kernels (C=A×B+C) or scaled multiply-add kernels (C=αA×B+βC); applies register reuse strategies to reduce register spills and redundant loads; inserts prefetch instructions (such as PLD) to optimize memory accesses; and generates code variants optimized for both big and small cores, targeting the ARM big.LITTLE architecture. The system also implements advanced optimization techniques such as software pipelining, SIMD instruction reorganization, and branch prediction optimization. The generated code is implemented in inline assembly or highly optimized C / C++, ensuring the compiler generates the most efficient machine code. The system also generates necessary performance annotations and memory alignment constraints to guide the runtime system for optimal scheduling. This fine-grained code optimization, tailored to the ARM architecture, significantly improves the execution efficiency of fused operations, ensuring optimal alignment between theoretical and actual performance.

[0127] The system collects runtime information from multiple sources and, using the optimized execution code, outputs a dynamic switching strategy. In this step, the system builds an intelligent runtime control mechanism to enable dynamic adaptation and switching of fusion operations. The system first designs a controller architecture, including decision logic, state monitoring, and an execution engine. Based on feedback control theory, the controller continuously monitors system status and adjusts execution strategies. The system configures decision parameters for each fusion operation group, including startup conditions (such as matrix size thresholds and sparsity thresholds), switching conditions (such as performance counter trigger values ​​and temperature thresholds), and exit conditions. The controller collects runtime information from multiple sources: hardware status (such as core frequency, temperature, and cache hit rate), execution progress (such as the amount of computation completed and the amount of remaining tasks), and matrix dynamics (such as changes in sparsity patterns and evolving numerical distributions). Based on this runtime information, the controller implements dynamic switching of multiple strategies: algorithm variant switching selects between different implementation methods, such as dynamically switching between dense and sparse matrix multiplication based on sparsity; precision configuration switching adjusts computational precision based on numerical characteristics to balance accuracy and performance; and resource configuration switching adjusts computational resource allocation, such as core count and frequency settings. The system implements a predictive switching mechanism that uses a state-space model to predict future characteristic changes, making switching decisions in advance and reducing switching latency. The controller uses a lightweight implementation to minimize decision-making overhead, replacing complex calculations with fast table lookups and heuristic rules. For ARM heterogeneous multi-core environments, the controller specifically optimizes core migration strategies, selecting the most appropriate core type (large or small) for execution based on the computational characteristics of the fusion operation and the current system load. The system outputs a complete dynamic switching strategy, including a decision tree, state transition diagram, and threshold parameter table. This adaptive control mechanism enables the execution of fusion operations to dynamically adapt to changes in matrix characteristics and fluctuations in system state, maintaining optimal performance in various execution environments and truly achieving fine-grained adaptive optimization.

[0128] Based on the dynamic switching strategy and execution feedback data, an optimization feedback model is constructed to generate a continuous optimization solution. In this step, the system establishes a complete learning feedback loop to achieve continuous evolution of matrix computation optimization. The system first designs a structured execution feedback data collection mechanism that records performance metrics, resource usage, and optimization decision results at key execution points. The feedback data contains multi-dimensional information: temporal data tracks performance trends over time; spatial data records differences in execution efficiency across different matrix regions; and decision data correlates switching decisions with performance results. The system establishes a multi-level optimization feedback model: a short-term feedback model uses online learning to adjust control parameters for the current execution, such as decision thresholds and switching timing; a medium-term feedback model optimizes pattern recognition and initial configuration for similar matrix computations, improving cold start performance; and a long-term feedback model accumulates execution experience to drive the evolution of the fusion pattern library and code generation strategy. The system utilizes an incremental learning algorithm to process feedback data, using lightweight models such as linear regression, decision trees, or simplified neural networks to adapt to the computational resource constraints of ARM devices. The model training process utilizes an online update strategy, instantly updating model parameters after each execution, enabling the system to quickly adapt to new matrix characteristics or execution environments. The system implements multi-level optimization adjustments: parameter-level adjustments fine-tune controller parameters and switching thresholds; policy-level adjustments refine decision logic and priority rules; and structural-level adjustments modify fusion operation combinations and code generation patterns. The system also maintains an optimization knowledge base, documenting successful optimization patterns and best practices for specific matrix types, supporting case-based optimization reasoning. Ultimately, the system outputs a continuous optimization plan consisting of an adaptive parameter table, a dynamic decision tree, and an optimization evolution roadmap. This plan not only guides the current execution but also provides an optimization benchmark for future similar calculations, forming a positive feedback loop. This learning-based continuous optimization mechanism enables the system to adapt to changing matrix characteristics and hardware environments, maintaining long-term optimal performance, a core characteristic of intelligent computing systems. By continuously learning and improving from actual execution, the system achieves true adaptive evolution, significantly improving matrix computation efficiency in diverse scenarios.

[0129] Example 10 The method of the present invention also includes mixed precision quantization ARM matrix calculation optimization and acceleration, which specifically includes the following steps: The system obtains the numerical distribution characteristics and precision requirements of the matrix, performs block floating-point representation design, and outputs a bidirectional block floating-point solution. In this step, the system first conducts an in-depth analysis of the matrix's numerical properties, laying the foundation for an efficient mixed-precision representation. It then calculates the matrix's detailed numerical distribution characteristics, including global statistical metrics (maximum, minimum, mean, and standard deviation) and local distribution characteristics (variation in the range of values ​​in the row and column directions). The system then performs multi-scale information entropy analysis on the matrix, assessing the information density and precision sensitivity of different regions. Based on the precision requirements of the application domain, it determines the acceptable upper bound for each region. Based on this analysis, the system designs an innovative bidirectional block floating-point representation scheme: First, in the row direction, the system partitions the matrix into several row blocks. Each row block shares a single exponent value, with each element storing only the mantissa. A similar strategy is used to partition the column blocks in the column direction, assigning an exponent to each column block. This bidirectional block floating-point representation forms a two-dimensional grid structure. Each grid intersection (subblock) is influenced by both the row and column exponents, and its effective precision is determined by the scaling factors in both directions. The system employs an adaptive block size strategy, dynamically adjusting block size based on the local similarity of numerical distributions: larger blocks are used in areas with gently varying values ​​to improve compression, while smaller blocks are used in areas with wide numerical spans to maintain accuracy. The system also optimizes exponent bit width allocation, allocating more bits to areas with high information density, maximizing compression while maintaining accuracy. Ultimately, the system outputs a complete bidirectional block floating-point solution, encompassing a block partitioning strategy, exponent allocation scheme, and quantization parameters. This representation is particularly well-suited for long-tail distribution matrices, significantly reducing overall storage space and computational complexity while maintaining accuracy in critical areas.

[0130] Based on the bidirectional block floating-point scheme and matrix region features, ternary region identification is performed to determine quantization regions. Matrix region features are a set of parameters that describe the geometric, numerical, and computational characteristics of different spatial regions of the matrix. In this step, the system further analyzes the matrix structure to identify regions suitable for extreme quantization, laying the foundation for ternary representation. The system first analyzes the distribution of values ​​in the bidirectional block floating-point representation, focusing specifically on the distribution characteristics of the mantissa. Using hierarchical cluster analysis, the system classifies matrix elements into three categories: significantly positive (making a significant positive contribution to the result), significantly negative (making a significant negative contribution to the result), and near-zero (making a negligible contribution). The system uses an adaptive thresholding technique to determine the ternary boundaries, employing different criteria for different regions: a more conservative threshold is used for high-activity regions (typically the hotspots of the matrix) to ensure that critical information is not lost; a more aggressive threshold is used for low-activity regions (typically the long tail) to maximize compression. The system performs region-specific ternary evaluation, considering multiple factors: the absolute value distribution of elements, the relative size relationships between elements, the sensitivity of elements in the computation (estimated through gradient analysis), and the functional role of the region in matrix operations. The system also uses information-theoretic methods to evaluate the information retention rate after ternary evaluation, ensuring that critical information is not lost due to quantization. For each candidate region, the system calculates the KL divergence or mean squared error before and after ternary evaluation to predict the impact of quantization on the final result. The system pays special attention to structural features, such as diagonal elements, frequently accessed rows / columns, or eigenvector-related regions, and formulates specialized quantization strategies for these regions. Finally, the system generates a detailed ternary region map, including each region's boundaries, applicable quantization parameters, and expected compression rate. The system also generates a hierarchical ternary scheme, allowing the quantization range to be dynamically adjusted during execution based on accuracy requirements and resource availability, achieving a flexible balance between accuracy and efficiency. This intelligent region identification strategy ensures that ternary evaluation is applied to the most appropriate regions, maximizing compression benefits while keeping accuracy losses within acceptable limits. Matrix region features refer to the computational and numerical characteristics of different regions of a matrix in different spatial dimensions. Specifically, these include the region's geometric characteristics (such as its location coordinates, area size, and shape parameters), numerical characteristics (such as the numerical distribution, sparsity, and activity level of the elements within the region), and computational characteristics (such as the region's importance in matrix operations, computational complexity, and memory access patterns). For example, in a 1024×1024 deep learning weight matrix, the 128×128 region in the upper left corner may have high sparsity (90% of the elements are zero) and low activity (contributing little to the result), while the central 256×256 region may have a dense distribution (only 10% of the elements are zero) and high activity (contributing significantly to the result). These regional characteristics directly influence the choice of quantization strategy: high-activity regions require high accuracy, while low-activity regions can adopt more aggressive quantization schemes.

[0131] The quantization region and precision parameter are subjected to ternary quantization with a scaling factor to obtain compressed representation data. The precision parameter is a set of configuration parameters that control the precision of numerical representation and computational accuracy. In this step, the system performs precise ternary quantization on the determined quantization region, converting the original floating-point data into a highly compressed representation. The system first optimizes the ternary quantization parameters and calculates the optimal scaling factor for each quantization region. This scaling factor is typically determined based on the statistical distribution characteristics of the elements within the region, such as using the mean or median of the absolute values ​​of the non-zero elements in the region as a benchmark. The system implements multiple ternary quantization strategies: threshold ternary quantization quantizes elements with absolute values ​​less than a threshold to 0, and the remaining elements are quantized to ±1 based on their sign; random ternary quantization introduces randomness near the threshold to bring the overall expected value closer to the original distribution; and lossy cluster ternary quantization clusters the original values ​​into three centers to minimize the overall quantization error. For each element, the system applies the optimized quantization function: Q(x) = sign(x) * (|x|>threshold) * scale_factor, where sign() extracts the sign, the threshold determines whether to retain the element, and scale_factor is the scaling factor. The quantization process is accelerated using ARM NEON vector instructions, using instructions such as VCGT (Vector Compare Greater Than) and VBSL (Vector Bit Select) to process multiple elements in parallel. The system employs a block-parallel quantization strategy, with each thread processing a region of the matrix, fully leveraging the ARM multi-core architecture. After quantization, the system implements an efficient compressed storage format: for a ternary matrix, each element requires only 2 bits to represent (00 represents 0, 01 represents +scale, and 10 represents -scale), allowing 32 elements to be compressed and stored in a single 64-bit integer. The system also maintains a scaling factor mapping table to record the scaling factor for each region for subsequent inverse quantization. For special regions (such as those requiring high precision), the system implements mixed-precision storage, preserving the original precision of key elements. The system ultimately outputs a highly compressed representation, consisting of a bit-compressed representation of the ternary matrix and a scaling factor mapping. This representation reduces storage space by over 87.5% compared to the original floating-point format while retaining key information required for computation. Precision parameters are a set of key configuration parameters that control numerical representation and computational accuracy. These parameters primarily include numerical representation parameters (such as the bit width of floating-point numbers, the number of exponent bits, and the number of mantissa bits), quantization parameters (such as the quantization threshold, scaling factor, and zero-point offset), and computational control parameters (such as rounding mode, overflow handling strategy, and error tolerance). For example, in mixed-precision computation, critical areas might use FP32 precision parameters (32-bit floating point, 8-bit exponent, 23-bit mantissa), moderately important areas might use FP16 precision parameters (16-bit floating point, 5-bit exponent, 10-bit mantissa), and non-critical areas might use INT8 quantization parameters (8-bit integer, scaling factor 0.1, and zero-point offset 128).These parameters directly determine the representation range, precision level, and computational overhead of the values.

[0132] A pre-fill operation is performed on the compressed representation data and the memory characteristics of the ARM processor, outputting a memory access optimization solution. In this step, the system further optimizes data storage and access patterns based on the compressed representation and the memory characteristics of the ARM processor. The system first analyzes the ARM processor's memory hierarchy, including cache line size (typically 64 bytes), cache capacity, memory alignment requirements, and DMA transfer characteristics. For the ternary compressed data, the system optimizes the memory layout: cache line aligned storage ensures frequently accessed data does not span cache lines, reducing cache misses; data reordering techniques are used to place frequently co-accessed elements in computations in adjacent locations to improve spatial locality; and special encodings such as run-length encoding or bitmap indexing are applied to sparse regions to further compress all-zero or highly sparse blocks. The system performs a pre-fill operation, inserting carefully designed padding bits into data structures to achieve multiple optimization goals: ensuring that the start addresses of critical data structures are aligned with cache line boundaries to improve memory access efficiency; reserving operation space for special processing instructions (such as NEON bit operations) to simplify runtime processing; and adjusting data block sizes to integer multiples of the ARM processor's vector register width to optimize vector load and store operations. The system also implements prefetch strategy optimization, generating dedicated prefetch instruction sequences for ternary matrix operations: analyzing the data access order in typical computing patterns and inserting PLD (preload) instructions to load the data to be used into the cache in advance; configuring hardware prefetcher parameters for predictable access patterns to maximize prefetch efficiency; and designing specialized prefetch templates for different computing modes (such as matrix multiplication and convolution). The system specifically optimizes the access pattern of scaling factors, organizing the scaling factors of related areas into continuous blocks to reduce cache misses when accessing the scaling table. The system ultimately outputs a complete memory access optimization solution, including a memory layout diagram, prefill strategy, and prefetch instruction templates. These optimizations significantly reduce memory access latency and bandwidth requirements, and are key factors in improving the performance of ternary matrix calculations.

[0133] Based on the memory access optimization scheme and the ARM processor instruction set, bit manipulation acceleration is performed to obtain the final optimized result. In this step, the system utilizes the bit manipulation instructions of the ARM architecture to design an efficient algorithm to accelerate ternary matrix calculations. The system first analyzes the bit manipulation instruction set supported by the ARM processor, focusing on instructions such as bit count (VCNT), bit select (VBSL), bit clear (BIC), and bit logical operations (AND, OR, XOR). Taking advantage of the characteristics of ternary representation, the system designs a dedicated computational kernel to efficiently execute basic matrix operations. For ternary matrix multiplication, the system implements a bit-parallel algorithm: the ternary matrix is ​​decomposed into a sign matrix and a mask matrix, and the multiplication is converted into bit operations, processing 32 or 64 elements at a time. NEON vector instructions are used to perform bit operations in parallel, such as using VAND and VEOR instructions to process the sign bit and using the VCNT instruction to quickly calculate the result. The system designs specialized algorithms for different operations: For matrix addition, the sign bit and scaling factor are directly calculated; for matrix multiplication, a sparsity-aware algorithm is implemented to skip calculations involving zero elements; and for special operations (such as dot products and convolutions), algorithms optimized for ternary representation are designed. The system implements a mixed-precision computing strategy, using high-precision accumulation for critical intermediate results and quantizing them before final output to ensure accuracy. The system specifically optimizes scaling factor processing: it precomputes and caches commonly used scaling factor combinations to reduce runtime computation; and it uses approximate computing techniques to accelerate scaling factor application, such as using bit shifts and additions to approximate multiplication operations. The system also implements an automatic vectorization framework that analyzes computational patterns and automatically generates optimal bit manipulation sequences, enabling the compiler to generate efficient machine code. To increase instruction-level parallelism, the system applies instruction pipeline optimization techniques, such as software pipelining and loop unrolling, to minimize instruction latency. The system ultimately outputs a complete bit manipulation acceleration solution, including optimized algorithms, instruction templates, and execution parameters. These optimizations increase the speed of ternary matrix operations by 3-15 times compared to traditional floating-point implementations while significantly reducing energy consumption, making it particularly suitable for resource-constrained ARM devices. By tightly integrating numerical representation, memory optimization, and instruction optimization, the system achieves ultimate performance in ternary matrix calculations.

[0134] The method of the present invention also includes energy efficiency optimization and monitoring, which specifically includes the following steps: The system acquires ARM processor state data and energy efficiency targets, executes execution controller design, and outputs an energy efficiency control policy. In this step, the system builds a sophisticated energy efficiency control mechanism to balance computing performance and energy consumption. The system first acquires comprehensive ARM processor state data, including each core's operating frequency, utilization, temperature status, and power consumption data. For processors that support DVFS (Dynamic Voltage and Frequency Scaling), the system obtains available frequency ranges and their corresponding power consumption profiles. The system also defines explicit energy efficiency targets, such as performance-first mode (pursuing maximum computing throughput), energy-first mode (pursuing the highest performance-to-power ratio), or power-constrained mode (maximizing performance within a fixed power limit). Based on these parameters, the system designs a multi-layered execution controller: First, a macro-strategy controller selects core operating modes based on overall task characteristics and system status, such as the number of cores, the large-core and small-core allocation strategy, and the overall frequency range. Second, a fine-grained DVFS controller adjusts the frequency and voltage of each core in real time to respond to load changes and temperature fluctuations. Third, a task scheduling controller allocates tasks based on computing characteristics and current energy efficiency, assigning compute-intensive tasks to high-efficiency cores and memory-intensive tasks to low-power cores. The system implements a predictive control algorithm, uses the least squares method or Kalman filter to establish a load prediction model, and adjusts the processor state in advance to cope with the upcoming computing peak. The system also designs a feedback control loop to monitor the actual execution status through performance counters, dynamically adjusts the control parameters, and achieves closed-loop optimization. For the ARM big.LITTLE architecture, the system implements a specialized heterogeneous scheduling strategy to optimize the load distribution and migration decisions of large and small cores. The system pays special attention to thermal management and designs a temperature-aware control strategy to actively reduce power consumption when approaching the thermal threshold to prevent a sharp drop in performance caused by thermal throttling. The system ultimately outputs a complete energy efficiency control strategy, including control rules, state transition diagrams, and parameter configuration tables. These strategies can significantly reduce energy consumption while ensuring computing performance, extending the operating time of battery-powered devices, which is particularly important for mobile and embedded ARM devices.

[0135] Based on the energy efficiency control strategy and ARM processor parameters, dynamic configuration adjustment is performed to obtain optimized operating parameters. ARM processor parameters are a set of parameters that describe the hardware characteristics and operating state of ARM architecture processors. In this step, the system converts the energy efficiency control strategy into specific runtime configuration parameters, enabling precise dynamic adjustment. The system first establishes a detailed power consumption model for the ARM processor, including static power consumption (leakage current related to temperature and voltage) and dynamic power consumption (related to computational load, clock frequency, and voltage). For a typical ARM processor, the system collects power consumption characteristic curves for each core type at different frequencies and establishes a power consumption prediction function. The system designs a dynamic parameter adjustment framework, which includes multiple control dimensions: the frequency control dimension dynamically selects the optimal processor frequency, choosing the lowest energy consumption configuration while meeting performance requirements based on the task's computational intensity and current temperature conditions; the core selection dimension determines the number and type of active processor cores, optimizing the utilization ratio of large and small cores; the memory control dimension adjusts memory controller parameters, such as bandwidth limits and latency settings, to balance memory performance and power consumption; and the peripheral control dimension manages peripheral states related to matrix computations, such as reducing unnecessary GPU or DSP power consumption. The system implements an adaptive adjustment algorithm, dynamically adjusting these parameters based on task characteristics and real-time performance feedback. During compute-intensive phases, the system increases core frequency and activates more cores; during memory wait phases, the system reduces frequency to save energy; and in temperature-sensitive scenarios, the system implements a temperature balancing strategy to avoid local hotspots. The system specifically optimizes parameter configuration for the characteristics of ternary matrix calculations: leveraging the low-power nature of bitwise operations to select lower voltage and frequency points; and optimizing front-end and back-end configurations, such as predictor strategies and execution unit allocation, based on instruction characteristics. The system implements a segmented control strategy, assigning different energy efficiency parameters to different stages of matrix calculations (such as initialization, compute-intensive phases, and finalization). The system ultimately outputs a complete operating parameter configuration, including frequency ranges, core utilization strategies, memory control parameters, and scheduling priority settings. These optimized parameters minimize energy consumption while maintaining performance targets, achieving true adaptive energy efficiency optimization. ARM processor parameters refer to a set of parameters that describe the hardware characteristics and operating state of ARM architecture processors. These parameters include architecture parameters (such as instruction set version, core type, and NEON vector unit specifications), performance parameters (such as clock frequency, cache configuration, and memory bandwidth), power consumption parameters (such as voltage level, power state, and thermal design power consumption), and dynamic state parameters (such as current load, temperature, and available resources). For example, a typical ARM Cortex-A78 processor has the following parameters: ARMv8.2 instruction set, four large cores, 32KB L1 instruction cache, 32KB L1 data cache, 512KB L2 cache, 128-bit NEON unit, 2.4GHz maximum frequency, and 1.2V operating voltage.These parameters provide hardware constraints and optimization targets for algorithm optimization and resource allocation.

[0136] Error tracking analysis is performed on the optimized operating parameters and precision representation data, generating a cumulative error report. The precision representation data contains detailed information about different numerical precision representation methods. During this step, the system implements a precise error monitoring mechanism to assess the precision loss introduced during the optimization process. The system first establishes an error measurement framework, defining multiple error metrics: absolute error quantifies the error magnitude of a single element; relative error assesses the ratio of the error to the original value; cumulative error tracks the error growth after consecutive operations; and stability metrics assess the risk of numerical instability. The system implements a multi-level error tracking strategy: element-level tracking selects key elements or statistical sampling points to compare the results of the optimized calculation with those of a full-precision reference calculation; operation-level tracking analyzes the error change before and after a single matrix operation (such as matrix multiplication); and computational graph-level tracking assesses the end-to-end error accumulation of the entire computational process. The system employs a progressive sampling technique to reduce tracking overhead. Initially, high-frequency, full-coverage sampling is used to establish a baseline. During the stabilization phase, sampling is used for monitoring, and then dense sampling is returned when abnormal patterns are detected. The system specifically monitors error patterns introduced by ternary quantization and block floating-point representation: quantization error (the loss of mapping continuous values ​​to discrete values), truncation error (the effect of discarding small values), and rounding error (limitations in numerical representation during computation). The system implements an error propagation model to predict the error accumulation characteristics under different combinations of operations, identifying potential points of error amplification (such as inversion operations) or error cancellation (such as the statistical averaging of random errors). The system also focuses on special numerical patterns, such as minimum value processing (to avoid information loss caused by underflow to zero) and maximum value representation (to prevent computational crashes caused by overflow). Finally, the system generates a detailed cumulative error report, including statistical error distribution (maximum value, mean, and standard deviation), error analysis at key locations (hotspots and sensitive points in the calculation results), and error trend prediction (estimated error growth in subsequent calculations). Furthermore, the system provides error visualizations, such as heat maps showing error distribution in a matrix, to help intuitively understand error patterns. This precise error tracking mechanism provides a reliable basis for subsequent precision adjustments, ensuring that precision losses during the optimization process remain within controllable limits. Precision representation data refers to the detailed information that records and describes different numerical precision representation methods. This includes a precision mapping table (specifying the precision type used in different regions of the matrix), a quantization configuration table (recording the quantization parameters and conversion rules for each region), error statistics (recording precision loss and error distribution), and precision conversion instructions (specifying the timing and method of precision conversion). For example, a precision representation data might include: Region A uses FP32 representation with an error cap of 1e-6; Region B uses FP16 representation with a scaling factor of 2.5 and an error cap of 1e-3; Region C uses 3-bit quantization with a threshold of 0.1 and an expected compression ratio of 8:1. This data provides detailed guidance for precision optimization and error control.

[0137] Based on the accumulated error reports and computational task characteristics, a precision improvement configuration is configured to obtain a balanced precision solution. The computational task characteristics are characteristic parameters that describe the properties and requirements of the matrix computation task. In this step, the system implements a precise precision balancing strategy based on the error analysis results, selectively improving computational precision in key locations. The system first analyzes the accumulated error reports and computational task characteristics to identify areas requiring precision improvement. These areas primarily include error-sensitive regions (where changes in error significantly impact the final result), error-accumulating regions (where error rapidly increases with each computational step), and functionally critical regions (where accuracy is crucial from an application perspective). For these regions, the system designs a precision improvement configuration and implements various precision balancing techniques: Precision hybridization strategies use higher-precision representations (such as upgrading from ternary to block floating point or from block floating point to full-precision floating point) in critical areas, while maintaining lower-precision representations in non-critical areas to optimize the overall accuracy and performance balance; precision compensation algorithms correct quantization errors through additional computational steps, such as using residual calculations to record and compensate for quantization loss; and numerical stability enhancement techniques employ special computational sequences or algorithmic variants, such as the Kahan summation algorithm, to reduce accumulated roundoff errors. The system designs specialized precision balancing strategies for different computational modes. For matrix multiplication, the system may use high precision during the accumulation phase, performing quantization only on the final output. For sensitive operations like inversion, the system may implement them entirely in high precision to avoid error amplification. For element-wise operations, the system may implement a location-adaptive precision strategy, using high precision in hotspots and low precision in marginal areas. The system establishes a precision control cost model, evaluating the resource overhead (computational effort, memory requirements, and increased energy consumption) of each precision improvement strategy and selecting the precision configuration with the highest return on investment. The system ultimately generates a detailed precision balancing plan, including a precision allocation map (specifying the precision representation used for each region of the matrix), an algorithm selection strategy (selecting the optimal algorithm for the current precision configuration), and a precision conversion guide (specifying the location and method of precision conversion). This intelligent precision balancing strategy ensures that the system meets precision requirements with minimal resource overhead, achieving an optimal balance between accuracy and performance. Computational task characteristics refer to characteristic parameters that describe the properties and requirements of a specific matrix computation task. These include task type characteristics (such as matrix multiplication, inversion, and eigenvalue calculation), performance requirements (such as latency requirements, throughput targets, and energy efficiency constraints), accuracy requirements (such as result accuracy requirements and tolerance for intermediate computational accuracy), and resource constraints (such as memory limits, computation time limits, and power budgets). For example, a scientific computing task might require high accuracy (relative error < 1e-12) and moderate performance (completion time < 1 hour), while a mobile inference task might require moderate accuracy (relative error < 1e-3), high performance (latency < 100ms), and strict power constraints (< 2W). These characteristics guide the development of overall optimization strategies and parameter tuning.

[0138] Based on the balanced precision scheme and system performance data, a precision-energy efficiency model is constructed, outputting the final optimization strategy. In this step, the system deeply analyzes the relationship between precision configuration and energy efficiency, constructing a systematic precision-energy efficiency model to guide the final optimization decision. The system first collects system performance data after the precision scheme is implemented, including performance metrics (throughput, latency) and energy efficiency metrics (power consumption, energy per operation). The system correlates this data with the precision configuration parameters, establishing a multidimensional mapping relationship, and analyzing the impact of different precision choices on performance and energy efficiency. Based on this analysis, the system constructs a precision-energy efficiency model that describes the functional relationship between precision selection and computational efficiency on a given hardware platform. The model considers several key factors: the computational complexity of the precision representation (e.g., the performance ratio of FP32 operations to ternary operations), the cost of precision conversion (e.g., the cost of converting between different precisions), changes in memory access patterns (e.g., the improved cache efficiency after reducing precision), and power consumption characteristics (e.g., the difference in energy consumption between different precision representations). The system implements model-based optimization strategy generation: Priority optimization prioritizes accuracy allocation across different stages and regions, prioritizing accuracy in critical areas. Automatic parameter tuning uses a model-based search algorithm to explore the optimal balance between accuracy and energy efficiency. Adaptive strategy generation generates different optimization solutions for different execution environments (such as battery status and temperature conditions). The system specifically focuses on ARM-specific optimization opportunities, such as leveraging the heterogeneous nature of the big.LITTLE architecture to perform critical high-precision computations on large cores and non-critical low-precision computations on small cores to maximize energy efficiency. The system also considers thermal management, designing a precision degradation cooling strategy that selectively reduces the accuracy of non-critical computations at high temperatures to reduce power consumption and heat generation. The system ultimately outputs a complete optimization strategy, including detailed implementation steps, parameter configuration tables, and expected benefit analysis. This strategy typically achieves a 30-70% improvement in energy efficiency while maintaining computational accuracy within acceptable application limits. Through systematic precision and energy efficiency modeling and optimization, the system finds the optimal balance between accuracy, performance, and energy efficiency for matrix computations. This is particularly suitable for battery-powered ARM devices, significantly extending the device's effective operating time while meeting computational quality requirements.

[0139] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, according to the concept of the present invention, there may be changes in the specific implementation methods and application scope. In summary, the present invention is not limited to the specific implementation methods described above. Any simple equivalent changes made on the basis of the technical solution of the present invention fall within the scope of protection of the present invention.

[0140] The present disclosure also provides a computer-readable storage medium having a computer program stored thereon. When executed by a processor, the computer program executes the steps of the ARM architecture-based matrix calculation adaptive optimization method in the above-described method embodiment. The storage medium may be a volatile or non-volatile computer-readable storage medium.

[0141] In addition, an embodiment of the present disclosure also provides a computer program product, which stores a computer program. When the computer program is run by a processor, it executes the steps of a matrix calculation adaptive optimization method based on ARM architecture provided in any of the above embodiments of the present disclosure. For details, please refer to the above method embodiments, which will not be repeated here.

[0142] The computer program product may be implemented in hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is embodied as a computer storage medium, which may be a volatile or non-volatile computer-readable storage medium. In another alternative embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK).

[0143] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment and devices can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed equipment, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0144] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0145] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0146] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0147] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The scope of protection of the present disclosure is not limited thereto. Although the present disclosure has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-mentioned embodiments within the technical scope disclosed in the present disclosure, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A matrix calculation adaptive optimization method based on ARM architecture, characterized in that: include: Obtaining matrix data to be processed and ARM processor information, preprocessing the matrix data to be processed to obtain preprocessed matrix data; Performing local activity calculation and hotspot area identification on the preprocessed matrix data to determine the long-tail distribution characteristics of the matrix; Based on the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the ARM processor information, the optimal block size range of the matrix is ​​calculated to generate an asymmetric block scheme; Based on the asymmetric block scheme, the execution time and cache hit rate of each block are collected to establish a mapping relationship between matrix characteristics and optimal block parameters, wherein the block is a basic sub-block divided by the preprocessed matrix data; Based on the asymmetric block scheme and the mapping relationship between the matrix characteristics and the optimal block parameters, the computational density and memory access pattern of each block are calculated to generate a task scheduling scheme; Based on the task scheduling scheme, matrix calculations are performed on an ARM big.LITTLE architecture processor to output the final calculation results.

2. The method according to claim 1, characterized in that The performing local activity calculation on the preprocessed matrix data includes: Dividing the preprocessed matrix data into basic sub-blocks of a reference size, and calculating the proportion of non-zero elements and the variance of the value distribution for each basic sub-block; Calculate the relative importance score of each basic sub-block according to the non-zero element ratio and value distribution variance of each basic sub-block to obtain the sub-block calculation contribution; Calculating the contribution of the sub-blocks, calculating the statistical distribution data of the local activity of the basic sub-blocks using NEON SIMD instructions, and obtaining a local activity distribution map of the matrix; Normalizing the local activity distribution map to obtain a normalized local activity distribution map; Based on the standardized local activity distribution graph, a sparse data structure is used to store basic sub-block information whose activity exceeds a first preset threshold.

3. The method according to claim 2, characterized in that The hotspot area identification includes: Based on the preprocessed matrix data, calculating statistical distribution data of global activity and constructing a global activity distribution graph, wherein the statistical distribution data of global activity includes a mean value and a standard deviation; Based on the statistical distribution data of the global activity, the OTSU algorithm is used to optimize the activity threshold segmentation point to obtain an optimized activity threshold; Obtaining the optimized activity threshold, and converting the global activity distribution map into a hotspot distribution binary map; Receive the hotspot distribution binary map, execute the connected region marking algorithm, cluster and merge adjacent hotspot regions, and obtain a cluster merging result; Obtaining cluster merging results, applying morphological operations to trim the hotspot area, removing isolated hotspots whose areas are smaller than a second preset threshold, and obtaining trimmed hotspot areas; The trimmed hotspot areas are received, and the location information, shape features, and activity features of each hotspot area are obtained.

4. The method according to claim 3, characterized in that The method of calculating the optimal block size range of the matrix based on the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the ARM processor information and generating an asymmetric block scheme includes: Obtaining statistical distribution data of the global activity and the local activity, designing blocks adapted to the L1 cache for regions where the activity exceeds a third preset threshold, and designing blocks adapted to the L2 / L3 cache for regions where the activity is below a fourth preset threshold, to obtain an initial block scheme; Based on the initial block scheme, identify cross-block hotspot areas, ensure that the hotspot elements are completely contained in a single block through overlapping cutting, and output block boundary data; Obtaining the block boundary data, performing memory alignment optimization, and ensuring that the block boundary is aligned to the cache line; Obtain historical execution data and fine-tune the chunk size and shape based on execution efficiency metrics.

5. The method according to claim 1, wherein The establishing of a mapping relationship between matrix features and optimal block parameters includes: Obtain block execution data, collecting the execution time, cache hit rate and instruction throughput of each block; Obtaining performance indicators, and analyzing the correlation between the block execution data and the performance indicators; Obtaining correlation data between the block execution data and the performance indicators, and establishing a mapping relationship model between matrix features and optimal block parameters; Deploy the mapping relationship model into the ARM TrustZone environment and update the block strategy history library; Obtain historical database data and record the optimal block parameters under different matrix characteristics.

6. The method according to claim 1, characterized in that The task scheduling scheme includes: Obtaining block characteristic data, allocating blocks having a computational density exceeding a fifth preset threshold to a first core for processing, and allocating blocks having a computational density below a sixth preset threshold to a second core for processing, wherein the number of the first cores is greater than the number of the second cores; Receive block priority data, set task execution order and preemption strategy; Get the core characteristics of the ARM processor, configure core affinity, get the core affinity configuration, and specify the execution core of a specific type of task; Receive the dependencies of the executed tasks, implement task group scheduling and synchronization checkpoint setting; Obtain cache characteristic data, optimize shared cache and memory access strategies, and reduce inter-core data transmission.

7. The method according to claim 6, characterized in that The matrix calculation is performed on the ARM big.LITTLE architecture processor, including: Obtaining the block characteristic data and selecting corresponding NEON instruction set optimization kernels for different types of blocks; Obtain block activity characteristics and configure mixed precision calculation matrix parameters; Obtain the memory access mode, configure ARM cache prefetch instructions, and optimize memory access order; According to the core affinity configuration, the calculation of each block is executed in parallel to obtain the calculation results of each block; Obtain the calculation results of each block, perform result merging and correctness verification.

8. The method according to claim 1, characterized in that The method further comprises: Obtain the matrix operation process and the characteristics of the ARM processor, use a formal language to define the operation axiom system, and obtain a formal specification; Analyze and process the formal specification, generate system verification assertions, and output executable verification rules; According to the executable verification rules, the correctness of the asymmetric block scheme is verified using a theorem proving tool, and a verification report is generated; Based on the verification report and mixed precision calculation data, perform error propagation analysis and establish an accuracy error model; Based on the accuracy error model and actual execution data, formal verification is performed and a formal proof result is output.

9. The method according to claim 1 or 8, characterized in that The method also includes execution-time verification and recovery, including: Obtain matrix calculation execution status information, perform verification checks, and generate verification results; Based on the verification results and the preset error level standards, perform hierarchical error classification and determine the error handling strategy; According to the error handling strategy and the accuracy problem data, the accuracy path is adjusted and the corrected calculation path is output; Based on the modified calculation path and the numerical distribution characteristics of the matrix, performing numerical stability adjustment to obtain optimized calculation parameters; According to the optimized calculation parameters and the current ARM processor state, task scheduling is reorganized and a new execution plan is output.

10. The method according to claim 1, characterized in that The method comprises: Obtaining the preprocessed matrix data and state space model parameters, performing dynamic characteristic analysis, and obtaining a characteristic sequence; Construct a complete computational operation graph, combine the feature sequence, identify fusionable operation combinations, and output a fusion solution; Obtaining optimized execution code according to the fusion solution and the characteristics of the ARM processor; Collecting multi-source runtime information and outputting a dynamic switching strategy using the optimized execution code; Based on the dynamic switching strategy and execution feedback data, an optimization feedback model is constructed to obtain a continuous optimization solution.

11. The method according to claim 1 or 10, characterized in that The method also includes mixed precision optimization, including: Obtaining the numerical distribution characteristics and precision requirements of the matrix, performing block floating-point representation design, and outputting a bidirectional block floating-point solution; Based on the bidirectional block floating point scheme and matrix region features, performing ternary region identification to determine quantization regions, wherein the matrix region features are a set of parameters describing geometric features, numerical features, and computational features of different spatial regions of a matrix; Performing ternary quantization with a scaling factor on the quantization region and the precision parameter to obtain compressed representation data, wherein the precision parameter is a set of configuration parameters that control numerical representation precision and calculation precision; Performing a pre-filling operation on the compressed representation data and the memory characteristics of the ARM processor, and outputting a memory access optimization solution; Based on the memory access optimization scheme and the ARM processor instruction set, bit operation acceleration processing is performed to obtain the final optimization result.

12. The method according to claim 1, characterized in that The method also includes energy efficiency optimization and monitoring, including: Obtain ARM processor status data and energy efficiency targets, execute execution controller design, and output energy efficiency control strategy; Based on the energy efficiency control strategy and ARM processor parameters, dynamically adjust the configuration to obtain optimized operating parameters, wherein the ARM processor parameters are a set of parameters that describe the hardware characteristics and operating status of the ARM architecture processor; Performing error tracking analysis on the optimized operating parameters and precision representation data, and outputting a cumulative error report, wherein the precision representation data is detailed information recording different numerical precision representation methods; Performing accuracy improvement configuration based on the cumulative error report and computational task characteristics to obtain a balanced accuracy solution, wherein the computational task characteristics are characteristic parameters that describe the attributes and requirements of the matrix computation task; Based on the balanced accuracy scheme and system operation data, an accuracy energy efficiency model is constructed and a final optimization strategy is output.

13. A matrix calculation adaptive optimization system based on ARM architecture, characterized in that: include: An acquisition module is used to obtain matrix data to be processed and ARM processor information, preprocess the matrix data to be processed, and obtain preprocessed matrix data; An identification module is used to calculate local activity and identify hot spots on the pre-processed matrix data to determine the long-tail distribution characteristics of the matrix; A calculation module is used to receive the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters of the ARM processor, calculate the optimal block size range, and generate an asymmetric block solution; Establish a module for obtaining the asymmetric block solution, collecting the execution time and cache hit rate of each block, and establishing a mapping relationship between matrix characteristics and optimal block parameters; A generation module is used to obtain the asymmetric block scheme and mapping relationship, calculate the computing density and memory access mode of each block, and generate a task scheduling plan; The output module is used to obtain the task scheduling plan, perform matrix calculations on an ARM big.LITTLE architecture processor, and output final calculation results.

Images