Three-dimensional packaging structure with embedded interconnection silicon bridge and packaging method
By using an embedded interconnect silicon bridge structure and packaging process, the high cost and thermal expansion coefficient mismatch issues of 3D packaging technology have been solved, achieving high-density interconnection and improved reliability, thus meeting the needs of complex packaging in the future.
Patent Information
- Application Number
- CN202511489782.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-17
- Publication Date
- 2026-01-13
AI Technical Summary
Existing 3D packaging technologies suffer from high costs, complex processes, and thermal expansion coefficient mismatch, which affect packaging reliability and make it difficult to meet future complex packaging needs.
Employing an embedded interconnect silicon bridge structure, high-density interconnection between chips is achieved through a combination of substrate, interconnect silicon bridge, conductive pillars and packaging layer. Solder ball connection is used to improve mechanical strength and communication efficiency, and packaging, etching and electroplating processes are combined to reduce manufacturing difficulty.
It improves the interconnect density and communication efficiency between chips, enhances the reliability of packaging, reduces production costs and process complexity, and adapts to the needs of future complex packaging.
Smart Images
Figure CN121335566A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor, in particular to a three-dimensional packaging structure with embedded interconnection silicon bridge and a packaging method. BACKGROUND
[0002] With the slowing down of advanced process development, the improvement of chip performance gradually slows down, and the traditional Moore's law is also facing the risk of failure. The integrated circuit technology gradually advances to 3nm or even 2nm node, and the design and development cost of a single system chip (Soc) has broken through 1 billion dollars, and the manufacturing of large chips is difficult and has low yield, which leads to gradually declining economic benefits. Under this background, Chiplet technology emerges as the times require, which can effectively reduce the chip area and production cost by disassembling the SoC into multiple small-size, cross-process node high-yield chiplets and realizing IP reuse, and at the same time, through advanced packaging technology, multiple functional modules are integrated into a single chip to improve its overall performance and functionality.
[0003] High-density interconnection between chiplets is the core of high-performance packaging. Currently, mainstream 2.5D and 3D packaging technologies rely on high-density wiring silicon interposers, which are manufactured through wafer processes and can achieve line widths and spacings of less than 2μm, thereby greatly improving the bandwidth and interconnection performance between chiplets, and thus improving the overall performance of the package. However, silicon interposers based on wafer processes have high manufacturing difficulty and require the use of high aspect ratio through silicon vias and complex redistribution layers (RDL), so their process requirements are high, and only a few advanced wafer manufacturers have the related manufacturing capabilities, and the high development cost also limits its popularization in practical applications.
[0004] In order to overcome the cost and process challenges of large-size silicon interposers, Intel proposed the EMIB (Embedded Multi-die Interconnect Bridge) technology. By embedding small-size silicon bridges into the substrate to realize 3D packaging, this technology effectively solves some packaging problems. However, the EMIB technology also faces some challenges.
[0005] Firstly, the silicon bridge still needs to use wafer manufacturing process, which has a long production cycle, and as the number of chiplets increases, the number of silicon bridges will also increase, leading to an increase in process complexity and cost.
[0006] Secondly, the coefficient of thermal expansion (CTE) of silicon is 2.4ppm / ℃, while the CTE of the commonly used FCBGA packaging substrate is 14.2ppm / ℃. There is a significant mismatch in the coefficient of thermal expansion between the two. When too many silicon bridges are embedded on the substrate, asymmetric stress and strain may occur on both sides of the substrate, leading to problems such as adhesion failure and line cracking between the substrate and the silicon bridge, thereby affecting the overall reliability of the package.
[0007] Therefore, there is an urgent need to develop a 3D packaging technology with lower cost, smaller thermal expansion coefficient mismatch, and higher reliability to meet the increasingly complex packaging requirements of the future. Summary of the Invention
[0008] This invention provides a three-dimensional packaging structure and packaging method with embedded interconnect silicon bridges. Its purpose is to provide a new packaging structure, reduce the difficulty of multi-chip interconnection, and achieve a 3D packaging structure and packaging method with high interconnection density and small package size.
[0009] To achieve the above objectives, embodiments of the present invention provide a three-dimensional package structure with an embedded interconnect silicon bridge, comprising:
[0010] A substrate having lead pads around its perimeter;
[0011] Interconnect silicon bridges are bonded to the center of the substrate;
[0012] Conductive pillars are formed above the pin pads and electrically connected to the pin pads.
[0013] An encapsulation layer is also provided above the substrate, the encapsulation layer wraps the interconnect silicon bridge and the conductive pillar, and the upper end surface of the conductive pillar is flush with the upper end surface of the encapsulation layer.
[0014] The chip is flip-chip mounted on top of the packaging layer, with some pins of the multiple chips electrically connected to the interconnect silicon bridge and other pins electrically connected to the conductive pillars.
[0015] Preferably, the encapsulation layer is formed by encapsulation with a molding compound.
[0016] Preferably, the encapsulation layer is a dummy silicon wafer.
[0017] Preferably, the chip and the interconnect silicon bridge, and the chip and the conductive pillar are connected by solder balls.
[0018] Preferably, the diameter of the solder ball connected to the interconnect silicon bridge is smaller than the diameter of the solder ball connected to the conductive post.
[0019] Preferably, the height of the interconnect silicon bridge is higher than the height of the encapsulation layer.
[0020] Preferably, the conductive post is made of copper or nickel.
[0021] This application also provides a three-dimensional packaging method with embedded interconnect junction units for fabricating the aforementioned three-dimensional packaging structure with embedded interconnect silicon bridges, comprising the following steps:
[0022] S10. Bond interconnect silicon bridges in the middle of the substrate;
[0023] S20. An encapsulation layer is provided at the upper end of the substrate, and the height of the encapsulation layer is lower than the height of the interconnect silicon bridge;
[0024] S30. An etch is performed above the encapsulation layer to form a receiving groove, and an electroplating is performed in the receiving groove to form a conductive post that is electrically connected to the lead pad;
[0025] S40. The chip is flip-chipped onto the package layer, and electrical connections between the chip and the interconnect silicon bridge and between the chip and the conductive pillars are achieved through solder balls.
[0026] Preferably, in step S20, the encapsulation layer is formed by molding or by bonding a dummy silicon wafer to the substrate.
[0027] Preferably, step S30 further includes:
[0028] S31. Fabricate a mask based on the pin pad positions of the substrate;
[0029] S32. Spin-coat photoresist onto the upper surface of the encapsulation layer and bake to cure;
[0030] S33. Fix the photomask above the photoresist and use a photolithography machine to irradiate the photoresist so that the photoresist is exposed at the position corresponding to the pin pad, and dissolve the photoresist in the exposed area;
[0031] S34. The encapsulation layer is etched according to the exposure area to form a receiving groove, and electroplating is performed in the receiving groove to form a conductive pillar.
[0032] The above-described solution of the present invention has the following beneficial effects:
[0033] 1. In this application, interconnection between chips is achieved through interconnect silicon bridges, which effectively increases interconnection density, thereby improving the smoother data flow within the system and significantly improving performance;
[0034] 2. Interconnect silicon bridges can also provide communication channels between multiple chips, enabling seamless data transmission between chips, improving collaboration capabilities, facilitating the combination of chips with different functions, and improving computing performance and energy efficiency.
[0035] 3. By connecting the chip to the interconnect silicon bridge and conductive pillars via solder balls, compared with traditional wire bonding, it not only has a good mechanical fixing effect, but also can increase the interconnect density by changing the size of the solder ball diameter, thereby further improving the interconnect effect and the scope of application.
[0036] 4. By employing sequential packaging, etching, and electroplating processes, the height difference caused by the bonding of interconnect silicon bridges is compensated, making the manufacturing process easier compared to existing EMIB technology.
[0037] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of the internal structure of the three-dimensional encapsulation.
[0039] Figure 2 This is a flowchart of the three-dimensional encapsulation method.
[0040] [Explanation of Labels in the Attached Image]
[0041] 10. Substrate; 11. Lead pads;
[0042] 20. Interconnected silicon bridges;
[0043] 30. Conductive pillar;
[0044] 40. Encapsulation layer;
[0045] 50. Chip; 51. Solder ball. Detailed Implementation
[0046] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.
[0047] like Figure 1 As shown, an embodiment of the present invention provides a three-dimensional package structure with an embedded interconnect silicon bridge, including a substrate 10. The substrate 10 has lead pads 11 around its perimeter. An interconnect silicon bridge 20 is disposed in the center of the substrate 10 and is connected to the substrate 10 by an adhesive bonding method. Conductive pillars 30 are also disposed on the lead pads 11 and are electrically connected to the lead pads 11, thereby enabling signal transmission between the lead pads 11 and the conductive pillars 30. An encapsulation layer 40 is also disposed on the substrate 10, which circumferentially surrounds the interconnect silicon bridge 20 and the conductive pillars 30. The upper surface of the encapsulation layer 40 is flush with the upper surface of the conductive pillars 30, meaning the upper ends of the conductive pillars 30 are exposed in the encapsulation layer 40. Several chips 50 are flip-chip mounted on top of the encapsulation layer 40, with some pins of each chip 50 electrically connected to the interconnect silicon bridge 20 and other pins electrically connected to the conductive pillars 30.
[0048] In this application, interconnection between chips 50 is achieved through interconnect silicon bridge 20, which can not only improve the interconnection communication channel of chips 50, but also match chips 50 with different functions to improve the performance and energy efficiency of the computer.
[0049] In one embodiment of this application, after the interconnect silicon bridge 20 is bonded to the substrate 10, a molding compound is used to encapsulate and shape the substrate 10 and the interconnect silicon bridge 20.
[0050] In another embodiment of this application, after the interconnect silicon bridge 20 is bonded to the substrate 10, a dummy silicon wafer is bonded to the substrate 10.
[0051] In one embodiment of this application, the chip 50 is connected to the interconnect silicon bridge 20 and the conductive pillar 30 using solder balls 51. The solder balls 51 enhance the mechanical strength between the chip 50 and the interconnect silicon bridge 20 and the conductive pillar 30. In this embodiment, the height of the interconnect silicon bridge 20 is higher than the height of the packaging layer 40, and the diameter of the solder balls 51 connected to the interconnect silicon bridge 20 is smaller than the diameter of the solder balls 51 connected to the conductive pillar 30. The smaller diameter of the solder balls 51 connected to the interconnect silicon bridge 20 not only allows for a more secure connection between the chip 50 and the interconnect silicon bridge 20, preventing asymmetric stress that could cause breakage between the chip 50 and the interconnect silicon bridge 20 and affect overall reliability, but also allows the chip 50 and the interconnect silicon bridge 20 to establish a denser communication channel through the solder balls 51, thereby improving overall computing performance.
[0052] Preferably, in this application, the conductive post 30 is made of copper or nickel.
[0053] like Figure 2 This application also provides a three-dimensional packaging method with embedded interconnect junction units for fabricating the aforementioned three-dimensional packaging structure with embedded interconnect silicon bridges, comprising the following steps:
[0054] S10. An interconnect silicon bridge 20 is bonded to the middle of the substrate 10;
[0055] S20. An encapsulation layer 40 is provided at the upper end of the substrate 10, and the height of the encapsulation layer 40 is lower than the height of the interconnect silicon bridge 20.
[0056] In one embodiment, the encapsulation layer 40 is formed of a molding compound, which is used to encapsulate the substrate 10. The molding compound forms a molded body around the interconnect silicon bridge 20 and above the substrate 10, and the height of the molded body is lower than the height of the interconnect silicon bridge 20.
[0057] In another embodiment of this application, the encapsulation layer 40 is formed of a dummy silicon wafer, which is bonded around the interconnect silicon bridge 20, and the height of the dummy silicon wafer is lower than the height of the interconnect silicon bridge 20.
[0058] S30. An etch is performed above the encapsulation layer 40 to form a receiving groove, and an electroplating is performed in the receiving groove to form a conductive post 30 that is electrically connected to the lead pad 11.
[0059] In this embodiment, before step S10, a mask is fabricated based on the position of the pin pads 11 on the substrate 10. After the mask is fabricated, steps S10 and S20 are performed. Photoresist is applied to the upper surface of the encapsulation layer 40 using a spin coater and then baked and cured. Subsequently, the mask is fixed above the photoresist and the photoresist is irradiated using a photolithography machine, so that the photoresist protects the position corresponding to the pin pads 11 and dissolves the photoresist in the exposed area. It is understood that the projection of the exposed area on the substrate 10 falls on the pin pads 11. The encapsulation layer 40 is etched according to the exposed area to form a receiving groove. Electroplating is performed layer by layer in the receiving groove to form conductive pillars 30 electrically connected to the pin pads 11.
[0060] Preferably, after etching is completed, the photoresist on the encapsulation layer 40 is cleaned.
[0061] S40. Each chip 50 is flip-chipped onto the package layer 40 one by one using solder balls 51, ensuring electrical connection between chip 50 and interconnect silicon bridge 20, and between chip 50 and conductive pillar 30.
[0062] By changing the packaging process, including encapsulation, etching, and electroplating, production difficulty can be reduced and production efficiency improved.
[0063] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A three-dimensional packaging structure with embedded interconnect silicon bridges, characterized in that, include: A substrate (10) having lead pads (11) around its perimeter. Interconnected silicon bridges (20) are bonded to the center of the substrate (10); Conductive posts (30) are formed above the pin pads (11) and electrically connected to the pin pads (11). An encapsulation layer (40) is also provided above the substrate (10). The encapsulation layer (40) wraps the interconnect silicon bridge (20) and the conductive pillar (30), and the upper end face of the conductive pillar (30) is flush with the upper end face of the encapsulation layer (40). Chips (50) are flip-chip mounted on top of the package layer (40). Some pins of the chips (50) are electrically connected to the interconnect silicon bridge (20), and other pins are electrically connected to the conductive pillars (30).
2. The three-dimensional packaging structure with embedded interconnect silicon bridge according to claim 1, characterized in that: The encapsulation layer (40) is formed by encapsulation with a molding material.
3. The three-dimensional packaging structure with embedded interconnect silicon bridge according to claim 1, characterized in that: The encapsulation layer (40) is a dummy silicon wafer.
4. The three-dimensional packaging structure with embedded interconnect silicon bridge according to claim 1, characterized in that: The chip (50) is connected to the interconnect silicon bridge (20) and to the conductive pillar (30) by solder balls (51).
5. The three-dimensional packaging structure with embedded interconnect silicon bridge according to claim 4, characterized in that: The diameter of the solder ball (51) connected to the interconnect silicon bridge (20) is smaller than the diameter of the solder ball (51) connected to the conductive post (30).
6. The three-dimensional packaging structure with embedded interconnect silicon bridge according to claim 1, characterized in that: The height of the interconnect silicon bridge (20) is higher than the height of the encapsulation layer (40).
7. The three-dimensional packaging structure with embedded interconnect silicon bridge according to claim 1, characterized in that: The conductive post (30) is made of copper or nickel.
8. A three-dimensional packaging method with embedded interconnect junction units, used to fabricate the three-dimensional packaging structure with embedded interconnect silicon bridges as described in any one of claims 1-7, characterized in that, Includes the following steps: S10. An interconnect silicon bridge (20) is bonded to the middle of the substrate (10). S20. An encapsulation layer (40) is provided on the upper end of the substrate (10), and the height of the encapsulation layer (40) is lower than the height of the interconnect silicon bridge (20); S30. An accommodating groove is formed by etching above the encapsulation layer (40), and a conductive post (30) electrically connected to the lead pad (11) is formed by electroplating in the accommodating groove. S40. The chip (50) is flip-chipped onto the package layer (40), and the chip (50) is electrically connected to the interconnect silicon bridge (20) and the conductive pillar (30) through solder balls (51).
9. The three-dimensional packaging method according to claim 8, characterized in that: In step S20, the encapsulation layer (40) is formed by encapsulation material or by bonding a dummy silicon wafer to the substrate (10).
10. The three-dimensional packaging method with embedded interconnect units according to claim 8, characterized in that: Step S30 further includes: S31. A mask is fabricated based on the position of the pin pad (11) on the substrate (10); S32. Spin-coat photoresist onto the upper surface of the encapsulation layer (40) and bake to cure; S33. Fix the mask above the photoresist and use a photolithography machine to irradiate the photoresist so that the photoresist is exposed at the position corresponding to the pin pad (11) and the photoresist in the exposed area is dissolved. S34. The encapsulation layer (40) is etched according to the exposure area to form a receiving groove, and an electroplating is performed in the receiving groove to form a conductive pillar (30).