Synchronizer flip-flop circuit

By providing a bias voltage to the inverter in the synchronizer trigger circuit, the transistor threshold voltage is reduced, thus solving the problem of synchronizer trigger delay, improving data storage speed and fault interval time, while reducing cost and area.

CN121444347APending Publication Date: 2026-01-30TEXAS INSTRUMENTS INC
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Patent Information

Application Number
CN202380100054.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2023-08-30
Filing Date
2023-12-29
Publication Date
2026-01-30

AI Technical Summary

Technical Problem

Existing synchronizer triggers suffer from latency issues, which affect the speed at which the triggers stably store data when data input and clock signal states change, and also increase design costs and area.

Method used

By providing a bias voltage to the inverter in the trigger circuit, the transistor threshold voltage of the inverter is reduced. Using a diode-connected transistor to provide a bias voltage to the inverter reduces delay and increases latching efficiency.

Benefits of technology

It reduces the delay of the trigger circuit, increases the mean time between failures, and reduces design costs and area requirements.

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Abstract

Embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. In an example, a synchronizer flip-flop circuit is provided. A synchronizer flip-flop circuit (100) includes: a first latch sub-circuit (112) coupled to receive input data (101); and a second latch sub-circuit (117) coupled to the first latch sub-circuit (112). The first latch sub-circuit (112) includes: a first inverter group; a first diode connected transistor (113) coupled in parallel to each of the inverters in the first group of inverters and configured to provide a first bias voltage to each of the inverters in the first group of inverters; and a second diode-connected transistor (114) coupled in parallel to each of the inverters in the first group of inverters and configured to provide a second bias voltage to each of the inverters in the first group of inverters.
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