A super junction fast recovery diode and a manufacturing method thereof

Abstract

The application relates to the technical field of semiconductors, in particular to a super-junction fast recovery diode and a manufacturing method thereof, which comprises a substrate, a buffer layer located on the substrate, a drift layer located on the buffer layer, a P-type region located on the drift layer, and a P column located in the drift layer and on the buffer layer, wherein the bottom of the P column is in contact with the upper edge of the buffer layer, and the top of the P column is not in contact with the lower edge of the P-type region. Through the structural arrangement of the super-junction fast recovery diode, the reverse withstand voltage of the device is greatly improved, the on-state voltage drop is reduced, the reverse recovery performance is enhanced, and the reverse recovery loss is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a superjunction fast recovery diode and its manufacturing method. Background Technology

[0002] Fast recovery diodes are typically used in anti-parallel connection with controllable main switching devices such as IGBTs for protection. When the main switching device is turned off, the fast recovery diode continues to maintain the current on the inductive load, preventing voltage spikes caused by sudden current drops. This is to reduce power consumption, protect the main switching device, and improve device reliability. To meet the requirements of the diode's operation, fast recovery diodes are required to have low forward voltage drop, high withstand voltage, low leakage current, short reverse recovery time, and excellent recovery softness. However, due to the structural characteristics of fast recovery diodes, the withstand voltage, switching time, reverse recovery time, and forward voltage drop parameters are contradictory, making it difficult to achieve a good compromise.

[0003] Currently, fast recovery diodes typically incorporate a superjunction structure, meaning that interconnected P-pillars are present in the P-region to form a superjunction fast recovery diode. These superjunction fast recovery diodes can, to some extent, resolve the trade-off between reverse breakdown voltage and forward voltage drop. However, in practical applications, current superjunction fast recovery diodes still suffer from relatively low reverse breakdown voltage and relatively high forward voltage drop. Summary of the Invention

[0004] This application provides a superjunction fast recovery diode and its manufacturing method, which solves the technical problems of low reverse breakdown voltage and high forward voltage drop in the prior art of superjunction fast recovery diodes, and achieves technical effects such as improving reverse breakdown voltage, reducing forward voltage drop, enhancing reverse recovery performance, and reducing reverse recovery loss.

[0005] In a first aspect, embodiments of the present invention provide a superjunction fast recovery diode, comprising:

[0006] Substrate;

[0007] A buffer layer, wherein the buffer layer is located on the substrate;

[0008] A drift layer, which is located above the buffer layer;

[0009] P-type region, the P-type region being located above the drift layer;

[0010] The P-pillar is located in the drift layer and above the buffer layer. The bottom of the P-pillar is in contact with the upper edge of the buffer layer, and the top of the P-pillar is not in contact with the lower edge of the P-shaped area.

[0011] Optionally, a set distance exists between the top of the P-pillar and the P-shaped area, the set distance ranging from 5um to 20um.

[0012] Optionally, the injection dose range of the P column is 1e12cm-2 to 5e16cm-2.

[0013] Optionally, the number of P-pillars is two, and the two P-pillars are distributed at intervals;

[0014] The drift layer region between the two P pillars is denoted as the N pillar. The N pillar and the P pillar must satisfy the relationship shown by the formula Nd×Wn=Na×Wp, where Nd is the doping concentration of the N pillar, Na is the doping concentration of the P pillar, Wn is the width of the N pillar, and Wp is the width of the P pillar.

[0015] Optionally, it also includes: two sets of P islands, each set of P islands including multiple P islands, each set of P islands replacing one P pillar; in each set of P islands, the multiple P islands are located in the drift layer and are arranged longitudinally, the bottom of the bottommost P island is in contact with the upper edge of the buffer layer, and the top of the topmost P island is not in contact with the lower edge of the P-shaped area and there is a set distance between them.

[0016] Optionally, in each group of P islands, the spacing between two adjacent P islands satisfies the relationship shown by the formula N1×W1=N2×W2, where N1 is the doping concentration of the drift layer region between two adjacent P islands, N2 is the doping concentration of the P island, W1 is the distance between two adjacent P islands, and W2 is the height of the P island.

[0017] Optionally, the injection dose range of the P-type region is 1e12cm-2 to 1e16cm-2.

[0018] Optionally, it may also include: an anode metal layer, the anode metal layer being located above the P-type region.

[0019] Optionally, it may also include a cathode metal layer located beneath the substrate.

[0020] Based on the same inventive concept, in a second aspect, the present invention also provides a method for manufacturing a superjunction fast recovery diode, for manufacturing the superjunction fast recovery diode as described in the first aspect, the method comprising:

[0021] A buffer layer is formed on the substrate;

[0022] A drift layer is formed on top of the buffer layer;

[0023] A P-type region is formed on the drift layer;

[0024] P-pillars are formed in the drift layer, wherein the P-pillars are located above the buffer layer, the bottom of the P-pillars is in contact with the upper edge of the buffer layer, and the top of the P-pillars is not in contact with the lower edge of the P-shaped region.

[0025] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0026] In this embodiment of the invention, a P-pillar is provided in the drift layer, and the P-pillar is connected to the buffer layer and separated from the P-type region. During forward conduction, the drift layer region between the P-type region and the P-pillar suppresses hole injection, reduces the stored charge of the drift layer, thereby reducing the reverse peak current Irrm, reverse recovery charge Qrr, and reverse recovery time trr of the fast recovery diode device, reducing reverse recovery losses, and thus significantly reducing the forward voltage drop of the device. Furthermore, when a reverse withstand voltage is applied to the fast recovery diode, not only is there a lateral electric field in the PN junction formed by the P-pillar and the drift layer to bear the voltage, but the P-pillar and the buffer layer also mutually deplete the voltage. Therefore, through the superjunction fast recovery diode structure of this embodiment of the invention, a higher reverse withstand voltage and a lower forward voltage drop can be obtained, better resolving the contradiction between reverse withstand voltage and forward voltage drop, and improving the reliability and practicality of the device. In addition, among fast recovery diodes with the same current specification, the area of ​​the fast recovery diode of this embodiment of the invention can be made smaller, further improving the reliability and practicality of the device. Attached Figure Description

[0027] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0028] Figure 1 A schematic diagram of the structure of the superjunction fast recovery diode in an embodiment of the present invention is shown;

[0029] Figure 2 A schematic diagram of a second embodiment of the superjunction fast recovery diode is shown.

[0030] Figure 3 This diagram illustrates a structure in which a buffer layer and a drift layer are sequentially formed on a substrate in an embodiment of the present invention.

[0031] Figure 4 This shows a schematic diagram of a structure in which a P-pillar is formed on the drift layer in an embodiment of the present invention;

[0032] Figure 5This diagram illustrates the structure of forming multiple drift layers and multiple P-pillars in an embodiment of the present invention.

[0033] Figure 6 A schematic diagram of the structure of the epitaxial drift layer at the top of the P-pillar in an embodiment of the present invention is shown;

[0034] Figure 7 A schematic diagram of the structure forming a complete and continuous P-pillar in an embodiment of the present invention is shown;

[0035] Figure 8 This diagram illustrates a structure in which a P-type region is formed on the drift layer according to an embodiment of the present invention.

[0036] Figure 9 A schematic diagram of the comparative device in an embodiment of the present invention is shown;

[0037] Figure 10 A schematic diagram comparing the reverse recovery curves of the device in the embodiment of the present invention with those of a comparative device is shown.

[0038] Figure 11 A schematic diagram comparing the reverse withstand voltage curves of the device in the embodiment of the present invention with those of a comparative device is shown.

[0039] Figure 12 A schematic diagram comparing the forward voltage drop curves of the device in the embodiment of the present invention with those of a comparative device is shown.

[0040] Figure 13 A schematic flowchart of the manufacturing method of the superjunction fast recovery diode according to an embodiment of the present invention is shown.

[0041] In the attached figures, 101 is the substrate; 102 is the buffer layer; 103 is the drift layer; 104 is the P-type region; 105 is the P-pillar; 106 is the anode metal layer; 107 is the cathode metal layer; and 108 is the P-island. Detailed Implementation

[0042] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0043] Example 1

[0044] The first embodiment of the present invention provides a superjunction fast recovery diode, such as... Figure 1As shown, the structure includes: a substrate 101, a buffer layer 102, a drift layer 103, a P-type region 104, and a P-pillar 105. The buffer layer 102 is located above the substrate 101, the drift layer 103 is located above the buffer layer 102, and the P-type region 104 is located above the drift layer 103. The P-pillar 105 is located within the drift layer 103 and above the buffer layer 102. The bottom of the P-pillar 105 contacts the upper edge of the buffer layer 102, while the top of the P-pillar 105 does not contact the lower edge of the P-type region 104, indicating that the P-pillar 105 is connected to the buffer layer 102 and isolated from the P-type region 104.

[0045] In this embodiment, a P-pillar 105 is provided in the drift layer 103, and the P-pillar 105 is connected to the buffer layer 102 and separated from the P-type region 104. During forward conduction, the drift layer 103 region between the P-type region 104 and the P-pillar 105 suppresses hole injection and reduces the stored charge in the drift layer 103, thereby reducing the reverse peak current Irrm, reverse recovery charge Qrr, and reverse recovery time trr of the fast recovery diode device, reducing reverse recovery losses, and thus significantly reducing the forward conduction voltage drop of the device. Furthermore, when the fast recovery diode is subjected to reverse withstand voltage, not only is there a lateral electric field in the PN junction formed by the P-pillar 105 and the drift layer 103 to bear the voltage, but the P-pillar 105 and the buffer layer 102 also mutually deplete the voltage. Therefore, through the superjunction fast recovery diode structure of this embodiment, a higher reverse withstand voltage and a lower forward voltage drop can be obtained, better solving the contradiction between reverse withstand voltage and forward voltage drop, and improving the reliability and practicality of the device. Furthermore, among fast recovery diodes with the same current rating, the area of ​​the fast recovery diode in this embodiment can be made smaller, further improving the reliability and practicality of the device.

[0046] Below, in conjunction with Figure 1 The structure of the superjunction fast recovery diode in this embodiment is described in detail:

[0047] exist Figure 1In this design, substrate 101 is a heavily doped N-type substrate, buffer layer 102 is a moderately doped N-type buffer layer, and drift layer 103 is a lightly doped N-type drift layer. P-pillar 105 is located within drift layer 103, with its bottom contacting buffer layer 102 and its top separated from P-type region 104. A predetermined distance exists between the top of P-pillar 105 and P-type region 104, specifically the distance from the top of P-pillar 105 to the lower edge of P-type region 104, ranging from 5µm to 20µm. By setting this distance, hole injection between P-type region 104 and P-pillar 105 is suppressed during forward conduction, reducing the stored charge in drift layer 103. This reduces the reverse peak current Irrm, reverse recovery charge Qrr, and reverse recovery time trr of the fast recovery diode device, decreasing reverse recovery losses and significantly reducing the forward voltage drop of the device. Furthermore, the P-pillar 105 is in contact with the buffer layer 102, so that when a reverse breakdown voltage is applied to the superjunction fast recovery diode, not only is there a lateral electric field in the PN junction formed by the P-pillar 105 and the drift layer 103 to bear the voltage, but the P-pillar 105 and the buffer layer 102 also mutually deplete the voltage. This improves the reverse breakdown voltage of the superjunction fast recovery diode and further optimizes the trade-off between the reverse breakdown voltage and the forward voltage drop of the device.

[0048] The injection dose range for P-column 105 is 1e12cm. -2 -5e16cm -2 The injection dose range for P-type region 104 is 1e12cm. -2 -1e16cm -2 By setting the implantation dose of P-pillar 105, the doping concentration and width of P-pillar 105 are matched with those of the corresponding N-pillar in drift layer 103, which can better meet the charge balance requirements in the superjunction structure. This helps P-pillar 105 and N-pillar to be fully depleted under reverse bias, thereby effectively improving the reverse breakdown voltage of the device. A suitable implantation dose can ensure that P-pillar 105 provides sufficient hole concentration to form good compensation with the electron concentration of N-pillar, so that the depletion region can expand uniformly under high reverse voltage, avoiding electric field concentration, and thus improving the breakdown voltage of the device. If the implantation dose of P-pillar 105 is too high, a larger spacing is required between P-pillars in order for P-pillar 105 and N-pillar to be fully depleted, thereby increasing the chip area and cost. If the implantation dose of P-pillar 105 is too low, it may not be able to effectively form an ideal superjunction structure, and the ability to increase breakdown voltage is limited. It is difficult to give full play to the advantages of the superjunction device in this embodiment in reducing on-state voltage drop and improving breakdown voltage, so that the reverse breakdown voltage and forward characteristics of the device cannot achieve the expected results.

[0049] There are two P-columns, such as... Figure 1The left and right P-pillars 105 are spaced apart. The drift layer 103 region between the two P-pillars 105 is denoted as the N-pillar. The N-pillar and P-pillar 105 must satisfy the relationship shown by the formula Nd×Wn=Na×Wp, where Nd is the doping concentration of the N-pillar, Na is the doping concentration of the P-pillar 105, Wn is the width of the N-pillar, and Wp is the width of the P-pillar 105. Figure 1 In the diagram, the width of the N-pillar represents the distance between the left and right P-pillars 105. The distance between the P-pillars 105 cannot be too small or too large. If the distance is too small, the superjunction fast recovery diode will have limited structural voltage withstand capability during reverse breakdown, limiting its ability to increase the breakdown voltage. If the distance is too large, it results in wasted device area, reduced device and chip integration, and increased cost.

[0050] like Figure 1 As shown, the superjunction fast recovery diode device structure of this embodiment further includes: an anode metal layer 106 and a cathode metal layer 107. The anode metal layer 106 is located above the P-type region 104. The cathode metal layer 107 is located below the substrate 101, and the substrate 101 and the cathode metal layer 107 form an ohmic contact.

[0051] This embodiment also includes a second scheme, which differs from the first scheme only in the structural arrangement of P-pillar 105; all other structural parameters are identical. Scheme 1 is as follows: Figure 1 The continuous P-pillar 105 structure is shown. Option two is as follows: Figure 2 The P-island 108 structure is shown with an interval distribution. In Scheme 2, as... Figure 2 As shown, the superjunction fast recovery diode device also includes: two sets of P-islands 108, i.e. Figure 2 The left and right groups of P-islands 108 are arranged in the middle. Each group of P-islands 108 includes multiple P-islands 108, and each group of P-islands 108 replaces one P-pillar 105. That is, each P-pillar 105 is replaced by multiple independent P-islands 108, i.e., a group of P-islands 108. The number of P-islands 108 in each group can be set according to actual needs. In each group of P-islands 108, the multiple P-islands 108 are located in the drift layer 103 and are arranged vertically. The bottom of the bottom P-island 108 is in contact with the upper edge of the buffer layer 102, and the top of the top P-island 108 is not in contact with the lower edge of the P-shaped area 104 and there is a set distance between them.

[0052] In each group of P islands 108, the spacing between two adjacent P islands 108 satisfies the relationship shown by the formula N1×W1=N2×W2. Where N1 is the doping concentration of the drift layer 103 region between two adjacent P islands 108, N2 is the doping concentration of the P island 108, W1 is the distance between two adjacent P islands 108, and W2 is the height of the P island 108.

[0053] In Scheme 2, in each group of P-islands 108 in the drift layer 103, the bottom P-island 108 (denoted as bottom P-island 108) is connected to the buffer layer 102, and the top P-island 108 (denoted as top P-island 108) is separated from the P-type region 104. During forward conduction, the drift layer 103 region between the top P-island 108 and the P-pillar 105 suppresses hole injection, reduces the stored charge of the drift layer 103, thereby reducing the reverse peak current Irrm, reverse recovery charge Qrr, and reverse recovery time trr of the fast recovery diode device, reducing reverse recovery losses, and thus significantly reducing the forward conduction voltage drop of the device. Furthermore, when the fast recovery diode is subjected to reverse withstand voltage, not only is there a lateral electric field in the PN junction formed by the P-island 108 and the drift layer 103 to bear the voltage, but the bottom P-pillar 105 and the buffer layer 102 also mutually deplete the voltage. Therefore, the superjunction fast recovery diode structure of this embodiment achieves higher reverse breakdown voltage and lower forward voltage drop, better resolving the contradiction between reverse breakdown voltage and forward voltage drop, and improving the reliability and practicality of the device. Furthermore, among fast recovery diodes with the same current rating, the area of ​​the fast recovery diode in this embodiment can be made smaller, further enhancing the reliability and practicality of the device.

[0054] The working principle of the superjunction fast recovery diode based on P-pillar 105 in this embodiment is as follows:

[0055] A P-pillar 105 is provided in the drift layer 103, and the P-pillar 105 is connected to the buffer layer 102. The P-pillar 105 is also separated from the P-type region 104, forming a PN-alternating structure. When the device is forward-biased, the drift layer 103 region between the P-type region 104 and the P-pillar 105 suppresses hole injection and reduces the stored charge in the drift layer 103. During the reverse recovery process, the superjunction fast recovery diode device needs to remove the stored charge from the forward-biased state. Since only a small amount of stored charge is stored in the drift layer 103, the reverse peak current Irrm, reverse recovery charge Qrr, and reverse recovery time trr of the fast recovery diode device are reduced during the reverse recovery process, reducing reverse recovery losses and significantly reducing the on-state voltage drop. Furthermore, when the fast recovery diode is subjected to reverse withstand voltage, not only is there a transverse electric field in the PN junction formed by the P-pillar 105 and the drift layer 103 to withstand the voltage, but the P-pillar 105 and the buffer layer 102 also mutually deplete each other to withstand the voltage. Therefore, the superjunction fast recovery diode structure of this embodiment achieves higher reverse breakdown voltage and lower forward voltage drop, better resolving the contradiction between reverse breakdown voltage and forward voltage drop, and improving the reliability and practicality of the device. Furthermore, among fast recovery diodes with the same current rating, the area of ​​the fast recovery diode in this embodiment can be made smaller, further enhancing the reliability and practicality of the device.

[0056] The manufacturing process of the superjunction fast recovery diode in this embodiment is as follows:

[0057] Step 1, as follows Figure 3 As shown, a buffer layer 102 is formed on a substrate 101, and a drift layer 103 is formed on the buffer layer 102. The doping concentration of the buffer layer 102 ranges from 1e17cm. -3 ~4e13 cm -3 The thickness of the buffer layer 102 ranges from 2 to 50 μm.

[0058] Step two, as Figure 4 As shown, phosphorus was injected onto the surface of the drift layer 103, followed by a superjunction P-pillar 105 injection. The phosphorus injection dose ranged from 1e13 to 5e16 cm⁻¹. -2 The injection dose range for P-column 105 is 1e12~5e16cm. -2 .

[0059] Step 3, as Figure 5 As shown, the operation process of step two is repeated to perform multiple epitaxial processes of drift layer 103 and the process of forming multiple superstructure pillars P pillars 105.

[0060] Step four, as Figure 6 As shown, a drift layer 103 is further epitaxially formed above the top of the P-pillar 105. The doping concentration of the drift layer 103 ranges from 1e16 cm⁻¹. -3 ~4e13 cm -3 The thickness of the drift layer 103 above the top of the P-pillar 105 can also range from 10 to 40 μm.

[0061] Step 5, as Figure 7 As shown, multi-segment superstructure P-pillar 105 diffusion annealing is performed to form a complete and continuous P-pillar 105.

[0062] Step six, as follows Figure 8 As shown, maskless P-type ion implantation is performed on the surface of the drift layer 103, followed by high-temperature push-bonding to form a P-type region 104.

[0063] Step six, as follows Figure 1 As shown, metal deposition is performed on the surface of the P-type region 104 and under the substrate 101, followed by electron irradiation and metallization. In this way, an anode metal layer 106 is formed on the P-type region 104 and a cathode metal layer 107 is formed under the substrate 101.

[0064] In the manufacturing process of the superjunction fast recovery diode of Scheme 2, only the formation process of each group of P islands 108 is different. In the formation process of each group of P islands 108, steps two and three are different from steps two and three of Scheme 1. In steps two and three, the thickness of each epitaxial drift layer 103 exceeds the depth of each P implantation and the depth after subsequent high-temperature diffusion, ensuring that each P pillar 105 is formed by multiple independent P islands 108.

[0065] The superjunction fast recovery diode device with P-pillar 105 structure in this embodiment is compared and analyzed with the comparative device:

[0066] The structure of the comparison device is as follows Figure 9 As shown, in the structure of the comparative device, the top of the P-pillar 105 is connected to the P-type region 104, and the bottom of the P-pillar 105 is isolated from the buffer layer 102. In the device structure of this embodiment, the top of the P-pillar 105 is isolated from the P-type region 104, and the bottom of the P-pillar 105 is in contact with the buffer layer 102.

[0067] The comparative device also incorporates a P-pillar 105. When a reverse voltage is applied to the comparative device, the P-pillar 105 and the N-type drift layer 103 deplete their voltage, increasing the lateral electric field and thus improving the withstand voltage of the comparative device. This provides room for reducing the thickness and resistivity of the substrate 101. Therefore, while achieving the same reverse withstand voltage, a thinner drift layer 103 can be used, resulting in a lower forward conduction voltage drop and resolving the contradiction between withstand voltage and conduction voltage drop. However, during forward conduction of the comparative device, due to conductivity modulation, a large number of holes from the P-type region 104 and the P-pillar 105 are injected into the drift layer 103, increasing the anode injection efficiency during forward conduction and storing a large number of holes in the P-pillar 105 and the drift layer 103. However, fast recovery diodes require the stored charge from forward conduction to be removed during reverse recovery. Therefore, although the comparative device resolves the contradiction between withstand voltage and forward voltage drop, it introduces more stored charge, which increases the reverse peak current Irrm, reverse recovery charge Qrr, and reverse recovery time trr.

[0068] Compared to the comparative device, in this embodiment, during forward conduction, the drift layer 103 region between the P-type region 104 and the P-pillar 105 suppresses hole injection and reduces the stored charge in the drift layer 103. During reverse recovery, the superjunction fast recovery diode needs to remove the stored charge from the forward conduction phase. Since the drift layer 103 of this embodiment stores only a small amount of stored charge, the reverse peak current Irrm, reverse recovery charge Qrr, and reverse recovery time trr of the fast recovery diode are reduced during reverse recovery, thus reducing reverse recovery losses and significantly lowering the on-state voltage drop. Furthermore, when the reverse withstand voltage is applied to the device in this embodiment, not only is there a lateral electric field in the PN junction formed by the P-pillar 105 and the drift layer 103 acting as a voltage bearer, but the P-pillar 105 and the buffer layer 102 also mutually deplete the voltage bearer. Therefore, through the device structure configuration of this embodiment, a higher reverse withstand voltage and a lower on-state voltage drop can be obtained, optimizing the trade-off between reverse withstand voltage and forward voltage drop, and improving the reliability and practicality of the device. Furthermore, among fast recovery diodes with the same current rating, the device area in this embodiment can be made smaller, further improving the device's reliability and practicality.

[0069] If the design parameters of the comparison device are consistent with those of the device in this embodiment, such as Figure 10 As shown, the horizontal axis represents the time during the reverse recovery process, and the vertical axis represents the current during the reverse recovery process. Compared to the comparative device, the device in this embodiment has a smaller reverse peak current Irrm, less reverse recovery charge Qrr, and a shorter reverse recovery time trr. Figure 11 As shown, the horizontal axis represents the reverse breakdown voltage, and the vertical axis represents the current corresponding to the breakdown voltage. Compared to the comparative device, the reverse withstand voltage of the device in this embodiment can reach 900V, indicating that the reverse withstand voltage performance of the device structure in this embodiment is superior. Figure 12 As shown, the horizontal axis represents the forward voltage drop, and the vertical axis represents the corresponding current. Compared to the comparative device, the device in this embodiment has a smaller forward voltage drop. Thus, under the same reverse withstand voltage, the device in this embodiment can achieve a thinner drift layer 103, thereby achieving a lower forward voltage drop.

[0070] Example 2

[0071] Based on the same inventive concept, the second embodiment of the present invention also provides a method for manufacturing a superjunction fast recovery diode, such as... Figure 13 As shown, a method for manufacturing a superjunction fast recovery diode as described in Example 1 includes:

[0072] S201, a buffer layer is formed on the substrate;

[0073] S202, a drift layer is formed on the buffer layer;

[0074] S203, a P-type region is formed on the drift layer;

[0075] S204, forming a P-pillar in the drift layer, wherein the P-pillar is located above the buffer layer, the bottom of the P-pillar is in contact with the upper edge of the buffer layer, and the top of the P-pillar is not in contact with the lower edge of the P-shaped region.

[0076] Since the manufacturing method of the superjunction fast recovery diode described in this embodiment is the same as the manufacturing method used for the superjunction fast recovery diode in Embodiment 1 of this application, those skilled in the art can understand the specific implementation method and various variations of the manufacturing method of the superjunction fast recovery diode in this embodiment based on the superjunction fast recovery diode described in Embodiment 1 of this application. Therefore, how the manufacturing method of this superjunction fast recovery diode implements the superjunction fast recovery diode in Embodiment 1 of this application will not be described in detail here. As long as those skilled in the art implement the manufacturing method used for the superjunction fast recovery diode in Embodiment 1 of this application, they are all within the scope of protection of this application.

[0077] Those skilled in the art will understand that although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0078] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A superjunction fast recovery diode, characterized in that, include: Substrate; A buffer layer, wherein the buffer layer is located on the substrate; A drift layer, which is located above the buffer layer; P-type region, the P-type region being located above the drift layer; The P-pillar is located in the drift layer and above the buffer layer. The bottom of the P-pillar is in contact with the upper edge of the buffer layer, and the top of the P-pillar is not in contact with the lower edge of the P-shaped area. There is a set distance between the top of the P-pillar and the P-shaped area, and the set distance ranges from 5um to 20um; By setting the distance, hole injection between the P-type region and the P-pillar is suppressed when the device is forward-biased, reducing the stored charge in the drift layer. This reduces the reverse peak current Irrm, reverse recovery charge Qrr, and reverse recovery time trr of the fast recovery diode, thus reducing reverse recovery losses. Furthermore, the contact between the P-pillar and the buffer layer ensures that when a reverse withstand voltage is applied to the superjunction fast recovery diode, not only is there a transverse electric field in the PN junction formed by the P-pillar and the drift layer acting as a withstand voltage, but the P-pillar and the buffer layer also mutually deplete each other to withstand the voltage.

2. The superjunction fast recovery diode as described in claim 1, characterized in that, The injection dose range of the P-column is 1e12cm. -2 -5e16cm -2 .

3. The superjunction fast recovery diode as described in claim 1, characterized in that, The number of P-pillars is two, and the two P-pillars are distributed at an interval; The drift layer region between the two P pillars is denoted as the N pillar. The N pillar and the P pillar must satisfy the relationship shown by the formula Nd×Wn=Na×Wp, where Nd is the doping concentration of the N pillar, Na is the doping concentration of the P pillar, Wn is the width of the N pillar, and Wp is the width of the P pillar.

4. The superjunction fast recovery diode as described in claim 1, characterized in that, The injection dose range for the P-type region is 1e12cm. -2 -1e16cm -2 .

5. A superjunction fast recovery diode, characterized in that, Also includes: Substrate; A buffer layer, wherein the buffer layer is located on the substrate; A drift layer, which is located above the buffer layer; P-type region, the P-type region being located above the drift layer; Two groups of P-islands are distributed horizontally at intervals, each group of P-islands includes multiple P-islands; in each group of P-islands, the multiple P-islands are located in the drift layer and are arranged at intervals in the longitudinal direction, the bottom of the bottommost P-island is in contact with the upper edge of the buffer layer, and the top of the topmost P-island is not in contact with the lower edge of the P-shaped area and there is a set distance between them. By setting the distance, when the device is forward-biased, hole injection between the P-type region and the top P-island is suppressed, reducing the stored charge of the drift layer. This reduces the reverse peak current Irrm, reverse recovery charge Qrr, and reverse recovery time trr of the fast recovery diode device, thereby reducing reverse recovery losses. Furthermore, the bottom P-island is in contact with the buffer layer, so that when the superjunction fast recovery diode is subjected to reverse breakdown voltage, not only is there a transverse electric field of the PN junction formed by the P-island and the drift layer acting as a bearing, but the bottom P-island and the buffer layer also mutually deplete the bearing.

6. The superjunction fast recovery diode as described in claim 5, characterized in that, In each group of P islands, the spacing between two adjacent P islands satisfies the relationship shown by the formula N1×W1=N2×W2, where N1 is the doping concentration of the drift layer region between two adjacent P islands, N2 is the doping concentration of the P island, W1 is the distance between two adjacent P islands, and W2 is the height of the P island.

7. The superjunction fast recovery diode as described in any one of claims 1 to 6, characterized in that, Also includes: An anode metal layer is located above the P-type region.

8. The superjunction fast recovery diode as described in claim 7, characterized in that, Also includes: A cathode metal layer, which is located beneath the substrate.

9. A method for manufacturing a superjunction fast recovery diode, characterized in that, The method for manufacturing a superjunction fast recovery diode as described in any one of claims 1-4 includes: A buffer layer is formed on the substrate; A drift layer is formed on top of the buffer layer; A P-type region is formed on the drift layer; The P-pillar is formed in the drift layer, wherein the P-pillar is located above the buffer layer, the bottom of the P-pillar is in contact with the upper edge of the buffer layer, and the top of the P-pillar is not in contact with the lower edge of the P-shaped region.

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