Chip system, data transmission method and related device

Abstract

The chip system, the data transmission method and the related equipment provided in the embodiments of the present application, the chip system comprises: an IO chip and a plurality of computing chips, each computing chip is configured with a corresponding chip hub, and each computing chip is connected with at least two physical interconnection ports in the IO chip through the chip hub; the chip hub comprises a splitting unit and a merging unit, the splitting unit is used for distributing the data stream sent by the computing chip to at least one physical interconnection port according to the service type; the merging unit is used for recombining or directionally forwarding the data stream received from the physical interconnection port to the computing chip, without modifying the external IO chip hardware specification, the data throughput rate and the overall transmission efficiency in the large-scale parallel computing scene are significantly improved.

Description

Technical Field

[0001] This application relates to the field of computational data processing technology, and in particular to chip systems, data transmission methods and related equipment. Background Technology

[0002] With the rapid development of high-performance computing (HPC) and artificial intelligence (AI), multi-chiplet integrated architecture has become the mainstream solution to overcome the limitations of single-wafer size and improve system computing power. Compute-die typically connects to input / output dies (IO-die) via standardized interconnect protocols (such as Universal Chiplet Interconnect Express (UCIe)) to enable cross-die data communication and external protocol access. In typical existing architectures, each compute-die usually connects to the IO-die through a single physical interconnect port. The IO-die uniformly carries various traffic flows, including die-to-die (D2D), peripheral component interconnect express (PCIe), and remote direct memory access (RDMA).

[0003] However, under the existing single-port connection architecture, the physical bandwidth between the computing chip and the IO-die is limited by the upper limit of a single physical interconnect port, making it difficult to meet the growing demand for ultra-high data throughput from massively parallel computing. In addition, since various types of service traffic (such as D2D, PCIe and RDMA) are mixed and transmitted on the same physical link, it is easy to cause physical layer resource contention and access congestion, resulting in relatively low transmission efficiency when using the existing interconnect architecture for data communication while keeping the IO-die hardware specifications unchanged. Summary of the Invention

[0004] This application provides a chip system, a data transmission method, and related equipment that can improve transmission efficiency during data communication by utilizing existing interconnect architectures while keeping the IO-die hardware specifications unchanged.

[0005] To achieve the above objectives, a first aspect of this application provides a chip system comprising:

[0006] The system includes an I / O core and multiple computing cores, each computing core being configured with a corresponding core hub, and each computing core being connected to at least two physical interconnect ports of the I / O cores through the core hub.

[0007] The core core includes a splitting unit and a merging unit. The splitting unit is used to distribute the data stream emitted by the computing core to at least one of the physical interconnect ports according to the service type.

[0008] The merging unit is used to reassemble or forward the data stream received from the physical interconnect port to the computing chip.

[0009] In some embodiments, the computing core includes at least one computing unit, and the internal unidirectional bandwidth between the computing unit and the core hub is set to be no less than the sum of the external unidirectional bandwidths of the two physical interconnect ports.

[0010] In some embodiments, the core hub is also used to accelerate data transfer between cores for symmetric memory access operations, the symmetric memory being configured to support synchronous access to multiple three-dimensional stacked memories by a single symmetric address.

[0011] To achieve the above objectives, a second aspect of this application proposes a data transmission method applied to a chip system, the chip system including I / O chips and multiple computing chips, each computing chip being connected to at least two physical interconnect ports in the I / O chips, the method comprising:

[0012] In response to a data transmission request for data to be transmitted in a transmission computing chip, and based on the target access address of the data to be transmitted, the service type is determined, wherein the transmission computing chip is one of a plurality of computing chips;

[0013] When the data to be transmitted is an outgoing data stream sent by the transmission computing chip, and the service type is an inter-chip communication service, the outgoing data stream is split into multiple sub-data streams, and the multiple sub-data streams are sent in parallel to the IO chip through at least two of the physical interconnect ports.

[0014] When the data to be transmitted is an outgoing data stream sent by the transmission computing chip, and the service type is an external protocol service, a designated port is determined from at least two of the physical interconnect ports, and the outgoing data stream is sent to the IO chip through the designated port.

[0015] In some embodiments, the inter-chip communication service includes direct-to-chip communication (D2D) service; the external protocol service includes high-speed peripheral component interconnect (PCIe) service and / or remote direct memory access (RDMA) service.

[0016] In some embodiments, the method further includes:

[0017] When the data to be transmitted is a received data stream sent to the transmission computing chip, and the service type is the inter-chip communication service, the received data stream sent by the IO chip is received in parallel through at least two of the physical interconnect ports, and the received data stream is reassembled and restored to obtain the restored data stream;

[0018] When the data to be transmitted is a received data stream sent to the transmission computing chip, and the service type is the external protocol service, a designated port is determined from at least two of the physical interconnect ports, and the received data stream sent by the IO chip is received through the designated port.

[0019] In some embodiments, determining the service type based on the target access address of the data to be transmitted includes:

[0020] The target access address is obtained by parsing the data to be transmitted;

[0021] When the address space range to which the target access address belongs is the first address space, the service type is determined to be the inter-chip communication service;

[0022] When the address space range to which the target access address belongs is the second address space, the service type is determined to be the external protocol service.

[0023] In some embodiments, determining the target access address from the target access address includes:

[0024] The header of the data to be transmitted is parsed to obtain the virtual address;

[0025] The virtual address is translated into a physical address to obtain the target access address.

[0026] In some embodiments, splitting the outgoing data stream into multiple sub-data streams and sending the multiple sub-data streams in parallel to the IO chip via at least two of the physical interconnect ports includes:

[0027] The emitted data stream is cut according to a preset splitting granularity to obtain multiple sub-data streams;

[0028] Multiple sub-data streams are alternately distributed to each transmission connection port, and the multiple sub-data streams are sent in parallel to the IO chip through the multiple transmission connection ports, wherein the transmission connection port is the physical interconnect port connected to the transmission computing chip.

[0029] In some embodiments, reconstructing and restoring the received data stream to obtain a restored data stream includes:

[0030] Obtain the sequence identifier of each data packet in the multi-path sub-data stream;

[0031] The multiple data packets are time-aligned according to the sequence identifier to obtain the restored data stream.

[0032] In some embodiments, determining the designated port from at least two of the physical interconnect ports includes:

[0033] When the service type is the high-speed peripheral component interconnect PCIe service, the first port of at least two physical interconnect ports shall be used as the designated port;

[0034] When the service type is the Remote Direct Memory Access (RDMA) service, the second port of at least two physical interconnect ports shall be used as the designated port.

[0035] In some embodiments, splitting the transmitted data stream into multiple sub-data streams further includes:

[0036] Based on the real-time bandwidth occupancy of the multiple physical interconnect ports, the amount of data allocated to each physical interconnect port's sub-data stream is dynamically adjusted.

[0037] To achieve the above objectives, a third aspect of this application provides a data transmission device integrated in the core of a chip system. The chip system includes I / O cores and multiple computing cores, each computing core being connected to at least two physical interconnect ports in the I / O cores via the core hub. The device includes:

[0038] A service type identification module is used to respond to a data transmission request for data to be transmitted in a transmission computing chip, and to determine the service type based on the target access address of the data to be transmitted, wherein the transmission computing chip is one of a plurality of computing chips;

[0039] The splitting module is connected to the service type identification module and to at least two physical interconnect ports respectively. It is used to split the data stream to be transmitted into multiple sub-data streams when the data to be transmitted is an outgoing data stream sent by the transmission computing chip and the service type is inter-chip communication service, and to send the multiple sub-data streams to the IO chip in parallel through at least two of the physical interconnect ports.

[0040] A directional routing module is used to determine a designated port from at least two physical interconnect ports and send the outgoing data stream to the IO core through the designated port when the data to be transmitted is an outgoing data stream sent by the transmission computing core and the service type is an external protocol service.

[0041] A merging module is used to reassemble or forward data streams received from the physical interconnect port to the computing chip.

[0042] To achieve the above objectives, a fourth aspect of this application provides an electronic device, the electronic device including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the data transmission method as described in the second aspect.

[0043] To achieve the above objectives, a fifth aspect of the present application provides a storage medium, which is a computer-readable storage medium storing a computer program that, when executed by a processor, implements the data transmission method described in the second aspect above.

[0044] The chip system, data transmission method, and related equipment proposed in this application include: an I / O chip and multiple computing chips. Each computing chip is configured with a corresponding chip hub, and each computing chip is connected to at least two physical interconnect ports of the I / O chips through the chip hub. The chip hub includes a splitting unit and a merging unit. The splitting unit is used to distribute the data stream sent by the computing chip to at least one physical interconnect port according to the service type. The merging unit is used to reassemble or forward the data stream received from the physical interconnect port to the computing chip. This application's embodiments break through the single-port bandwidth bottleneck at the hardware level by physically connecting each computing chip to at least two physical interconnect ports of the IO chip. Combined with the logical enhancements of the splitting and merging units in the chip's central core, the chip system provided by this application can implement differentiated routing strategies based on service type: for D2D communication services, the dual-port parallel transmission characteristic doubles the communication bandwidth between computing chips; for protocol services such as PCIe and RDMA, physical layer traffic isolation is achieved through directed routing to designated ports, effectively alleviating resource contention and congestion problems caused by mixed transmission of multiple protocol services on a single link. Therefore, without modifying the external IO chip hardware specifications, it significantly improves data throughput and overall transmission efficiency in large-scale parallel computing scenarios.

[0045] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of a typical heterogeneous chip-integrated interconnect architecture provided in an embodiment of this application.

[0047] Figure 2 This is a schematic diagram of the structural concept of a chip system provided in another embodiment of this application.

[0048] Figure 3 This is a schematic diagram of the structure of a chip system provided in another embodiment of this application.

[0049] Figure 4 This is a schematic diagram of the structure of a core core in another embodiment of this application.

[0050] Figure 5 This is a flowchart of a data transmission method provided in another embodiment of this application.

[0051] Figure 6 yes Figure 5 The flowchart for step 501.

[0052] Figure 7 yes Figure 6 The flowchart for step 601.

[0053] Figure 8 yes Figure 5 The flowchart for step 502.

[0054] Figure 9 yes Figure 5 The flowchart for step 503.

[0055] Figure 10 This is a schematic diagram of data transmission for sending a data stream, provided in another embodiment of this application.

[0056] Figure 11 This is a data receiving flowchart of a data transmission method provided in another embodiment of this application.

[0057] Figure 12 yes Figure 11 The flowchart for step 1101.

[0058] Figure 13 This is a schematic diagram of data transmission for receiving a data stream, provided in another embodiment of this application.

[0059] Figure 14 This is a flowchart of a dynamic adjustment and splitting of multiple sub-data streams provided in another embodiment of this application.

[0060] Figure 15 This is a schematic diagram of the structure of a data transmission device provided in another embodiment of this application.

[0061] Figure 16 This is a schematic diagram of the hardware structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0063] It should be noted that although functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0065] With the rapid development of high-performance computing (HPC) and artificial intelligence (AI), multi-chiplet integrated architecture has become the mainstream solution to overcome the limitations of single-wafer size and improve system computing power. Compute-die typically connects to input / output dies (IO-die) via standardized interconnect protocols (such as Universal Chiplet Interconnect Express (UCIe)) to enable cross-die data communication and external protocol access. In typical existing architectures, each compute-die usually connects to the IO-die through a single physical interconnect port. The IO-die uniformly carries various traffic flows, including die-to-die (D2D), peripheral component interconnect express (PCIe), and remote direct memory access (RDMA).

[0066] Reference Figure 1 This is a schematic diagram of a typical heterogeneous chip-integrated interconnect architecture provided in an embodiment of this application. Figure 1 As shown in the diagram, in this architecture, the core layer is an I / O die, whose integrated internal interconnect matrix acts as a traffic hub. The upper layer connects to a PCIe switch via a high-speed peripheral component interconnect (PCIe) controller and to an RDMA switch via a remote direct memory access (RDMA) controller, enabling external expansion and high-speed communication of the chip-level system. At the underlying physical connection level, the I / O die connects through multiple high-speed general purpose interconnect (UCIe) ports (such as...). Figure 1 Ports 0 to 7 shown in the diagram form point-to-point serial connections with multiple computing cores (cores 0 to 7). In this architecture, each computing core typically occupies only one physical port of the input / output core, and all traffic destined for external switches or across cores must compete for the bandwidth resources of this single physical channel.

[0067] like Figure 1 As shown in the existing single-port connection architecture, the physical bandwidth between the computing chip and the IO-die is limited by the upper limit of a single physical interconnect port, making it difficult to meet the growing demand for ultra-high data throughput from massively parallel computing. In addition, since various types of service traffic (such as D2D, PCIe and RDMA) are mixed and transmitted on the same physical link, it is easy to cause physical layer resource contention and access congestion, resulting in relatively low transmission efficiency when using the existing interconnect architecture for data communication while keeping the IO-die hardware specifications unchanged.

[0068] To improve the execution efficiency between heterogeneous computing units in a chip system, this application embodiment breaks through the single-port bandwidth bottleneck at the hardware level by physically connecting each computing chip to at least two physical interconnect ports of the IO chip. Combined with the logical enhancements of the splitting and merging units in the chip's central core, the chip system provided by this application can implement differentiated routing strategies based on service type: for D2D communication services, the dual-port parallel transmission characteristic doubles the communication bandwidth between computing chips; for protocol services such as PCIe and RDMA, physical layer traffic isolation is achieved through directed routing to designated ports, effectively alleviating resource contention and congestion problems caused by mixed transmission of multiple protocol services on a single link. Thus, without modifying the external IO chip hardware specifications, the data throughput and overall transmission efficiency in large-scale parallel computing scenarios are significantly improved.

[0069] The chip system, data transmission method, and related devices provided in the embodiments of this application will be further described below. First, the chip system will be described.

[0070] Reference Figure 2 This is a schematic diagram illustrating the structural concept of a chip system provided in an embodiment of this application. For example... Figure 2 As shown, in the concept of this application, by introducing multiple times the input / output chips (such as...) Figure 2 The input / output cores 0 and 1 shown in the diagram change the traditional single IO core service for all computational cores (such as...). Figure 1 The diagram illustrates a limitation where one input / output core serves eight cores. Each input / output core independently serves four compute cores, meaning two input / output cores serve eight cores. This redundant configuration of physical resources at the system level provides the hardware foundation for each compute core to connect to more physical interconnect ports. Under this architecture, each compute core can overcome the bandwidth bottleneck of a single-port connection, establishing double the physical links with its connected input / output cores. This provides core topology support for subsequent service-aware routing and bandwidth doubling achieved through the core core hub.

[0071] Based on such Figure 2 The technical concept shown is referenced. Figure 3 This is a schematic diagram of a chip system provided in an embodiment of this application. Figure 3 As shown, the chip system provided in this application includes I / O chips (input / output chips) and multiple computing chips (such as... Figure 3 The diagram shows die 0 to die 3. The I / O die is primarily responsible for handling communication protocols between the chip system and external devices (such as PCIe and RDMA protocols) and providing a unified interconnect matrix; the compute die is the unit that performs core data processing and logical operations. Each compute die is configured with a corresponding die hub, which serves as a crucial relay control hub between the internal logic of the compute die and the external physical interface.

[0072] Understandably, to adapt to different process technologies, packaging techniques, and the comprehensive design requirements of chip power consumption, performance, and area, the physical architecture of the chip core and computing chip can have a variety of flexible implementation methods. Specifically, the chip core can be fully integrated inside the computing chip as a native hardware module of its on-chip system to achieve the lowest communication latency between the computing unit and the core; or, the chip core can adopt a partially integrated form, for example, keeping the high-frequency logic control part inside the computing chip, while stripping the buffer circuits involving the underlying physical layer or partially split and merged units; furthermore, the chip core can also be an independent logic unit (such as a dedicated router or core chip), achieving a very short-distance tight coupling connection with the computing chip on the substrate through advanced packaging technologies (such as 2.5D intermediate layer or 3D vertical stacking packaging). It should be understood that, regardless of the physical form used, the computing chip can logically coordinate with the chip hub via a communication connection. The chip hub is responsible for connecting to at least two physical interconnect ports of the IO chip to perform splitting and parallel or directed routing of outgoing data streams, as well as reassembling or directed forwarding of received data streams. These equivalent substitutions of physical topologies all achieve the core objective of this application—to increase the bandwidth of heterogeneous interconnects—and fall within the protection scope of this application.

[0073] Each computing core is connected to at least two physical interconnect ports in the I / O cores via a core hub. Specifically, combining Figure 3 As can be seen, the IO core contains multiple high-speed general-purpose core interconnect ports (such as ports 0 to 7, i.e., physical interconnect ports). Taking the computing core 0 as an example, it is no longer limited to a single-port connection under the traditional architecture, but is physically connected to both interconnect port 0 and interconnect port 1 of the IO core. This multi-port connected hardware topology provides the computing core with a foundation for a significantly increased physical link bandwidth.

[0074] In some embodiments, the chip hub includes a splitting unit and a merging unit at the microarchitecture level. The splitting unit distributes data streams emitted by computing chips to at least one physical interconnect port based on the service type. Here, "service type" refers to the communication intent or protocol category corresponding to the data stream, such as D2D services for inter-chip communication, or PCIe and RDMA services for accessing external devices. The splitting unit has service awareness and intelligent traffic splitting capabilities. When sending a data stream, the splitting unit first parses the service type of the data. For example, when identifying a D2D service that requires maximum bandwidth, the splitting unit can split the data stream into multiple parts and transmit them in parallel to the two physical interconnect ports connected to it (such as port 0 and port 1) for coordinated transmission; while when identifying specific protocol traffic (such as PCIe services), the splitting unit will transmit it completely to at least one designated physical interconnect port (such as only using port 0), thereby implementing differentiated routing based on service characteristics at the hardware transport layer.

[0075] Additionally, the merging unit is used to reassemble or forward data streams received from physical interconnect ports to the computing chip. The merging unit, as the data stream enters the receiving console of the computing chip, is responsible for parsing and post-processing data from multiple physical interconnect ports (such as port 0 and port 1), including reassembly and forwarding.

[0076] "Reassembly" refers to the ability of the merging unit to reassemble out-of-order sub-data packets into the original complete data stream when it receives multiple sub-data packets of the same service (such as D2D service) that have been split and transmitted from two physical interconnect ports, based on the timing information or sequence identifier carried within the data packets. This reassembly is then submitted to the internal computing unit of the computing chip. "Directed forwarding," on the other hand, refers to the ability of the merging unit to directly direct the data stream to the corresponding protocol processing module within the computing chip when it receives an independent data stream with a clear protocol label (such as RDMA data from port 1) from a specific physical interconnect port, without performing a splitting and restoration operation.

[0077] The chip system provided in this application, without changing the existing IO chip hardware specifications and number of interfaces, enables a single computing chip to physically connect to two or more interconnect ports through system topology reconstruction, fundamentally breaking through the traditional single-port physical bandwidth limit. Furthermore, in conjunction with the functional components (i.e., splitting and merging units) in the chip's central core, it can intelligently identify service types and perform splitting and parallel transmission or protocol-oriented isolation based on underlying physical link redundancy. This not only doubles the data interaction bandwidth between computing chips but also effectively avoids congestion and conflicts of various protocol traffic on a single physical link, significantly improving the data throughput and communication efficiency of the entire high-performance computing chip system.

[0078] Reference Figure 4 This is a schematic diagram of the structure of a core core in an embodiment of this application. Figure 4 As shown, the computing chip includes at least one computing unit, such as Figure 4 The system comprises computing units 0, 1, 2, and 3. These computing units, as the physical hardware within the computing core, perform core processing and logical operations, and are responsible for initiating low-level data access requests and receiving processed massive amounts of data. To achieve efficient data interaction with external components, each computing unit establishes a physical connection with the core's central hub via an internal high-speed data bus. The core's central hub acts as a global intermediary module, uniformly managing and scheduling the low-level data flow entering and leaving the computing units.

[0079] In addition, such as Figure 4 As shown, for each computing unit (e.g., computing unit 0), the core core is equipped with a corresponding logic processing submodule (e.g., ...). Figure 4 The box marked "0" connected to computing unit 0 in the middle (the part marked "0") is the logic processing submodule, which specifically includes a splitting unit and a merging unit. The input of the splitting unit is connected to the data transmission bus of the computing unit, and its output extends to two physical interconnect ports (such as the core hub and the input / output cores) respectively. Figure 4 (Ports 0 and 1 are located at the top of the core core). Similarly, the input of the merging unit is connected to the receiving side of these two physical interconnect ports, and its output is converged to the data receiving bus of the computing unit. In addition, the core core core also integrates intra-core and aggregated communication units, which also maintain specific link connections with the underlying computing units and the top-level ports to handle collaborative computing and specific communication needs within the core.

[0080] To effectively support efficient data stream splitting and parallel transmission at the physical level, the internal unidirectional bandwidth between the computing unit and the core hub is set to be no less than the sum of the external unidirectional bandwidths of the two physical interconnect ports. For example... Figure 4 As shown, "internal unidirectional bandwidth" is represented as Figure 4 The thicker solid lines (i.e., "full bandwidth" links) represent the high-throughput data channels established between computing units and the core processing hub; "external unidirectional bandwidth" is reflected in... Figure 4 The thinner solid lines (i.e., links labeled "half-bandwidth") represent the external interface communication capability between a single physical interconnect port and the input / output chip; therefore, in this embodiment, the transmission capability of the internal data bus must be greater than or equal to the sum of the transmission capabilities of the two external interfaces. By designing the internal "full bandwidth" to be sufficient to cover the sum of the two external "half-bandwidths," this solution ensures from the outset that the computing unit has sufficient data throughput to transmit data to the two external physical interconnect ports.

[0081] To further meet the demands of massive memory access bandwidth in large-scale parallel computing, the chip hub is also used to accelerate data transfer between chips during symmetric memory access operations. Specifically, the symmetric memory configuration in the chip system supports synchronous access to multiple three-dimensional stacked memories (such as high-bandwidth memory, HBM) distributed across different computing chips via a single symmetric address. When a computing unit within a computing chip initiates a read / write request for this single symmetric address, it requires mobilizing multiple storage resources across chips, triggering instantaneous high-concurrency, high-throughput inter-chip communication. At this time, the splitting unit within the chip hub can accurately identify the service characteristics of the symmetric memory access operation and quickly slice the resulting massive parallel data stream, using at least two physical interconnect ports (such as dual UCIe ports) for load-balanced parallel transmission; while at the receiving end, the merging unit performs strict timing alignment and seamless reassembly of data packets arriving from multiple physical channels. By using this dual-port splitting, parallelizing, merging, and recombining mechanism at the core core level, the single-port bandwidth bottleneck when synchronously accessing multiple 3D stacked memories across cores is completely broken from the physical hardware link. This greatly accelerates the data transfer rate of symmetric memory access operations, ensuring not only high consistency of memory data among multiple cores but also fully releasing the performance of the 3D stacked memory.

[0082] The chip system provided in this application establishes a strict physical matching relationship of "one full bandwidth corresponding to two half bandwidths" between the computing unit and the physical interconnect port within the chip core. This ensures that the underlying hardware of the chip system has the channel capability to support the splitting of high-concurrency data streams into two and full-load parallel transmission during data communication. This architecture, which combines internal bandwidth redundancy with external dual ports, breaks through the "barrel effect" bottleneck caused by the traditional single physical port. It also ensures that the split unit will not be limited by internal bus congestion when performing traffic sharing and parallel transmission. Thus, without any modification to the existing input / output chip hardware specifications, it maximizes the underlying communication potential of the computing chip and achieves a leap in the overall data throughput and parallel processing efficiency of the system.

[0083] Based on the chip system provided above, the data transmission method applied to this chip system will be further described below. (Refer to...) Figure 5 This is an optional flowchart of the data transmission method provided in the embodiments of this application. Figure 5 The method may include, but is not limited to, steps 501 to 503. It is also understood that this embodiment... Figure 5 The order of steps 501 to 503 is not specifically limited. The order of steps can be adjusted or some steps can be reduced or added according to actual needs.

[0084] Step 501: In response to the data transmission request of the data to be transmitted in the transmission computing chip, and determine the service type according to the target access address of the data to be transmitted, the transmission computing chip is one of multiple computing chips.

[0085] Step 501 is described in detail below.

[0086] In step 501 of some embodiments, the first operation performed is to respond to a data transmission request for the data to be transmitted from the transmission computing chip and determine the service type based on the target access address of the data to be transmitted. In this process, the "transmission computing chip" refers to a computing chip that actively initiates or passively receives data communication in the current time slot. When any computing unit in the computing chip performs active data transmission or passive data reception, it generates a "data transmission request" containing the target address and control instructions and outputs it to the chip central hub in the computing chip.

[0087] This data transmission request not only encapsulates the high-throughput payload (i.e., the data to be transmitted) that the computing unit actually needs to send out, but also includes control metadata (i.e., the destination access address) that indicates the data flow direction and protocol characteristics. During this data interaction, the destination access address typically exists in the form of a packet header, which carries destination information generated by upper-layer software or processing logic, such as virtual addresses, destination IDs, or specific protocol markers—key routing parameters.

[0088] When the core-core hub receives the data transmission request, it uses it as a trigger to initiate the underlying data scheduling logic. It extracts and parses the virtual address in the header, maps it to the underlying physical address, and then uses this as the target access address to accurately identify the service type of the current data stream (e.g., whether it belongs to high-bandwidth inter-core D2D communication, or high-speed peripheral component interconnection PCIe or remote direct memory access RDMA communication using a specific protocol). This request generation and parsing process provides an absolutely reliable underlying decision-making and scheduling foundation for the subsequent splitting units within the core-core hub to accurately execute dual-port splitting parallel transmission or single-port directed isolated transmission.

[0089] It is understood that the service types in this application include inter-chip communication services and external protocol services. Inter-chip communication services include die-to-die (D2D) communication between computing chips. D2D services primarily support collaborative computing and massive data sharing between computing chips, requiring extremely high data throughput. Furthermore, external protocol services include high-speed peripheral component interconnect (PCIe) services and / or remote direct memory access (RDMA) services. These external protocol services involve high-speed communication between computing chips and external graphics cards, solid-state storage, or cross-node networks, and have stringent requirements for packet timing, protocol structure integrity, and low latency of the transmission channel.

[0090] The following section will describe in more detail how to determine the business type.

[0091] Reference Figure 6 The service type is determined based on the target access address of the data to be transmitted, including the following steps 601 to 603.

[0092] Step 601: Parse the target access address from the data to be transmitted.

[0093] Step 601 will be described in detail below.

[0094] In step 601 of some embodiments, when determining the service type, the first step is to determine the target access address from the data to be transmitted. When the computing unit inside the computing core initiates a data communication request for the data to be transmitted, it generates data packets containing communication control information. The "target access address" refers to the header portion of these data packets. The hardware logic module inside the core parses the headers of these data packets to extract the destination memory address that the data packet is expected to reach, i.e., the "target access address". In actual low-level hardware addressing operations, since the computing unit often issues a virtual address from a software perspective, this also involves converting the virtual address into a physical address that the system bus can directly recognize through a hardware address translation unit. The converted physical address is then used as the final target access address for comparison to ensure the accuracy of the routing decision, as described below.

[0095] Reference Figure 7 The target access address is obtained by parsing the data to be transmitted, including the following steps 701 to 702.

[0096] Step 701: Parse the header of the data to be transmitted to obtain the virtual address.

[0097] Step 702: Perform physical address translation on the virtual address to obtain the target access address.

[0098] Steps 701 to 702 are described in detail below.

[0099] In step 701 of some embodiments, after acquiring the data to be transmitted, the first operation performed is to parse the header of the data to be transmitted to obtain a virtual address. Specifically, the hardware parsing logic inside the core core performs "header parsing" on the beginning part (i.e., the header) of the incoming data packet (i.e., the data to be transmitted) to extract the data transmission destination information indicated by the software layer. In modern computer and chip architectures, operating systems or upper-level applications allocate and use a contiguous logical address space to simplify memory management and ensure data security between processes. Therefore, the destination address directly parsed from the header is the "virtual address." This virtual address is a logical marker generated by the processor when executing program instructions. It provides a unified memory view for the software but does not represent the actual physical connection location of the underlying hardware memory or external devices.

[0100] In step 702 of some embodiments, a further step is to perform physical address translation on the virtual address to obtain the target access address. Since the interconnect matrix and routing nodes at the bottom layer of the multi-chip architecture (such as various physical interconnect ports, external PCIe switches, or RDMA controllers) cannot directly identify and route the virtual logical addresses of the software layer, they must rely on the real hardware address space for precise physical path guidance. Therefore, the chip hub or its cooperating memory management unit (such as a Memory Management Unit (MMU) or Input / Output Memory Management Unit (IOMMU)) will map and convert the previously extracted virtual address into the underlying physical address according to the address mapping table pre-established by the system. This "physical address" refers to the unique, real hardware absolute address in the chip system corresponding to the actual memory storage unit, cross-chip interconnect node, or peripheral component register. The physical address obtained after this conversion operation is determined as the "target access address" subsequently used to compare the address space range and determine the service type.

[0101] Through steps 701 to 702 above, a mechanism for resolving and converting virtual addresses from the software layer to physical addresses from the hardware layer is introduced in the early stages of data transmission and routing determination at the core node hub. This achieves deep decoupling between upper-layer software applications and the complex physical topology of the underlying multi-core structure. As a result, when the upper-layer software on the computing unit initiates service transmission, it does not need to be aware of whether the current system adopts a dual-port connection or a multi-core architecture. It can simply perform normal data reading and writing according to the conventional virtual address space. The underlying core node hub, by obtaining the converted absolute physical address, can match it with the underlying hardware address space range with extremely high accuracy. This completely eliminates the underlying routing misjudgment problem that may be caused by dynamic allocation of virtual addresses or memory fragmentation. This provides absolutely reliable underlying data support for the subsequent system to accurately identify D2D, PCIe, or RDMA service types and perform corresponding parallel splitting or directed routing.

[0102] Step 602: When the address space range corresponding to the target access address is the first address space, determine the service type as inter-chip communication service.

[0103] Step 603: When the address space range corresponding to the target access address is the second address space, determine the service type as an external protocol service.

[0104] Steps 602 to 603 are described in detail below.

[0105] In step 602 of some embodiments, when it is determined that the address space range corresponding to the target access address is the first address space, the service type is determined to be inter-core communication service. It can be understood that in the global memory mapping architecture of a multi-core system, the overall physical address space of the system is pre-divided into multiple continuous or non-contiguous regions with different functions. Therefore, the "first address space" is a memory address segment specifically allocated in the system firmware or hardware addressing logic for internal interconnection and data sharing between various computing cores.

[0106] Based on this, once the address decoding logic of the core node detects that the extracted target access address falls within the range of this first address space, it can accurately determine within a very short hardware clock cycle that the current data flow is for high-speed data interaction between cores (Die-to-Die, D2D). Since D2D communication has extremely high data throughput requirements and is an internally closed communication, this accurate service type determination result will directly trigger the core node to call the splitting unit to execute the dual-port parallel flow splitting mechanism in subsequent transmissions.

[0107] In step 603 of some embodiments, when it is determined that the address space range corresponding to the target access address is the second address space, the system will determine the service type as an external protocol service. In contrast to the first address space, the "second address space" is specifically mapped in the system's memory mapping table to various external physical devices or network interfaces connected to the input / output (IO) chips. Specifically, high-speed peripheral component interconnect (PCIe) services involve control and data communication with standard PCIe peripherals such as external graphics cards, network cards, or high-speed solid-state storage, while remote direct memory access (RDMA) services involve cross-node, low-latency direct network memory read and write operations.

[0108] When the target access address hits the second address space used for external expansion and network communication, the core hub can determine that the data flow belongs to an external protocol service with extremely high requirements for protocol integrity and channel independence. Therefore, in subsequent transmissions, a directional routing strategy is adopted to skip the splitting logic and directly perform physical port isolation (e.g., PCIe goes through the first port, RDMA goes through the second port) to ensure the timing accuracy and transmission compliance of external protocol data.

[0109] Through steps 601 to 603 above, a "protocol-aware" mechanism with zero software overhead and extremely low latency is implemented by directly using the matching relationship between the target access address and the preset address space range at the underlying hardware level to determine the service type. This pure hardware address space addressing and classification method not only ensures that the chip hub can accurately and in real time distinguish between D2D internal communication and external PCIe / RDMA communication in massive high-speed data streams, but also provides an absolutely reliable decision-making basis for subsequent differentiated routing (i.e., D2D splitting and parallelization and PCIe / RDMA specific port isolation). This enables the entire chip system to automatically and efficiently perform cross-chip and cross-protocol data scheduling under high load, maximizing the utilization of multi-port hardware bandwidth resources.

[0110] Step 502: When the data to be transmitted is an outgoing data stream sent by the transmission computing chip and the service type is inter-chip communication service, the outgoing data stream is split into multiple sub-data streams and the multiple sub-data streams are sent to the IO chip in parallel through at least two physical interconnect ports.

[0111] Step 502 is described in detail below.

[0112] In step 502 of some embodiments, when the identification result indicates that the data to be transmitted is an outgoing data stream sent by the transmission computing chip and the service type is inter-chip communication service, the outgoing data stream will be split into multiple sub-data streams by the splitting unit, and the multiple sub-data streams will be sent to the IO chip in parallel through at least two physical interconnect ports. As mentioned above, the "inter-chip communication service" in this application corresponds to the inter-chip communication service (D2D) with extremely high bandwidth requirements. In this scenario, in order to overcome the bandwidth bottleneck of a single physical link, the splitting logic within the chip hub will be activated. At this time, the continuous original data stream will be cut according to a preset granularity (e.g., by packet or by byte) to generate two or more load-balanced "sub-data streams". Subsequently, these sub-data streams will be simultaneously scheduled to two or more physical interconnect ports (e.g., UCIe Port 0 and UCIe Port 1) connected to the computing chip for synchronous transmission, as described below.

[0113] Reference Figure 8 The process involves splitting the emitted data stream into multiple sub-data streams and sending the multiple sub-data streams in parallel to the IO chip via at least two physical interconnect ports, including steps 801 to 802.

[0114] Step 801: Cut the outgoing data stream according to the preset splitting granularity to obtain multiple multi-path sub-data streams.

[0115] Step 802: Alternately distribute multiple sub-data streams to each transmission connection port, and send the multiple sub-data streams in parallel to the IO chip through multiple transmission connection ports. The transmission connection port is the physical interconnect port connected to the transmission computing chip.

[0116] Steps 801 to 802 are described in detail below.

[0117] In step 801 of some embodiments, when synchronously sending data, the first operation performed is to cut the transmitted data stream according to a preset splitting granularity to obtain multiple multi-path sub-data streams. Specifically, when the core core determines that the current service type requires high-bandwidth parallel transmission using multiple ports (e.g., internal communication between core cores), its internal splitting unit will perform splitting processing on the high-speed and continuous "transmitted data stream" generated by the upper-layer computing unit.

[0118] Understandably, "preset splitting granularity" refers to the data segmentation unit pre-defined during the system's underlying hardware design or initial configuration. This could be based on a specific number of bytes (e.g., 64 bytes or 512 bits per clock cycle), a specific bit width, or a single standard data packet. The splitting unit, according to this defined granularity, truncates the massive data stream originally transmitted within a single channel, "cutting" it into multiple uniformly sized, independent, and logically continuous data slices. These slices constitute the "multiple sub-data streams" subsequently used for independent transmission across multiple physical channels. By setting a fixed and uniform splitting granularity, not only is the underlying hardware's segmentation logic greatly simplified, but the uniformity of the split data is also ensured, providing a standardized data foundation for subsequent timing alignment and seamless reassembly at the receiving end.

[0119] In step 802 of some embodiments, a further step is to alternately distribute multiple sub-data streams to each transmission connection port, and send the multiple sub-data streams in parallel to the IO core through multiple transmission connection ports. The transmission connection ports are physical interconnect ports connected to the transmission computing core. After the splitting unit completes the data segmentation, in order to make full and balanced use of the physical layer hardware link resources, a polling or uniform mapping mechanism is used to evenly distribute (i.e., "alternately distribute") the obtained multiple sub-data streams to different output channels.

[0120] Understandably, the "transmission connection port" refers to a high-speed interconnect port (such as a UCIe port) that connects the computing chip directly to the IO chip via a chip hub. For example, if the current transmission computing chip has two physical interconnect ports, the splitting unit will allocate the first sub-data stream to the first transmission connection port, the second to the second, the third back to the first port, and so on. Ultimately, these alternately allocated sub-data streams will be simultaneously output (i.e., "parallel transmission") through these "multiple transmission connection ports" within the same time window, thus merging into the IO chip at high speed across physical boundaries.

[0121] Through steps 801 to 802 above, by introducing a microarchitectural design of "preset splitting granularity" and "alternating allocation," a purely hardware-driven data load balancing mechanism is implemented at the data sending end (i.e., inside the computing chip). This mechanism allows the massive traffic data, originally limited by the bandwidth limit of a single interconnect port, to be evenly distributed across at least two physical interconnect ports for parallel transmission. This not only doubles the actual peak bandwidth of the computing chip's outward communication at the physical level, completely breaking the "barrel effect" of transmission caused by a single port of the IO chip, but also makes this even splitting and alternating transmission process completely transparent to the upper-layer computing unit. Therefore, the data transmission method provided in this application can greatly improve the cross-chip communication throughput in large-scale parallel computing scenarios without modifying the existing IO chip hardware specifications, at a very low logical latency cost.

[0122] Step 503: When the data to be transmitted is an outgoing data stream sent by the transmission computing chip and the service type is an external protocol service, determine the designated port from at least two physical interconnect ports and send the outgoing data stream to the IO chip through the designated port.

[0123] Step 503 will be described in detail below.

[0124] In step 503 of some embodiments, when the identification result indicates that the data to be transmitted is an outgoing data stream originating from the transmission computing chip and the service type is an external protocol service, directed routing logic is executed to determine a designated port from at least two physical interconnect ports, and the outgoing data stream is sent to the IO chip through the designated port. As mentioned above, "external protocol service" refers to services with high requirements for protocol consistency or physical isolation, such as high-speed peripheral component interconnect (PCIe) services or remote direct memory access (RDMA) services. In this case, the chip hub no longer splits the data, but locks a specific physical interconnect port as the "designated port" according to a preset port mapping table or real-time configuration. The data to be transmitted is then transmitted completely and exclusively through the designated port to the IO chip. This processing method ensures that data streams of different protocols do not interfere with each other at the physical layer, meeting the strict requirements of specific services for transmission path determinism and protocol integrity.

[0125] The following section will describe in more detail how to determine the specified port.

[0126] Reference Figure 9 Determining a designated port from at least two physical interconnect ports includes the following steps 901 to 902.

[0127] Step 901: When the service type is high-speed peripheral component interconnect PCIe service, the first port of at least two physical interconnect ports shall be designated as the designated port.

[0128] Step 902: When the service type is Remote Direct Memory Access (RDMA) service, the second port of at least two physical interconnect ports shall be designated as the specified port.

[0129] Steps 901 to 902 are described in detail below.

[0130] In step 901 of some embodiments, when determining the designated port, the first step is to designate the first port among at least two physical interconnect ports as the designated port when the service type is High-Speed ​​Peripheral Component Interconnect (PCIe) service. During this process, the routing logic of the chip core identifies that the current data flow belongs to "High-Speed ​​Peripheral Component Interconnect (PCIe) service," which represents high-speed serial communication protocol data between the computing chip and external peripherals such as graphics processing units (GPUs), solid-state drives (SSDs), or network interface cards (NICs).

[0131] Because the PCIe protocol has strict requirements on packet transmission order, latency jitter, and transaction layer integrity, this application adopts a static or dynamic binding strategy, marking a specific port physically connected to the IO core (i.e., the "first port," such as UCIe Port 0 in the physical topology) as a dedicated PCIe channel. Once the service type is determined, the splitting unit does not need to split the packets; it directly directs all packets belonging to this PCIe service to the "first port" intact, making it the "designated port" for this transmission. This ensures that the PCIe data stream can sequentially reach the IO core through a single physical path and be forwarded to the external PCIe switch.

[0132] In step 902 of some embodiments, the opposite is performed when the service type is Remote Direct Memory Access (RDMA) service, the second port of at least two physical interconnect ports is designated as the designated port. Similar to PCIe services, when the core hub recognizes that the current data flow is for cross-node "Remote Direct Memory Access (RDMA) service" (i.e., high-throughput, low-latency network communication that bypasses the operating system kernel to directly access remote memory), another independent routing rule will be activated. At this time, the scheme of this application locks another port that is physically different from the first port (i.e., the "second port", such as UCIe Port 1 in the physical topology) as the "designated port" for this service.

[0133] Since RDMA services are typically extremely sensitive to network congestion and packet loss, by forcibly mapping them to the second port, the solution in this application opens a physically dedicated channel for RDMA traffic at the exit of the computing chip. This allows RDMA data streams to be sent independently and unimpeded to the IO chip through the second port, regardless of how high the PCIe load is on the first port, and then connected to the external RDMA network.

[0134] Through steps 901 to 902 above, by mapping different external protocol services (PCIe and RDMA) to different physical interconnect ports (the first port and the second port), the solution of this application achieves "protocol isolation" at the physical layer of the chip system. This physical isolation mechanism completely eliminates resource contention and mutual interference between two very different protocol traffic streams on a single physical link. For example, it prevents sudden large PCIe data block transmissions from blocking low-latency RDMA requests. At the same time, by specifying a single port for transmission instead of splitting the transmission, the strict ordering of PCIe and RDMA protocol data packets is guaranteed, avoiding the additional logical overhead and potential timing risks caused by splitting and reassembling. Thus, while improving bandwidth utilization, it ensures high reliability and deterministic latency for the system's external communication.

[0135] Furthermore, in some embodiments, in order to further overcome the limitations of purely static binding and improve the flexibility of data transmission, the splitting unit inside the core core hub integrates a traffic monitoring and arbitration module to realize dynamic bandwidth borrowing under sudden load conditions, as described below.

[0136] First, during the real-time monitoring and status assessment phase, the system by default statically maps the first service (such as PCIe) to the first port and the second service (such as RDMA) to the second port. During operation, the traffic monitoring and arbitration module within the splitting unit polls the transmit queue depth of both the first and second ports in real time at a fixed clock cycle, as well as the flow control credit points received from the peer. This assessment process aims to accurately determine the current physical layer congestion level and available transmit margin for each physical interconnect port.

[0137] As can be understood, the send queue depth refers to the total number of data packets or data blocks currently being queued and waiting to be sent in the internal buffer of a specific physical interconnect port. This metric reflects the transmission load and congestion level of that physical port at the current moment. The larger the queue depth value, the more severe the data backlog on that link.

[0138] Flow control credit points are a data transmission permission mechanism based on the available capacity of the receiver's buffer. They represent the amount of data the receiver can safely receive without buffer overflow. Before sending data through a physical port each time, the sender must check and consume the corresponding credit points. When the credit points are exhausted, transmission must be paused, thus effectively preventing data overwriting and packet loss at the underlying hardware level.

[0139] Secondly, during the triggering of the bypass and identification encapsulation phase, when a sudden surge in PCIe traffic occurs on the service side, causing the sending queue depth of the first port to exceed the warning threshold, and the traffic monitoring module detects that the credit score of the second port (such as the dedicated port corresponding to RDMA) is sufficient (i.e., it is lightly loaded or idle), the arbitration logic of the splitting unit will dynamically trigger the "bandwidth borrowing" mode. In this mode, the splitting unit will intercept some PCIe data packets that should be queued for sending to the first port, insert a specific "bypass identifier" into their physical layer header, and then route these PCIe data packets with the identifier to the idle second port for transmission. This allows high-priority or congested services to temporarily utilize idle physical bandwidth, maximizing the overall system throughput.

[0140] Finally, during the receiver identification and fault escape phase, when a data packet with a "passage identifier" arrives at the receiver through the second port, the receiver's merging unit will first identify the underlying identifier, thereby ignoring the physical port attribute it entered, forcibly redirecting it and forwarding it to the correct PCIe protocol processing logic.

[0141] Furthermore, as a redundancy guarantee mechanism for this process, if the traffic monitoring module detects a physical layer link disconnection or an unrecoverable hardware verification error on the first port, the system will immediately activate the "fault escape" mechanism, update the internal hardware routing table, and forcibly and seamlessly switch all data originally assigned to the first port to the intact second port for degraded transmission. Through the above dynamic borrowing and escape process, the system significantly improves the elastic bandwidth utilization of interconnect links and the flexible utilization capability at the chip level while ensuring protocol isolation.

[0142] Reference Figure 10 This is a schematic diagram of data transmission for sending a data stream, provided in an embodiment of this application. For example... Figure 10 The diagram illustrates the principle behind how, when a computing chip transmits data, the splitting unit within the chip's central processing unit performs differentiated routing and data distribution for different service types. For example... Figure 10The diagram, from left to right, illustrates the data flow at the sending end in three different business scenarios: computing cores sending data to PCIe (PCIe), computing cores sending data to Remote Direct Memory Access (RDMA), and computing cores sending data to other computing cores (i.e., D2D communication between cores). In all three scenarios, the underlying data to be transmitted is initiated by the underlying computing unit and flows upwards to the splitting unit in the core hub for protocol awareness and path scheduling.

[0143] Specifically, such as Figure 10 As shown in the scenario on the left, "Computational Chip Sending Data to High-Speed ​​Peripheral Component Interconnect (PCIe)," when the splitting unit identifies that the data stream sent by the computing unit belongs to PCIe service, it does not execute its internal splitting logic. Instead, the splitting unit routes the complete data stream to a specific single physical interconnect port (e.g., PCIe). Figure 10 The data is transmitted via port 0 (identified in the diagram). After the transmitted data stream enters the input / output chip through port 0, it is further forwarded to the external PCIe component.

[0144] like Figure 10 As shown in the middle scenario of "sending computing chips to remote direct memory access (RDMA)," when the service type is identified as an RDMA service, the splitting unit also maintains the integrity of the original data stream and routes it to another independent physical channel (such as...). Figure 10 The data (port 1) is then forwarded in the input / output chip to the external RDMA network. These two directional transmission mechanisms together achieve strict isolation of traffic from different protocols at the physical port level, avoiding resource contention and timing interference between protocols.

[0145] like Figure 10 As shown in the concurrent transmission scenario of "computing core to computing core" on the right, when the splitting unit determines that the current service is inter-core communication (D2D) requiring ultra-high throughput support, its internal hardware splitting logic is activated, splitting the high-bandwidth data stream reported by the computing unit into two sub-data streams. Subsequently, these two sub-data streams are mapped and simultaneously allocated to port 0 and port 1, respectively, and sent synchronously and in parallel to the input and output cores using the aggregated link of the two physical interconnect ports, and finally guided to the target computing core.

[0146] like Figure 10 The data distribution principle shown in the diagram demonstrates that, through the splitting unit within the core, single-port isolated directional transmission can be performed for specific external protocol services such as PCIe and RDMA, while dual-port splitting and parallel transmission can be performed for internal interconnection services such as D2D, without changing the underlying hardware link. This design reuses physical port resources, ensuring both the stability and determinism of external protocol communication, and successfully doubling the interconnection bandwidth between computing cores through the parallel mechanism.

[0147] Through steps 501 to 503 above, by accurately identifying the service type at the beginning of data transmission and dynamically selecting either "split parallel" or "directed routing" transmission strategies accordingly, intelligent allocation of bandwidth resources is successfully achieved at the underlying hardware architecture. For high-throughput computing services, parallel transmission unlocks the physical potential of multiple ports, doubling the bandwidth. For sensitive protocol services, directed transmission achieves physical isolation, avoiding resource contention and congestion. This design significantly improves the overall data throughput and communication efficiency of the chip system without increasing the cost of external I / O chip hardware.

[0148] In addition, refer to Figure 11 The data transmission method provided in this application also includes steps 1101 to 1102.

[0149] Step 1101: When the data to be transmitted is the received data stream sent to the transmission computing chip, and the service type is inter-chip communication service, the received data stream sent by the IO chip is received in parallel through at least two physical interconnect ports, and the received data stream is reassembled and restored to obtain the restored data stream.

[0150] Step 1101 will be described in detail below.

[0151] In step 1101 of some embodiments, the system performs the following operation: when the data to be transmitted is a received data stream sent to the transmission computing chip, and the service type is inter-chip communication service, it receives the received data stream sent by the IO chip in parallel through at least two physical interconnect ports, and reassembles and restores the received data stream to obtain a restored data stream. In this step, the merging unit in the chip hub is in working state and is responsible for processing the data entering the computing chip. When the received data is identified as "inter-chip communication service" (usually referring to services requiring high bandwidth such as inter-chip D2D communication), it means that the data stream has been split at the sending end and sent through multiple paths. Therefore, the chip hub will simultaneously activate "at least two physical interconnect ports" (e.g., UCIe port 0 and port 1) connected to it, and listen in real time and capture the sub-data streams from the IO chip in parallel. Since the difference in physical paths may cause inconsistent data arrival times (i.e., out-of-order), these sub-data packets are reassembled and restored to the original, logically continuous complete data stream before splitting (i.e., "restored data stream"), and then submitted to the internal computing unit for processing. The following will describe in more detail how the received data stream is reassembled and restored.

[0152] Reference Figure 12 The received data stream is reassembled and restored to obtain a restored data stream, including the following steps 1201 to 1202.

[0153] Step 1201: Obtain the sequence identifier of each data packet in the multi-path sub-data stream.

[0154] Step 1202: Perform time-series alignment processing on multiple data packets according to the sequence identifier to obtain the restored data stream.

[0155] Steps 1201 to 1202 are described in detail below.

[0156] In step 1201 of some embodiments, during data reconstruction, the first step is to obtain the sequence identifier of each data packet in the multiple sub-data streams. When the merging unit in the core hub of the receiving end is in operation, it will concurrently receive data that has been split and sent by the other end from at least two physical interconnect ports (e.g., the first port and the second port).

[0157] Because these data are transmitted through multiple different links at the physical layer, minute differences in signal propagation delays or port processing states can cause originally continuous data to arrive at the receiving end with temporal differences, forming "multi-path sub-data streams" containing out-of-order packets. To accurately identify the original order of these packets, the merging unit's hardware logic parses each incoming "data packet." This "sequence identifier" refers to a globally unique number or sequence label attached to the header or specific control field of each data packet during data splitting at the sending end. This identifier accurately records the precise position or temporal order of the data packet within the original complete data stream. By extracting this identifier, the merging unit can determine the original arrangement logic of each discrete data packet.

[0158] In step 1202 of some embodiments, a further step is to perform time-series alignment processing on multiple data packets based on sequence identifiers to obtain a restored data stream. After extracting the sequence identifiers of each data packet, the reassembly control logic within the merging unit begins to operate. It can be understood that "time-series alignment processing" means no longer relying on the absolute time order of data packets arriving at the physical ports, but strictly following the logical order of the obtained sequence identifiers to reorder and concatenate multiple out-of-order data packets temporarily stored in the buffer. For example, if a data packet from port 1 (identified as sequence number 2) arrives before a data packet from port 0 (identified as sequence number 1), it is suspended and waited until sequence number 1 arrives and is placed at the head of the queue, after which sequence number 2 is concatenated immediately after it. Through this precise sorting and seamless concatenation based on sequence identifiers, the independent sub-data streams originally scattered across multiple physical links are merged back into a logically continuous high-speed data stream, i.e., the final output "restored data stream." Subsequently, this restored data stream is safely and sequentially submitted to the receiving end's computing unit for subsequent processing.

[0159] Through steps 1201 to 1202 above, by introducing a "sequence identifier" and a corresponding "timing alignment processing" mechanism, the solution of this application efficiently solves the technical problem of data out-of-order transmission that inevitably occurs in multi-port parallel transmission at the underlying hardware level. The hardware reorganization logic in the solution of this application is completely transparent to the upper-layer software application. This not only ensures the data integrity and timing correctness of high-speed parallel communication across chips, but also ensures that the system will not introduce any risk of data corruption or upper-layer protocol errors due to out-of-order transmission while fully enjoying the bandwidth doubling benefit brought by dual physical ports. This greatly improves the communication stability and throughput efficiency of the entire chip system.

[0160] In addition, in some embodiments, the merging unit inside the core core introduces a sliding window mechanism and a deskipation buffer to further improve the robustness of data reconstruction, as described below.

[0161] First, during the data acquisition and skew calculation phase, when multiple physical interconnect ports of the merging unit (such as port 0 and port 1) receive sub-data packets from the input / output cores in parallel, the header parsing logic inside the merging unit extracts the sequence identifier of each sub-data packet in real time. Due to differences in physical link characteristics, the receive clocks of port 0 and port 1 often have a phase difference. The merging unit uses the first arriving data packets with the reference sequence identifier to calculate the instantaneous transmission delay difference (Skew) between the two ports and initializes the read / write pointers of the deskew buffer accordingly.

[0162] Secondly, during the window verification and buffer alignment phase, the reassembly controller of the merging unit activates a sliding window with a set receive window threshold (e.g., a range of 64 consecutive sequence numbers). For each newly arrived sub-data packet, the reassembly controller compares its sequence identifier with the valid range of the current sliding window. If the sequence identifier falls within the window range, it is temporarily stored in the corresponding address of the de-skew buffer; if the sequence identifier has expired (below the lower limit of the window) or illegally preceded the data packet (above the upper limit of the window), it is directly discarded or an underlying hardware error record is triggered, thereby effectively resisting the impact of scrambled data packets on the buffer.

[0163] Finally, during the anomaly arbitration and window sliding phase, the reassembly controller monitors the integrity of consecutive sequence identifiers in the deskew buffer in real time. When a consecutive data packet sequence is detected starting from the window's beginning, it is immediately concatenated into a restored data stream and submitted to the underlying computation unit. Simultaneously, the receiving window slides forward according to the number of consecutive packets. Furthermore, if the controller detects that a data packet with a specific sequence identifier has not arrived within a preset timeout clock period, to prevent head-of-line blocking at the receiving end from causing a system deadlock, the merging unit will proactively send a retransmission control message to the sending end and temporarily freeze the sliding of the current window until the missing data packets are replenished or the maximum number of retries is reached, triggering an error interrupt. Through the aforementioned hardware-level sliding window and timeout arbitration mechanism, the system achieves efficient correction of physical layer out-of-order data and deadlock prevention with extremely limited on-chip cache resources.

[0164] Step 1102: When the data to be transmitted is a received data stream sent to the transmission computing chip and the service type is an external protocol service, determine a designated port from at least two physical interconnect ports and receive the received data stream sent by the IO chip through the designated port.

[0165] Step 1102 will be described in detail below.

[0166] In step 1102 of some embodiments, the corresponding action is to determine a designated port from at least two physical interconnect ports when the data to be transmitted is a received data stream sent to the transmission computing chip and the service type is an external protocol service, and to receive the received data stream sent by the IO chip through the designated port. In this process, similar to the above-described data transmission method, for "external protocol services" (usually referring to services such as PCIe and RDMA that have specific requirements for protocol timing or physical channels), the solution of this application adopts a directed reception strategy. At this time, the chip hub locks a specific physical interconnect port as the "designated port" according to a preset protocol mapping relationship or routing table (for example, PCIe service locks port 0, RDMA service locks port 1).

[0167] Then, the merging unit will only receive data from the designated port, without obtaining data fragments of the service from other ports. This mechanism ensures that the data stream of this service type enters the computing chip completely and sequentially through a single physical channel, without the need for complex reassembly operations. It directly maintains the original structure and timing integrity of the external protocol data packets, and then forwards them to the corresponding protocol processing module.

[0168] Through steps 1101 to 1102 above, a complete closed loop of the data transmission link is achieved by mirroring the processing logic on the receiving and sending sides. For inter-chip communication services, the solution of this application greatly improves the bandwidth resource utilization at the receiving end by using parallel reception and reconstruction at dual ports, and solves the interface technology problem when large amounts of data enter the computing chip. For external protocol services, strict protocol isolation is achieved at the physical receiving level by using directional reception at designated ports, which effectively avoids mutual interference and resource competition of various external protocol traffic when entering the computing chip. Thus, while greatly improving the overall reception throughput of the system, it ensures high reliability and low latency transmission of key protocol services.

[0169] Reference Figure 13 This is a schematic diagram of data transmission for receiving a data stream, provided in an embodiment of this application. For example... Figure 13 The diagram illustrates the principle behind how the merging unit within the computing chip performs differentiated targeted reception and data reconstruction for different service types when receiving data. Figure 13 The diagram, from left to right, illustrates the data flow at the receiving end in three different business scenarios: high-speed peripheral component interconnect (PCIe) to compute chip, remote direct memory access (RDMA) to compute chip, and compute chip to compute chip (i.e., D2D communication between chips). In all three scenarios, the top-level data to be received flows downward from the input / output chips to the merging unit in the chip's central processing unit for protocol awareness and path scheduling, and is ultimately transmitted to the bottom-level compute unit (CU).

[0170] Specifically, such as Figure 13 As shown in the "High-speed peripheral component interconnect transmission to computing chip" scenario on the left, when the merging unit recognizes that the data stream sent from the input / output chip belongs to PCIe service, it does not execute the internal reassembly logic. Instead, the merging unit directs the complete data stream from a specific single physical interconnect port (such as...). Figure 13 The data stream is received via port 0 (identified in the diagram). After entering the core core through port 0, the received data stream is further forwarded by the merging unit to the underlying computing unit.

[0171] like Figure 13 As shown in the "Remote Direct Memory Access to Compute Chip" scenario, when the service type is identified as an RDMA service, the merging unit also maintains the integrity of the original data stream and forces it to be sent from another independent physical channel (such as...). Figure 13 The system receives data from port 1 (identified in the diagram) and then forwards it to the underlying computing unit within the core. These two targeted reception mechanisms work together to achieve strict isolation of different protocol traffic at the physical port level, avoiding resource contention and timing interference between protocols at the receiving end.

[0172] like Figure 13 As shown in the concurrent reception scenario of "computing chip to computing chip" on the right, when the merging unit determines that the current reception service is inter-chip communication (D2D) requiring ultra-high throughput support, its internal hardware reassembly and restoration logic is activated. Through the aggregation link of the two physical interconnect ports, port 0 and port 1, it synchronously and in parallel receives two sub-data streams from the input and output chips. Subsequently, these two sub-data streams are spliced ​​and reassembled by the merging unit into a complete high-bandwidth data stream, which is ultimately directed to the underlying computing unit.

[0173] like Figure 13 The data reception principle shown in the diagram demonstrates that, through the merging unit within the core, single-port isolated directional reception of specific external protocol services such as PCIe and RDMA can be performed without changing the underlying hardware link, while dual-port parallel reception and reconstruction can be performed for internal interconnection services such as D2D. This design reuses physical port resources, ensuring both the stability and determinism of external protocol communication reception, and successfully doubling the data reception bandwidth between computing cores through the parallel mechanism.

[0174] In addition, refer to Figure 14 The process of parsing the target access address from the data to be transmitted also includes the following step 1401.

[0175] Step 1401: Based on the real-time bandwidth usage of multiple physical interconnect ports, dynamically adjust the amount of data allocated to each physical interconnect port for the sub-data stream.

[0176] Step 1401 will be described in detail below.

[0177] In step 1401 of some embodiments, to maximize the overall system throughput under sudden high load or non-uniform network traffic scenarios, the splitting unit within the chip core also integrates traffic monitoring and dynamic arbitration logic to dynamically adjust the amount of data allocated to each physical interconnect port based on the real-time bandwidth occupancy of multiple physical interconnect ports. Specifically, the splitting unit can poll and obtain the underlying status parameters of each physical interconnect port in real time at a preset clock cycle, such as the current internal buffer send queue depth (reflecting the link congestion level) and the flow control credit score received from the peer (reflecting the peer's available receive capacity quota). Through these multi-dimensional underlying status perceptions, the chip system can accurately and continuously assess the current actual bandwidth load and remaining available send capacity of each physical interconnect port.

[0178] Based on the above real-time evaluation results, when a load imbalance is detected among multiple physical interconnect ports (for example, the first physical interconnect port's transmission queue depth exceeds the warning threshold due to a sudden large-scale data transmission, while the second physical interconnect port still has sufficient credit points and is under light load), the arbitration logic of the splitting unit will trigger a dynamic bandwidth adjustment mechanism. At this time, the splitting unit no longer adopts a static uniform alternating allocation strategy, but adaptively changes the allocation weight or splitting ratio of the sub-data streams, redirecting or preferentially allocating the portion of the data originally scheduled to be sent to the congested port to idle ports with spare bandwidth for cross-boundary transmission as needed.

[0179] In one example, when performing on-demand redirection or skewed allocation to idle ports with spare bandwidth for cross-boundary transmission, the splitting unit within the core core dynamically breaks through preset static protocol mapping or uniform splitting rules. Specifically, when it is determined that the first physical interconnect port is in a high-load congestion state, while the second physical interconnect port is in a light-load or idle state with spare bandwidth, the splitting unit will actively intercept some data packets originally scheduled to be sent to the first physical interconnect port and dynamically insert a specific 'delegation identifier' into its physical layer header. Subsequently, the splitting unit routes these data packets carrying the delegation identifier to the idle second physical interconnect port for transmission, thereby realizing cross-boundary transmission of heterogeneous data streams. Correspondingly, when a data packet with the delegation identifier crosses the physical boundary and arrives at the receiving end, the merging unit at the receiving end will first identify and parse the underlying identifier, thereby directly ignoring the physical port attribute that the data packet actually entered. Subsequently, based on the identifier, the merging unit forcibly redirects and seamlessly forwards it to the correct protocol processing logic (for example, merging it into the PCIe protocol processing logic corresponding to the original first physical interconnect port), thereby forming a complete closed loop at the underlying hardware level, realizing flexible bandwidth borrowing across physical links and completely transparent transmission to the upper-layer computing unit.

[0180] This underlying hardware-level dynamic fine-tuning of data volume and bandwidth high-low "borrowing" mechanism not only effectively avoids the risk of head-of-line blocking and buffer overflow in a single physical channel, but also endows the chip interconnect link with strong elasticity and self-healing ability. Thus, in complex and ever-changing heterogeneous computing environments, it greatly improves the elastic bandwidth utilization of interconnect links and the flexible utilization capability at the chip level.

[0181] This application embodiment also provides a data transmission device that can implement the above-described data transmission method. The data transmission device is integrated into the chip core of the aforementioned chip system. The chip system includes I / O chips and multiple computing chips. Each computing chip is connected to at least two physical interconnect ports in the I / O chips through the chip core. (Refer to...) Figure 15 The device 1500 includes:

[0182] The service type identification module 1510 is used to respond to the data transmission request of the data to be transmitted in the transmission computing chip, and to determine the service type according to the target access address of the data to be transmitted, wherein the transmission computing chip is one of multiple computing chips.

[0183] The splitting module 1520 is connected to the service type identification module and to at least two physical interconnect ports respectively. When the data to be transmitted is an outgoing data stream sent by the transmission computing chip and the service type is inter-chip communication service, the outgoing data stream is split into multiple sub-data streams and the multiple sub-data streams are sent to the IO chip in parallel through at least two physical interconnect ports.

[0184] The directional routing module 1530 is used to determine a designated port from at least two physical interconnect ports and send the outgoing data stream to the IO core through the designated port when the data to be transmitted is an outgoing data stream sent by the transmission computing core and the service type is an external protocol service.

[0185] The merging module 1540 is used to reassemble or forward data streams received from physical interconnect ports to computing chips.

[0186] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, the specific implementation of the data transmission device is basically the same as the specific implementation of the data transmission method described above, and will not be repeated here.

[0187] This application also provides an electronic device, including:

[0188] At least one memory;

[0189] At least one processor;

[0190] At least one program;

[0191] The program is stored in memory, and the processor executes at least one program to implement the data transmission method described above. The electronic device can be any smart terminal, including mobile phones, tablets, personal digital assistants (PDAs), and in-vehicle computers.

[0192] Please see Figure 16 , Figure 16 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes:

[0193] The processor 1601 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0194] The memory 1602 can be implemented in the form of ROM (Read Only Memory), static storage device, dynamic storage device, or RAM (Random Access Memory). The memory 1602 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1602 and is called and executed by the processor 1601 using the data transmission method of the embodiments of this application.

[0195] The input / output interface 1603 is used to implement information input and output;

[0196] The communication interface 1604 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0197] Bus 1605 transmits information between various components of the device (e.g., processor 1601, memory 1602, input / output interface 1603, and communication interface 1604);

[0198] The processor 1601, memory 1602, input / output interface 1603 and communication interface 1604 are connected to each other within the device via bus 1605.

[0199] This application also provides a storage medium, which is a computer-readable storage medium, storing a computer program that, when executed by a processor, implements the above-described data transmission method.

[0200] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0201] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0202] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0203] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0204] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0205] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0206] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0207] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. The coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, or indirect coupling or communication connection between the apparatus or units, and may be electrical, mechanical, or other forms.

[0208] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0209] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0210] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0211] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A chip system, characterized in that, include: The system includes an I / O core and multiple computing cores, each computing core being configured with a corresponding core hub, and each computing core being connected to at least two physical interconnect ports in the I / O core through the core hub. The core core includes a splitting unit and a merging unit. The splitting unit is used to distribute the data stream emitted by the computing core to at least one of the physical interconnect ports according to the service type. The merging unit is used to reassemble or forward the data stream received from the physical interconnect port to the computing chip; The computing core includes at least one computing unit, and the internal unidirectional bandwidth between the computing unit and the core hub is set to be no less than the sum of the external unidirectional bandwidths of the two physical interconnect ports.

2. The chip system according to claim 1, characterized in that, The core hub is also used to accelerate the data transfer between cores for symmetric memory access operations, the symmetric memory being configured to support synchronous access of a single symmetric address to multiple three-dimensional stacked memories.

3. A data transmission method applied to a chip system, the chip system comprising I / O chips and multiple computing chips, each computing chip being configured with a corresponding chip hub, each computing chip being connected to at least two physical interconnect ports in the I / O chips, each computing chip comprising at least one computing unit, the internal unidirectional bandwidth between the computing unit and the chip hub being set to be not less than the sum of the external unidirectional bandwidths of the two physical interconnect ports, characterized in that... The method includes: In response to a data transmission request for data to be transmitted in a transmission computing chip, and based on the target access address of the data to be transmitted, the service type is determined, wherein the transmission computing chip is one of a plurality of computing chips; When the data to be transmitted is an outgoing data stream sent by the transmission computing chip, and the service type is an inter-chip communication service, the outgoing data stream is split into multiple sub-data streams, and the multiple sub-data streams are sent in parallel to the IO chip through at least two of the physical interconnect ports. When the data to be transmitted is an outgoing data stream sent by the transmission computing chip, and the service type is an external protocol service, a designated port is determined from at least two of the physical interconnect ports, and the outgoing data stream is sent to the IO chip through the designated port.

4. The data transmission method according to claim 3, characterized in that, The inter-chip communication service includes direct communication between chips (D2D) service; the external protocol service includes high-speed peripheral component interconnect (PCIe) service and / or remote direct memory access (RDMA) service.

5. The data transmission method according to claim 3, characterized in that, The method further includes: When the data to be transmitted is a received data stream sent to the transmission computing chip, and the service type is the inter-chip communication service, the received data stream sent by the IO chip is received in parallel through at least two of the physical interconnect ports, and the received data stream is reassembled and restored to obtain the restored data stream; When the data to be transmitted is a received data stream sent to the transmission computing chip, and the service type is the external protocol service, a designated port is determined from at least two of the physical interconnect ports, and the received data stream sent by the IO chip is received through the designated port.

6. The data transmission method according to claim 3, characterized in that, Determining the service type based on the target access address of the data to be transmitted includes: The target access address is obtained by parsing the data to be transmitted; When the address space range corresponding to the target access address is the first address space, the service type is determined to be the inter-chip communication service; When the address space range corresponding to the target access address is the second address space, the service type is determined to be the external protocol service.

7. The data transmission method according to claim 6, characterized in that, The step of parsing the target access address from the data to be transmitted includes: The header of the data to be transmitted is parsed to obtain the virtual address; The virtual address is translated into a physical address to obtain the target access address.

8. The data transmission method according to claim 4, characterized in that, The step of splitting the transmitted data stream into multiple sub-data streams and sending the multiple sub-data streams in parallel to the IO chip through at least two of the physical interconnect ports includes: The emitted data stream is cut according to a preset splitting granularity to obtain multiple multi-path sub-data streams; Multiple sub-data streams are alternately distributed to each transmission connection port, and the multiple sub-data streams are sent in parallel to the IO chip through the multiple transmission connection ports, wherein the transmission connection port is the physical interconnect port connected to the transmission computing chip.

9. The data transmission method according to claim 5, characterized in that, The step of reassembling and restoring the received data stream to obtain a restored data stream includes: Obtain the sequence identifier of each data packet in the multi-path sub-data stream; The multiple data packets are time-aligned according to the sequence identifier to obtain the restored data stream.

10. The data transmission method according to claim 4, characterized in that, Determining the designated port from at least two of the physical interconnect ports includes: When the service type is the high-speed peripheral component interconnect PCIe service, the first port of at least two physical interconnect ports shall be used as the designated port; When the service type is the Remote Direct Memory Access (RDMA) service, the second port of at least two physical interconnect ports shall be used as the designated port.

11. The data transmission method according to claim 3, characterized in that, The step of splitting the transmitted data stream into multiple sub-data streams further includes: Based on the real-time bandwidth occupancy of the multiple physical interconnect ports, the amount of data allocated to each physical interconnect port's sub-data stream is dynamically adjusted.

12. A data transmission device, characterized in that, The device is integrated into the core hub of a chip system. The chip system includes I / O cores and multiple computing cores. Each computing core is configured with a corresponding core hub. Each computing core is connected to at least two physical interconnect ports in the I / O cores through the core hub. Each computing core includes at least one computing unit. The internal unidirectional bandwidth between the computing unit and the core hub is set to be no less than the sum of the external unidirectional bandwidths of the two physical interconnect ports. The device includes: A service type identification module is used to respond to a data transmission request for data to be transmitted in a transmission computing chip, and to determine the service type based on the target access address of the data to be transmitted, wherein the transmission computing chip is one of a plurality of computing chips; The splitting module is connected to the service type identification module and to at least two physical interconnect ports respectively. It is used to split the data stream to be transmitted into multiple sub-data streams when the data to be transmitted is an outgoing data stream sent by the transmission computing chip and the service type is inter-chip communication service, and to send the multiple sub-data streams to the IO chip in parallel through at least two of the physical interconnect ports. A directional routing module is used to determine a designated port from at least two physical interconnect ports and send the outgoing data stream to the IO core through the designated port when the data to be transmitted is an outgoing data stream sent by the transmission computing core and the service type is an external protocol service. A merging module is used to reassemble or forward data streams received from the physical interconnect port to the computing chip.

13. An electronic device, characterized in that, It includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the data transmission method according to any one of claims 3 to 11.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the data transmission method according to any one of claims 3 to 11.

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