Low-delay inter-core communication system and method

Abstract

The invention discloses a low-delay inter-core communication system and method, and belongs to the technical field of multi-core processor inter-core communication. The system comprises a dual-core processor, an inter-general processor communication module GPIC and a shared memory, the dual-core processor is connected with the communication module GPIC between the general processor and the hardware transmission interrupt signal, and the shared memory is provided with a data interaction area containing control information and a data storage area. Through system initialization, data interaction areas in the dual-core processor, the GPIC module and the shared memory are configured; in the communication preparation stage, dual cores configure parameters and establish connection; when data are sent, the sending core writes the data into the data interaction area and sends an interrupt signal through the GPIC module; the receiving core reads the processing data and sends a confirmation signal after receiving interruption; and finally completing communication. The communication efficiency and reliability are improved through dual-core cooperation, bidirectional communication is supported, the flexibility is high, and the method is suitable for the fields of industrial control, automotive electronics and the like with high real-time requirements.

Description

A low-latency inter-core communication system and method Technical Field

[0001] This invention relates to the field of inter-core communication technology for multi-core processors, specifically to a low-latency inter-core communication method and system based on a 32-bit Cortex-R52+ dual-core processor and implemented using the GPIC module. Background Technology

[0002] In the field of embedded systems, multi-core processors have been widely used as applications demand increasingly higher processing power and real-time performance. The 32-bit Cortex R52 dual-core processor, with its high performance and excellent real-time capabilities, plays a vital role in industrial control, automotive electronics, and other fields.

[0003] Inter-core communication is crucial for the collaborative work of multi-core processors, and its communication latency directly impacts the performance of the entire system. Currently common inter-core communication methods have several shortcomings. For example, shared memory-based communication is prone to data races, requires complex synchronization mechanisms, and increases communication latency; interrupt-based communication introduces significant latency in interrupt response and processing, making it difficult to meet the requirements of low-latency communication.

[0004] The GPIC (Generic Inter-Processor Communication) module, as a hardware module specifically designed for inter-core communication, is characterized by high efficiency and reliability, making low-latency inter-core communication possible. However, existing solutions using the GPIC module to implement inter-core communication on a 32-bit Cortex R52 dual-core processor still have room for improvement in terms of communication efficiency and synchronization mechanisms. Summary of the Invention

[0005] This invention aims to solve the problems of high communication latency and complex synchronization mechanisms in existing inter-core communication methods for 32-bit Cortex R52 dual-core processors. It provides a low-latency inter-core communication method and system based on the GPIC module, which improves inter-core communication efficiency and reduces communication latency through dual-core cooperation.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a low-latency inter-core communication system, comprising: a dual-core processor 1, a general-purpose inter-processor communication module GPIC, and shared memory 2; wherein, the dual-core processor 1 includes Croe0 and Croe1, which are connected to the general-purpose inter-processor communication module GPIC for hardware transmission of interrupt signals; the shared memory 2 includes a data interaction area for inter-core communication, which is connected to the dual-core processor 1 via an internal system bus.

[0007] Furthermore, the dual-core processor 1 includes an initialization module and a communication control module. The initialization module can configure the data interaction area of ​​the dual-core processor 1, the general-purpose inter-processor communication module GPIC, and the shared memory 2. The communication control module can manage the communication connection, data transmission and reception process between Croe0 and Croe1.

[0008] Furthermore, the General Purpose Interprocessor Communication Module (GPIC) includes an interrupt controller, a message buffer, and one or more communication channels, the priority of which is configurable; the data interaction area divided in shared memory 2 includes a control information storage area and a data storage area.

[0009] This invention also provides a communication method for a low-latency inter-core communication system, comprising the following steps: S1: Configuring the dual-core processor 1, the general-purpose inter-processor communication module (GPIC), and the data interaction area in shared memory 2 through system initialization; S2: In the communication preparation phase, the dual-core Croe0 and Croe1 configure communication parameters respectively and establish a communication connection through the GPIC; S3: The data sending core writes the data to be sent into the data interaction area and sends an interrupt signal to the receiving core through the GPIC; S4: The receiving core responds to the interrupt signal, reads data from the data interaction area, and performs verification processing; S5: After processing, the receiving core sends an acknowledgment signal to the sending core through the GPIC.

[0010] Furthermore, in step S1, system initialization includes initializing the dual-core processors Core0 and Core1 respectively, setting the processor operating frequency and registers; configuring the interrupt controller, message buffer and communication channel parameters of the general inter-processor communication module GPIC; and dividing and initializing the data interaction area in shared memory 2, setting its starting address, size and control information.

[0011] Furthermore, the control information includes data length and status flags, which are used to identify whether the data interaction area is idle or occupied.

[0012] Furthermore, in step S3, the data sending core checks the status flag of the data interaction area before writing data. If it is idle, it writes data and updates the control information.

[0013] Furthermore, upon receiving the nuclear response interrupt signal, non-urgent tasks are suspended, the data receiving process begins, and integrity verification is performed after the data is read.

[0014] Furthermore, after completing data reception, the receiving core updates the status flag of the data interaction area to idle.

[0015] Furthermore, this method supports bidirectional communication. After completing one communication, the receiving core can switch to the sending core and send feedback data to the original sending core according to the same process.

[0016] The low-latency inter-core communication system and method of the present invention have the following advantages: (1) The present invention uses the general-purpose inter-processor communication module GPIC to directly transmit interrupt signals, avoiding the multi-level response and scheduling overhead in traditional software interrupt handling. Big data is directly accessed through shared memory and triggered only by small-sized interrupt signals, reducing software intervention on the data transmission path and significantly reducing overall communication latency.

[0017] (2): This invention achieves lightweight mutual exclusion by using preset status flags such as "free" and "occupied" in shared memory, without the need to introduce complex synchronization primitives such as semaphores and mutexes. The checking and updating of status flags can be performed atomically with hardware support, effectively avoiding data races, simplifying software design, and improving system reliability.

[0018] (3): The communication process includes a data verification step to ensure the integrity of data transmission. After completing data processing, the receiving core sends an acknowledgment signal to implement a reliable response mechanism, supporting retransmission and exception handling in case of communication failure. The system has high reliability.

[0019] (4): The communication role can be dynamically switched. Any core can act as a sender or receiver, supporting bidirectional communication and data exchange. The communication channel priority of the General Processor Inter-Processor Communication Module (GPIC) is configurable, which can adapt to task scenarios with different real-time requirements.

[0020] (5): This invention highly integrates the Cortex R52 dual-core architecture with the GPIC dedicated communication hardware for general-purpose inter-processor communication, giving full play to its high real-time and low latency characteristics. The shared memory area can be flexibly divided and configured, supporting message passing of different sizes and structures, and has high resource utilization. Attached Figure Description

[0021] This specification includes the following figures, which show the following: Figure 1 is a logical structure diagram of a low-latency inter-core communication system according to the present invention; Figure 2 is an overall flowchart of a low-latency inter-core communication method according to the present invention; wherein, 1, dual-core processor, 2, shared memory. Detailed Implementation

[0022] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, in order to help those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention, and to facilitate its implementation.

[0023] As shown in Figure 1, the low-latency inter-core communication system provided by this invention mainly includes the following components: a dual-core processor 1, a general-purpose inter-processor communication module (GPIC), and shared memory 2. These components are interconnected through a high-speed system bus inside the chip, forming a high-efficiency inter-core communication hardware platform.

[0024] This invention employs a 32-bit Cortex-R52 dual-core processor based on the ARM architecture. This processor contains two independent and symmetrically configured processing cores, denoted as Core0 and Core1. Each core possesses complete computation, control, and interrupt handling capabilities, and includes a dedicated initialization module and communication control module for inter-core collaboration. The initialization module is responsible for performing basic configurations of its own core, the General Processor Interface (GPIC) module, and the communication area in shared memory 2 after power-on or reset. The communication control module is responsible for managing the establishment and maintenance of communication links, as well as controlling the data transmission and reception process.

[0025] The General Purpose Inter-Processor Communication (GPIC) module integrates the following sub-units: an interrupt controller, a message buffer, and multiple configurable communication channels. The interrupt controller achieves efficient distribution of inter-core interrupt points (IPIs) through hardware register mapping and dedicated interrupt channels. Each processor core has independent IPI send and receive registers. When a core needs to interrupt another core, it simply writes a specific command to the target core's corresponding IPI send register. The interrupt routing matrix within the interrupt controller immediately decodes the request, sets the target core's pending interrupt bit, and transmits the physical interrupt signal via the system interconnect bus. Upon receiving the signal, the target core's local interrupt controller submits it to the processor for execution based on priority. It can be configured with different interrupt priorities to ensure that high-priority communication requests are responded to promptly.

[0026] The message buffer provides a small, high-speed storage area for temporarily storing very short control messages or emergency notifications. For small data transfers, there is no need to go through the complete "write-notification-read" process of shared memory. The sending core directly writes to the message buffer and triggers a specific interrupt. The interrupt service routine of the receiving core reads the message directly from the buffer, reducing access latency and shared memory conflicts, and avoiding frequent access to shared memory for small amounts of data.

[0027] Multiple configurable communication channels support the establishment of multiple independent logical communication links between Core0 and Core1. The priority and operating mode of each channel can be configured independently to meet communication tasks with different real-time and bandwidth requirements.

[0028] Shared memory 2 is a physical memory area that can be accessed by both Core 0 and Core 1. In this invention, a specific area is designated as a data interaction area for inter-core transfer of large amounts of data. This data interaction area is further subdivided into: a control information storage area and a data storage area. The control information storage area stores metadata that manages data interaction, such as data length, checksum, and status flags like "free" and "occupied." The data storage area stores the actual application data to be transferred.

[0029] Figure 2 shows the overall flowchart of the method described in this invention, implemented according to the following steps: S1: After the system is powered on or reset, a comprehensive initialization operation is first performed to establish a stable inter-core communication environment. The dual-core processor 1 is initialized, with Core0 and Core1 initialized separately, setting their respective operating frequencies, power states, and necessary system registers such as the MMU and MPU to ensure the dual cores enter a state where they can execute instructions normally. The general-purpose inter-processor communication module GPIC is initialized, configuring the interrupt controller, setting the inter-core interrupt vector, priority, and triggering mode; the message buffer is initialized, setting its physical base address and size; one or more communication channels are configured. For example, channel 0 can be set as a high-priority interrupt channel for transmitting emergency control commands; channel 1 can be set as a normal-priority channel for transmitting regular data. The shared memory 2 data interaction area is initialized, defining and dividing the specific address range of the data interaction area through software. The control information storage area is initialized, uniformly setting the status flag to "idle" and clearing fields such as data length to zero. The data storage area is cleared or assigned initial values. After initialization, both Core0 and Core1 know the location, size, and access rules of the data interaction area.

[0030] S2: Core0 and Core1 each set the parameters for this communication by writing to the configuration registers of the General Processor Communication Module (GPIC), such as selecting the communication channel, data bit width, and message sending and receiving modes. Subsequently, the dual-core processor 1 exchanges predefined handshake signals through the GPIC. For example, Core0 sends a "connection request," and Core1 replies with "connection ready." This process is quickly completed by the GPIC, confirming that both sides are configured and ready, and the logical link is successfully established.

[0031] S3: Taking Core0 sending data to Core1 as an example, Core0's communication control module first checks the status flag in the control information storage area of ​​the data interaction area. If the flag is "Idle," it indicates that the data area is available; if it is "Occupied," Core0 can enter a brief polling wait or execute other tasks until it becomes idle. After confirming that it is idle, Core0 writes the application data to be sent to the data storage area of ​​shared memory 2. Next, Core0 updates the control information storage area, writes the data length into the corresponding field, calculates and writes the data checksum, and finally atomically updates the status flag to "Written and ready to send." This prevents race conditions caused by both cores modifying the status flag simultaneously. After the data is ready, Core0 sends a hardware interrupt signal to Core1 by triggering the communication channel configured in the general-purpose inter-processor communication module GPIC. This signal is transmitted directly through a dedicated wire inside the chip, avoiding the delay of software polling.

[0032] Step S4: When a hardware interrupt signal generated by the General Purpose Inter-Processor Communication (GPIC) module arrives at the Core1's general purpose interrupt controller, the interrupt controller identifies it as a high-priority inter-core communication interrupt based on preset priorities. If the priority of the task currently being executed by Core1 is lower than this interrupt, the interrupt controller will immediately send an interrupt request to the Core1 CPU core. After completing the execution of the current instruction, the CPU core responds to the interrupt and performs the following operations: After a quick context save, the current non-urgent, preemptible task is immediately suspended. Core1 executes the interrupt service routine, reads the control information storage area of ​​the data exchange area, and obtains the status flag and data length. Based on the data length, the data is read from the data storage area into Core1's local buffer. The read checksum is used to perform an integrity check on the data. If the check fails, an error flag can be set, and a retransmission request can be sent to Core0 through another GPIC channel. After the data verification is successful, Core1 updates the status flag to "Read and awaiting confirmation". Subsequently, Core1 sends a hardware confirmation interrupt signal to Core0 through another independent channel of the GPIC module. This signal informs Core0 that the data has been successfully received. Finally, Core1 updates the status flag to "idle", releases the data exchange area, exits the interrupt service routine, and resumes the previously paused tasks.

[0033] S5: Upon receiving an acknowledgment interrupt from Core1, Core0 recognizes the successful completion of the data transmission. The communication control module can log or notify the upper-layer application. This concludes a one-way communication cycle. If Core1 needs to send feedback data to Core0, it can immediately switch to the "sending core" role. Core1 follows the exact same process as in S3: checking status flags, writing data, updating control information, and sending an interrupt to Core0 via the General Processor Communication Module (GPIC). Core0 then switches to the "receiving core" role and executes the process in S4. By configuring independent GPIC channels and data exchange areas for communication in both directions, bidirectional low-latency data exchange is achieved.

[0034] The above embodiments of the present invention provide a low-latency inter-core communication system and method based on a 32-bit Cortex-R52 dual-core processor and a general-purpose inter-processor communication module (GPIC). Through refined design with hardware and software collaboration, this embodiment effectively solves the problems of high latency, complex synchronization mechanisms, and insufficient reliability in existing inter-core communication technologies, and achieves efficient, reliable, and flexible inter-core data exchange in multi-core embedded real-time systems.

[0035] This embodiment revolutionizes the communication event notification mechanism by utilizing the General Purpose Inter-Processor Communication Module (GPIC). The sending core, Core0, directly triggers the hardware logic to generate an interrupt signal through a single write operation to the GPIC register. This signal is transmitted to the interrupt controller of the receiving core, Core1, via a dedicated physical connection within the chip, bypassing any software intermediaries or latency introduced by the data bus. Compared to the traditional "write to memory—trigger software interrupt—operating system scheduling—interrupt dispatch" process, the latency is reduced by one to two orders of magnitude.

[0036] This embodiment employs a pure hardware path, where the transmission delay of interrupt signals is deterministic and predictable, virtually unaffected by the load of other software tasks in the system. The interrupt signals generated by the General Processor Communication Module (GPIC) can be configured to have the highest priority. Once the receiving core, Core1, receives this hardware interrupt, the processor hardware immediately suspends its current non-highest priority tasks and forces the execution of an interrupt service routine optimized for inter-core communication. This ensures that communication events always receive the highest priority processing.

[0037] This embodiment establishes a dedicated control information storage area in shared memory, which contains status flags. The sending core (Core0) and receiving core (Core1) read and write these flags solely through atomic load and store instructions from the processor. Atomic operations ensure the indivisibility of the "read-modify-write" process, thus eliminating the need for any additional locking mechanisms. Compared to software locks, the synchronization overhead is negligible, offering significant advantages, especially in high-frequency communication scenarios.

[0038] Status flags define explicit state transitions such as "Idle" — "Written" — "Read" — "Idle". The communication control modules of the sending core Core0 and the receiving core Core1 only need to follow a fixed process of "checking the status — performing the operation — atomically updating the status", which greatly reduces coding complexity and error probability. Through atomic operations, the update of control information is completed instantaneously. The receiving core can obtain a complete and consistent control information through atomic reading, fundamentally avoiding data corruption or logical errors caused by improper synchronization.

[0039] This embodiment leverages the flexibility of the General Purpose Inter-Processor Communication Module (GPIC) and shared memory management to provide a configurable, multi-mode communication framework. The GPIC provides multiple configurable communication channels, allowing the system to allocate dedicated paths for data streams with different characteristics. For example, channel 0 can be configured with the highest priority for transmitting safety shutdown commands; channel 1 can be configured with normal priority for transmitting periodic sensor data; and channel 2 can be combined with DMA for transmitting large blocks of configuration data. This ensures the timeliness of critical messages without affecting the throughput of large data blocks, optimizing overall system performance.

[0040] The present invention has been described above by way of example with reference to the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvements made using the inventive concept and technical solution; or the direct application of the inventive concept and technical solution to other situations without modification, are all within the protection scope of the present invention.

Claims

1. A low-latency inter-core communication system, characterized in that, include: The dual-core processor (1), the general-purpose inter-processor communication module (GPIC), and the shared memory (2) are described. The dual-core processor (1) includes Croe0 and Croe1, which are connected to the general-purpose inter-processor communication module (GPIC) and transmit interrupt signals via hardware. The shared memory (2) includes a data interaction area for inter-core communication and is connected to the dual-core processor (1) via an internal system bus.

2. The low-latency inter-core communication system according to claim 1, characterized in that, The dual-core processor (1) includes an initialization module and a communication control module. The initialization module can configure the data interaction area of ​​the dual-core processor (1), the general inter-processor communication module (GPIC), and the shared memory (2). The communication control module can manage the communication connection, data sending and receiving process between Croe0 and Croe1.

3. The low-latency inter-core communication system according to claim 1, characterized in that, The general-purpose inter-processor communication module (GPIC) includes an interrupt controller, a message buffer, and one or more communication channels, the priority of which is configurable; the data interaction area divided in the shared memory (2) includes a control information storage area and a data storage area.

4. A communication method based on the low-latency inter-core communication system according to any one of claims 1-3, characterized in that, Includes the following steps: S1: Configure the data interaction area in the dual-core processor (1), the general-purpose inter-processor communication module (GPIC), and the shared memory (2) through system initialization; S2: During the communication preparation phase, the dual-core Croe0 and Croe1 configure communication parameters respectively and establish a communication connection through the General Processor Inter-Processor Communication Module (GPIC); S3: The data sending core writes the data to be sent into the data interaction area and sends an interrupt signal to the receiving core through the General Processor Inter-Processor Communication Module (GPIC); S4: The receiving core responds to the interrupt signal, reads data from the data interaction area and performs verification processing; S5: After processing, the receiving core sends an acknowledgment signal to the sending core through the General Interprocessor Communication Module (GPIC).

5. A low-latency inter-core communication method according to claim 4, characterized in that, In step S1, system initialization includes initializing the dual-core processors (1) Core0 and Core1 respectively, setting the processor operating frequency and registers; configuring the interrupt controller, message buffer and communication channel parameters of the general inter-processor communication module (GPIC); dividing and initializing the data interaction area in the shared memory (2), and setting its starting address, size and control information.

6. The low-latency inter-core communication method according to claim 5, characterized in that, The control information includes data length and status flags, the status flags being used to identify whether the data interaction area is idle or occupied.

7. A low-latency inter-core communication method according to claim 4, characterized in that, In step S3, the data sending core checks the status flag of the data interaction area before writing data. If the flag is idle, it writes data and updates the control information.

8. A low-latency inter-core communication method according to claim 4, characterized in that, After the receiving core responds to the interrupt signal, it suspends non-urgent tasks, enters the data receiving process, and performs integrity verification after reading the data.

9. A low-latency inter-core communication method according to claim 4, characterized in that, After completing data reception, the receiving core updates the status flag of the data interaction area to idle.

10. A low-latency inter-core communication method according to claim 4, characterized in that, The method supports bidirectional communication. After completing a communication, the receiving core can switch to the sending core and send feedback data to the original sending core according to the same process.

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