LCD debugging method, device and equipment

Abstract

The application provides an LCD debugging method, device and equipment. The method isolates the asynchronous parameter update of the device tree plug-in and the synchronous display clock domain of the physical register by establishing a shadow register mapping area in the Linux kernel, and limits the writing path of the physical register. Without triggering the power switching or the driving re-measurement, the shadow mapping area parameters are synchronized to the physical register by listening to the V-Sync signal and using the atomic transmission instruction in the vertical blanking period, so that the incremental debugging parameters are re-locked as a whole in the display frame scanning gap. The application effectively avoids the display timing conflict caused by the partial effect of the parameters, realizes the non-sensing and real-time effect of the LCD parameters in the state of maintaining the display activation, and significantly improves the debugging efficiency and system stability.

Description

Technical Field

[0001] This invention relates to the field of image display and driver debugging technology, specifically to an LCD debugging method, apparatus, and device. Background Technology

[0002] In the development of embedded devices based on the Linux kernel, the parameter adjustment of the LCD (liquid crystal display) is a core step in ensuring the display effect.

[0003] Existing technologies (such as Chinese patent: CN112860324B) sometimes compile the LCD driver into a device tree file in dtb format and push it to the device storage directory. After parsing and saving the parameters through kernel functions, the parameters are made effective by executing the system's "sleep wake-up" operation.

[0004] However, existing technologies still have many shortcomings. First, triggering parameter reloading using the sleep-wake mechanism typically takes seconds and involves a noticeable black screen, making it impossible to achieve real-time, seamless comparison after parameter modification. Second, the sleep-wake operation involves a complete call to the kernel power management (PM) protocol stack. When the system is running high-throughput data streams or multiple tasks concurrently, forcibly switching power states can easily lead to bus deadlock or system crashes. Moreover, when the display controller is active, directly rewriting the timing register may cause tearing or screen distortion in the current scan frame. Existing technologies avoid this problem by stopping and resetting, but this sacrifices the continuity of debugging. Summary of the Invention

[0005] This invention provides an LCD debugging method, apparatus, and device to solve the technical problems in the prior art, such as slow debugging effectiveness, reliance on power management stack leading to limited system stability, and inability to perform real-time online optimization.

[0006] The above-mentioned technical objective of the present invention is achieved through the following technical solution: a method for debugging an LCD, the method being applied under the Linux kernel, the method comprising: A shadow register mapping area corresponding to the configuration space of the physical LCD controller is established in the kernel space. The shadow register mapping area is used to isolate the asynchronous parameter update process of the device tree plugin from the synchronous display clock domain of the physical register, and the write path of the physical register is limited to be completed synchronously only through the shadow register mapping area. Receive the device tree plugin containing incremental debugging parameters and overwrite it onto the shadow register mapping area; Monitor the vertical synchronization signal V-Sync of the LCD controller; Without triggering the power state switching and drive re-probing of the LCD controller, in response to the V-Sync signal entering the vertical blanking period, the parameters of the shadow register mapping area are synchronized to the physical register within a single vertical blanking period cycle through atomic transfer instructions, so that the incremental debugging parameters are re-locked in timing as a whole during the display frame scan interval, thereby avoiding display timing conflicts caused by partial parameter effectiveness.

[0007] Furthermore, the shadow register mapping area has a one-to-one offset mapping relationship with the address space of the physical register.

[0008] Furthermore, synchronizing the parameters of the shadow register mapping area to the physical register via atomic transfer instructions includes: By using Direct Memory Access (DMA), the updated parameter nodes in the shadow register mapping area are written in batches to the addresses corresponding to the physical registers.

[0009] Furthermore, the synchronization process is configured to be completed before the start pulse of the next frame to ensure that the physical registers achieve seamless parameter activation in the display active state.

[0010] Furthermore, the atomic transfer instruction is triggered on the rising edge of the vertical blanking period, and the physical window of the vertical blanking period is used to avoid interference with the kernel data stream.

[0011] Furthermore, the device tree plugin only contains attribute key-value pairs that differ from the existing LCD device tree file, and the overwrite process directly rewrites the corresponding node in the shadow register mapping area through memory.

[0012] The present invention also provides an apparatus for debugging an LCD, applied under the Linux kernel, the apparatus comprising: The shadow mapping unit is used to establish a shadow register mapping area in the kernel space corresponding to the configuration space of the physical LCD controller; The parameter parsing module is used to receive the device tree plugin containing incremental debugging parameters and overwrite them onto the shadow register mapping area; The signal monitoring module is used to monitor the vertical synchronization signal V-Sync of the LCD controller; The synchronization control unit is used to call the atomic transfer module to synchronize the parameters of the shadow register mapping to the physical register when the V-Sync signal enters the vertical blanking period, without triggering the power state switching and drive re-probing of the LCD controller.

[0013] The present invention also provides a device for debugging an LCD, including a memory and a processor, wherein the processor executes instructions stored in the memory to implement the above-described debugging method.

[0014] The present invention also provides a computer-readable storage medium having computer instructions stored thereon, which, when executed, implement the above-described debugging method.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention establishes a shadow register mapping area, which realizes spatial isolation between the debugging parameter writing process and the hardware display reading process, effectively avoiding address access conflicts caused by directly modifying physical registers and improving kernel stability during debugging.

[0016] 2. This invention achieves seamless parameter replacement during the physical scan "gap" by monitoring the V-Sync signal and triggering synchronization during the vertical blanking period, thus avoiding screen distortion or image tearing caused by incorrect parameter activation timing.

[0017] 3. This invention achieves synchronization within a single vertical blanking period through atomic transmission instructions, enabling parameters to take effect in real time at the millisecond level. This allows debugging personnel to immediately observe changes in the display effect, significantly improving debugging efficiency.

[0018] 4. By skipping the system power state switching and driver re-detection process, this invention achieves online hot reload without interrupting system tasks or disconnecting the bus connection, ensuring the continuity of background services such as audio and network during the debugging process, and overcoming the technical limitations of existing technologies that rely on sleep-wake mechanisms. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the method for debugging an LCD in an embodiment of the present invention; Figure 2 This is a schematic diagram of the logical architecture and memory mapping of the system for debugging the LCD in an embodiment of the present invention; Figure 3 This is a structural block diagram of the device for debugging the LCD in an embodiment of the present invention. Detailed Implementation

[0020] The working principle, specific process and technical details of the LCD debugging method, device and equipment involved in this technical solution will be explained in detail below with reference to the accompanying drawings and specific implementation scheme.

[0021] In Linux kernel-based embedded systems, display drivers are typically initialized during kernel startup. In existing implementations, their timing parameters (such as pixel clock and horizontal / vertical synchronization period) are often statically locked. To achieve parameter tuning without restarting the system or interrupting the display, this solution implements atomic parameter overloading through a hardware-software collaborative mechanism.

[0022] Reference Figures 1 to 3 During the initial debugging phase, the system allocates a contiguous storage region in the kernel memory space as a shadow register mapping area through a shadow mapping unit. The capacity of this shadow register mapping area corresponds to the physical register configuration space in the physical controller hardware, and there is a one-to-one correspondence between the register bit offset addresses of the two. By establishing this mirror region in the kernel space, the write operations of the driver and the read operations of the physical controller are isolated in the clock domain. Specifically, when a debug command is issued, the parameters are first written to the shadow register mapping area, while the physical controller hardware is still performing frame scanning according to the original physical register parameters. This isolation mechanism helps avoid the timing logic chaos that may be caused by directly modifying hardware registers during the display scan, and helps maintain the baseline stability of the system kernel during parameter tuning.

[0023] Debuggers use debugging tools or terminals to issue a Device Tree Optimizer (DTBO) containing incremental debugging parameters. The DTBO only contains the key-value pairs that need modification, such as modifying only the horizontal trailing edge or pixel clock frequency. In addition to the parameters mentioned above, incremental tuning may also involve core timing variables such as the vertical trailing edge and sync pulse width; these parameters collectively define the physical boundaries of the hardware scan.

[0024] After receiving the device tree plugin DTBO, the parameter parsing module uses the kernel dynamic loading mechanism to parse it into the corresponding kernel attribute node and overwrites the corresponding address in the shadow register mapping area. During this process, since the shadow register mapping area is only used as logical storage space, its write operation will not trigger the LCD driver's re-probing process, nor will it cause the display protocol stack to be reset, thus helping to maintain the continuity of the display data stream during parameter modification.

[0025] To ensure the safe and consistent application of new parameters in the shadow register mapping area, the signal monitoring module continuously monitors the vertical synchronization signal V-Sync fed back from the physical controller hardware. The V-Sync signal marks the end of one frame of image display scanning. During the physical interval following each frame scan, i.e., the vertical blanking period (the non-display period consisting of the vertical sync pulse, the vertical leading edge, and the vertical trailing edge), the display controller stops sending pixel data streams to the LCD panel. Upon capturing the rising edge pulse of the vertical blanking period, the signal monitoring module sends a trigger signal to the synchronization control unit.

[0026] In response to the trigger signal, the synchronization control unit invokes the atomic transfer module to perform the synchronization operation. The atomic transfer module preferably employs Direct Memory Access (DMA) to atomically write the updated full or incremental parameters from the shadow register mapping area to the physical registers of the physical controller hardware in the form of burst transfers. It should be understood that, besides DMA, other fast transfer mechanisms with burst write capabilities can also be used to achieve atomic synchronization from the shadow register mapping area to the physical registers without departing from the principles of this technical solution. Atomization refers to the complete physical-level overlay of all register groups involved in display timing, bias current, or voltage polarity as a whole within a specific vertical blanking period. If registers are written one by one, the hardware logic may read a configuration in a mixed state of old and new parameters during the write process, leading to timing lockout or hardware deadlock. The instantaneous injection during the blanking window through atomic transfer helps ensure that the physical controller hardware completes the relocking of the internal counters and timing generators before the start pulse of the next frame arrives.

[0027] Upon receiving the modification instruction, the physical controller hardware loads the new timing reference starting from the next frame. Because the entire synchronization process is compressed into a single vertical blanking period (in one embodiment, this process takes less than 1ms), the LCD panel's display visually avoids flickering, blackouts, or screen tearing. Furthermore, since this method does not involve the suspension and wake-up processes of the kernel power management protocol stack, the system-level bus controller, memory controller, and clock frequency lock remain active, thereby reducing the impact on the operating rhythm of other system functional modules (such as audio decoding and network transmission).

[0028] At the device implementation level, the debugging device is integrated as a logical whole into the display driver layer. The shadow mapping unit and the parameter parsing module work together to complete data preprocessing, while the signal monitoring module, as a timing control unit, helps to enhance the synchronization of operations. The synchronization control unit and the atomic transmission module form an execution closed loop, acting on the physical controller hardware by modifying instructions. This reload mechanism based on physical timing gaps utilizes the physical characteristics of the display scanning pattern, overcoming the technical limitation of existing technologies that require power switching to reset the hardware state.

[0029] For systems supporting multi-layer displays, this atomic transfer operation can also be extended to synchronously update the configurations of each display layer. By simultaneously refreshing the basic timing register and the layer control register during the vertical blanking period, it helps to achieve globally consistent reload of the overall display state. This method is not only suitable for module adaptation and debugging, but can also be applied to display optimization during system operation.

[0030] In summary, the above technical solution establishes a parameter preprocessing mechanism independent of the hardware clock domain by constructing a shadow register mapping area in the kernel space. Utilizing the physical characteristics of the vertical blanking period and combining it with atomic transfer instructions, it achieves synchronous update of display timing parameters at frame boundaries without interfering with the system power management protocol stack or interrupting the display data stream. This mechanism not only resolves the logical conflict between asynchronous writing and hardware scanning, avoiding display anomalies such as screen tearing and glitches, but also provides millisecond-level real-time feedback during debugging. While ensuring the stability of multi-tasking operation of embedded devices, it significantly optimizes the adaptation and debugging efficiency of LCD modules.

[0031] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for debugging an LCD, characterized in that, The method is applied under the Linux kernel, and the method includes: A shadow register mapping area corresponding to the configuration space of the physical LCD controller is established in the kernel space. The shadow register mapping area is used to isolate the asynchronous parameter update process of the device tree plugin from the synchronous display clock domain of the physical register, and the write path of the physical register is limited to be completed synchronously only through the shadow register mapping area. Receive the device tree plugin containing incremental debugging parameters and overwrite it onto the shadow register mapping area; Monitor the vertical synchronization signal V-Sync of the LCD controller; Without triggering the power state switching and drive re-probing of the LCD controller, in response to the V-Sync signal entering the vertical blanking period, the parameters of the shadow register mapping area are synchronized to the physical register within a single vertical blanking period cycle through atomic transfer instructions, so that the incremental debugging parameters are re-locked in timing as a whole during the display frame scan interval, thereby avoiding display timing conflicts caused by partial parameter effectiveness.

2. The method according to claim 1, characterized in that, The shadow register mapping area has a one-to-one offset mapping relationship with the address space of the physical register.

3. The method according to claim 1, characterized in that, The step of synchronizing the parameters of the shadow register mapping area to the physical register via atomic transfer instructions includes: By using Direct Memory Access (DMA), the updated parameter nodes in the shadow register mapping area are written in batches to the addresses corresponding to the physical registers.

4. The method according to claim 1, characterized in that, The synchronization process is configured to be completed before the start pulse of the next frame to ensure that the physical registers achieve seamless parameter activation in the display active state.

5. The method according to claim 1, characterized in that, The atomic transfer instruction is triggered on the rising edge of the vertical blanking period, and the physical window of the vertical blanking period is used to avoid interference with the kernel data stream.

6. The method according to claim 1, characterized in that, The device tree plugin contains only attribute key-value pairs that differ from the existing LCD device tree file, and the overwrite process directly rewrites the corresponding node in the shadow register mapping area through memory.

7. An apparatus for debugging an LCD, characterized in that, The device is used under the Linux kernel, and the device includes: The shadow mapping unit is used to establish a shadow register mapping area in the kernel space corresponding to the configuration space of the physical LCD controller. The shadow register mapping area is used to isolate the asynchronous parameter update process of the device tree plugin from the synchronous display clock domain of the physical register, and to limit the write path of the physical register to be completed synchronously only through the shadow register mapping area. The parameter parsing module is used to receive the device tree plugin containing incremental debugging parameters and overwrite them onto the shadow register mapping area; The signal monitoring module is used to monitor the vertical synchronization signal V-Sync of the LCD controller; The synchronization control unit is used to call the atomic transmission module to synchronize the parameters of the shadow register mapping area to the physical register within a single vertical blanking period when the V-Sync signal is detected to enter the vertical blanking period without triggering the power state switching and drive re-probing of the LCD controller, so that the incremental debugging parameters as a whole can complete the timing relocking during the display frame scan interval.

8. The apparatus according to claim 7, characterized in that, The atomic transfer module is specifically a DMA transfer module.

9. A device for debugging an LCD, characterized in that, include: Memory; And a processor coupled to the memory, the processor being configured to perform a method for debugging an LCD as described in any one of claims 1 to 6 based on instructions stored in the memory.

10. A computer-readable storage medium, characterized in that, It stores computer instructions, which, when executed by a processor, implement the method for debugging an LCD as described in any one of claims 1 to 6.

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