LDO circuit for realizing accurate control of zero point position through cascode compensation

Abstract

This invention belongs to the field of integrated circuit technology, specifically relating to an LDO circuit that achieves precise zero-point control through Cascode compensation. The circuit includes a first-stage error amplifier, a second-stage buffer, a third-stage output power transistor, a feedback circuit, and a compensation module for precise zero-point control. By employing a unique controlled resistor combined with Cascode compensation technology, this invention achieves precise zero-point tracking of the output power transistor's load current changes during compensation. This solves the core problem of difficulty in controlling the Q-value of the conjugate pole under heavy loads in Cascode compensation, which leads to low bandwidth and slow output transient response.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an LDO circuit that achieves precise control of zero-point position through Cascode compensation. Background Technology

[0002] With the increasing demands on power management performance in modern systems-on-a-chip (SoCs), low-dropout linear regulators (LDOs), as core power supply units, face severe challenges in terms of dynamic performance and stability. Especially in applications such as processor cores and high-speed serial links, load currents can experience dramatic fluctuations of hundreds of milliamperes within nanoseconds to microseconds. This necessitates that LDOs possess wider loop bandwidth and faster transient response speeds while maintaining absolute stability across the entire load range.

[0003] To improve the transient response performance of LDOs, the industry commonly adopts the approach of increasing loop bandwidth. However, bandwidth expansion significantly increases the difficulty of frequency compensation design. Traditional Miller compensation techniques, due to the right-half-plane zero-point problem, limit further bandwidth increases, and their frequency characteristics are prone to deterioration under heavy load conditions. Therefore, advanced frequency compensation techniques such as Cascode compensation have been introduced into LDO design. By introducing a zero located in the left-half-plane to cancel non-dominant poles, the system stability is ensured while expanding bandwidth.

[0004] While Cascode compensation technology is superior to traditional methods, its effectiveness largely depends on the accuracy of the zero-point locations within the compensation network. In existing designs, the compensation zeros are typically determined by fixed resistor and capacitor values, leading to an inherent limitation: when the load current varies significantly, the dominant pole position of the LDO power stage drifts considerably, and the fixed zero position cannot dynamically track this drift, causing the compensation to fail under partial load conditions. Under light loads, the zeros may fail to effectively cancel the target pole, resulting in insufficient phase margin; under heavy loads, inaccurate zero positions may introduce conjugate poles with high Q values ​​into the loop, causing significant sharp spikes and phase changes in the frequency response, leading to ringing and overshoot in the transient response, and in severe cases, even system oscillation.

[0005] Furthermore, existing technologies that use the linear region of a MOSFET as a controllable resistor for dynamic compensation generally suffer from a non-linear relationship between the resistance value and the control current. This non-linearity prevents the zero-point position from linearly and synchronously tracking the load current, resulting in insufficient control precision for the conjugate pole Q value, making it difficult to stabilize it within the optimal damping range of 0.5 to 0.7. Therefore, the entire LDO system cannot simultaneously achieve high bandwidth, fast transient response, and high stability over a wide load range.

[0006] In summary, a key problem in the existing technology is the lack of a control mechanism that enables the zero-point position of the Cascode compensation network to change linearly and accurately with the load current. This invention is proposed to overcome this technical deficiency. Summary of the Invention

[0007] The purpose of this invention is to propose an LDO circuit that uses Cascode compensation technology to precisely control the zero position.

[0008] The technical solution of this invention is as follows:

[0009] An LDO circuit that achieves precise zero-point position control through Cascode compensation includes a first-stage error amplifier, a second-stage buffer, a third-stage output power transistor, a feedback circuit, and a compensation module for precise zero-point control.

[0010] The first-stage error amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a first resistor. The source of the first PMOS transistor MP1 is connected to the power supply of the first-stage error amplifier, and its gate and drain are interconnected. The drain of the first NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP1, the gate of the first NMOS transistor MN1 is connected to the feedback voltage, and the source of the first NMOS transistor MN1 is connected to one end of the first resistor and the drain of the third NMOS transistor MN3. The gate of the third NMOS transistor MN3 is connected to the bias voltage, and its source is grounded. The source of the second PMOS transistor MP2 is connected to the power supply of the first-stage error amplifier, and its gate... The drain of the first PMOS transistor MP1 is connected to the drain of the second PMOS transistor MP2, which is connected to the drain and gate of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor M6. The source of the third PMOS transistor MP3 is connected to the power supply of the first-stage error amplifier, and its gate and drain are interconnected. The drain of the second NMOS transistor MN2 is connected to the drain of the third PMOS transistor MP3, and the gate of the second NMOS transistor MN2 is connected to the reference voltage. The source of the second NMOS transistor MN2 is connected to the other end of the first resistor and the drain of the fourth NMOS transistor MN4. The source of the fourth PMOS transistor MP4 is connected to the power supply of the first-stage error amplifier, and its gate is connected to the drain of the third PMOS transistor MP3. The drain of the fourth PMOS transistor MP4 is connected to the drain of the sixth NMOS transistor MN6. The sources of the fourth NMOS transistor MN3, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 are grounded.

[0011] The second-stage buffer includes a fifth PMOS transistor MP5, a seventh NMOS transistor MN7, a second resistor, and a third resistor. The source of the fifth PMOS transistor MP5 is connected to the input voltage, and its gate and drain are interconnected and connected to one end of the second resistor. The other end of the second resistor is connected to the input voltage. The drain of the seventh NMOS transistor MN7 is connected to the drain of the fifth PMOS transistor MP5, the gate of the seventh NMOS transistor MN7 is connected to the drain of the fourth PMOS transistor MP4, and the source of the seventh NMOS transistor MN7 is grounded through the third resistor.

[0012] The source of the output power transistor is connected to the input voltage, the gate is connected to one end of the second resistor, and the drain is connected to the feedback circuit.

[0013] The feedback circuit includes a fourth resistor, a fifth resistor, and a sixth resistor. One end of the fourth resistor is connected to the drain of the output power transistor, and the other end of the fourth resistor is grounded after passing through the fifth resistor and the sixth resistor in sequence. The connection point between the fourth resistor and the output power transistor is defined as the first feedback point, the connection point between the fourth resistor and the fifth resistor is defined as the second feedback point, and the connection point between the fifth resistor and the sixth resistor is defined as the third feedback point. The feedback voltage output at the third feedback point is connected to the gate of the first NMOS transistor MN1.

[0014] The precise zero-point control compensation module includes a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor M11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a first capacitor, a second capacitor, a mirror MOS transistor, a controlled resistor MOS transistor, and a current-controlled resistor MOS transistor. One end of the first capacitor is connected to the drain of the second PMOS transistor MP2, and the other end of the first capacitor is connected to the source of the controlled resistor MOS transistor. The drain of the controlled resistor MOS transistor is connected to the first feedback point, and its gate is connected to the drain of the eighth PMOS transistor MP8. The source of the mirror MOS transistor is connected to the input voltage, its gate is connected to one end of the second resistor, and its drain is connected to the drain of the eighth NMOS transistor MN8. The source of the current-controlled resistor MOS transistor is connected to the first feedback point, its gate is connected to the drain of the eighth PMOS transistor MP8, and its drain is connected to the drain of the ninth NMOS transistor MN9 and the gate of the eleventh NMOS transistor MN11. The eighth NMOS transistor M11... The gate of N8 is connected to the gate of the ninth NMOS transistor MN9, and the sources of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are grounded; the source of the sixth PMOS transistor MP6 is connected to the input voltage, and its gate and drain are interconnected; the drain of the tenth NMOS transistor MN10 is connected to the drain of the sixth PMOS transistor MP6, the gate of the tenth NMOS transistor MN10 is connected to the second feedback point, and the source of the tenth NMOS transistor MN10 is connected to the source of the eleventh NMOS transistor MN11 and the drain of the twelfth NMOS transistor MN12; the seventh PMOS transistor... The source of S-MOSFET MP7 is connected to the input voltage, and its gate is connected to the drain of the sixth PMOS transistor MP6. The drain of the seventh PMOS transistor MP7 is connected to one end of the second capacitor, the gate of the eighth PMOS transistor MP8, and the drain of the eleventh NMOS transistor MN11. The gate of the twelfth NMOS transistor MN12 is connected to the bias voltage, and its source is grounded. The source of the eighth PMOS transistor MP8 is connected to the input voltage, and its drain is connected to the other end of the second capacitor and the drain of the thirteenth NMOS transistor M13. The gate of the thirteenth NMOS transistor MN13 is connected to the bias voltage, and its source is grounded.

[0015] The beneficial effects of this invention are as follows: First, the LDO circuit described in this invention, by employing a unique controlled resistor combined with Cascode compensation technology, achieves precise zero-point tracking of the output power transistor's load current changes during the compensation process. This solves the core problem of difficulty in controlling the Q value of the conjugate pole under heavy load in Cascode compensation, which leads to low bandwidth and slow output transient response.

[0016] Secondly, because the present invention makes reasonable use of the current multiplication technology of the first-stage error amplifier, the bandwidth of the LDO can be further extended on the basis of the above, the gain of the first-stage error amplifier is improved, and the transient response of the output current is also enhanced.

[0017] In summary, this invention employs Cascode compensation technology to precisely control the zero-point position of an LDO circuit. This circuit not only solves the core problem of controlling the conjugate pole Q value under heavy load in Cascode compensation, which leads to low bandwidth and slow output transient response, but also further expands the bandwidth of the LDO under this compensation technology through reasonable structural arrangement, thus diversifying the application of Cascode compensation technology. Attached Figure Description

[0018] Figure 1 This is a circuit structure diagram of an LDO according to an embodiment of the present invention;

[0019] Figure 2 This is the schematic diagram of the LDO circuit of the present invention;

[0020] Figure 3 This is a diagram of the LDO small-signal model of the present invention;

[0021] Figure 4 The gain and phase margin curves of the LDO circuit of this invention are shown.

[0022] Figure 5 This is a Q-value distribution diagram of the conjugate poles under heavy load in the LDO circuit compensation circuit of the present invention;

[0023] Figure 6 This is a transient response characteristic diagram of the LDO circuit of the present invention. Detailed Implementation

[0024] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] Example:

[0026] like Figure 1 As shown, the LDO circuit in this example includes a classic first-stage error amplifier, a second-stage buffer, a third-stage output power transistor and feedback circuit, as well as a compensation module for precise zero control.

[0027] The first-stage error amplifier uses source degradation resistors to improve output linearity and current multiplication technology to enhance the gain and loop bandwidth of the first-stage error amplifier; the second-stage buffer drives the output power transistor; the third-stage output power transistor and feedback circuit are used to output a 3.3V voltage with lower ripple.

[0028] The first-stage error amplifier includes input transistors MN1 and MN2; bias transistors MN3 and MN4; active load transistors MP1 and MP3; source degradation resistor Rs; and the drain of PMOS transistor PM1 is connected to an ideal current source I. senseThe source of PMOS transistor PM1 and the drain of PMOS transistor PM2 are simultaneously connected to an ideal voltage source VCC; the source S2 of PMOS transistor PM2 is connected to capacitor C1, and the other end of capacitor C1 is connected to a second ideal voltage source.

[0029] The precise zero-point control compensation module achieves linear change in zero-point position following the load current by replacing the resistor in the Cascode compensation loop with a controlled resistor.

[0030] The second-stage buffer contains MOSFETs MN7 and MP5; resistor Rs1 is connected to the source of MN7; resistor R1 is connected to the gate of MP5 and is also connected to the input voltage VIN.

[0031] The output power transistor is a PDEMOS transistor MP, and the feedback circuit includes resistors RFB1', RFB1", and RFB2;

[0032] The zero-point control compensation module comprises three parts: the first part is the compensation section, including capacitor Ccl and the equivalent controlled resistor MOSFET MPC; the second part is the current-controlled resistor section, including the mirror transistor MS, MOSFETs MN8 and MN7, and current-controlled resistor MOSFETs MPs; the third part is the OTA amplifier, including MOSFETs MN10, MN1, MP6, MP7, MN12, MN13, MP8, and capacitor Cm. The drain-source resistance Rds of the equivalent controlled resistor MOSFET MPC in the compensation section changes linearly with the load current, controlling the zero point generated by MOSFET MPC and capacitor Ccl. Cascode compensation is used. MOSFETs MN8 and MN7 in the compensation section, along with the current-controlled resistor MOSFETs MPs, control MPs to convert the mirror current of the output power transistor into the gate voltage of MPs, thereby controlling the equivalent drain-source resistance of MPC. In this example, the LDO circuit can achieve a bandwidth of up to 600kHz under an output current of 400mA by controlling the equivalent resistance Rds of PMOS transistor PM2. ds2 Under heavy load, the Q value of the conjugate pole drops to 0.5~0.7, no frequency spikes appear, the phase margin is above 45°, and the response time is less than or equal to 1us when the load changes from 0 to 400mA step.

[0033] like Figure 3 The diagram shown is a complete small-signal model of the LDO circuit in this example. The first-stage error amplifier uses a source degradation resistor to improve the linearity of the output, and a current multiplication technique is used to improve the gain and loop bandwidth of the first-stage error amplifier. The gain of the first-stage error amplifier can be expressed by the formula:

[0034]

[0035] Where g mN1It is the small-signal transconductance of MOSFET MN1, r o1 It is the output impedance of the first-stage error amplifier, g mN1 It is the small-signal transconductance of MOSFET MN1, R s It is the source degradation resistor.

[0036] The second-stage buffer drives the output power transistor. The gain of the second-stage buffer can be expressed by the formula:

[0037]

[0038] Where g mN7 It is the small-signal transconductance of MOSFET MN7, g mP5 R1 is the small-signal transconductance of MOSFET MP5, and R1 is used to provide bias current under light load.

[0039] The third-stage output power transistor and feedback circuit are used to output a 3.3V voltage with lower ripple. The gain of the third-stage output power transistor can be expressed by the formula:

[0040]

[0041] Where g mP It is the small-signal transconductance of the output power transistor, R oeq It is the output equivalent resistance, R load It is the load resistance, r ds,MP It is the equivalent resistance of the power transistor.

[0042] By breaking the loop at the feedback point, the open-loop gain expression can be obtained as follows:

[0043]

[0044]

[0045]

[0046]

[0047] Where R FB1 R FB2 It is the feedback resistor g mN6 C1 is the small-signal transconductance of MOSFET MN6, and C1 is the equivalent capacitance of the first-stage error amplifier output. cl It is a compensation capacitor, C OUT It is the load equivalent capacitance, R c It is the equivalent capacitance of a controlled resistor.

[0048] From the open-loop gain expression, we can see that the pole and zero locations under light load are expressed as follows:

[0049]

[0050]

[0051]

[0052] The precise zero-point control compensation module achieves linear change in zero-point position following the load current by replacing the resistor in the Cascode compensation loop with a controlled resistor.

[0053] like Figure 4 As shown, under light load, the controlled resistor follows the load current to compensate for the position of the secondary point; under heavy load, the controlled resistor compensates for the Q value of the conjugate pole.

[0054] From the open-loop gain expression, we can see that under heavy load, the expression for the Q value of the conjugate pole is as follows:

[0055]

[0056] like Figure 5 As shown, by appropriately setting the value of the controlled resistor, the Q value compensation of the conjugate pole is made between 0.5 and 0.7, reducing the oscillation of the transient output caused by the conjugate frequency spike. In this example, the transient output is as follows: Figure 6 As shown.

Claims

1. An LDO circuit that achieves precise control of zero position through Cascode compensation, characterized in that, It includes a first-stage error amplifier, a second-stage buffer, a third-stage output power transistor, a feedback circuit, and a compensation module for precise zero-point control; The first-stage error amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a first resistor. The source of the first PMOS transistor MP1 is connected to the power supply of the first-stage error amplifier, and its gate and drain are interconnected. The drain of the first NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP1, the gate of the first NMOS transistor MN1 is connected to the feedback voltage, and the source of the first NMOS transistor MN1 is connected to one end of the first resistor and the drain of the third NMOS transistor MN3. The gate of the third NMOS transistor MN3 is connected to the bias voltage, and its source is grounded. The source of the second PMOS transistor MP2 is connected to the power supply of the first-stage error amplifier, and its gate... The drain of the first PMOS transistor MP1 is connected to the drain of the second PMOS transistor MP2, which is connected to the drain and gate of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor M6. The source of the third PMOS transistor MP3 is connected to the power supply of the first-stage error amplifier, and its gate and drain are interconnected. The drain of the second NMOS transistor MN2 is connected to the drain of the third PMOS transistor MP3, and the gate of the second NMOS transistor MN2 is connected to the reference voltage. The source of the second NMOS transistor MN2 is connected to the other end of the first resistor and the drain of the fourth NMOS transistor MN4. The source of the fourth PMOS transistor MP4 is connected to the power supply of the first-stage error amplifier, and its gate is connected to the drain of the third PMOS transistor MP3. The drain of the fourth PMOS transistor MP4 is connected to the drain of the sixth NMOS transistor MN6. The sources of the fourth NMOS transistor MN3, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 are grounded. The second-stage buffer includes a fifth PMOS transistor MP5, a seventh NMOS transistor MN7, a second resistor, and a third resistor. The source of the fifth PMOS transistor MP5 is connected to the input voltage, and its gate and drain are interconnected and connected to one end of the second resistor. The other end of the second resistor is connected to the input voltage. The drain of the seventh NMOS transistor MN7 is connected to the drain of the fifth PMOS transistor MP5, the gate of the seventh NMOS transistor MN7 is connected to the drain of the fourth PMOS transistor MP4, and the source of the seventh NMOS transistor MN7 is grounded through the third resistor. The source of the output power transistor is connected to the input voltage, the gate is connected to one end of the second resistor, and the drain is connected to the feedback circuit. The feedback circuit includes a fourth resistor, a fifth resistor, and a sixth resistor. One end of the fourth resistor is connected to the drain of the output power transistor, and the other end of the fourth resistor is grounded after passing through the fifth resistor and the sixth resistor in sequence. The connection point between the fourth resistor and the output power transistor is defined as the first feedback point, the connection point between the fourth resistor and the fifth resistor is defined as the second feedback point, and the connection point between the fifth resistor and the sixth resistor is defined as the third feedback point. The feedback voltage output at the third feedback point is connected to the gate of the first NMOS transistor MN1. The precise zero-point control compensation module includes a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor M11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a first capacitor, a second capacitor, a mirror MOS transistor, a controlled resistor MOS transistor, and a current-controlled resistor MOS transistor. One end of the first capacitor is connected to the drain of the second PMOS transistor MP2, and the other end of the first capacitor is connected to the source of the controlled resistor MOS transistor. The drain of the controlled resistor MOS transistor is connected to the first feedback point, and its gate is connected to the drain of the eighth PMOS transistor MP8. The source of the mirror MOS transistor is connected to the input voltage, its gate is connected to one end of the second resistor, and its drain is connected to the drain of the eighth NMOS transistor MN8. The source of the current-controlled resistor MOS transistor is connected to the first feedback point, its gate is connected to the drain of the eighth PMOS transistor MP8, and its drain is connected to the drain of the ninth NMOS transistor MN9 and the gate of the eleventh NMOS transistor MN11. The eighth NMOS transistor M11... The gate of N8 is connected to the gate of the ninth NMOS transistor MN9, and the sources of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are grounded; the source of the sixth PMOS transistor MP6 is connected to the input voltage, and its gate and drain are interconnected; the drain of the tenth NMOS transistor MN10 is connected to the drain of the sixth PMOS transistor MP6, the gate of the tenth NMOS transistor MN10 is connected to the second feedback point, and the source of the tenth NMOS transistor MN10 is connected to the source of the eleventh NMOS transistor MN11 and the drain of the twelfth NMOS transistor MN12; the seventh PMOS transistor... The source of S-MOSFET MP7 is connected to the input voltage, and its gate is connected to the drain of the sixth PMOS transistor MP6. The drain of the seventh PMOS transistor MP7 is connected to one end of the second capacitor, the gate of the eighth PMOS transistor MP8, and the drain of the eleventh NMOS transistor MN11. The gate of the twelfth NMOS transistor MN12 is connected to the bias voltage, and its source is grounded. The source of the eighth PMOS transistor MP8 is connected to the input voltage, and its drain is connected to the other end of the second capacitor and the drain of the thirteenth NMOS transistor M13. The gate of the thirteenth NMOS transistor MN13 is connected to the bias voltage, and its source is grounded.

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