Virtual clock device, time synchronization method, device, equipment and storage medium

Abstract

A virtual clock device, a time synchronization method, a device, equipment and a storage medium are disclosed, and relate to the technical field of time management and time synchronization. The device comprises a processor. The processor determines a frequency adjustment signal corresponding to a virtual clock based on a target time error between a target hardware clock and the virtual clock within a time synchronization period of the virtual clock and the target hardware clock. The processor resets a first time parameter of the virtual clock in a previous time synchronization period based on the frequency adjustment signal, obtains a second time parameter of the virtual clock, and writes the second time parameter into a shared memory. The processor reads the second time parameter from the shared memory in response to a time reading request of the virtual clock by an application program, and determines a current virtual time of the virtual clock based on the second time parameter and a time value of a hardware monotonic clock at a current time. The device can establish a high-precision smooth synchronization mechanism between the two time axes of the virtual clock and the target hardware clock, and the reading overhead is very low.

Description

Technical Field

[0001] This disclosure relates to the field of time management and time synchronization technology, and in particular to a virtual clock device, time synchronization method, apparatus, device and storage medium. Background Technology

[0002] The reliable operation of intelligent driving systems typically relies on at least two independent timelines. Within this framework, the perception pipeline places extremely high demands on the frequency of timestamp readings, while existing time synchronization solutions generally have limitations, making it difficult to balance multi-timeline support with low read overhead.

[0003] While the operating system can provide system time with extremely low overhead through the Virtual Dynamically-linked Shared Object (VDSO) mechanism, this mechanism only supports a single time axis and cannot adapt to the multi-time axis application scenarios of intelligent driving systems. If the perception pipeline directly reads the Precision Time Protocol (PTP) hardware clock (PHC) of the network card at high frequency, each read will trigger system calls and kernel driver lock contention, generating a large amount of kernel-mode overhead. This will lead to a sharp increase in the utilization of central processing unit (CPU) resources, which will seriously affect the overall performance of the intelligent driving system.

[0004] Therefore, how to achieve high-frequency, low-overhead time synchronization while supporting multiple time axes has become a key and urgent problem to be solved in the field of time management for intelligent driving systems. Summary of the Invention

[0005] Existing virtual clock devices either cannot adapt to the multi-time axis application scenarios of the system, or have very high read overhead, affecting the overall system performance, making it difficult to balance the requirements of multi-time axis adaptation and low overhead.

[0006] To address the aforementioned technical problems, a first aspect of this disclosure provides a virtual clock device, which includes a processor configured to: Within the time synchronization period between the virtual clock and the target hardware clock, the target time error between the target hardware clock and the virtual clock is determined; wherein, the virtual clock is constructed using a hardware monotonic clock as the underlying time reference; Based on the target time error, determine the frequency adjustment signal corresponding to the virtual clock; Based on the frequency adjustment signal, the first time parameter of the virtual clock in the previous time synchronization cycle is reset to obtain the second time parameter of the virtual clock; wherein, the second time parameter is used in conjunction with the frequency adjustment signal to ensure that the time of the virtual clock is continuous and monotonic; Write the second time parameter to shared memory; In response to an application's request to read the virtual clock's time, a second time parameter is read from shared memory. Based on the second time parameter and the time value of the hardware monotonic clock at the current moment, the current virtual time of the virtual clock is determined.

[0007] A second aspect of this disclosure provides a time synchronization method applied to a virtual clock device, the method comprising: Within the time synchronization period between the virtual clock and the target hardware clock, the target time error between the target hardware clock and the virtual clock is determined; wherein, the virtual clock is constructed using a hardware monotonic clock as the underlying time reference; The frequency adjustment signal is determined based on the target time error; Based on the frequency adjustment signal, the first time parameter of the virtual clock in the previous time synchronization cycle is reset to obtain the second time parameter of the virtual clock; wherein, the second time parameter is used in conjunction with the frequency adjustment signal to ensure that the time of the virtual clock is continuous and monotonic; Write the second time parameter to shared memory; In response to an application's request to read the virtual clock's time, a second time parameter is read from shared memory. Based on the frequency adjustment signal, the second time parameter, and the time value of the hardware monotonic clock at the current moment, the current virtual time of the virtual clock is determined.

[0008] A third aspect of this disclosure provides a time synchronization device, the device comprising: The first determining module is used to determine the target time error between the target hardware clock and the virtual clock within the time synchronization period between the virtual clock and the target hardware clock; wherein, the virtual clock is constructed with a hardware monotonic clock as the underlying time reference; The second determining module is used to determine the frequency adjustment signal based on the target time error; The reset module is used to reset the first time parameter of the virtual clock in the previous time synchronization cycle based on the frequency adjustment signal, so as to obtain the second time parameter of the virtual clock; wherein, the second time parameter is used in conjunction with the frequency adjustment signal to ensure that the time of the virtual clock is continuous and monotonic. The write module is used to write the second time parameter to shared memory; The third determining module is used to respond to the application's request to read the time of the virtual clock, read the second time parameter from the shared memory, and determine the current virtual time of the virtual clock based on the frequency adjustment signal, the second time parameter and the time value of the hardware monotonic clock at the current moment.

[0009] A fourth aspect of this disclosure provides an electronic device including the processor described above and a memory for storing processor-executable instructions; the processor is configured to read executable instructions from the memory and execute the instructions to implement the time synchronization method of the second aspect described above.

[0010] A fifth aspect of this disclosure provides a computer-readable storage medium storing a computer program for performing the time synchronization method provided in the second aspect above.

[0011] A sixth aspect of this disclosure provides a computer program product that, when instructions in the computer program product are executed by a processor, performs the time synchronization method provided in the second aspect described above.

[0012] The virtual clock device provided in this disclosure involves two time axes: a virtual clock and a target hardware clock. Since the target time error between the target hardware clock and the virtual clock reflects their time deviation during time synchronization, the processor, within the time synchronization period of the virtual clock and the target hardware clock, determines the frequency adjustment signal corresponding to the virtual clock based on the target time error, and resets the first time parameter of the virtual clock in the previous time synchronization period based on the frequency adjustment signal, thereby obtaining a second time parameter of the virtual clock that reflects the time synchronization state and continuous monotonicity calibration result. Furthermore, based on this second time parameter, the time of the virtual clock can be gradually calibrated to the time of the target hardware clock without disrupting time continuity, resulting in a highly stable and accurate virtual clock source. Simultaneously, after obtaining the second time parameter and writing it to shared memory, when the application reads the time, it only needs to read the time parameter from the shared memory and perform simple calculations in conjunction with the current value of the hardware monotonic clock, without directly calling or accessing the hardware clock or performing complex real-time calculations through the kernel, significantly reducing system call and computational overhead and improving the response speed and efficiency of time queries. Thus, a high-precision, smooth synchronization mechanism was established between the virtual clock and the target hardware clock, while providing the application with a low-overhead read interface. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the structure of a virtual clock device provided in an exemplary embodiment of the present disclosure.

[0014] Figure 2This is a flowchart illustrating a time synchronization method provided in an exemplary embodiment of this disclosure.

[0015] Figure 3 This is a flowchart illustrating another time synchronization method provided by an exemplary embodiment of the present disclosure.

[0016] Figure 4 This is a flowchart illustrating another time synchronization method provided by an exemplary embodiment of this disclosure.

[0017] Figure 5 This is a flowchart illustrating another time synchronization method provided by an exemplary embodiment of this disclosure.

[0018] Figure 6 This is a flowchart illustrating another time synchronization method provided by an exemplary embodiment of this disclosure.

[0019] Figure 7 This is a flowchart illustrating another time synchronization method provided by an exemplary embodiment of this disclosure.

[0020] Figure 8 This is a flowchart illustrating another time synchronization method provided by an exemplary embodiment of this disclosure.

[0021] Figure 9 This is a flowchart illustrating another time synchronization method provided by an exemplary embodiment of this disclosure.

[0022] Figure 10 This is a flowchart illustrating another time synchronization method provided by an exemplary embodiment of this disclosure.

[0023] Figure 11 This is a schematic diagram of the structure of a time synchronization device provided in an exemplary embodiment of the present disclosure.

[0024] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of the present disclosure. Detailed Implementation

[0025] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0026] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0027] Application Overview With the widespread application of kernels (such as Linux) in the perception domain of intelligent driving, their time systems face new challenges in managing multiple time axes. Typical intelligent driving systems usually rely on two independent time axes: Management plane time axis: Used to synchronize with global time sources such as Global Navigation Satellite System (GNSS) / or Global Positioning System (GPS) to obtain absolute time, but time jumps may occur when the signal is lost / regained.

[0028] Sensor domain time axis: It operates independently based on a local clock, requires high stability, and can support high-frequency, low-jitter readings to ensure consistency of sensor timestamp fusion, triggering, and causality.

[0029] However, the relevant system time architecture is difficult to support this dual timeline requirement, and the specific contradictions include: 1. A single system time cannot meet the needs of multi-time axis scenarios.

[0030] The kernel only provides a fast user-space read path for system time such as CLOCK_REALTIME through the VDSO mechanism, lacking a second time axis with equivalent "fast read" capability.

[0031] 2. The hardware monotonic clock CLOCK_MONOTONIC_RAW cannot be aligned with an external time base.

[0032] Although hardware monotonic clocks such as CLOCK_MONOTONIC_RAW have fast read speeds, averaging about 40 nanoseconds, they are purely local hardware timers and cannot be adjusted by software programs. Therefore, they cannot be synchronized with external time bases (such as PHC or GNSS) and cannot meet business time alignment requirements.

[0033] 3. Directly reading PHC results in excessive overhead and jitter.

[0034] If the PHC (Physical Layer Clock) is read directly at high frequency, each read will require entering the kernel and may trigger low-level lock contention, significantly increasing the time consumption (reaching or even exceeding 1000 nanoseconds), causing a sharp increase in CPU resource utilization and seriously affecting the overall performance of the autonomous driving system.

[0035] In summary, how to achieve high-frequency, low-overhead time synchronization while supporting multiple time axes has become a critical and urgent problem to be solved in the field of time management for intelligent driving systems.

[0036] To address the aforementioned technical problems, this disclosure proposes a virtual clock device. The processor, within a time synchronization period between the virtual clock and a target hardware clock, determines a frequency adjustment signal corresponding to the virtual clock based on the target time error between the target hardware clock and the virtual clock. Based on this frequency adjustment signal, the processor resets the first time parameter of the virtual clock in the previous time synchronization period to obtain a second time parameter. Furthermore, the second time parameter is written to shared memory. When the application reads the virtual clock's time, the second time parameter is read from the shared memory. Based on the second time parameter and the current time value of the virtual clock's underlying time base (hardware monotonic clock), the current virtual time of the virtual clock is determined.

[0037] Since this virtual clock device involves two time axes—a virtual clock and a target hardware clock—and the target time error between the virtual clock and the target hardware clock reflects their time deviation during the time synchronization process, the processor, within the time synchronization period between the virtual clock and the target hardware clock, determines the frequency adjustment signal corresponding to the virtual clock based on the target time error, and resets the first time parameter of the virtual clock in the previous time synchronization period based on the frequency adjustment signal. This yields the second time parameter of the virtual clock, which reflects the time synchronization status and continuous monotonicity calibration results. Furthermore, based on this second time parameter, the virtual clock's time can be gradually calibrated to the target hardware clock's time without disrupting time continuity, resulting in a highly stable and accurate virtual clock source. Simultaneously, after obtaining the second time parameter and writing it to shared memory, when the application reads the time, it only needs to read the time parameter from shared memory and perform simple calculations based on the current value of the hardware monotonic clock. There is no need to directly call or access the hardware clock, nor is there a need for complex real-time calculations through the kernel, significantly reducing system calls and computational overhead, and improving the response speed and efficiency of time queries. Thus, a high-precision, smooth synchronization mechanism was established between the virtual clock and the target hardware clock, while providing the application with a low-overhead read interface.

[0038] Exemplary virtual clock device Figure 1 This is a schematic diagram of the structure of a virtual clock device provided in an exemplary embodiment of this disclosure. Figure 1 As shown, the virtual clock device 10 includes a processor 101. The processor 101 is configured to: Within the time synchronization period between the virtual clock and the target hardware clock, determine the target time error between the target hardware clock and the virtual clock; Based on the target time error, the frequency adjustment signal corresponding to the virtual clock is determined; the virtual clock is constructed using a hardware monotonic clock as the underlying time reference. Based on the frequency adjustment signal, the first time parameter of the virtual clock in the previous time synchronization cycle is reset to obtain the second time parameter of the virtual clock; wherein, the second time parameter is used in conjunction with the frequency adjustment signal to ensure that the time of the virtual clock is continuous and monotonic; Write the second time parameter to shared memory; In response to an application's request to read the virtual clock's time, a second time parameter is read from shared memory. Based on the second time parameter and the time value of the hardware monotonic clock at the current moment, the current virtual time of the virtual clock is determined.

[0039] Processor 101 refers to a processing device used to execute software processing programs to achieve virtual clock calibration, etc. Its specific implementation can be flexibly selected according to the deployment scenario of the virtual clock device 10. In high-performance computing platforms such as intelligent driving domain controllers, processor 101 may include a CPU, a microcontroller unit (MCU), or an embedded processing unit. This disclosure does not limit the type of processor 101; however, this disclosure uses a CPU as an example for illustrative purposes.

[0040] A hardware monotonic clock is a strictly monotonically increasing hardware clock whose count value increases only with physical time and will not roll back or jump due to any operation such as manual modification of the system time, switching of clock sources, or changes in system state.

[0041] In some examples, a hardware monotonic clock can be constructed based on physical timing elements such as a local crystal oscillator or a micro-electro-mechanical system (MEMS) resonator. Taking the Linux kernel as an example, the hardware monotonic clock can be the CLOCK_MONOTONIC_RAW, which has the lowest overhead in the Linux system. This disclosure does not limit the specific type of hardware monotonic clock; this disclosure uses CLOCK_MONOTONIC_RAW as an example for illustrative purposes.

[0042] A virtual clock is a software clock that uses a hardware monotonic clock as its underlying time base and calculates its time value through a software program. In some examples, the time of the virtual clock can be determined based on the current time value of the hardware monotonic clock and a pre-built time mapping relationship between the hardware monotonic clock and the virtual clock.

[0043] The target hardware clock is a hardware clock that provides an external time reference to the virtual clock, and its specific form can be determined according to the system architecture requirements.

[0044] In some examples, the target hardware clock can be a PHC that is synchronized with a global time source such as GNSS / GPS via the PTP protocol, or it can be other external clock sources with high-precision timing capabilities, such as a time-to-digital converter (TDC) implemented with a field-programmable gate array (FPGA). This disclosure does not limit the type of target hardware clock; however, this disclosure uses a PHC as an example for illustrative purposes.

[0045] The time synchronization period between the virtual clock and the target hardware clock can be determined according to the application scenario and protocol type. This disclosure does not limit the specific value of the time synchronization period. This disclosure uses a time synchronization period of 1 second as an example for illustrative explanation.

[0046] The target time error is used to characterize the time error between the virtual clock and the target hardware clock within the time synchronization period.

[0047] Frequency adjustment signal refers to the control signal used to adjust the running frequency of the virtual clock relative to the hardware monotonic clock.

[0048] For example, the processor 101 can first perform multiple time samplings on the virtual clock and the target hardware clock within the time synchronization period between the virtual clock and the target hardware clock, and then determine the target time error between the target hardware clock and the virtual clock based on the multiple time sampling data; then, process the target time error to obtain a frequency adjustment signal.

[0049] The first time parameter refers to the parameter used to reflect the time mapping relationship between the hardware monotonic clock and the virtual clock within the previous time synchronization cycle. In some examples, the first time parameter may include the virtual time start point v_ref(k-1) of the previous time synchronization cycle (the virtual time corresponding to the anchor point), the hardware monotonic clock time t_ref(k-1) corresponding to the time start point v_ref(k-1) (the reference anchor point of the hardware monotonic clock domain), and the frequency correction rate_ppb(k-1) used to characterize the frequency deviation between the virtual clock and the hardware monotonic clock within the previous time synchronization cycle. Here, k is an integer greater than or equal to 1, representing the current time synchronization cycle, and k-1 represents the previous time synchronization cycle.

[0050] The second time parameter refers to the parameter obtained after resetting the first time parameter, and is used to reflect the time mapping relationship between the hardware monotonic clock and the virtual clock within the current time synchronization period. In some examples, the second time parameter may include the virtual time start point v_ref(k) of the current time synchronization period, the hardware monotonic clock time t_ref(k) corresponding to the time start point v_ref(k), and the frequency correction rate_ppb(k) used to characterize the frequency deviation between the virtual clock and the hardware monotonic clock within the current time synchronization period.

[0051] The processor 101 can reset the first time parameter based on the frequency adjustment signal using the pivot equal-value rebase algorithm to obtain the second time parameter.

[0052] Shared memory can be created during system initialization and can be used to provide a zero-copy, lock-free, high-concurrency data exchange channel between processor 101 and applications. It adopts a single-write-multiple-read (1W-NR) architecture, with write operations performed by a time synchronization process and multiple application processes completing high-frequency reads with lock-free, constant-time complexity.

[0053] In some examples, shared memory can adopt a fast read-first design, where reading virtual time only requires accessing the fewest critical fields, and a consistent snapshot mechanism ensures that the read time parameters are of the same version, avoiding data tearing; at the same time, access efficiency is improved through cache line alignment and cache-friendly layout, and standard Portable Operating System Interface (POSIX) interfaces (such as shm_open, ftruncate, mmap) are supported without kernel modification.

[0054] The layout of shared memory can be as follows: +-------------------------+ Offset 0x0000 (Cache line 0) | magic (u32) | | version (u32) | | seq (atomic u32) | / / seqlock count: even = stable, odd = in progress | flags (u32) | / / Reserved: status bits / feature bits | domain_id (u32) | / / Logical instance number ( / vtimeX) | reserved

[11] u32 | / / Alignment padding for easier future expansion +----------------------+ Offset 0x0040 (Cache line 1) Fast Path (Core triplet) | t_ref_ns (s64) | / / MONOTONIC_RAW anchor point | virt_ref_ns (s64) | / / Virtual time corresponding to the anchor point | rate_ppb (s64) | / / Frequency correction | fast_pad[5] s64 | / / Fill the entire row to avoid contamination of subsequent fields. +----------------------+ Offset 0x0080 (Cache line 2) Fast Path Auxiliary / Snapshot | last_mono_ns (s64) | / / The mono used in the most recent release | last_virt_ns (s64) | / / Virtual time calculated as above | ema_err_ns (s64) | / / EMA post-error (for diagnostic purposes) | servo_err_ns (s64) | / / This period represents the sample error | step0_done (s64) | / / First phase alignment marker | fp_aux_pad[3] s64 | +---------------------+ Offset 0x00C0 (Cache line 3) Policy / Limiting / Statistics (Cold Zone) | max_rate_ppb (s64) | | min_rate_ppb (s64) | | stats_xxx ... | / / Optional: Number of samples / alarm count, etc. | cold_pad[...] | The cache line 0 (offset 0x0000) is the header control area, used to implement the lock-free synchronization mechanism seqlock, verify the validity of shared memory, and distinguish between multiple clock instances; the cache line 1 (offset 0x0040) is the FastPath core triplet area, used to store the hardware monotonic clock reference anchor point, the corresponding virtual time reference value, and the frequency correction amount; the cache line 2 (offset 0x0080) is the Fast Path auxiliary / snapshot area, used for system debugging, status observation, and logging; the cache line 3 (offset 0x00C0) is the policy and statistics cold area, which is only used by the write process and not accessed by the read process. It is completely isolated from the fast path to avoid false cache sharing.

[0055] Processor 101 can first read the current value s of the seq variable from shared memory, and update the value of seq to s|1 through an atomic operation, that is, perform a bitwise OR operation between s and 1, set the least significant bit of seq to 1, making seq an odd number, and marking that it has entered the writing state; then, write the second time parameter sequentially to the Fast Path core triplet area of ​​shared memory; next, optionally write the auxiliary fields in the synchronization process to the Fast Path auxiliary / snapshot area of ​​shared memory; finally, set the value of seq to (s|1)+1 through an atomic operation, making seq an even number, indicating that the current version has been updated and is in a stable readable state, thereby realizing the writing of the second time parameter to shared memory.

[0056] When an application initiates a time read request for the virtual clock through a user-mode library function, the library function will directly access the second time parameter in shared memory, and then combine it with the current value of the hardware monotonic clock and the time mapping relationship between the hardware monotonic clock and the virtual clock to determine the current virtual time of the virtual clock.

[0057] The virtual clock device provided in this disclosure dynamically determines the frequency adjustment signal corresponding to the virtual clock based on the target time error between the target hardware clock and the virtual clock, and updates the time parameters of the virtual clock based on the frequency adjustment signal. This achieves high stability and high precision time synchronization while ensuring time continuity and monotonicity. Simultaneously, the final time parameters are written to shared memory, allowing the application program to directly read the final time parameters and calculate the current virtual time. This avoids frequent system calls and computational overhead, achieving a low-overhead, highly stable virtual clock.

[0058] For example, the processor 101 uses a high-precision hardware timer to perform periodic timing. When the time synchronization period arrives, the timer triggers an interrupt, and the processor 101 responds to the interrupt to initiate the time synchronization process between the virtual clock and the target hardware clock. During the time synchronization period, the processor 101 samples the virtual clock and the target hardware clock at least once to obtain time sample data, processes the time sample data, and obtains a frequency adjustment signal.

[0059] In some examples, processor 101 is specifically configured to: determine at least one set of time data packets corresponding to the virtual clock and the target hardware clock within the time synchronization period between the virtual clock and the target hardware clock; determine a target time error between the target hardware clock and the virtual clock based on the at least one set of time data packets; and perform filtering and frequency modulation processing on the target time error to obtain a frequency adjustment signal.

[0060] At least one set of time data packets may include one or more sets of time data packets. This disclosure does not limit the specific number of time data packets; however, this disclosure uses the example of at least one set of time data packets including multiple sets of time data packets for illustrative purposes. A set of time data packets refers to three time values ​​(phc1, Vt1, and phc2) obtained through three consecutive sampling actions within the same time sampling window, corresponding sequentially to the target hardware clock, virtual clock, and target hardware clock.

[0061] The processor 101 can temporarily switch the thread scheduling policy for executing the time sampling task to the highest priority at the start of the time synchronization period between the virtual clock and the target hardware clock, in order to minimize the uncertainty caused by the operating system scheduling and ensure the accuracy and determinism of the time sampling process. Then, multiple time samples are performed on the same time sampling window in the order of target hardware clock, virtual clock, and target hardware clock to obtain multiple sets of time data packets.

[0062] When each group of time data packets includes the first time value Vt1, the processor 101 can calculate the first time value Vt1 of the virtual clock at the sampling time based on the first time parameters including v_ref(k-1), t_ref(k-1) and rate_ppb(k-1) determined in the previous time synchronization cycle, the time value of the hardware monotonic clock at the sampling time, and the time mapping relationship between the pre-built hardware monotonic clock and the virtual clock.

[0063] In some examples, processor 101 may be specifically configured to: use the time parameter of the previous time synchronization cycle read from shared memory by the application as a first time parameter; read the time value of the hardware monotonic clock at the first sampling moment as a first current time value; determine the time mapping relationship between the pre-built hardware monotonic clock and the virtual clock; and calculate the first time value of the virtual clock at the first sampling moment based on the first time parameter, the first current time value, and the time mapping relationship; wherein the time data includes the first time value.

[0064] The first sampling moment refers to the moment when the data corresponding to the virtual clock is collected during the process of sequentially collecting a set of time data packets in the order of target hardware clock, virtual clock, and target hardware clock.

[0065] The time mapping relationship between the hardware monotonic clock and the virtual clock can be constructed during system initialization, and this time mapping relationship can be found in the following formula (1).

[0066] V(mono) = v_ref + ((mono - t_ref) (1000000000+rate_ppb)) / 1000000000 (1); Where V(mono) represents the current virtual time in nanoseconds (ns); v_ref represents the virtual time start point in nanoseconds; t_ref represents the hardware monotonic clock time corresponding to v_ref; and rate_ppb represents the frequency correction, the absolute value of which is usually 1. 10 5 ~ 5 10 5 (Corresponding to ±100 ~ ±500ppm), within the safe range for clock adjustment, it will not cause time jumps or abnormal drift. When rate_ppb>0, the virtual clock speeds up to catch up with the leading target hardware clock; when rate_ppb<0, the virtual clock slows down to wait for the lagging target hardware clock.

[0067] mono-t_ref represents the time elapsed since the start of the hardware monotonic clock; s=(1000000000+rate_ppb)) / 1000000000=1+rate_ppb / 1000000000 represents the ratio of the virtual clock's running rate to its underlying hardware monotonic clock, which can be called the slope or frequency scaling factor.

[0068] The processor 101 can perform three consecutive sampling operations. At the third sampling time t3, it acquires the target hardware clock time value to obtain a third time value phc1. Then, at the first sampling time t1, it acquires the virtual clock time value to obtain a first time value Vt1. Subsequently, at the second sampling time t2, it acquires the target hardware clock time value to obtain a second time value phc2. The third sampling time t3 is earlier than the first sampling time t1, and the first sampling time t1 is earlier than the second sampling time t2.

[0069] The processor 101 acquires the first time value Vt1 of the virtual clock by executing an application program. The process includes: reading the first time parameters v_ref(k-1), t_ref(k-1), and rate_ppb(k-1) determined and written after the end of the previous time synchronization cycle from the shared memory; then, reading the first current time value mono1 of the hardware monotonic clock at the first sampling moment and the above formula (1); substituting v_ref(k-1), t_ref(k-1), rate_ppb(k-1), and mono1 into formula (1) to calculate the time value of the virtual clock at the first moment, which is used as the first time value Vt1.

[0070] The virtual clock device provided in this embodiment calculates (rather than directly reads) the first time value of the virtual clock in real time based on the first time parameter of the previous synchronization cycle, the first current time value of the current hardware monotonic clock, and the pre-built time mapping relationship between the hardware monotonic clock and the virtual clock. This can filter out random errors in a single reading and obtain a stable and accurate first time value.

[0071] Taking at least one set of time data packets as an example, after acquiring the set of time data packets, the processor 101 determines its measurement delay. If the delay is less than a preset delay threshold, this data packet is identified as the target time data packet, and the time error between its corresponding virtual clock and the target hardware clock is identified as the target time error for subsequent frequency modulation processing. If the delay is greater than or equal to the preset threshold, it indicates that the current sampling is affected too much by random delays such as system interrupts and scheduling, and the processor 101 will abandon time synchronization for the current time synchronization period.

[0072] Taking at least one set of time data packets as an example, after acquiring multiple sets of time data packets, the processor 101 will determine the measurement delay of each set of time data packets, and based on the measurement delay of each set of time data packets, determine the target time error from the time error between the virtual clock corresponding to each set of time data packets and the target hardware clock.

[0073] In some examples, processor 101 is specifically configured to: determine the measurement delay corresponding to each set of time data packets and the time error between the virtual clock and the target hardware clock corresponding to each set of time data packets, based on at least one set of time data packets; and determine a target time error from at least one time error based on the measurement delay corresponding to each set of time data packets.

[0074] Each time data packet includes a first time value, a second time value, and a third time value corresponding to three consecutive sampling actions. The first time value is the time value of the virtual clock at the first sampling moment, the second time value is the time value of the target hardware clock at the second sampling moment, and the third time value is the time value of the target hardware clock at the third sampling moment. The third sampling moment is earlier than the first sampling moment, and the first sampling moment is earlier than the second sampling moment.

[0075] The processor 101 can calculate the measurement delay corresponding to the set of time data packets and the intermediate time value corresponding to the target hardware clock at the first sampling moment based on the second time value and the third time value in the set of time data packets, and determine the time error between the virtual clock corresponding to the time data packet and the target hardware clock based on the difference between the intermediate time value and the first time value.

[0076] In some examples, processor 101 is specifically configured to: determine the measurement delay corresponding to the time data packet based on the difference between the second time value and the third time value; determine the intermediate time value corresponding to the target hardware clock at the first sampling moment based on the second time value and the third time value; and determine the time error between the virtual clock corresponding to the time data packet and the target hardware clock based on the difference between the intermediate time value and the first time value. The processor 101 can calculate the difference between the second time value phc2 and the third time value phc1 to obtain the measurement delay corresponding to the time data packet delay=phc2-phc1; calculate the average value (phc1+phc2) / 2 of the second time value phc2 and the third time value phc1 as the intermediate time value t_mid=(phc1+phc2) / 2 corresponding to the first sampling time t1 of the target hardware clock; finally, calculate the difference t_mid-Vt1 between the intermediate time value t_mid and the first time value Vt1 as the time error e=t_mid-Vt1 between the virtual clock corresponding to the time data packet and the target hardware clock.

[0077] The virtual clock device provided in this disclosure can accurately calculate the measurement delay corresponding to the time data packet by using the difference between the second time value and the third time value, and more accurately evaluate the intermediate time value corresponding to the target hardware clock at the first sampling moment by averaging the two values. Based on this, the time error between the virtual clock corresponding to the time data packet and the target hardware clock can be accurately determined by using the difference between the intermediate time value and the first time value.

[0078] The controller 101 can determine the degree to which each group of time data packets is affected by random delays such as system interruptions and scheduling based on the measurement delay magnitude corresponding to each group of time data packets. Thus, from at least one time error, the time error corresponding to the time data packet that is least affected by random delays such as system interruptions and scheduling is taken as the target time error.

[0079] In some examples, controller 101 is specifically configured to: in response to the existence of a minimum measurement delay among the measurement delays corresponding to each group of time data packets, and the minimum measurement delay being less than a preset delay threshold, determine the group of time data packets corresponding to the minimum measurement delay as the target time data packet; and determine the time error between the virtual clock corresponding to the target time data packet and the target hardware clock as the target time error.

[0080] The preset delay threshold refers to the maximum tolerable time consumed in acquiring a set of time data packets, and can be determined according to the accuracy requirements of time synchronization. This disclosure does not limit the size of the preset delay threshold.

[0081] After acquiring each set of time data packets, the controller 101 calculates the corresponding measurement delay and continues acquiring data until the measurement delay of the current set of time data packets is less than a preset delay threshold, or the number of acquired time data packets reaches a preset number. Then, from all acquired data packets, the controller selects the set of time data packets with the smallest measurement delay and determines whether this smallest measurement delay is less than the preset delay threshold. If the smallest measurement delay is less than the preset delay threshold, the time data packet corresponding to the smallest measurement delay is taken as the target time data packet, and the time error between the virtual clock and the target hardware clock corresponding to the target time data packet is taken as the target time error. If the smallest measurement delay is greater than or equal to the preset delay threshold, time synchronization for this time synchronization cycle is abandoned.

[0082] The preset quantity refers to the maximum number of time data packet sampling groups pre-set for the time synchronization process. It is used to constrain the upper limit of the number of samplings within a single time synchronization cycle, preventing the sampling process from running indefinitely due to link anomalies or persistently high latency, thus ensuring the real-time performance and reliability of time synchronization. This disclosure does not limit the size of the preset quantity; however, this disclosure uses a preset quantity of 10 as an example for illustrative purposes.

[0083] The virtual clock device provided in this disclosure determines a set of time data packets corresponding to the minimum measurement delay as the target time data packet when the minimum measurement delay is less than a preset delay threshold. This filters out time data packets that are distorted due to excessive system delay, resulting in a target time data packet that is least affected by random delays such as system interruptions and scheduling. Furthermore, the time error between the virtual clock corresponding to the target time data packet and the target hardware clock is determined as the target time error. This enables the acquisition of high-quality data that best reflects the actual clock deviation, ensuring the accuracy and stability of time synchronization.

[0084] The processor 101 performs filtering and frequency modulation processing on the target time error to obtain a frequency adjustment signal. This may include sequentially performing sliding average filtering, proportional-integral adjustment, and amplitude limiting processing on the target time error to obtain a frequency adjustment signal.

[0085] In some examples, the processor 101 is specifically configured to: perform a moving average filtering process on the target time error to obtain a smoothed error value; process the smoothed error value based on a proportional-integral control algorithm to obtain a target frequency correction amount; and adjust the target frequency correction amount to a preset safe range to obtain a frequency adjustment signal.

[0086] Due to the target time error e k (The target time error corresponding to the current time synchronization period) is unstable and is affected by noise, latency jitter, and hardware fluctuations. Therefore, the processor 101 can adjust the target time error e for multiple consecutive periods. k Smoothing is performed to remove burrs and noise, resulting in a smoother and more reliable error smoothing value.

[0087] The processor 101 can use the Exponential Moving Average (EMA) algorithm for smoothing, as shown in formula (2) below.

[0088] EMA_k = (1-ɑ)× EMA_{k-1}+ɑ×e k (2); Where EMA_k represents the error smoothing value of the k-th time synchronization period, e k EMA_{k-1} represents the target time error calculated in the k-th time synchronization period, EMA_{k-1} represents the error smoothing value in the (k-1)-th time synchronization period, and α represents the smoothing coefficient, which is between 0 and 1. The larger α is, the faster the smoothing value responds and can quickly keep up with the real error changes, but it is more sensitive to noise and jitter; the smaller α is, the stronger the noise resistance and the more stable the result, but the speed of tracking changes will be slower. In the first period, the smoothing value can be directly set to equal the original error value (EMA0 = e0).

[0089] After obtaining the error smoothing value EMA_k, the processor 101 can input the error smoothing value EMA_k into the proportional-integral controller. The proportional-integral controller integrates and accumulates the error smoothing value EMA_k to obtain the integral term I_k, as shown in formula (3) below.

[0090] I_k=I_{k-1}+EMA_k (3; Where I_{k-1} represents the error smoothing value of the (k-1)th time synchronization period (relative to the previous time synchronization of I_k).

[0091] Next, the error smoothing value and integral term are weighted by the proportional coefficient Kp and the integral coefficient Ki respectively to obtain the rate correction amount Δr_k required for the current cycle, as shown in formula (4) below.

[0092] Δr_k=Kp×EMA_k +Ki×I_k (4); Next, the rate correction Δr_k corresponding to the kth time synchronization period is superimposed on the historical rate deviation to obtain the target frequency correction r_k, as shown in formula (5) below. r_k=r_{k-1}+Δr_k (5; Where r_{k-1} represents the target frequency correction amount for the (k-1)th time synchronization period.

[0093] Since the target frequency correction amount r_k being too large or too small will affect the output safety, the controller 101 can limit the target frequency correction amount r_k based on the minimum safety threshold r_min and the maximum safety threshold r_max, adjust the target frequency correction amount r_k to the preset safety range, and obtain the output safe and executable frequency adjustment signal rate_ppb, see formula (6) below.

[0094] rate_ppb=clip(r_k, r_min, r_max) (6); Here, clip() is the clipping function.

[0095] The virtual clock device provided in this disclosure can effectively suppress error fluctuations caused by transmission jitter, noise, and measurement anomalies during time synchronization by performing sliding mean filtering on the target time error, thereby improving the stability and reliability of error data. Based on a proportional-integral control algorithm, the error smoothing value is processed, enabling rapid adjustment of instantaneous time errors and precise elimination of long-term static frequency offset and accumulated errors, thus improving the convergence speed and steady-state accuracy of clock synchronization. Limiting the target frequency correction within a preset safety range avoids problems such as sudden clock frequency changes and system synchronization failures caused by excessively large or small frequency adjustment amplitudes, thereby ensuring a smooth, safe, and reliable clock frequency adjustment process.

[0096] In some embodiments, the processor 101 is specifically configured to: in response to initiating a pivot equivalent rebase processing flow, read the time value of the hardware monotonic clock at the current moment as a second current time value; determine a pivot point based on the second current time value; determine a first virtual time corresponding to the virtual clock at the pivot point based on a first time parameter and the pivot point; and determine a second time parameter of the virtual clock based on the pivot point, the first virtual time, and a frequency adjustment signal.

[0097] The pivot point mono_pivot is the time anchor point selected to achieve smooth frequency adjustment of the virtual clock. It is used to ensure that the old and new time mapping curves are strictly equal at this point when the frequency switches, thereby achieving a smooth transition without steps or time rollback.

[0098] Taking the second time parameters including v_ref(k), t_ref(k), and rate_ppb(k) as an example. When the processor 101 decides to start the rebase process, it immediately reads the hardware monotonic clock and uses the read current time value as the second current time value. Then, it directly uses the second current time value as the pivot point mono_pivot. Next, it substitutes the first time parameter and the pivot point mono_pivot into the above formula (1) to calculate the old virtual time V_old(mono_pivot) corresponding to the pivot point mono_pivot as the first virtual time. Finally, it uses the pivot point mono_pivot as the new anchor point of the virtual clock (t_ref_new = mono_pivot), that is, taking the pivot point mono_pivot as t_ref(k) of the current k-th time synchronization cycle, taking the first virtual time V_old(mono_pivot) as the virtual time corresponding to the new anchor point, that is, taking V_old(mono_pivot) as the virtual clock start point v_ref(k) of the current k-th time synchronization cycle, and taking the frequency adjustment signal rate_ppb as the frequency correction rate_ppb(k) of the frequency deviation between the virtual clock and the hardware monotonic clock in the previous k-th time synchronization cycle.

[0099] The virtual clock device provided in this disclosure determines a pivot point based on reading the time value of a hardware monotonic clock at the current moment; it determines a first virtual time corresponding to the pivot point based on a first time parameter and the pivot point; and it determines a second time parameter of the virtual clock based on the pivot point, the first virtual time, and a frequency adjustment signal. This not only corrects the accumulated time error of the old parameters but also sets a better clock rate, thereby enabling the virtual clock to run more stably and accurately in the future. At the same time, it ensures an absolutely smooth transition from the old parameters to the new parameters without any time jumps.

[0100] In some examples, processor 101 is specifically configured to: in response to an application's request to read the time of the virtual clock, control the application to read a second time parameter from the shared memory; read the time value of the hardware monotonic clock at the current moment as a third current time value; and determine the current virtual time of the virtual clock based on the second time parameter, the third current time value, and a pre-built time mapping relationship between the hardware monotonic clock and the virtual clock.

[0101] Taking the second time parameters including v_ref(k), t_ref(k), and rate_ppb(k) as an example, the processor 101 responds to the application's request to read the virtual clock time and controls the application to perform the following steps: First, under the read protection of the sequence lock, v_ref(k), t_ref(k), and rate_ppb(k) are atomically read from the shared memory; then, the time value of the hardware monotonic clock at the current moment is read to obtain the third current time value mono3, and v_ref(k), t_ref(k), rate_ppb(k), and mono3 are substituted into formula (1) to calculate the current virtual time Vt of the virtual clock.

[0102] The virtual clock device provided in this disclosure determines the current virtual time of the virtual clock in real time based on a second time parameter, a third current time value of the hardware monotonic clock at the current moment, and a pre-built time mapping relationship between the hardware monotonic clock and the virtual clock. It can filter out random errors in a single read and obtain a stable and accurate current virtual time of the virtual clock, ultimately realizing a high-precision virtual time reading mechanism with high concurrency, low latency, and consistent data.

[0103] Exemplary methods Corresponding to the virtual clock device provided in the above embodiments, this disclosure also provides a time synchronization method.

[0104] Figure 2 This is a flowchart illustrating an exemplary embodiment of the time synchronization method provided in this disclosure. Figure 2 As shown, this time synchronization method can be applied to, for example... Figure 1 The virtual clock device 10 shown may include the following steps 201 to 205.

[0105] Step 201: Within the time synchronization period between the virtual clock and the target hardware clock, determine the target time error between the target hardware clock and the virtual clock.

[0106] The virtual clock is built using a hardware monotonic clock as its underlying time reference.

[0107] Step 202: Determine the frequency adjustment signal based on the target time error.

[0108] Step 203: Based on the frequency adjustment signal, reset the first time parameter of the virtual clock in the previous time synchronization cycle to obtain the second time parameter of the virtual clock.

[0109] The second time parameter is used in conjunction with the frequency adjustment signal to ensure that the virtual clock's time is continuously monotonic.

[0110] Step 204: Write the second time parameter into shared memory.

[0111] Step 205: In response to the application's request to read the virtual clock's time, read the second time parameter from shared memory, and determine the current virtual time of the virtual clock based on the frequency adjustment signal, the second time parameter, and the time value of the hardware monotonic clock at the current moment.

[0112] like Figure 3 As shown above, in the above Figure 2 Based on the illustrated embodiment, determining the target time error between the target hardware clock and the virtual clock in step 201 may include the following steps 2011 and 2012.

[0113] Step 2011: Within the time synchronization period between the virtual clock and the target hardware clock, determine at least one set of time data packets corresponding to the virtual clock and the target hardware clock.

[0114] Step 2012: Determine the target time error between the target hardware clock and the virtual clock based on at least one set of time data packets.

[0115] Continue to refer to Figure 3 As shown, step 202 determines the frequency adjustment signal corresponding to the virtual clock based on the target time error, including the following step 2021.

[0116] Step 2021: Filter and frequency modulate the target time error to obtain a frequency adjustment signal.

[0117] like Figure 4 As shown, the time data includes the first time value, in the above... Figure 3Based on the embodiment shown, step 2011 determines a set of time data packets corresponding to the virtual clock and the target hardware clock, including the following steps 401 to 404.

[0118] Step 401: Use the time parameter of the previous time synchronization period read from shared memory by the application as the first time parameter; Step 402: Read the time value of the hardware monotonic clock at the first sampling moment and use it as the first current time value; Step 403: Determine the time mapping relationship between the pre-built hardware monotonic clock and the virtual clock; Step 404: Based on the first time parameter, the first current time value, and the time mapping relationship, calculate the first time value of the virtual clock at the first sampling moment.

[0119] like Figure 5 As shown above, in the above Figure 3 Based on the embodiment shown, step 2012 determines the target time error between the target hardware clock and the virtual clock based on at least one set of time data packets, including the following steps 501 and 502.

[0120] Step 501: Based on at least one set of time data packets, determine the measurement delay corresponding to each set of time data packets, and the time error between the virtual clock and the target hardware clock corresponding to each set of time data packets; Step 502: Based on the measurement delay corresponding to each group of time data packets, determine the target time error from at least one time error.

[0121] like Figure 6 As shown above, in the above Figure 5 Based on the embodiment shown, step 501 determines the time error between the virtual clock and the target hardware clock corresponding to each set of time data packets based on at least one set of time data packets, which may include steps 5011 to 5013 below.

[0122] Step 5011: Determine the measurement delay corresponding to the time data packet based on the difference between the second time value and the third time value.

[0123] Step 5012: Based on the second time value and the third time value, determine the intermediate time value corresponding to the first sampling moment of the target hardware clock.

[0124] Step 5013: Based on the difference between the intermediate time value and the first time value, determine the time error between the virtual clock corresponding to the time data packet and the target hardware clock.

[0125] Each time data packet includes a first time value, a second time value, and a third time value corresponding to three consecutive sampling actions. The first time value is the time value of the virtual clock at the first sampling moment, the second time value is the time value of the target hardware clock at the second sampling moment, and the third time value is the time value of the target hardware clock at the third sampling moment. The third sampling moment is earlier than the first sampling moment, and the first sampling moment is earlier than the second sampling moment.

[0126] like Figure 7 As shown above, in the above Figure 5 Based on the embodiment shown, step 502 determines the target time error from at least one time error based on the measurement delay corresponding to each group of time data packets, and may include the following steps 5021 and 5022.

[0127] Step 5021: In response to the existence of a minimum measurement delay among the measurement delays corresponding to each group of time data packets, and the minimum measurement delay being less than a preset delay threshold, the group of time data packets corresponding to the minimum measurement delay is determined as the target time data packet.

[0128] Step 5022: Determine the time error between the virtual clock corresponding to the target time data packet and the target hardware clock as the target time error.

[0129] like Figure 8 As shown above, in the above Figure 3 Based on the embodiment shown, step 2021 filters and modulates the target time error to obtain a frequency adjustment signal, which may include the following steps 801 to 803.

[0130] Step 801: Perform moving average filtering on the target time error to obtain the error smoothing value.

[0131] Step 802: Based on the proportional-integral control algorithm, process the error smoothing value to obtain the target frequency correction amount.

[0132] Step 803: Adjust the target frequency correction amount to the preset safe range to obtain the frequency adjustment signal.

[0133] like Figure 9 As shown above, in the above Figure 2 Based on the illustrated embodiment, step 203, based on the frequency adjustment signal, resets the first time parameter of the virtual clock in the previous time synchronization cycle to obtain the second time parameter of the virtual clock, including: Step 2031: In response to the start of the pivot equivalent rebase processing flow, read the time value of the hardware monotonic clock at the current moment as the second current time value; Step 2032: Determine the pivot point based on the second current time value; Step 2033: Based on the first time parameter and the pivot point, determine the first virtual time corresponding to the virtual clock at the pivot point; Step 2034: Determine the second time parameter of the virtual clock based on the pivot point, the first virtual time, and the frequency adjustment signal.

[0134] like Figure 10 As shown above, in the above Figure 2 Based on the illustrated embodiment, step 205, which determines the current virtual time of the virtual clock based on the frequency adjustment signal, the second time parameter, and the time value of the hardware monotonic clock at the current moment, includes: Step 2051: Read the time value of the hardware monotonic clock at the current moment and use it as the third current time value; Step 2052: Based on the second time parameter, the third current time value, and the pre-built time mapping relationship between the hardware monotonic clock and the virtual clock, determine the current virtual time of the virtual clock.

[0135] Regarding the time synchronization method in the above embodiments, the specific steps of each time synchronization method and the corresponding beneficial effects have been described in detail in the corresponding embodiment section of the aforementioned virtual clock device section. Please refer to the corresponding execution operation mode and beneficial technical effects in the aforementioned exemplary device section, which will not be repeated here.

[0136] Exemplary time synchronization device Corresponding to the time synchronization method provided in the above embodiments, this disclosure also provides a time synchronization device.

[0137] Figure 11 This is a schematic flowchart of a time synchronization device provided in an exemplary embodiment of this disclosure. Figure 11 As shown, the time synchronization device 110 may include a first determining module 1101, a second determining module 1102, a reset module 1103, a storage module 1104, and a third determining module 1105.

[0138] The first determining module 1101 is used to determine the target time error between the target hardware clock and the virtual clock within the time synchronization period between the virtual clock and the target hardware clock.

[0139] The virtual clock is built using a hardware monotonic clock as its underlying time reference.

[0140] The second determining module 1102 is used to determine the frequency adjustment signal based on the target time error.

[0141] The reset module 1103 is used to reset the first time parameter of the virtual clock in the previous time synchronization cycle based on the frequency adjustment signal, so as to obtain the second time parameter of the virtual clock.

[0142] The second time parameter is used in conjunction with the frequency adjustment signal to ensure that the virtual clock's time is continuously monotonic.

[0143] The storage module 1104 is used to write the second time parameter into shared memory.

[0144] The third determining module 1105 is used to respond to the application's request to read the time of the virtual clock, read the second time parameter from the shared memory, and determine the current virtual time of the virtual clock based on the frequency adjustment signal, the second time parameter and the time value of the hardware monotonic clock at the current moment.

[0145] In some embodiments of this disclosure, the first determining module 1101 is specifically used to determine at least one set of time data packets corresponding to the virtual clock and the target hardware clock within the time synchronization period between the virtual clock and the target hardware clock; and to determine the target time error between the target hardware clock and the virtual clock based on the at least one set of time data packets.

[0146] The second determining module 1102 is specifically used to filter and frequency modulate the target time error to obtain a frequency adjustment signal.

[0147] In some embodiments of this disclosure, the time data includes a first time value. The first determining module 1101 is specifically used to: use the time parameter of the previous time synchronization period read from the shared memory by the application as the first time parameter; read the time value of the hardware monotonic clock at the first sampling moment as the first current time value; determine the time mapping relationship between the pre-constructed hardware monotonic clock and the virtual clock; and calculate the first time value of the virtual clock at the first sampling moment based on the first time parameter, the first current time value, and the time mapping relationship.

[0148] In some embodiments of this disclosure, the first determining module 1101 is specifically used to determine the measurement delay corresponding to each set of time data packets and the time error between the virtual clock and the target hardware clock corresponding to each set of time data packets, based on at least one set of time data packets; and to determine the target time error from at least one time error based on the measurement delay corresponding to each set of time data packets.

[0149] In some embodiments of this disclosure, the first determining module 1101 is specifically used to determine the measurement delay corresponding to the time data packet based on the difference between the second time value and the third time value; determine the intermediate time value corresponding to the target hardware clock at the first sampling time based on the second time value and the third time value; and determine the time error between the virtual clock corresponding to the time data packet and the target hardware clock based on the difference between the intermediate time value and the first time value. Each set of time data packets includes a first time value, a second time value, and a third time value corresponding to three consecutive sampling actions; the first time value is the time value of the virtual clock at the first sampling time, the second time value is the time value of the target hardware clock at the second sampling time, and the third time value is the time value of the target hardware clock at the third sampling time; the third sampling time is earlier than the first sampling time, and the first sampling time is earlier than the second sampling time.

[0150] In some embodiments of this disclosure, the first determining module 1101 is specifically used to determine a group of time data packets corresponding to the minimum measurement delay as a target time data packet in response to the existence of a minimum measurement delay among the measurement delays corresponding to each group of time data packets, and the minimum measurement delay being less than a preset delay threshold; and to determine the time error between the virtual clock and the target hardware clock corresponding to the target time data packet as a target time error.

[0151] In some embodiments of this disclosure, the second determining module 1102 is specifically used to perform sliding mean filtering on the target time error to obtain an error smoothing value; process the error smoothing value based on the proportional-integral control algorithm to obtain a target frequency correction amount; and adjust the target frequency correction amount to a preset safe range to obtain a frequency adjustment signal.

[0152] In some embodiments of this disclosure, the reset module 1103 is specifically used to respond to the start of the pivot equal-value rebase processing flow, read the time value of the hardware monotonic clock at the current moment as the second current time value; determine the pivot point based on the second current time value; determine the first virtual time corresponding to the virtual clock at the pivot point based on the first time parameter and the pivot point; and determine the second time parameter of the virtual clock based on the pivot point, the first virtual time and the frequency adjustment signal.

[0153] In some embodiments of this disclosure, the third determining module 1105 is specifically used to read the time value of the hardware monotonic clock at the current moment as the third current time value; and to determine the current virtual time of the virtual clock based on the second time parameter, the third current time value and the pre-built time mapping relationship between the hardware monotonic clock and the virtual clock.

[0154] Regarding the time synchronization device in the above embodiments, the specific methods of operation of each module and the corresponding beneficial effects have been described in detail in the corresponding embodiments of the aforementioned time synchronization method section. Please refer to the corresponding operation methods and beneficial technical effects in the above exemplary method section, which will not be repeated here.

[0155] Exemplary electronic devices Figure 12 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this disclosure, such as... Figure 12 As shown, the electronic device 120 may include a processor 1201 and a memory 1202 for storing executable instructions of the processor 1201; wherein, the processor 1201 is used to read executable instructions from the memory 1202 and execute the instructions to implement the above. Figures 2 to 10 The time synchronization method provided in the illustrated embodiment.

[0156] The processor 1201 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 120 to perform desired functions.

[0157] The memory 1202 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1201 may execute the program instructions to implement the time synchronization methods of the various embodiments of this disclosure above and / or other desired functions.

[0158] In one example, the electronic device 120 may also include an input device 1203 and an output device 1204, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0159] Of course, for the sake of simplicity, Figure 12 Only some of the components of the electronic device 120 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 120 may include any other suitable components depending on the specific application.

[0160] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the time synchronization methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0161] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0162] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps of the time synchronization methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0163] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0164] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0165] Various modifications and variations can be made to this disclosure without departing from its spirit and scope. Therefore, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. A virtual clock device, the virtual clock device comprising a processor, the processor being configured to: Within the time synchronization period between the virtual clock and the target hardware clock, the target time error between the target hardware clock and the virtual clock is determined; wherein, The virtual clock is constructed using a hardware monotonic clock as the underlying time reference; Based on the target time error, determine the frequency adjustment signal corresponding to the virtual clock; Based on the frequency adjustment signal, the first time parameter of the virtual clock in the previous time synchronization period is reset to obtain the second time parameter of the virtual clock; wherein, the second time parameter is used in conjunction with the frequency adjustment signal to ensure that the time of the virtual clock is continuously monotonic; Write the second time parameter to the shared memory; In response to an application's request to read the time of the virtual clock, the second time parameter is read from the shared memory, and the current virtual time of the virtual clock is determined based on the second time parameter and the time value of the hardware monotonic clock at the current moment.

2. The apparatus according to claim 1, wherein, The processor is specifically configured as follows: Within the time synchronization period between the virtual clock and the target hardware clock, at least one set of time data packets corresponding to the virtual clock and the target hardware clock is determined; Based on the at least one set of time data packets, the target time error between the target hardware clock and the virtual clock is determined; The target time error is filtered and frequency-modulated to obtain a frequency adjustment signal.

3. The apparatus according to claim 2, wherein, The processor is specifically configured as follows: The first time parameter is based on the time parameter of the previous time synchronization period read by the application from the shared memory; Read the time value of the hardware monotonic clock at the first sampling moment and use it as the first current time value; Determine the time mapping relationship between the pre-built hardware monotonic clock and the virtual clock; Based on the first time parameter, the first current time value, and the time mapping relationship, the first time value of the virtual clock at the first sampling moment is calculated; wherein, the time data includes the first time value.

4. The apparatus according to claim 2, wherein, The processor is specifically configured as follows: Based on the at least one set of time data packets, the measurement delay corresponding to each set of time data packets and the time error between the virtual clock corresponding to each set of time data packets and the target hardware clock are determined respectively. The target time error is determined from at least one of the time errors based on the measurement delay corresponding to each group of time data packets.

5. The apparatus according to claim 4, wherein, The processor is specifically configured as follows: The measurement delay corresponding to the time data packet is determined based on the difference between the second time value and the third time value; Based on the second time value and the third time value, the intermediate time value corresponding to the target hardware clock at the first sampling time is determined; Based on the difference between the intermediate time value and the first time value, the time error between the virtual clock corresponding to the time data packet and the target hardware clock is determined; Each time data packet includes the first time value, the second time value, and the third time value corresponding to three consecutive sampling actions; the first time value is the time value of the virtual clock at the first sampling moment, the second time value is the time value of the target hardware clock at the second sampling moment, and the third time value is the time value of the target hardware clock at the third sampling moment. The third sampling time is earlier than the first sampling time, and the first sampling time is earlier than the second sampling time.

6. The apparatus according to claim 4, wherein, The processor is specifically configured as follows: In response to the existence of a minimum measurement delay among the measurement delays corresponding to each group of time data packets, and the minimum measurement delay being less than a preset delay threshold, the group of time data packets corresponding to the minimum measurement delay is determined as the target time data packet; The time error between the virtual clock corresponding to the target time data packet and the target hardware clock is determined as the target time error.

7. The apparatus according to claim 2, wherein, The processor is specifically configured as follows: The target time error is subjected to moving average filtering to obtain a smoothed error value; Based on the proportional-integral control algorithm, the error smoothing value is processed to obtain the target frequency correction amount; The target frequency correction amount is adjusted to a preset safe range to obtain the frequency adjustment signal.

8. The apparatus according to any one of claims 1-7, wherein, The processor is specifically configured as follows: In response to the start of the pivot equivalent rebase processing procedure, the time value of the hardware monotonic clock at the current moment is read as the second current time value; Determine the pivot point based on the second current time value; Based on the first time parameter and the pivot point, the first virtual time corresponding to the virtual clock at the pivot point is determined; The second time parameter of the virtual clock is determined based on the pivot point, the first virtual time, and the frequency adjustment signal.

9. The apparatus according to any one of claims 1-7, wherein the processor is specifically configured as follows: In response to an application's request to read the time from the virtual clock, the application is controlled to read the second time parameter from the shared memory; Read the time value of the hardware monotonic clock at the current moment, and use it as the third current time value; Based on the second time parameter, the third current time value, and the pre-built time mapping relationship between the hardware monotonic clock and the virtual clock, the current virtual time of the virtual clock is determined.

10. A time synchronization method applied to a virtual clock device, the method comprising: Within the time synchronization period between the virtual clock and the target hardware clock, a target time error between the target hardware clock and the virtual clock is determined; wherein, the virtual clock is constructed using a hardware monotonic clock as the underlying time reference; Based on the target time error, determine the frequency adjustment signal; Based on the frequency adjustment signal, the first time parameter of the virtual clock in the previous time synchronization period is reset to obtain the second time parameter of the virtual clock; wherein, the second time parameter is used in conjunction with the frequency adjustment signal to ensure that the time of the virtual clock is continuously monotonic; Write the second time parameter to the shared memory; In response to an application's request to read the time of the virtual clock, the second time parameter is read from the shared memory, and the current virtual time of the virtual clock is determined based on the frequency adjustment signal, the second time parameter, and the time value of the hardware monotonic clock at the current moment.

11. The method according to claim 10, wherein, Determining the target time error between the target hardware clock and the virtual clock includes: Within the time synchronization period between the virtual clock and the target hardware clock, at least one set of time data packets corresponding to the virtual clock and the target hardware clock is determined; Based on the at least one set of time data packets, the target time error between the target hardware clock and the virtual clock is determined; The step of determining the frequency adjustment signal corresponding to the virtual clock based on the target time error includes: filtering and frequency modulation processing the target time error to obtain the frequency adjustment signal.

12. The method according to claim 10, wherein, The step of resetting the first time parameter of the virtual clock in the previous time synchronization period based on the frequency adjustment signal to obtain the second time parameter of the virtual clock includes: In response to the start of the pivot equivalent rebase processing procedure, the time value of the hardware monotonic clock at the current moment is read as the second current time value; Determine the pivot point based on the second current time value; Based on the first time parameter and the pivot point, the first virtual time corresponding to the virtual clock at the pivot point is determined; The second time parameter of the virtual clock is determined based on the pivot point, the first virtual time, and the frequency adjustment signal.

13. The method according to any one of claims 10 to 12, wherein, Determining the current virtual time of the virtual clock based on the frequency adjustment signal, the second time parameter, and the time value of the hardware monotonic clock at the current moment includes: Read the time value of the hardware monotonic clock at the current moment, and use it as the third current time value; Based on the second time parameter, the third current time value, and the pre-built time mapping relationship between the hardware monotonic clock and the virtual clock, the current virtual time of the virtual clock is determined.

14. A time synchronization device, the device comprising: The first determining module is used to determine the target time error between the target hardware clock and the virtual clock within the time synchronization period between the virtual clock and the target hardware clock; wherein the virtual clock is constructed based on a hardware monotonic clock as the underlying time reference; The second determining module is used to determine the frequency adjustment signal based on the target time error; The reset module is used to reset the first time parameter of the virtual clock in the previous time synchronization cycle based on the frequency adjustment signal to obtain the second time parameter of the virtual clock; wherein, the second time parameter is used in conjunction with the frequency adjustment signal to ensure that the time of the virtual clock is continuously monotonic; The write module is used to write the second time parameter into shared memory; The third determining module is used to respond to the application's request to read the time of the virtual clock, read the second time parameter from the shared memory, and determine the current virtual time of the virtual clock based on the frequency adjustment signal, the second time parameter and the time value of the hardware monotonic clock at the current moment.

15. An electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the time synchronization method according to any one of claims 10-12.

16. A computer-readable storage medium storing a computer program, which, when executed by a processor, performs the time synchronization method according to any one of claims 10-12.

Images