A register verification method, platform and storage medium based on UVM
By using a UVM-based register verification method, test cases are automatically generated, solving the problems of low efficiency and long cycle in existing register verification technologies, and realizing comprehensive verification of complex SOC chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI CHIPON MICRO ELECTRONICS CO LTD
- Filing Date
- 2026-03-10
- Publication Date
- 2026-06-26
AI Technical Summary
In the existing technology, the register verification method of SOC chip relies on manual intervention, which is inefficient, time-consuming and difficult to maintain. It cannot fully verify the registers in complex SOC chips, especially the U/SV/SE and SFF attributes, boundary conditions and other aspects.
A UVM-based register verification method is adopted, which automatically generates various test cases by generating register tables with one click, including register attribute read/write checks, bus checks, SFF checks, bit_bash checks, and hw_reset checks. The systemVerilog file is automatically generated using library functions to achieve comprehensive register verification.
It achieves automated generation of test cases without human intervention, improves the efficiency and completeness of complex register verification, simplifies the maintenance process, and adapts to the verification needs of complex SOC chips.
Smart Images
Figure CN122285491A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of signal processing technology, specifically relating to a register verification method, platform, and storage medium based on UVM. Background Technology
[0002] A System-on-Chip (SoC) chip is a chip that integrates multiple functional modules such as a CPU processor, memory, and peripherals. It can be used in various electronic devices, such as smartphones, IoT devices, and computers. Registers are a crucial component of an SoC chip, used to represent states, configuration information, or store data. Register verification is an integral part of the entire process before chip delivery and is a vital step in ensuring the correct and stable function of registers. As the complexity and functionality of SoC chips increase, the number of registers also increases, leading to higher requirements for register verification and a significantly increased proportion of the verification cycle time. UVM provides a testing method for built-in sequences in the register model, including UVM_REG and UVM_MEM, which offers advantages such as portability and reusability. However, these methods only verify the read / write functionality and default values of registers, and do not cover other register verifications such as U / SV / SE and SFF attribute verification, boundary condition verification, timing verification, and atomic operations. The development process of traditional register testing methods relies on manual intervention, requiring manual exclusion of certain registers that do not need to be checked. It can only verify the basic functions of registers, and the rules for constructing test cases are not uniform, making it difficult to maintain later. For complex and numerous registers, the manual development of test cases is time-consuming, inefficient, and lacks completeness. Traditional register verification methods no longer meet the requirements of current complex SOC chip design. Summary of the Invention
[0003] The purpose of this invention is to address the problems existing in the prior art by providing a UVM-based register verification method that can generate various register-related test cases with one click based on the register table.
[0004] The technical solution is as follows: A register verification method based on UVM includes the following steps: Step 1: Compile a register table with a uniform format, showing all the various format errors of the register under test and the corresponding correction methods; Step 2: Create a program instance and define various events, create and display the main window, start the program's event loop, and respond to user actions; Step 3: Read and check the format of the register table. After the format check passes, call the execution event, including register attribute read and write check, register model generation, register bus check, register SFF check, register bit_bash check, and register hw_reset check. Step 4: When the register attribute read / write check, bus check, SFF check, bit_bash check, and hw_reset check events are triggered, the trigger library function automatically calls the corresponding template file and replaces the insertion point declared in the template file with the corresponding register in the register table. After the event is completed, the corresponding SystemVerilog file for the check is automatically generated in the current directory. Step 5: When the register model generation event is triggered, the trigger library function automatically calls the corresponding template file and extracts the register name, bit width, attributes, default value, bit, and reserved bit from the register table. Then, the gen_ral script is run to automatically generate a SystemVerilog file based on UVM's reg_model. Step 6: Clear the user interface using the function clear_text_display(); Step 7: Import the SystemVerilog test cases generated in the above steps into the corresponding verification environment, compile and run them.
[0005] Furthermore, the events in step 2 include keyboard input and mouse clicks; the main window is created and its size, background, layout, and creation buttons are defined by the MainWindow() function.
[0006] Furthermore, the read / write check of register attributes in step 4 includes the U attribute, SV attribute, and SE attribute.
[0007] Furthermore, the library function triggered by the read / write check of register attributes in step 4 is gen_reg_model_ralf().
[0008] Furthermore, the library function triggered by the register bus check in step 4 is gen_bus_check().
[0009] Furthermore, the library function triggered by the SFF register check in step 4 is gen_reg_sff_check().
[0010] Furthermore, the library function triggered by the register bit_bash check in step 4 is gen_bit_bash_check().
[0011] Furthermore, the library function triggered by the register hw_reset check in step 4 is gen_hw_reset_check().
[0012] A register verification platform includes a bus interface, a design under test (DUT), a memory, a processor, and a computer program stored in the memory. The DUT is a register circuit written in a hardware description language. The DUT is connected to the processor through the bus interface. When the processor executes the computer program in the memory, it runs the steps of the UVM-based register verification method described above.
[0013] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the UVM-based register verification method described above.
[0014] Beneficial effects: 1) This invention enables one-click automated generation of various test cases for register checks, eliminating the need for traditional manual intervention and overcoming the drawbacks of manual test case development, such as long development cycles, low efficiency, difficulty in maintenance, and low completeness.
[0015] 2) It can easily achieve comprehensive verification of more complex registers. Attached Figure Description
[0016] Figure 1 This is a flowchart of the method of the present invention; Figure 2 This is a schematic diagram of the device structure in an embodiment of the present invention. Detailed Implementation
[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit it. Terms such as "upper," "lower," "front," "rear," "left," "right," "bottom," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the purpose of describing the invention. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.
[0018] like Figure 1 The present invention relates to a UVM-based register verification method, comprising the following steps: Step 1: Compile a register table with a uniform format, showing all the various format errors of the register under test and the corresponding correction methods; Step 2: Create a program instance and define various events, including keyboard input and mouse clicks; create and display the main window, which is created using the MainWindow() function, and define its size, background, layout, and creation button; start the program's event loop to respond to user actions; Step 3: Read and check the format of the register table. After the format check passes, call the execution event, including register attribute read and write check, register model generation, register bus check, register SFF check, register bit_bash check, and register hw_reset check. Step 4: When register attribute read / write checks, bus checks, SFF checks, bit_bash checks, and hw_reset checks are triggered, the triggering library function automatically calls the corresponding template file and replaces the insertion points declared in the template file with the corresponding registers in the register table. After the event is completed, the corresponding SystemVerilog file for the check is automatically generated in the current directory. Register attribute read / write checks include U attribute, SV attribute, and SE attribute. The library function triggered by register attribute read / write checks is gen_reg_model_ralf(); the library function triggered by register bus checks is gen_bus_check(); the library function triggered by register SFF checks is gen_reg_sff_check(); the library function triggered by register bit_bash checks is gen_bit_bash_check(); and the library function triggered by register hw_reset checks is gen_hw_reset_check().
[0019] Step 5: When the register model generation event is triggered, the trigger library function automatically calls the corresponding template file and extracts the register name, bit width, attributes, default value, bit, and reserved bit from the register table. Then, the gen_ral script is run to automatically generate a SystemVerilog file based on UVM's reg_model. Step 6: Clear the user interface using the function clear_text_display(); Step 7: Import the SystemVerilog test cases generated in the above steps into the corresponding verification environment, compile and run them.
[0020] A register verification platform includes a bus interface, a design under test (DUT), a memory, a processor, and a computer program stored in the memory. The DUT is a register circuit written in a hardware description language. The DUT is connected to the processor through the bus interface. When the processor executes the computer program in the memory, it runs the steps of the UVM-based register verification method described above.
[0021] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the UVM-based register verification method described above.
[0022] Example: The register verification method of this invention uses a user interface written in Python. The user provides an Excel spreadsheet of the register to be tested. When the file is read and the Excel format is checked, the functions `check_format()` defined in the custom Python library `gen_reg` and `check_all()` defined in `register_class` can be used to check the offset address format, register attribute format, other read / write attribute format, reserved bit format, SFF bit format, and permission conflicts in the register table. The user interface will then indicate which format errors are present and provide corresponding correction methods. After the file is read and the Excel format check passes, different register check test cases can be generated. Each test case is independent and does not affect the others.
[0023] When the user selects register read / write attributes for verification, the functions gen_reg_rw_access() and gen_reg_rw_access_sv() defined in the Python custom library gen_reg call the template file reg_rw_access stored in the files folder. The template file iterates through the insertion points defined in the template file and replaces the corresponding insertion point position with the description of the corresponding register in the register table to verify the register behavior under boundary conditions, such as minimum value, maximum value, overflow, and reset.
[0024] When a user selects to generate a register model, the functions gen_reg_model_ralf() and gen_reg_model_ralf_sv() defined in the Python custom library gen_reg call the template file reg_ralf stored in the files folder, iterate through the insertion points defined in the template file, and replace the corresponding insertion point position with the description of the corresponding register in the register table.
[0025] When the user selects to generate a register bus check, the functions gen_bus_check() and gen_bus_check_sv() defined in the Python custom library gen_reg call the template file reg_bus_check stored in the files folder, iterate through the insertion points defined in the template file, and replace the position of the corresponding insertion point with the description of the corresponding register in the register table.
[0026] When the user selects to generate a register SFF check, the functions gen_sff_check() and gen_sff_check_sv() defined in the Python custom library gen_reg call the template file reg_sff_check stored in the files folder, iterate through the insertion points defined in the template file, and replace the position of the corresponding insertion point with the description of the corresponding register in the register table.
[0027] When the user selects register bit_bash for checking, the functions gen_bit_bash_check() and gen_bit_bash_check_sv() defined in the Python custom library gen_reg call the template file reg_bit_bash stored in the files folder. The template file iterates through the insertion points defined in the template file and replaces the corresponding insertion point with the description of the corresponding register in the register table. At the same time, RO and WO type registers are automatically filtered.
[0028] When the user selects register hw_reset for checking, the functions gen_hw_reset_check() and gen_hw_reset_check_sv() defined in the Python custom library gen_reg call the template file reg_hw_reset stored in the files folder. The template file iterates through the insertion points defined in the template file and replaces the corresponding insertion point with the description of the corresponding register in the register table, while automatically filtering WO type registers.
[0029] When the user chooses to clear the interface content, the interface content is cleared directly using the function clear_txt_display() defined in the Python custom library ui_module.
[0030] like Figure 2As shown, the tilelink_if bus interface in the register verification platform, as a hardware entity, serves as a bridge between the hardware and software. In the UVM verification environment, a virtual tilelink_if acts as a handle to receive the bus interface, transmitting signal-level timing information to the DUT (Design Under Test) through the bus interface at the software layer, thus enabling hardware-software interaction. The DUT is the design circuit written in the hardware description language RTL.
[0031] In the verification platform, test cases, also known as test vectors, are derived from uvm_test. They use register models to generate various bus transactions, creating different test cases to access the bus. The register model (registermodel) is a class type used in the UVM environment to describe registers. The register table to be checked is equivalently transformed into a register model for description, converting register operations into register model operations. These are then converted into various bus transaction operations via the adapter and sent to the sequence generator (sqr). After arbitration, the sqr sends the sequence generator to the driver. The driver, based on the timing requirements of the Tilelink bus protocol, converts the corresponding bus transactions into signal timing on the Tilelink bus interface, ultimately driving the design under test (DUT). The monitor detects whether the signal timing information on the Tilelink bus interface meets the requirements and converts the signal timing on the Tilelink bus into bus transactions to send to other UVM components. The bus agent (tilelink_agent) is a driver component (active agent) that acts as a container encapsulating the driver, monitor, and sequence generator (sqr). It can also be configured to use only the monitor, becoming a passive agent.
[0032] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the principles and spirit of the present invention should be included within the protection scope of the present invention.
Claims
1. A UVM-based register verification method, characterized in that: Includes the following steps: Step 1: Compile a register table with a uniform format, showing all the various format errors of the register under test and the corresponding correction methods; Step 2: Create a program instance and define various events, create and display the main window, start the program's event loop, and respond to user actions; Step 3: Read and check the format of the register table. After the format check passes, call the execution event, including register attribute read and write check, register model generation, register bus check, register SFF check, register bit_bash check, and register hw_reset check. Step 4: When the register attribute read / write check, bus check, SFF check, bit_bash check, and hw_reset check events are triggered, the trigger library function automatically calls the corresponding template file and replaces the insertion point declared in the template file with the corresponding register in the register table. After the event is completed, the corresponding SystemVerilog file for the check is automatically generated in the current directory. Step 5: When the register model generation event is triggered, the trigger library function automatically calls the corresponding template file and extracts the register name, bit width, attributes, default value, bit, and reserved bit from the register table. Then, the gen_ral script is run to automatically generate a SystemVerilog file based on UVM's reg_model. Step 6: Clear the user interface using the function clear_text_display(); Step 7: Import the SystemVerilog test cases generated in the above steps into the corresponding verification environment, compile and run them.
2. The UVM-based register verification method of claim 1, wherein: In step 2, the events include keyboard input and mouse clicks; the main window is created and its size, background, layout, and creation button are defined by the MainWindow() function.
3. The UVM-based register verification method of claim 1, wherein: The register attribute read / write check in step 4 includes the U attribute, SV attribute, and SE attribute.
4. The library function triggered by the register bus check in step 4 as described in claim 1 is gen_bus_check().
5. The UVM based register verification method as claimed in claim 1, wherein: In step 4, the library function triggered by the SFF register check is gen_reg_sff_check().
6. The UVM based register verification method as claimed in claim 1, wherein: In step 4, the library function triggered by the register bit_bash check is gen_bit_bash_check().
7. The UVM based register verification method as claimed in claim 1, wherein: In step 4, the library function triggered by the register hw_reset check is gen_hw_reset_check().
8. A register verification platform, characterized by: The device includes a bus interface, a design under test (DUT), a memory, a processor, and a computer program stored in the memory. The DUT is a register circuit written in a hardware description language. The DUT is connected to the processor via the bus interface. When the processor executes the computer program in the memory, it performs the steps of the UVM-based register verification method as described in any one of claims 1 to 7.
9. A computer-readable storage medium, characterized in that: The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the UVM-based register verification method according to any one of claims 1 to 7.