A method, apparatus, device and storage medium for interconnecting modules

Abstract

This invention discloses a method, apparatus, device, and storage medium for interconnecting modules, comprising: selecting a target bus from a chip interconnect channel according to preset requirements for connecting a transmitting module and a receiving module, and adjusting the routing of the target bus based on the receiving module; configuring a credit transmission channel interconnect structure and a bus matrix for the adjusted target bus; adjusting the bus connection method of the transmitting module and the receiving module based on the bus matrix, and performing protocol-free interconnection through the credit transmission channel interconnect structure. By adjusting the routing of the target bus for interconnecting modules on the chip interconnect channel based on the receiving module to alleviate wiring congestion in the interconnect channel, thereby facilitating physical implementation and high-speed interconnection, and by configuring a credit transmission channel interconnect structure and a bus matrix on the target bus after routing adjustment to perform protocol-free interconnection of the transmitting module and the receiving module, the transmission efficiency is improved while ensuring effective module interconnection.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more particularly to a method, apparatus, device, and storage medium for interconnecting modules. Background Technology

[0002] As AI chips carry larger amounts of data and become more complex, they contain more and more modules. Due to manufacturing limitations, many design modules need to be designed within the constraints of area. Inevitably, these modules need to access and interact with each other. As the complexity of task processing increases, these interaction networks become larger and larger. Typically, traditional interconnect networks are used inside the chip to achieve interconnection between modules.

[0003] However, with the increasing demand for interconnect bandwidth and the increasing width of interconnect bus, the requirements for the width of the routing channels are becoming more and more stringent. However, the relatively complex routing structure of traditional interconnect networks makes it difficult to achieve high-frequency and low-latency transmission at high bandwidth, thus failing to meet the high-performance requirements. Furthermore, when multiple sets of buses are used for interconnection between modules, more complex design structures are introduced, resulting in a waste of area resources. Summary of the Invention

[0004] This invention provides a method, apparatus, device, and storage medium for interconnecting modules, enabling flexible and efficient module interconnection under the constraints of chip interconnect channel area resources.

[0005] According to a first aspect of the present invention, a method for interconnecting modules is provided, the method comprising: selecting a target bus from a chip interconnect channel for connecting a transmitting module and a receiving module according to preset requirements, and adjusting the routing of the target bus based on the receiving module; The adjusted target bus is configured with a credit transmission channel interconnection structure and a bus matrix, wherein the bus matrix is ​​located at the front end of the credit transmission channel interconnection structure; The sending module and the receiving module adjust the bus connection method based on the bus matrix, and perform protocol-free interconnection through the credit transmission channel interconnection structure.

[0006] According to another aspect of the present invention, an interconnection device for modules is provided, the device comprising: a routing pattern adjustment module, configured to select a target bus for connecting a transmitting module and a receiving module from a chip interconnection channel according to preset requirements, and adjust the routing pattern of the target bus based on the receiving module; A configuration module is used to configure a credit transmission channel interconnection structure and a bus matrix for the adjusted target bus, wherein the bus matrix is ​​located at the front end of the credit transmission channel interconnection structure; The interconnection module is used for the sending module and the receiving module to adjust the bus connection mode based on the bus matrix, and to perform protocol-free interconnection through the credit transmission channel interconnection structure.

[0007] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: one or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any embodiment of the present invention.

[0008] According to another aspect of the present invention, a storage medium for computer-executable instructions is provided, on which a computer program is stored, which, when executed by a processor, implements the method as described in any of the embodiments of the present invention.

[0009] The technical solution of this invention alleviates the congestion of the chip interconnect channel by adjusting the routing of the target bus that interconnects modules on the chip interconnect channel based on the receiving module, so as to facilitate physical implementation and high-speed interconnection. By configuring a credit transmission channel interconnection structure and bus matrix on the target bus after the routing adjustment, the transmitting module and the receiving module are interconnected without protocol, thereby improving the efficiency of transmission while ensuring effective interconnection of modules.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart of a module interconnection method provided according to Embodiment 1 of the present invention; Figure 2 This is a comparison diagram of the connection method of the module provided in Embodiment 1 of the present invention before and after the change; Figure 3 This is a schematic diagram of the target bus after adjusting the routing method according to Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the interconnection structure of the credit transmission channel provided in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the structure of the first protocol converter and the second protocol converter provided in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the credit transmission channel interconnection substructure with added bus matrix provided in Embodiment 1 of the present invention; Figure 7 This is a flowchart of a module interconnection method provided according to Embodiment 2 of the present invention; Figure 8 This is a schematic diagram of the module connection after adding an expansion channel according to Embodiment 2 of the present invention; Figure 9 This is a schematic diagram of the structure of an interconnection device for modules according to Embodiment 3 of the present invention; Figure 10 This is a structural block diagram of an electronic device provided in Embodiment 4 of the present invention. Detailed Implementation

[0013] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0014] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, apparatus, product, or terminal device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or terminal devices.

[0015] Example 1 Figure 1 This is a flowchart of a module interconnection method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where modules within a chip are interconnected efficiently. The method can be executed by a module interconnection device, which can be implemented in hardware and / or software, and can be integrated into an electronic device with data processing capabilities. Figure 1 As shown, the method includes: S101 selects the target bus for connecting the transmitting module and the receiving module from the chip interconnect channel according to preset requirements, and adjusts the routing method of the target bus based on the receiving module.

[0016] Optionally, before selecting the target bus for connecting the transmitting module and the receiving module from a specified location on the chip interconnect channel, the method further includes: when it is determined that the chip has a two-level cache structure, reducing the distance between the transmitting module and the master device and increasing the distance between the transmitting module and the receiving module, wherein the transmitting module is a first-level cache and the receiving module is a second-level cache; determining that the transmitting module and the master device communicate using a first type of interconnection relationship, and the transmitting module and the receiving module communicate using a second type of interconnection relationship, wherein the first type of interconnection relationship includes address routing and mapping, and the second type of interconnection relationship includes point-to-point communication.

[0017] Specifically, when the chip is determined to have a two-level cache structure, the master device connects to the receiver module through the transmitting module. The transmitting module acts as the first-level cache, and the receiver module acts as the second-level cache. The master device and the transmitting module form a first-level interconnect, while the transmitting module and the receiver module form a second-level interconnect. The interconnection between multiple master devices and the first-level cache is the most complex, involving various address routing and mapping operations. The second-level interconnect between the first and second-level caches, however, has a structure close to a point-to-point interconnect because address routing and other operations are already completed at the first-level interconnect. Therefore, the module connection method can be modified, such as... Figure 2 As shown, the left side is a schematic diagram before the module connection method was changed. If the first-level cache is far from the main device, the first-level interconnect is limited by the complex connection relationships and long physical distance, resulting in a very large area overhead. Therefore, this embodiment changes the connection method by reducing the distance between the sending module and the main device and increasing the distance between the sending module and the receiving module. This means that the simple second-level interconnect network is used to handle a larger physical distance. Figure 2 The diagram on the right shows the changed connection method of the module. By adopting the above connection method, the area ratio of the interconnect network in the entire chip can be significantly reduced.

[0018] Optionally, the routing method of the target bus can be adjusted based on the receiving module, including: determining the horizontal bus in the target bus according to the width of the chip interconnect channel, and adjusting the horizontal bus to be routed horizontally on the chip interconnect channel; determining the vertical bus in the target bus according to the height of the receiving module, and adjusting the vertical bus to be routed vertically on the receiving module.

[0019] Specifically, in this embodiment, in order to further reduce the footprint of the interconnect bus, the following will be implemented: Figure 2The connection bus between the transmitting and receiving modules is adjusted. Since there are multiple buses between the transmitting and receiving modules, and the area of ​​the chip interconnect channel is fixed, considering the relatively wide bus width, if the interconnect buses were all routed in a rectangular channel from top to bottom, congestion would easily occur during subsequent physical layout and routing due to the limitations of the X-axis and overall area. In this embodiment, the multiple buses of the transmitting and receiving modules in the chip interconnect channel are filtered according to preset requirements to obtain the target bus. For example, the bus with the longest physical length can be selected as the target bus. Of course, this embodiment is only an example and does not limit the specific filtering method. The routing method is adjusted for the target bus, such as... Figure 3 The diagram shows the target bus after the routing method has been adjusted. A is the receiving module, B is the transmitting module, the credit pipe (the target bus that needs adjustment in this application), and the handshake pipe (the bus that the receiving and transmitting modules use for handshake protocol transmission and does not require adjustment). Specifically, in this embodiment, the horizontal bus in the target bus is determined based on the width of the chip interconnect channel and is adjusted to be routed horizontally on the chip interconnect channel. The vertical bus in the target bus is determined based on the height of the receiving module and is adjusted to be routed vertically on the receiving module. In this embodiment, the target bus utilizes the area of ​​receiving module A for routing, thereby alleviating the routing pressure on the chip interconnect channel. The remaining buses of the transmitting and receiving modules can directly follow the originally planned channels.

[0020] S102, configures the credit transmission channel interconnection structure and bus matrix for the adjusted target bus.

[0021] Optionally, configuring a credit transmission channel interconnect structure and a bus matrix for the adjusted target bus includes: configuring a credit transmission channel interconnect structure for the adjusted target bus, wherein the credit transmission channel interconnect structure includes at least one credit transmission channel interconnect substructure connected in sequence; configuring a bus matrix in front of the first credit transmission channel interconnect substructure, wherein the bus matrix is ​​connected to the clock controller.

[0022] Specifically, in this embodiment, a credit transmission channel interconnection structure is configured for the adjusted target bus, such as... Figure 4The diagram shows a schematic of a credit transmission channel interconnection structure. This structure includes at least one sequentially connected credit transmission channel interconnection substructure. Each substructure comprises a first protocol converter, a pipeline repeater, a second protocol converter, and a credit controller, all connected sequentially. The first protocol converter includes a reverse voltage converter and a signal shaper, while the second protocol converter includes a buffer. Figure 5 The diagram shows the structure of the first protocol converter and the second protocol converter. Additionally, in this embodiment, a bus matrix can be configured at the front end of the first credit transmission channel interconnect substructure, wherein the bus matrix is ​​connected to the clock controller, as shown below. Figure 6 The diagram shows a credit transmission channel interconnection substructure with an added bus matrix.

[0023] It should be noted that, since the interconnection distance between the sending and receiving modules may be relatively long, if only one credit transmission channel interconnection substructure is used throughout the entire path, a large buffer is required at the end because a buffer needs to be set up at the end credit controller to handle the round-trip data. This may exceed the area limit at the end. Therefore, this embodiment adopts the segmented connection method described above. Figure 4 As shown, it is split into two interconnected substructures of credit transmission channels. Of course, this embodiment is only an example and does not limit the specific number of interconnected substructures of credit transmission channels. It can be reasonably split according to the actual physical distance, thereby spreading the larger buffer at the end across the entire path and alleviating the area pressure of the end node.

[0024] S103, the transmitting module and the receiving module adjust the bus connection method based on the bus matrix, and perform protocol-free interconnection through the credit transmission channel interconnection structure.

[0025] Optionally, the transmitting module and the receiving module adjust the bus connection method based on the bus matrix, including: when it is determined that there is a damaged bus, sending a control command to the clock controller so that the clock controller generates a clock enable signal for the damaged bus according to the control command; and the bus matrix turns off the clock of the channel corresponding to the damaged bus according to the clock enable signal.

[0026] Specifically, as chip areas increase, manufacturing defects inevitably lead to some buses becoming unusable. This embodiment introduces a bus matrix to bypass unusable buses, enabling the still-functioning parts instead of directly discarding the chip. This embodiment introduces a configurable bus matrix at the front end of the interconnect structure of the data transmission channels. Software configuration allows for flexible switching between multiple bus groups, enabling a single starting point to different destinations. When a bus fails, a control command is sent to the clock controller, which then generates a clock enable signal for the damaged bus. The bus matrix then shuts down the clock of the corresponding channel on the damaged bus based on the clock enable signal, thus saving energy consumption of the invalid channels and achieving power saving.

[0027] Optionally, protocol-free interlocking via a credit transmission channel interconnection structure includes: a first protocol converter receiving protocol message data transmitted by the sending module through a bus matrix, and converting the protocol message data into protocol-free message data through a signal shaper; a pipeline repeater receiving the protocol-free message data and transmitting it to a second protocol converter via pure interlocking; the second protocol converter buffering the protocol-free message data in a buffer, converting the protocol-free message data in the buffer into protocol message data, and sending it to the receiving module; when the second protocol converter receives an over-processing capacity warning from the receiving module, it calculates the remaining space in the buffer through a credit controller; when the remaining space is less than a space threshold, it generates a data pause receiving instruction and sends the data pause receiving instruction to the first protocol converter sequentially through the second protocol converter and the pipeline repeater; the first protocol converter shuts down the bus interface communicating with the sending module according to the data pause receiving instruction.

[0028] Specifically, since most bus interconnects use handshake protocols, directly incorporating these protocols for transmission timing is limited by the combinational logic used in the implementation. In this case, the physical trace distance of the first-level pipe is shorter than that of a pure timing design without a protocol. Since the actual physical trace distance is fixed, for longer physical trace distances, using the handshake protocol for timing will result in a higher actual number of timings, leading to increased transmission latency and performance degradation. Therefore, this implementation introduces a credit transmission channel interconnect structure to enable protocol-free timing interconnection.

[0029] In a specific implementation, this embodiment uses a credit transmission channel interconnection structure containing only one credit transmission channel interconnection substructure as an example. After receiving the protocol message data transmitted by the sending module through the bus matrix, the first protocol converter first converts it into protocol-free message data. Specifically, the signal shaper in the first protocol converter converts the protocol message data into protocol-free message data, and then sends the protocol-free message data to the pipeline repeater. The pipeline repeater transmits the protocol-free message data to the second protocol converter through a pure handshake protocol. That is, transmitting data according to the protocol-free method significantly improves the data transmission efficiency. After the pipeline repeater sends the protocol-free message data to the second protocol converter, the second protocol converter buffers the protocol-free message data through a buffer, and then converts the buffered protocol-free message data back into protocol message data before sending it to the receiving module. Thus, the protocol-free transmission of data in the pipeline repeater is completed through the above process. Moreover, the protocol-free transmission adopted in this embodiment significantly improves the data transmission efficiency compared to the handshake protocol's ...

[0030] It should be noted that since the external bus interface has a handshake backpressure, and this method is eliminated during intermediate transmission, a credit controller is connected to the second protocol converter in this embodiment to control the actual amount of data that can be received on the right side. Specifically, when the amount of data received by the receiving module exceeds its processing capacity, the receiving module generates an over-processing capacity warning and sends it to the second protocol converter. Upon receiving the warning, the second protocol converter calculates the remaining space of the buffer through the credit controller. Since the second protocol converter includes multiple buffers, the credit controller only calculates the buffers involved in the current interaction between the transmission and transmission modules. When the remaining space is less than a preset space threshold, a data pause reception command is generated and sent sequentially to the first protocol converter through the second protocol converter and the pipeline repeater. At this time, the first protocol converter closes the bus interface communicating with the transmission module according to the data pause reception command, thereby alleviating the storage pressure on the second protocol converter side. However, when the remaining space is greater than the preset space threshold, no data pause receiving instruction will be generated. That is, although the processing capacity of the receiving module is limited, the buffer space of the second protocol converter is sufficient, so the receiving module will continue to receive the data sent by the sending module, and the data sending process of the sending module will not be interrupted.

[0031] The technical solution of this invention alleviates the congestion of the chip interconnect channel by adjusting the routing of the target bus that interconnects modules on the chip interconnect channel based on the receiving module, so as to facilitate physical implementation and high-speed interconnection. By configuring a credit transmission channel interconnection structure and bus matrix on the target bus after the routing adjustment, the transmitting module and the receiving module are interconnected without protocol, thereby improving the efficiency of transmission while ensuring effective interconnection of modules.

[0032] Example 2 Figure 7 This is a flowchart of another module interconnection method provided by an embodiment of the present invention. Based on the above embodiment, the receiving module consists of multiple sub-modules with a mirror-symmetric relationship, and the credit transmission channel interconnection substructure is evenly distributed on the sub-modules. The method further includes: determining the queued and unqueued buses in the sub-modules, and adding extension channels for the unqueued buses; connecting the extension channels in the sub-modules to the unqueued buses in the mirror sub-modules; and cross-connecting the queued buses in the sub-modules to the matched queued buses in the mirror sub-modules. Figure 7 As shown, the method includes: S201: Select the target bus for connecting the transmitting module and the receiving module from the chip interconnect channel according to preset requirements, and adjust the routing method of the target bus based on the receiving module.

[0033] Optionally, before selecting the target bus for connecting the transmitting module and the receiving module from a specified location on the chip interconnect channel, the method further includes: when it is determined that the chip has a two-level cache structure, reducing the distance between the transmitting module and the master device and increasing the distance between the transmitting module and the receiving module, wherein the transmitting module is a first-level cache and the receiving module is a second-level cache; determining that the transmitting module and the master device communicate using a first type of interconnection relationship, and the transmitting module and the receiving module communicate using a second type of interconnection relationship, wherein the first type of interconnection relationship includes address routing and mapping, and the second type of interconnection relationship includes point-to-point communication.

[0034] Optionally, the routing method of the target bus can be adjusted based on the receiving module, including: determining the horizontal bus in the target bus according to the width of the chip interconnect channel, and adjusting the horizontal bus to be routed horizontally on the chip interconnect channel; determining the vertical bus in the target bus according to the height of the receiving module, and adjusting the vertical bus to be routed vertically on the receiving module.

[0035] S202, configures the credit transmission channel interconnection structure and bus matrix for the adjusted target bus.

[0036] Optionally, configuring a credit transmission channel interconnect structure and a bus matrix for the adjusted target bus includes: configuring a credit transmission channel interconnect structure for the adjusted target bus, wherein the credit transmission channel interconnect structure includes at least one credit transmission channel interconnect substructure connected in sequence; configuring a bus matrix in front of the first credit transmission channel interconnect substructure, wherein the bus matrix is ​​connected to the clock controller.

[0037] S203, the transmitting module and the receiving module adjust the bus connection method based on the bus matrix, and perform protocol-free interconnection through the credit transmission channel interconnection structure.

[0038] Optionally, the transmitting and receiving modules adjust the bus connection method based on the bus matrix, including: when a damaged bus is determined to exist, sending a control command to the clock controller so that the clock controller generates a clock enable signal for the damaged bus according to the control command; and the bus matrix switches the damaged bus to an invalid channel according to the clock enable signal.

[0039] Optionally, protocol-free interlocking via a credit transmission channel interconnection structure includes: a first protocol converter receiving protocol message data transmitted by the sending module through a bus matrix, and converting the protocol message data into protocol-free message data through a signal shaper; a pipeline repeater receiving the protocol-free message data and transmitting it to a second protocol converter via pure interlocking; the second protocol converter buffering the protocol-free message data in a buffer, converting the protocol-free message data in the buffer into protocol message data, and sending it to the receiving module; when the second protocol converter receives an over-processing capacity warning from the receiving module, it calculates the remaining space in the buffer through a credit controller; when the remaining space is less than a space threshold, it generates a data pause receiving instruction and sends the data pause receiving instruction to the first protocol converter sequentially through the second protocol converter and the pipeline repeater; the first protocol converter shuts down the bus interface communicating with the sending module according to the data pause receiving instruction.

[0040] S204, when the receiving module is composed of multiple sub-modules with a mirror-symmetric relationship, determine the queued bus and unquenched bus in the sub-module, and add an extension channel for the unquenched bus.

[0041] Specifically, large chips typically contain numerous complex modules. To save time and manpower in backend implementation, there is a general tendency to reuse modules as much as possible. However, due to limitations in actual physical implementation, it may also be necessary for modules to satisfy a mirror symmetry relationship. But for directional interconnect designs, it is generally not possible to directly achieve module reuse and mirror requirements. Therefore, in this embodiment, when the receiving module is composed of multiple sub-modules with a mirror symmetry relationship, and the aforementioned credit transmission channel interconnect sub-structure is evenly distributed on the sub-modules, the queued and unquenched buses in the sub-modules will be determined, and an extension channel will be added for the unquenched buses.

[0042] S205 connects the extended channel in the submodule to the unteamed bus in the mirror submodule, and cross-connects the teamed bus in the submodule to the matched teamed bus in the mirror submodule.

[0043] In this embodiment, the connection of sub-modules will be implemented based on the extended channel, such as... Figure 8 The diagram shows the module connection after adding an extended channel. Data flows from top to bottom, and the two sub-modules are identical and mirror images of each other. chnl0-chnl2 are inherent channels in the original design. If the sub-modules are directly mirrored and reused, a conflict arises between the directions of chnl0 and its counterpart. Furthermore, for a single sub-module, chnl1 and chnl2 form a queued bus due to their opposite directions, while chnl0 is an unqueued bus. Therefore, in this implementation, an extended channel ext_chnl0 is added to chnl0. Then, chnl0 is connected to the ext_chnl0 channel, and the already bidirectional chnl1 and chnl2 are cross-connected, thus completing the module mirroring and reuse of the chip interconnect channels.

[0044] The technical solution of this invention alleviates the congestion of the chip interconnect channel by adjusting the routing of the target bus that interconnects modules on the chip interconnect channel based on the receiving module, so as to facilitate physical implementation and high-speed interconnection. By configuring a credit transmission channel interconnection structure and bus matrix on the target bus after the routing adjustment, the transmitting module and the receiving module are interconnected without protocol, thereby improving the efficiency of transmission while ensuring effective interconnection of modules.

[0045] Example 3 Figure 9 This is a schematic diagram of the structure of an interconnection device for modules provided in an embodiment of the present invention. For example... Figure 9 As shown, the device includes: a wiring pattern adjustment module 310, a configuration module 320, and an interconnection module 330.

[0046] The routing mode adjustment module 310 is used to select the target bus for connecting the transmitting module and the receiving module from the chip interconnect channel according to preset requirements, and adjust the routing mode of the target bus based on the receiving module. Configuration module 320 is used to configure the credit transmission channel interconnection structure and bus matrix for the adjusted target bus, wherein the bus matrix is ​​located at the front end of the credit transmission channel interconnection structure; Interconnect module 330 is used to adjust the bus connection method between the sending module and the receiving module based on the bus matrix, and to perform protocol-free interconnection through the credit transmission channel interconnection structure.

[0047] Optionally, a routing method adjustment module is used to determine the lateral bus in the target bus based on the width of the chip interconnect channel, and adjust the lateral bus to be routed laterally on the chip interconnect channel; The vertical bus in the target bus is determined based on the height of the receiving module, and the vertical bus is adjusted to be routed vertically on the receiving module.

[0048] Optionally, a configuration module is provided for configuring a credit transmission channel interconnect structure for the adjusted target bus, wherein the credit transmission channel interconnect structure includes at least one credit transmission channel interconnect substructure connected in sequence. A bus matrix is ​​configured at the front end of the first credit transmission channel interconnect substructure, wherein the bus matrix is ​​connected to the clock controller.

[0049] Optionally, the credit transmission channel interconnection substructure includes a first protocol converter, a pipeline repeater, a second protocol converter, and a credit controller connected in sequence. The first protocol converter includes a voltage converter and a signal shaper, while the second protocol converter includes a buffer.

[0050] Optionally, the interconnect module includes a connection mode adjustment unit for sending a control command to the clock controller when a damaged bus is detected, so that the clock controller generates a clock enable signal for the damaged bus according to the control command. The bus matrix shuts down the clock of the channel corresponding to the damaged bus based on the clock enable signal.

[0051] Optionally, the interconnect module includes an interconnect unit, which is used for the first protocol converter to receive protocol message data transmitted by the transmitting module through the bus matrix, and to convert the protocol message data into protocol-free message data through a signal shaper. The pipeline repeater receives the protocol-free message data and transmits the protocol-free message data to the second protocol converter through a pure stepping method. The second protocol converter buffers protocol-free message data through a buffer, and then converts the protocol-free message data in the buffer into protocol message data before sending it to the receiving module. When the second protocol converter receives an over-processing capacity warning from the receiving module, it calculates the remaining space of the buffer through the credit controller. When the remaining space is less than the space threshold, it generates a data pause receiving instruction and sends the data pause receiving instruction to the first protocol converter through the second protocol converter and the pipeline repeater in sequence. The first protocol converter shuts down the bus interface that communicates with the transmitting module based on the data pause receiving command.

[0052] Optionally, the receiving module consists of multiple sub-modules with a mirror-symmetric relationship, and the interconnection substructure of the credit transmission channel is evenly distributed on the sub-modules. The device also includes a mirror multiplexing module for determining the queued and unqueued buses in the sub-modules and adding an extension channel for the unqueued buses. Connect the extended channels in the submodule to the unteamed buses in the mirror submodule, and cross-connect the teamed buses in the submodule to the matched teamed buses in the mirror submodule.

[0053] Optionally, the device also includes a distance adjustment module, used to reduce the distance between the transmitting module and the master device and increase the distance between the transmitting module and the receiving module when it is determined that the chip has a two-level cache structure, wherein the transmitting module is the first-level cache and the receiving module is the second-level cache; The transmitting module and the master device communicate using a first type of interconnection relationship, and the transmitting module and the receiving module communicate using a second type of interconnection relationship. The first type of interconnection relationship includes address routing and mapping, and the second type of interconnection relationship includes point-to-point communication.

[0054] The module interconnection device provided in this embodiment of the invention can execute the module interconnection method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0055] Example 4 Figure 10 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0056] The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the invention described and / or claimed herein.

[0057] like Figure 10 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0058] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other electronic devices through computer networks such as the Internet and / or various telecommunications networks.

[0059] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the interconnection methods of modules.

[0060] That is, the target bus for connecting the transmitting module and the receiving module is selected from the chip interconnect channel according to preset requirements, and the routing method of the target bus is adjusted based on the receiving module; Configure a credit transmission channel interconnection structure and a bus matrix for the adjusted target bus, wherein the bus matrix is ​​located at the front end of the credit transmission channel interconnection structure; The sending and receiving modules adjust the bus connection method based on the bus matrix and perform protocol-free interconnection through the credit transmission channel interconnection structure.

[0061] In some embodiments, the module interconnection method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the module interconnection method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to execute the module interconnection method by any other suitable means (e.g., by means of firmware).

[0062] Various embodiments of the apparatuses and techniques described above herein can be implemented in digital electronic circuit devices, integrated circuit devices, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), device-on-a-chip (SoC) devices, complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable device including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage device, at least one input device, and at least one output device, and transmitting data and instructions to the storage device, the at least one input device, and the at least one output device.

[0063] Computer programs used to implement the interconnection method of the modules of this invention can be written in any combination of one or more programming languages. These computer programs can be provided to the processor of a general-purpose computer, a special-purpose computer, or other business-uninterrupted data migration device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer programs can be executed entirely on the machine, partially on the machine, as a standalone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0064] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution apparatus, device, or electronic device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage electronics, magnetic storage electronics, or any suitable combination thereof.

[0065] To provide interaction with a user, the devices and techniques described herein can be implemented on an electronic device having: a display device (e.g., a touchscreen) for displaying information to the user; and buttons through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0066] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0067] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for interconnecting modules, characterized in that, The method includes: The target bus for connecting the transmitting module and the receiving module is selected from the chip interconnect channel according to preset requirements, and the routing method of the target bus is adjusted based on the receiving module. The adjusted target bus is configured with a credit transmission channel interconnection structure and a bus matrix, wherein the bus matrix is ​​located at the front end of the credit transmission channel interconnection structure; The sending module and the receiving module adjust the bus connection method based on the bus matrix, and perform protocol-free interconnection through the credit transmission channel interconnection structure.

2. The method according to claim 1, characterized in that, The step of adjusting the routing of the target bus based on the receiving module includes: The horizontal bus in the target bus is determined based on the width of the chip interconnect channel, and the horizontal bus is adjusted to be routed horizontally on the chip interconnect channel; The vertical bus in the target bus is determined based on the height of the receiving module, and the vertical bus is adjusted to be routed vertically on the receiving module.

3. The method according to claim 1, characterized in that, The configuration of the credit transmission channel interconnection structure and bus matrix for the adjusted target bus includes: The adjusted target bus is configured with a credit transmission channel interconnection structure, wherein the credit transmission channel interconnection structure includes at least one credit transmission channel interconnection substructure connected in sequence. The bus matrix is ​​configured at the front end of the first credit transmission channel interconnect substructure, wherein the bus matrix is ​​connected to the clock controller.

4. The method according to claim 3, characterized in that, The interconnection substructure of the credit transmission channel includes a first protocol converter, a pipeline repeater, a second protocol converter, and a credit controller connected in sequence. The first protocol converter includes a reverse voltage converter and a signal shaper, and the second protocol converter includes a buffer.

5. The method according to claim 3, characterized in that, The transmitting module and the receiving module adjust the bus connection method based on the bus matrix, including: When a damaged bus is detected, a control command is sent to the clock controller so that the clock controller generates a clock enable signal for the damaged bus according to the control command. The bus matrix shuts down the clock of the channel corresponding to the damaged bus according to the clock enable signal.

6. The method according to claim 4, characterized in that, The protocol-free auction interconnection via the credit transmission channel interconnection structure includes: The first protocol converter receives protocol message data transmitted by the sending module through the bus matrix, and converts the protocol message data into protocol-free message data through the signal shaper. The pipeline repeater receives the protocol-free message data and transmits the protocol-free message data to the second protocol converter through a pure stepping method. The second protocol converter caches the protocol-free message data through the buffer, and then converts the protocol-free message data in the buffer into protocol message data before sending it to the receiving module. When the second protocol converter receives an over-processing capacity warning from the receiving module, it calculates the remaining space of the buffer through the credit controller. When the remaining space is less than the space threshold, it generates a data pause receiving instruction and sends the data pause receiving instruction to the first protocol converter through the second protocol converter and the pipeline repeater in sequence. The first protocol converter shuts down the bus interface communicating with the transmitting module according to the data pause receiving instruction.

7. The method according to claim 3, characterized in that, The receiving module is composed of multiple sub-modules with a mirror-symmetric relationship, and the interconnection substructure of the credit transmission channel is evenly distributed on the sub-modules. The method further includes: Identify the queued and unqueued buses in the submodule, and add an extension channel for the unqueued buses; Connect the extended channel in the submodule to the unteamed bus in the mirror submodule, and cross-connect the teamed bus in the submodule to the matched teamed bus in the mirror submodule.

8. The method according to claim 1, characterized in that, Before selecting the target bus for connecting the transmitting and receiving modules from a specified location on the chip interconnect channel, the method further includes: When the chip is determined to be a two-level cache structure, the distance between the transmitting module and the master device is reduced and the distance between the transmitting module and the receiving module is increased, wherein the transmitting module is the first-level cache and the receiving module is the second-level cache; The transmitting module and the master device communicate using a first type of interconnection relationship, and the transmitting module and the receiving module communicate using a second type of interconnection relationship. The first type of interconnection relationship includes address routing and mapping, and the second type of interconnection relationship includes point-to-point communication.

9. An interconnection device for modules, characterized in that, The device includes: The routing method adjustment module is used to select the target bus for connecting the transmitting module and the receiving module from the chip interconnect channel according to preset requirements, and adjust the routing method of the target bus based on the receiving module. A configuration module is used to configure a credit transmission channel interconnection structure and a bus matrix for the adjusted target bus, wherein the bus matrix is ​​located at the front end of the credit transmission channel interconnection structure; The interconnection module is used for the sending module and the receiving module to adjust the bus connection mode based on the bus matrix, and to perform protocol-free interconnection through the credit transmission channel interconnection structure.

10. An electronic device, characterized in that, The electronic device includes: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1-8.

11. A storage medium for computer-executable instructions, wherein a computer program is stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-8.

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