Display module, data voltage debugging method thereof and display device

Abstract

This invention discloses a display module, its data voltage adjustment method, and a display device. The display module includes a pixel circuit, a light-emitting element, a first chip, and a second chip. The pixel circuit includes a pulse amplitude modulation module and a pulse width modulation module. The pulse amplitude modulation module includes a first data writing unit, the input terminal of which is electrically connected to the first chip, and the first chip provides a data voltage to the first data writing unit. The pulse width modulation module includes a second data writing unit, the input terminal of which is electrically connected to the second chip, and the second chip provides a data voltage to the second data writing unit. This invention achieves flexible control of the light-emitting current and light-emitting duration of the light-emitting element by providing an adjustable data voltage to the pulse amplitude modulation module through the first chip and the second chip, thereby improving the display effect of different gray levels.

Description

Technical Field

[0001] The present invention relates to display technology, and more particularly to a display module and its data voltage debugging method and display device. Background Technology

[0002] In the field of display panel brightness adjustment, the mainstream dimming methods currently used in the industry are mainly DC dimming and PWM dimming. DC dimming adjusts the data voltage to change the luminous current of the light-emitting element, thereby achieving linear adjustment of display brightness. DC dimming is flicker-free and offers high visual comfort, but it is prone to color shift and uneven grayscale at low brightness. PWM dimming adjusts the duty cycle of the effective data signal to change the emission time of the light-emitting element, achieving brightness adjustment while keeping the luminous current constant. PWM dimming offers high grayscale control precision and minimal color shift, but high-frequency flicker can easily cause visual fatigue, and there are visual effect optimization bottlenecks in low grayscale scenarios. Summary of the Invention

[0003] This invention provides a display module and its data voltage adjustment method and display device. The display module is equipped with a first chip and a second chip. The first chip provides an adjustable data voltage to the pulse amplitude modulation module, and the second chip provides an adjustable data voltage to the pulse width modulation module, so as to realize flexible control of the light emission current and light emission duration of the light-emitting element and improve the display effect of different gray levels.

[0004] In a first aspect, embodiments of the present invention provide a display module, including a pixel circuit, a light-emitting element, a first chip, and a second chip. The pixel circuit includes a pulse amplitude modulation module and a pulse width modulation module. The output terminal of the pulse width modulation module is electrically connected to the pulse amplitude modulation module, and the output terminal of the pulse amplitude modulation module is electrically connected to the light-emitting element. The pulse amplitude modulation module includes a first data writing unit, the input terminal of which is electrically connected to the first chip, and the first chip is used to provide a data voltage to the first data writing unit; the pulse width modulation module includes a second data writing unit, the input terminal of which is electrically connected to the second chip, and the second chip is used to provide a data voltage to the second data writing unit.

[0005] Secondly, embodiments of the present invention also provide a data voltage debugging method for a display module, applicable to the display module described in the first aspect, the data voltage debugging method comprising: Obtain the power supply voltage values ​​of the first chip and the second chip; The display module is tested based on the power supply voltage values ​​of the first chip and the second chip to obtain the correspondence between the first data voltage and the second data voltage. The correspondence is stored in the display module; Wherein, the first data voltage is a pulse amplitude modulation data voltage, provided by the first chip, and the second data voltage is a pulse width modulation data voltage, provided by the second chip.

[0006] Thirdly, embodiments of the present invention also provide a display device, including the display module described in the first aspect.

[0007] This invention provides a display module including a pixel circuit, a light-emitting element, a first chip, and a second chip. The pixel circuit includes a pulse amplitude modulation module and a pulse width modulation module, enabling the pixel circuit to drive the light-emitting element to emit light through a PAM+PWM mode. The pulse amplitude modulation module includes a first data writing unit, and the pulse width modulation module includes a second data writing unit. The first chip provides an adjustable data voltage to the first data writing unit of the pulse amplitude modulation module, and the second chip provides an adjustable data voltage to the second data writing unit of the pulse width modulation module. This allows for flexible control of the light-emitting current and duration of the light-emitting element, ensuring high grayscale brightness while significantly improving the low grayscale display effect and enhancing the display effect at different grayscale levels. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the structure of a display module provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 3 A timing diagram of the driving signals for a pixel circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of a pixel circuit driving a light-emitting element to emit light, provided in an embodiment of the present invention. Figure 7 This is a schematic diagram of another display module provided in an embodiment of the present invention; Figure 8 As a kind of Figure 1 or Figure 7 A schematic diagram of the cross-sectional structure along the central section line A1A2; Figure 9 For another kind of along Figure 1 A schematic diagram of the cross-sectional structure along the central section line A1A2; Figure 10 This is a cross-sectional structural diagram of a display module provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of another display module provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of the structure of another display module provided in an embodiment of the present invention; Figure 13 A flowchart illustrating a data voltage debugging method for a display module provided in an embodiment of the present invention; Figure 14 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0009] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0010] The terminology used in the embodiments of this invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. It should be noted that directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this invention are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this invention. Furthermore, in the context, it should be understood that when referring to an element being formed "upper" or "lower" of another element, it can be formed not only directly "upper" or "lower" of the other element, but also indirectly "upper" or "lower" of the other element through an intermediate element. The terms "first," "second," etc., are used for descriptive purposes only and do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0011] The pixel circuits used in PWM dimming typically include a pulse amplitude modulation module and a pulse width modulation module. The inventors discovered in their research that, for existing PWM dimming architectures, the data voltage of the pulse amplitude modulation module is set to a fixed value in PWM dimming mode. This makes it impossible to dynamically adjust the voltage based on the displayed grayscale, thus failing to adapt to the brightness and visual effect optimization needs of different grayscale levels and application scenarios. This leads to the following technical contradictions: Low grayscale visual degradation: In low grayscale display scenarios, the fixed data voltage of the pulse amplitude modulation module corresponds to a large luminous current. The transient response characteristics of the luminous unit and the visual perception characteristics of the human eye can lead to problems such as uneven brightness, flickering, and lack of layering in low grayscale images, seriously affecting display quality. High and low grayscale performance cannot be balanced: If the data voltage of the pulse amplitude modulation module is actively reduced to improve low grayscale visual effects (since the data voltage of the pulse amplitude modulation module is constant in the existing technology, reducing the data voltage will lower the overall voltage value) to reduce the luminous current, it will directly lead to insufficient maximum brightness of the luminous unit in high grayscale scenarios, failing to meet the high brightness and high contrast requirements of the display panel. Lack of flexibility in dimming architecture: The existing PWM dimming architecture can only adjust the luminous time by adjusting the PWM data voltage, and cannot achieve coordinated dynamic control of the data voltage of the pulse amplitude modulation module and the pulse width modulation module, making it unable to adapt to the brightness and visual effect optimization requirements of different grayscale levels and different application scenarios.

[0012] To address the aforementioned problems, this invention provides a display module comprising a pixel circuit, a light-emitting element, a first chip, and a second chip. The pixel circuit includes a pulse amplitude modulation (PAM) module and a pulse width modulation (PWM) module, enabling the pixel circuit to drive the light-emitting element to emit light via a PAM+PWM mode. The PAM module includes a first data writing unit, and the PWM module includes a second data writing unit. The first chip provides an adjustable data voltage to the first data writing unit of the PAM module, and the second chip provides an adjustable data voltage to the second data writing unit of the PWM module. This allows for flexible control of the light-emitting current and duration of the light-emitting element, ensuring high grayscale brightness while significantly improving low grayscale display effects and enhancing the display effects across different grayscale levels.

[0013] The above is the core idea of ​​the embodiments of the present invention. The specific embodiments of the present invention are described below with reference to the accompanying drawings.

[0014] For example, Figure 1 This is a schematic diagram of the structure of a display module provided in an embodiment of the present invention, with reference to... Figure 1The display module provided in this embodiment of the invention includes a pixel circuit 10, a light-emitting element 20, a first chip 30, and a second chip 40. The pixel circuit 10 includes a pulse amplitude modulation module 11 and a pulse width modulation module 12. The output terminal of the pulse width modulation module 12 is electrically connected to the pulse amplitude modulation module 11, and the output terminal of the pulse amplitude modulation module 11 is electrically connected to the light-emitting element 20. The pulse amplitude modulation module 11 includes a first data writing unit 111, and the input terminal of the first data writing unit 111 is electrically connected to the first chip 30. The first chip 30 is used to provide a data voltage to the first data writing unit 111. The pulse width modulation module 12 includes a second data writing unit 121, and the input terminal of the second data writing unit 121 is electrically connected to the second chip 40. The second chip 40 is used to provide a data voltage to the second data writing unit 121.

[0015] The display module includes multiple arrayed pixel circuits 10 and light-emitting elements 20, the specific number of which can be designed according to actual conditions. The light-emitting elements 20 can be micro LEDs or organic light-emitting diodes (OLEDs), and the type of light-emitting elements 20 is not limited in this embodiment of the invention. Figure 1The diagram illustrates the principle of the display module rather than its actual structure. In the actual structure, the pixel circuit 10 is located below the light-emitting element 20. The pixel circuit 10 controls the light-emitting element 20 to emit light based on the PAM+PWM method. The pulse amplitude modulation module 11 is connected to the light-emitting element 20 and controls the current flowing through the light-emitting element 20 according to the data voltage PAM_DATA provided by the first chip 30 to the first data writing unit 111. The pulse width modulation module 12 is connected to the pulse amplitude modulation module 11 and controls the duration of the output current of the pulse amplitude modulation module 11 according to the data voltage PWM_DATA provided by the second chip 40 to the second data writing terminal 121, that is, controls the duration of the light emission of the light-emitting element 20. Understandably, when PAM_DATA is constant, the longer the duration of the output current of the PWM_DATA-controlled pulse amplitude modulation module 11, i.e., the larger the duty cycle of the light-emitting stage, the higher the brightness (grayscale) of the light-emitting element 20; conversely, the shorter the duration of the output current of the PWM_DATA-controlled pulse amplitude modulation module 11, i.e., the smaller the duty cycle of the light-emitting stage, the lower the brightness (grayscale) of the light-emitting element 20. When PWM_DATA is constant, the larger the output current of the PAM_DATA-controlled pulse amplitude modulation module 11, the higher the brightness of the light-emitting element 20; and the smaller the output current of the PAM_DATA-controlled pulse amplitude modulation module 11, the lower the brightness of the light-emitting element 20. Existing technologies typically connect the first data writing unit 111 to a fixed voltage terminal and the second data writing unit 121 to a chip, thereby keeping PAM_DATA constant and adjusting only the light emission duration to achieve brightness adjustment. This results in poor visual effects at low grayscale levels. In this embodiment of the invention, by setting the first chip 30, PAM_DATA can be adjusted on demand. At high grayscale levels, adjusting PAM_DATA causes the pulse amplitude modulation module 11 to output a large current, ensuring the display brightness of the light-emitting element 20. At low grayscale levels, adjusting PAM_DATA causes the pulse amplitude modulation module 11 to output a small current, improving display uniformity and ensuring the display effect of the light-emitting element 20.It should also be noted that, due to different circuit structure designs, in one embodiment, a larger PAM_DATA voltage value may result in a larger output current of the pulse amplitude modulation module 11, and a smaller PAM_DATA voltage value may result in a smaller output current of the pulse amplitude modulation module 11. In another embodiment, a larger PAM_DATA voltage value may result in a smaller output current of the pulse amplitude modulation module 11, and vice versa. In one embodiment, a larger PWM_DATA voltage value may result in a longer light-emitting duration of the light-emitting element 20, and a smaller PWM_DATA voltage value may result in a shorter light-emitting duration of the light-emitting element 20. In another embodiment, a larger PWM_DATA voltage value may result in a shorter light-emitting duration of the light-emitting element 20, and vice versa. The specific implementation can be designed according to the actual situation. For example, in one embodiment, the pixel circuit includes multiple P-type transistors. The voltage source of PWMDATA operates in the positive voltage domain, and the voltage of PWMDATA is positive, ranging from 0.5V to 6.5V. The voltage source of PAM_DATA operates in the negative voltage domain, ranging from -6.5V to 0V. If PWM_DATA is fixed, the larger PWM_DATA is, the brighter the light-emitting element; if PWMDATA is fixed, the smaller PAM_DATA is, the brighter the light-emitting element. In other embodiments, if PWM_DATA is negative, it indicates that the voltage change is transmitted to the pulse amplitude control module through capacitive coupling to control the light emission time. If PAM_DATA is negative, it indicates that its voltage source is in the negative voltage domain.

[0016] This embodiment of the invention does not limit the structure of the pixel circuit, as long as the pixel circuit 10 controls the light-emitting element 20 to emit light in a PAM+PWM manner. For example, Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 2 The pulse amplitude modulation module 11 includes a driving transistor M1, and the output terminal of the pulse width modulation module 12 is electrically connected to the gate (N1 node) of the driving transistor M1.

[0017] Among them, the driving transistor M1 is the driving unit of the pulse amplitude modulation module 11. The pulse amplitude modulation module 11 also includes transistors M3, M4, M5, M6, M7, M8 and capacitor C1. The pulse amplitude modulation module 11 includes 7 transistors and 1 capacitor. Its basic structure and principle are the same as the structure of the 7T1C circuit with 7 transistors and 1 capacitor in the prior art. The power supply voltage of the pulse amplitude modulation module 11 is PVDD, and the cathode voltage of the light-emitting element 20 is PVEE. M3 and M8 are the light-emitting control units of the pulse amplitude modulation module 11. The control terminals of M3 and M8 are connected to the light-emitting control signal terminal PAM_EM of the pulse amplitude modulation module 11. M4 and M5 are the driving units of the pulse amplitude modulation module 11. The initialization unit of the pulse amplitude modulation module 11 is used to initialize the N1 node and the anode of the light-emitting element 20 respectively. The control terminal of M4 is connected to the scanning signal terminal PAM_S1 of the pulse amplitude modulation module 11, and the input terminal is connected to the reference signal terminal PAM_VREF1 of the pulse amplitude modulation module 11. The control terminal of M5 is connected to the scanning signal terminals PAM_S1 / PAM_S2 of the pulse amplitude modulation module 11, and the input terminal is connected to the reference signal terminal PAM_VREF2 of the pulse amplitude modulation module 11. M6 and M7 are data writing and threshold compensation units. The input terminal of M6 inputs PAM_DATA, and the control terminals of M6 and M7 are connected to the scanning signal terminal PAM_S2. The pulse width modulation module 12 includes transistors M9, M10, M11, M12, M13, and M14, and capacitor C2. The pulse width modulation module 12 comprises six transistors and one capacitor. Its basic structure and principle are similar to the existing 7T1C circuit, which includes seven transistors and one capacitor. The difference is that the first terminal of capacitor C2 is not connected to PVDD, but to the scanning signal terminal SWEEP. Furthermore, since the pulse width modulation module 12 is not directly electrically connected to the light-emitting element 20, the initialization unit (corresponding to M5 in the pulse amplitude modulation module 11) connected to the anode of the light-emitting element 20 is removed. M10 and M14 are pulse... The control terminals of the light-emitting control unit M10 and M14 of the pulse width modulation module 12 are both connected to the light-emitting control signal terminal PWM_EM of the pulse width modulation module 12. M11 is the initialization unit of the pulse width modulation module 12, used to initialize the N2 node. The control terminal of M11 is connected to the scanning signal terminal PWM_S1 of the pulse width modulation module 12, and the input terminal is connected to the reference signal terminal PWM_VREF1 of the pulse width modulation module 12. M12 and M13 are data writing and threshold compensation units. The input terminal of M12 inputs PWM_DATA, and the control terminals of M12 and M13 are connected to the scanning signal terminal PWM_S2.

[0018] Figure 3 This is a timing diagram of the driving signals for a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 3The pixel circuit driving process includes PAM input stage T1, PWM input stage T2, and emission stage T3. In PAM input stage T1, the scan signal PAM_SCAN1 provided by the scan signal terminal PAM_S1 first controls M4 to turn on. The reference voltage signal provided by the reference voltage terminal PAM_VREF1 is written to node N1 to initialize the voltage of N1. Then, the scan signal PAM_SCAN2 provided by the scan signal terminal PAM_S2 controls M6 and M7 to turn on, and the data signal PAM_DATA is written to node N1, simultaneously achieving threshold compensation for M1. In PWM input stage T2, the scan signal PWM_SCAN1 provided by the scan signal terminal PWM_S1 first controls M11 to turn on, and the reference voltage signal provided by the reference voltage terminal PWM_VRFE1 is written to node N2 to achieve… The voltage of N2 is initialized, and then the scan signal PWM_SCAN2 provided by the scan signal terminal PWM_S2 controls M12 and M13 to turn on. The data signal PWM_DATA is written to node N2, and threshold compensation of M9 is realized at the same time. In the light-emitting stage T3, the enable signal terminal PWM_EM provides the enable signal PWM_EMIT to control M10 and M14 to turn on. At the same time, the sweep frequency signal SWEEP is applied to the pulse width modulation module. The gate voltage of M9 is changed by using the bootstrap effect of the capacitor. When the voltage of the sweep frequency signal reaches the threshold, the pulse width modulation module outputs a turn-off signal to the gate of M1 to control M1 to turn off. At the same time, in this stage, the enable signal PAM_EMIT provided by the enable signal terminal PAM_EM controls M3 and M8 to turn on. The light-emitting element is in the light-emitting state before M1 is turned off.

[0019] In this embodiment, the output terminal of the pulse width modulation module 12 is electrically connected to the gate of the driving transistor M1. When the output signal of the pulse width modulation module 12 controls the driving transistor M1 to turn on, the pulse amplitude modulation module 11 provides driving current to the light-emitting element 20, and the light-emitting element 20 emits light. When the output signal of the pulse width modulation module 12 controls the driving transistor M1 to turn off, the pulse amplitude modulation module 11 cannot provide driving current to the light-emitting element 20, and the light-emitting element 20 does not emit light.

[0020] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 4 The overall structure of the pixel circuit is similar to Figure 2 Similar to the previous text, but simplified in some places, only showing the similarities. Figure 2 Different parts, and Figure 2 The difference in the embodiment is that the pulse amplitude modulation module 11 includes a driving transistor M1 and a control transistor M2, with the control transistor M2 connected between the driving transistor M1 and the light-emitting element 20; the output terminal of the pulse width modulation module 12 is electrically connected to the gate of the control transistor M2.

[0021] In this embodiment, the control transistor M2 is used to control whether the pulse amplitude modulation module 11 outputs a drive current. The output terminal of the pulse width modulation module 12 is electrically connected to the gate of the control transistor M2. When the output signal of the pulse width modulation module 12 causes the control transistor M2 to be turned on, the pulse amplitude modulation module 11 provides a drive current to the light-emitting element 20, and the light-emitting element 20 emits light. When the output signal of the pulse width modulation module 12 causes the control transistor M2 to be turned off, the pulse amplitude modulation module 11 cannot provide a drive current to the light-emitting element 20, and the light-emitting element 20 does not emit light.

[0022] Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention, with reference to... Figure 5 The overall structure of the pixel circuit is similar to Figure 2 Similar to the previous text, but simplified in some places, only showing the similarities. Figure 2 Different parts, and Figure 2 The difference in the embodiments is that the pulse amplitude modulation module 11 includes a driving transistor M1, the pixel circuit also includes a connecting capacitor C, the output terminal of the pulse width modulation module 12 is electrically connected to the first terminal of the connecting capacitor C, and the second terminal of the connecting capacitor C is electrically connected to the gate of the driving transistor M1.

[0023] In this embodiment, when the output signal of the pulse width modulation module 12 controls the driving transistor M1 through the coupling effect of the connecting capacitor C, the light-emitting element 20 emits light when the driving transistor M1 is turned on, and the light-emitting element 20 does not emit light when the driving transistor M1 is turned off.

[0024] Understandable, Figure 2 , Figure 4 and Figure 5 The pixel circuit structure shown is only illustrative. Other pixel circuit structures can be used in other embodiments. The structure of the pixel circuit can be designed according to the actual situation during specific implementation.

[0025] When the display module displays an image, the pulse amplitude modulation module 11 controls the magnitude of the light-emitting current of the light-emitting element 20, and the pulse width modulation module 12 controls the duration of the light-emitting time of the light-emitting element 20. For example, Figure 6 This is a schematic diagram of a pixel circuit driving a light-emitting element to emit light, provided in an embodiment of the present invention. (Refer to...) Figure 6The first chip is IC1, which controls the adjustment range of the light-emitting current from a to b. The second chip is IC2, which controls the adjustment range of the light-emitting time from c to d. By setting the first and second chips, the PAM_DATA and PWM_DATA voltages can be adjusted simultaneously. For example, when displaying high grayscale, adjusting PAM_DATA causes the light-emitting element 20 to output a large current, thereby ensuring the display brightness of the light-emitting element 20. When displaying low grayscale, adjusting PAM_DATA causes the light-emitting element 20 to output a small current, improving display uniformity and thus improving the display effect. The light-emitting time is adjusted according to the actual situation. For example, high grayscale and low grayscale can correspond to the same light-emitting time, or the light-emitting time of high grayscale can be set to be longer than that of low grayscale. This embodiment of the invention does not limit this.

[0026] Optionally, the display module includes a first display mode and a second display mode, in which the light-emitting element 20 has different brightness; in the first display mode, the first chip 30 provides a first voltage to the first data writing unit 111, and the second chip 40 provides a second voltage to the second data writing unit 121; in the second display mode, the first chip 30 provides a third voltage to the first data writing unit 111, and the second chip 40 provides a fourth voltage to the second data writing unit 121; the first voltage and the third voltage are different, and the second voltage and the fourth voltage are different.

[0027] The display module can have multiple different display modes during display. The brightness of the light-emitting element 20 is different in different display modes. In this embodiment, the light-emitting current of the light-emitting element 20 is different for different display modes, and the light-emitting duration of the light-emitting element 20 can be set to be the same or different according to the actual situation. In one embodiment, optionally, the brightness of the light-emitting element in the first display mode is greater than the brightness of the light-emitting element in the second display mode. When the first data writing unit 111 writes the first voltage, the pulse amplitude modulation module 11 outputs the first current. When the first data writing unit 111 writes the third voltage, the pulse amplitude modulation module 11 outputs the second current, and the first current is greater than the second current. When the second data writing unit 121 writes the second voltage, the pulse width modulation module 12 controls the light-emitting element to emit light for a first duration. When the second data writing unit 121 writes the fourth voltage, the pulse width modulation module 12 controls the light-emitting element to emit light for a second duration, and the first duration is greater than the second duration.

[0028] For example, in one embodiment, if the higher the data voltage of the first data writing unit 111, the greater the output current of the pulse amplitude modulation module 11, and the higher the data voltage of the second data writing unit 121, the longer the light emission duration controlled by the pulse width modulation module 12 for the light-emitting element, then the first voltage is greater than the third voltage, and the second voltage is greater than the fourth voltage. In another embodiment, if the higher the data voltage of the first data writing unit 111, the smaller the output current of the pulse amplitude modulation module 11, and the higher the data voltage of the second data writing unit 121, the shorter the light emission duration controlled by the pulse width modulation module 12 for the light-emitting element, then the first voltage is less than the third voltage, and the second voltage is less than the fourth voltage. The specific implementation is designed according to the actual pixel circuit structure.

[0029] It is understood that, in the technical solution of the present invention, since the brightness of the light-emitting element 20 can be adjusted by adjusting the data voltage of the first data writing unit 111, in another embodiment, the light-emitting duration of the light-emitting element 20 can be set to be the same in the first display mode and the second display mode. That is, in the first display mode, the first data writing unit 111 writes the first voltage and the second data writing unit 121 writes the second voltage; in the second display mode, the first data writing unit 111 writes the third voltage and the second data writing unit 121 writes the second voltage.

[0030] Continue to refer to Figure 1 Optionally, the display module also includes a storage module 50, which stores the output voltage relationship between the first chip 30 and the second chip 40 under the first display mode and the second display mode.

[0031] By pre-storing the output voltage relationship between the first chip 30 and the second chip 40 in the storage module 50, the first chip 30 and the second chip 40 can directly output voltages via a lookup table during display by the display module, eliminating the need for real-time calculations. This reduces the power consumption and hardware cost of the driver chip and improves response speed. Optionally, the output voltage relationship between the first chip 30 and the second chip 40 can be pre-tested and calibrated. The testing and calibration process can refer to the embodiment of the data voltage debugging method for the display module, which will not be detailed here.

[0032] Continue to refer to Figure 1 Optionally, the display module also includes multiple first data lines 60 extending along the first direction x and multiple second data lines 70 extending along the first direction x. The input terminal of the first data writing unit 111 is electrically connected to the first chip 30 through the first data lines 60, and the input terminal of the second data writing unit 121 is electrically connected to the second chip 40 through the second data lines 70.

[0033] Wherein, the first direction x can be the row or column direction of the array formed by the pixel circuits 10. The first data line 60 is electrically connected to the first data writing unit 111 in a row or column of the pixel circuits 10, and is used to transmit the data voltage provided by the first chip 30 to the corresponding first data writing unit 111. The second data line 70 is electrically connected to the second data writing unit 121 in a row or column of the pixel circuits 10, and is used to transmit the data voltage provided by the second chip 40 to the corresponding second data writing unit 121. Both the first data line 60 and the second data line 70 are located in the metal layer of the display module, and in specific implementations, they can be located in the same metal layer or different metal layers. Figure 1 In the illustrated embodiment, optionally, the first chip 30 and the second chip 40 are located on the first and second sides opposite to each other of the display module, and the first data line 60 and the second data line 70 are located on the same metal layer or different metal layers.

[0034] For example, Figure 1 In one embodiment, the first chip 30 and the second chip 40 are located on the upper and lower sides of the display module, respectively. The extension direction of the first data line 60 and the second data line 70 is the column direction of the pixel circuit 10. In other embodiments, the first chip 30 and the second chip 40 can also be located on the left and right sides of the display module, respectively, and the extension direction of the first data line 60 and the second data line 70 is the row direction of the pixel circuit 10. The specific implementation can be designed according to the actual situation. When the first chip 30 and the second chip 40 are located on both sides of the display module, the first data line 60 and the second data line 70 will not intersect with the chips. Therefore, the data line 60 and the second data line 70 can be located on the same metal layer or different metal layers.

[0035] Figure 7 This is a schematic diagram of another display module provided in an embodiment of the present invention, with reference to... Figure 7 Optionally, the first chip 30 and the second chip 40 are located on the same side of the display module along the first direction x, and the first data line 60 and the second data line 70 are located on different metal layers.

[0036] Figure 7 The illustration showing that both the first chip 30 and the second chip 40 are located on the lower side of the display module, and that the first chip 30 is located above the second chip 40, is only illustrative. In other embodiments, the positions of the first chip 30 and the second chip 40 can be designed according to actual conditions. Figure 8 As a kind of Figure 1 or Figure 7 A schematic diagram of the cross-sectional structure along the central section line A1A2. Figure 9 For another kind of along Figure 1 A schematic diagram of the cross-sectional structure along the central section line A1A2, wherein, Figure 8 and Figure 9Other film layers in the display module are not shown; only the data lines are schematically shown. The first data line 60 and the second data line 70 are located in the same metal layer. Figure 9 ) or different metal layers ( Figure 8 In specific implementation, the film layer structure can be designed according to the actual display module. Figure 1 and Figure 7 In the intersections shown, solid dots indicate electrical connections, while intersections without solid dots are not connected. The same applies to other embodiments.

[0037] Figure 10 This is a cross-sectional structural diagram of a display module provided in an embodiment of the present invention, with reference to... Figure 10 or Figure 8 Optionally, the display module includes a first surface 101 and a second surface 102 disposed opposite to each other. The first surface 102 is a light-emitting surface, that is, the first surface 101 is the display surface of the display module, and the second surface 102 is the back surface of the display module. The second surface 102 is provided with a first chip 30 and a second chip 40. The display module also includes a side trace 80. The first end of the side trace 80 is located on the first surface 101 of the display module. A portion of the side trace 80 covers the sidewall 103 of the display module. The second end of the side trace 80 is located on the second surface 102 of the display module. The side trace 80 includes a first side trace 81 and a second side trace 82. The first data line is connected to the first chip 30 through the first side trace 81, and the second data line is connected to the second chip 40 through the second side trace 82.

[0038] Specifically, the first end of the first side trace 81 is bonded to the connection terminal of the first surface 101 of the display module to achieve connection with the first data line; the first chip 30 is bonded to the second end of the first side trace 81; the first end of the second side trace 82 is bonded to the connection terminal of the first surface 101 of the display module to achieve connection with the second data line; and the second chip 40 is bonded to the second end of the second side trace 82. In a specific implementation, the side trace 80 may include side trace silver paste and outer encapsulation adhesive. Figure 10 The specific film structure of the display panel in the display module is not shown in the figure. Figure 10 In one embodiment, a narrow bezel is achieved by placing the first chip 30 and the second chip 40 on the back of the display module.

[0039] In the structure of a display module, a flexible circuit board is usually set at one end of the display panel as a flexible interconnection bridge between the panel and the driver / motherboard, responsible for transmitting display signals, power and control signals, etc. Since the flexible circuit board usually needs to occupy a certain space, optionally, the width of the first side trace is greater than the width of the second side trace, and / or the spacing between two adjacent first side traces is greater than the spacing between two adjacent second side traces.

[0040] For example, Figure 11 This invention provides a schematic diagram of the structure of a display module, as shown in the following embodiment. Figure 11 The lower frame of the display module is provided with a flexible circuit board 200. The width d1 of the first side trace 81 is greater than the width d2 of the second side trace 82, and the spacing d3 between two adjacent first side traces 81 is greater than the spacing d4 between two adjacent second side traces 82.

[0041] Understandable, Figure 11 The diagram shows a front view of the display module. The first chip 30 and the second chip 40 are located on the back of the display module and are represented by dashed lines because they are not visible. Since the top of the display module does not have a flexible circuit board, there is more space for the first side trace 81. Therefore, the width d1 of the first side trace 81 is greater than the width d2 of the second side trace 82, and the spacing d3 between two adjacent first side traces 81 is greater than the spacing d4 between two adjacent second side traces 82, thereby reducing signal interference. In other embodiments, if the flexible circuit board is on the same side as the first chip, the width of the second side trace is greater than the width of the first side trace, and / or the spacing between two adjacent second side traces is greater than the spacing between two adjacent second side traces.

[0042] Figure 12 This is a schematic diagram of another display module provided in an embodiment of the present invention, with reference to... Figure 12 Optionally, the display module also includes multiple first scan lines 90 and multiple second scan lines 100. The first scan lines 90 are electrically connected to the control terminal of the first data writing unit 111, and the second scan lines 100 are electrically connected to the control terminal of the second data writing unit 121. The first chip 30 or the second chip 40 is also used to provide corresponding scan signals to the first scan lines 90 and the second scan lines 100.

[0043] in, Figure 12The illustration shows that both the first scan line 90 and the second scan line 100 are electrically connected to the second chip 40. That is, the second chip 40 provides corresponding scan signals to the first scan line 90 and the second scan line 100. This is merely illustrative and not a limitation of the embodiments of the present invention. In other embodiments, the first chip 30 may also be configured to provide scan signals, or a first shift register unit and a second shift register unit may be configured in the display module. The first and second shift register units may include multi-level connected shift registers. The specific structure of the shift registers can be designed according to actual conditions. The first chip 30 or the second chip 40 is used to provide initial signals (e.g., clock signal CK, start signal STV, etc.) to the first and second shift register units. The first and second shift register units can be set in the display area to achieve a borderless layout, providing scan signals to the corresponding scan lines to achieve pixel-level control.

[0044] Figure 13 This is a flowchart illustrating a data voltage debugging method for a display module according to an embodiment of the present invention. This data voltage debugging method is applicable to any of the display modules provided in the above embodiments and is used to calibrate the output voltage relationship between the first chip and the second chip. (Refer to...) Figure 13 The data voltage adjustment method includes: S110: Obtain the power supply voltage value of the first chip and the power supply voltage value of the second chip.

[0045] In this embodiment, both the first chip and the second chip include multiple preset power supply voltage values. Before conducting the correspondence test, it is necessary to first determine the power supply voltage values ​​that the first chip can output and the power supply voltage values ​​of the second chip, and then conduct the test.

[0046] S120. Perform display module testing based on the power supply voltage values ​​of the first chip and the second chip to obtain the correspondence between the first data voltage and the second data voltage.

[0047] Under laboratory conditions, various combinations of power supply voltage values ​​provided by the first chip and the second chip can be applied to the display module to test different brightness levels, uniformity, etc., obtaining and recording the corresponding relationships that meet the requirements. In practical implementation, the influence of environmental factors such as temperature can be comprehensively considered to test and maintain multiple corresponding relationships.

[0048] In specific implementation, optionally, the power supply voltage value of the first chip includes multiple first voltages, and the power supply voltage value of the second chip includes multiple second voltages corresponding to multiple display grayscale levels; the display module is tested based on the power supply voltage values ​​of the first chip and the second chip to obtain the correspondence between the first data voltage and the second data voltage, including: Each first data voltage is fixed sequentially, and the corresponding second data voltage is determined sequentially under different display grayscale levels to obtain multiple sets of first data voltage and second data voltage first correspondences, wherein the first correspondence includes one first data voltage and multiple second data voltages.

[0049] Optionally, the number of first data voltages is n, where n is an integer greater than or equal to 2, and the first correspondence is determined according to the following steps: By fixing the first data voltage, controlling the light-emitting element to display different gray levels, measuring the second data voltage corresponding to each gray level, and fitting the data, the first gray level-second data voltage curve corresponding to the first data voltage is obtained. By fixing the second first data voltage, controlling the light-emitting element to display different display gray levels, measuring the second data voltage corresponding to each display gray level, and fitting the data to obtain the second gray level-second data voltage curve corresponding to the second first data voltage; The corresponding steps are executed sequentially until the nth first data voltage is fixed. The light-emitting element is controlled to display different display gray levels. The second data voltage corresponding to each display gray level is measured. The data is fitted to obtain the nth gray level-second data voltage curve corresponding to the nth first data voltage, and n first correspondences are obtained.

[0050] For example, taking n=16 as an example, Table 1 is the test data table for determining the first correspondence in the embodiment of the present invention. The first data voltage (PAM_DATA) includes VA0~VA15, and the difference between two adjacent data voltages can be 0.1V. The light-emitting element is controlled to sequentially display the second data voltage (PWM_DATA) corresponding to gray levels 0, 2, 4, 8, 16, 32, 64, 128, and 255 in gray level. The test process is as follows: First, fix the first data voltage VA0, that is, the first data voltage provided by the first chip is always VA0, and control the light-emitting element to display the second data voltage (PWM_DATA) corresponding to gray levels 0, 2, 4, 8, 16, 32, 64, 128, and 255 in gray level. Do not display gray levels 0, 2, 4, 8, 16, 32, 64, 128, and 255. Measure the second data voltages VW00, VW10, VW20, VW30, VW40, VW50, VW60, VW70, and VW80 corresponding to each displayed gray level (i.e., the data in the second row of Table 1). Fit the data to obtain the first gray level-second data voltage curve (a gamma curve) corresponding to the first first data voltage VA0. Based on the first gray level-second data voltage curve, the second data voltages corresponding to other gray levels can be calculated. Then, fix the second first data voltage. VA1, the first data voltage provided by the first chip, is always VA1. This controls the light-emitting elements to display gray levels of 0, 2, 4, 8, 16, 32, 64, 128, and 255 respectively. The second data voltages VW01, VW11, VW21, VW31, VW41, VW51, VW61, VW71, and VW81 corresponding to each displayed gray level are measured (see the data in row 3 of Table 1). The data is fitted to obtain the second gray level-second data voltage curve corresponding to the second first data voltage VA1. Based on the first gray level-second data voltage curve, the corresponding values ​​for other gray levels can be calculated. The second data voltage; similarly, the corresponding steps are executed sequentially until the 16th first data voltage VA15 is fixed, and the light-emitting element is controlled to display 0 gray level, 2 gray level, 4 gray level, 8 gray level, 16 gray level, 32 gray level, 64 gray level, 128 gray level and 255 gray level respectively. The second data voltage VW015, VW115, VW215, VW315, VW415, VW515, VW615, VW715 and VW815 corresponding to each displayed gray level are measured. The data is fitted to obtain the 16th gray level-second data voltage curve corresponding to the 16th first data voltage, and 16 first correspondences are obtained.

[0051] It is understandable that the more gray levels tested during testing, the more accurate the gray level-second data voltage curve will be. The selection of each test gray level in this embodiment is only illustrative. In other embodiments, other test gray levels can be selected. This article only introduces the test method and does not limit the number of test gray levels or the specific gray level selection.

[0052] Table 1 Test data table for determining the first correspondence After obtaining multiple sets of first correspondences, the first data voltage and the second data voltage under each display grayscale are selected from the multiple sets of first correspondences according to preset requirements.

[0053] The preset requirements can be selected according to the actual application scenario. For example, in a low-power scenario, the combination of the first data voltage and the second data voltage with the lowest power consumption at each display grayscale can be selected from multiple sets of first correspondence relationships. In a scenario with high display effect requirements, the combination of the first data voltage and the second data voltage with the best display uniformity can be selected from multiple sets of first correspondence relationships. In other scenarios, the combination of the first data voltage and the second data voltage can also be selected according to the priority of different specifications and the actual situation.

[0054] Record the first and second data voltages corresponding to all display grayscale levels to obtain the correspondence. Optionally, for each display grayscale level, there are n sets of data voltage groups, each data voltage group including a first data voltage and a second data voltage; select the first and second data voltages for each display grayscale level from multiple sets of first correspondences, including: Based on the preset requirements, a set of data voltage groups is selected for each display grayscale, and the corresponding relationship is obtained by fitting the curve.

[0055] For example, taking 16 first data voltages as an example, referring to Table 1, each display grayscale corresponds to 16 groups of data voltages. For instance, when the first data voltage provided by the first chip is VA0 and the second data voltage provided by the second chip is VW00, the display module displays 0 grayscale. When the first data voltage provided by the first chip is VA1 and the second data voltage provided by the second chip is VW01, the display module also displays 0 grayscale. VA2 and VW02, VA3 and VW03, VA4 and VW04, VA5 and VW05, VA6 and VW06, VA7 and VW07, VA8 and VW08, VA9 and VW09, VA10 and VW010, VA11 and VW011, VA12 and VW012, VA13 and VW013, VA... The combinations of 14 and VW014, as well as VA15 and VW015, both enable the display module to display 0 grayscale. Based on actual needs, a set of data voltage groups is selected for each display grayscale. For example, in one embodiment, VA0 and VW00 are selected for 0 grayscale, VA2 and VW12 for 2 grayscale, VA5 and VW25 for 4 grayscale, VA7 and VW37 for 8 grayscale, VA7 and VW47 for 16 grayscale, VA9 and VW59 for 32 grayscale, VA10 and VW610 for 64 grayscale, VA13 and VW713 for 128 grayscale, and VA13 and VW813 for 255 grayscale. Based on the above data voltage groups, a curve (the final gamma curve) can be fitted to obtain the first and second data voltages corresponding to other grayscale levels.

[0056] S130. Store the corresponding relationship in the display module.

[0057] The first data voltage is a pulse amplitude modulation data voltage, provided by the first chip, and the second data voltage is a pulse width modulation data voltage, provided by the second chip.

[0058] By pre-calibrating the correspondence between the first data voltage and the second data voltage and storing it in the storage module of the display module, when the display module is displaying, the first chip 30 and the second chip 40 can directly output the voltage by looking up the table, without the need for real-time calculation, thereby reducing the power consumption and hardware cost of the driver chip and improving the response speed.

[0059] Figure 14 This is a schematic diagram of a display device provided in an embodiment of the present invention. (Reference) Figure 14 The display device 1 includes any of the display modules 2 provided in the embodiments of the present invention. Specifically, the display device 1 can be a mobile phone, a computer, or a smart wearable device, etc.

[0060] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display module, characterized in that, The device includes a pixel circuit, a light-emitting element, a first chip, and a second chip. The pixel circuit includes a pulse amplitude modulation module and a pulse width modulation module. The output terminal of the pulse width modulation module is electrically connected to the pulse amplitude modulation module, and the output terminal of the pulse amplitude modulation module is electrically connected to the light-emitting element. The pulse amplitude modulation module includes a first data writing unit, the input terminal of which is electrically connected to the first chip, and the first chip is used to provide a data voltage to the first data writing unit; the pulse width modulation module includes a second data writing unit, the input terminal of which is electrically connected to the second chip, and the second chip is used to provide a data voltage to the second data writing unit.

2. The display module according to claim 1, characterized in that, The display module includes a first display mode and a second display mode, wherein the light-emitting brightness of the light-emitting element is different in the first display mode and the second display mode; In the first display mode, the first chip provides a first voltage to the first data writing unit, and the second chip provides a second voltage to the second data writing unit; in the second display mode, the first chip provides a third voltage to the first data writing unit, and the second chip provides a fourth voltage to the second data writing unit. The first voltage is different from the third voltage, and the second voltage is different from the fourth voltage.

3. The display module according to claim 2, characterized in that, The brightness of the light-emitting element in the first display mode is greater than that in the second display mode. When the first data writing unit writes the first voltage, the pulse amplitude modulation module outputs a first current. When the first data writing unit writes the third voltage, the pulse amplitude modulation module outputs a second current. The first current is greater than the second current. When the second data writing unit writes the second voltage, the pulse width modulation module controls the light-emitting element to emit light for a first duration. When the second data writing unit writes the fourth voltage, the pulse width modulation module controls the light-emitting element to emit light for a second duration, wherein the first duration is longer than the second duration.

4. The display module according to claim 2, characterized in that, It also includes a storage module, which stores the output voltage relationship between the first chip and the second chip under the first display mode and the second display mode.

5. The display module according to claim 4, characterized in that, The output voltage relationship between the first chip and the second chip is pre-tested and calibrated.

6. The display module according to claim 1, characterized in that, It also includes multiple first data lines extending along a first direction and multiple second data lines extending along the first direction. The input terminal of the first data writing unit is electrically connected to the first chip through the first data lines, and the input terminal of the second data writing unit is electrically connected to the second chip through the second data lines.

7. The display module according to claim 6, characterized in that, The first chip and the second chip are located on the same side of the display module along the first direction, and the first data line and the second data line are located on different metal layers.

8. The display module according to claim 6, characterized in that, The first chip and the second chip are located on opposite first and second sides of the display module, and the first data line and the second data line are located on the same metal layer or different metal layers.

9. The display module according to claim 7 or 8, characterized in that, The display module includes a first surface and a second surface disposed opposite to each other, the first surface being a light-emitting surface; the second surface is provided with the first chip and the second chip. The display module further includes a side trace, the first end of which is located on the first surface of the display module, a portion of which covers the sidewall of the display module, and the second end of which is located on the second surface of the display module. The side trace includes a first side trace and a second side trace. The first data line is connected to the first chip through the first side trace, and the second data line is connected to the second chip through the second side trace.

10. The display module according to claim 9, characterized in that, The width of the first side trace is greater than the width of the second side trace, and / or the spacing between two adjacent first side traces is greater than the spacing between two adjacent second side traces.

11. The display module according to claim 6, characterized in that, It also includes multiple first scan lines and multiple second scan lines, wherein the first scan lines are electrically connected to the control terminal of the first data writing unit, and the second scan lines are electrically connected to the control terminal of the second data writing unit; the first chip or the second chip is also used to provide corresponding scan signals to the first scan lines and the second scan lines.

12. A method for adjusting the data voltage of a display module, characterized in that, The data voltage debugging method, applicable to any of the display modules described in claims 1 to 11, includes: Obtain the power supply voltage values ​​of the first chip and the second chip; The display module is tested based on the power supply voltage values ​​of the first chip and the second chip to obtain the correspondence between the first data voltage and the second data voltage. The correspondence is stored in the display module; Wherein, the first data voltage is a pulse amplitude modulation data voltage, provided by the first chip, and the second data voltage is a pulse width modulation data voltage, provided by the second chip.

13. The data voltage debugging method for a display module according to claim 12, characterized in that, The power supply voltage values ​​of the first chip include multiple first voltages, and the power supply voltage values ​​of the second chip include multiple second voltages corresponding to multiple display grayscale levels; display module testing is performed based on the power supply voltage values ​​of the first chip and the power supply voltage values ​​of the second chip to obtain the correspondence between the first data voltage and the second data voltage, including: Each first data voltage is fixed sequentially, and the corresponding second data voltage is determined sequentially under different display grayscale levels to obtain multiple sets of first data voltage and second data voltage first correspondences, wherein the first correspondences include one first data voltage and multiple second data voltages; According to preset requirements, select the first data voltage and the second data voltage for each of the display grayscale levels from multiple sets of the first correspondence relationships; Record the first and second data voltages corresponding to all the displayed grayscale levels to obtain the correspondence.

14. The data voltage debugging method for a display module according to claim 13, characterized in that, The number of the first data voltages is n, where n is an integer greater than or equal to 2. The first correspondence is determined according to the following steps: The first data voltage is fixed, and the light-emitting element is controlled to display different display gray levels. The second data voltage corresponding to each display gray level is measured, and the data is fitted to obtain the first gray level-second data voltage curve corresponding to the first data voltage. By fixing the second first data voltage, controlling the light-emitting element to display different display gray levels, measuring the second data voltage corresponding to each display gray level, and fitting the data to obtain the second gray level-second data voltage curve corresponding to the second first data voltage; The corresponding steps are executed sequentially until the nth first data voltage is fixed. The light-emitting element is controlled to display different display gray levels. The second data voltage corresponding to each display gray level is measured. The data is fitted to obtain the nth gray level-second data voltage curve corresponding to the nth first data voltage, and n first correspondences are obtained.

15. The data voltage debugging method for a display module according to claim 14, characterized in that, Under each of the aforementioned display grayscale levels, there are n sets of data voltage groups, and each set of data voltage groups includes a first data voltage and a second data voltage; Selecting the first data voltage and the second data voltage under each display grayscale from multiple sets of the first correspondence includes: According to the preset requirements, a set of data voltage groups is selected for each of the display grayscale levels, and the corresponding relationship is obtained by fitting a curve.

16. A display device, characterized in that, Includes the display module described in any one of claims 1 to 11.

Images